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pinctrl: abx500: suppress hardcoded value
[deliverable/linux.git] / drivers / pinctrl / pinctrl-abx500.c
CommitLineData
0493e649
PC		 1/*
2 * Copyright (C) ST-Ericsson SA 2013
3 *
4 * Author: Patrice Chotard <patrice.chotard@st.com>
5 * License terms: GNU General Public License (GPL) version 2
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/slab.h>
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/err.h>
f30a3839
LJ		 17#include <linux/of.h>
18#include <linux/of_device.h>
0493e649
PC		 19#include <linux/platform_device.h>
20#include <linux/gpio.h>
21#include <linux/irq.h>
ac652d79 22#include <linux/irqdomain.h>
0493e649
PC		 23#include <linux/interrupt.h>
24#include <linux/bitops.h>
25#include <linux/mfd/abx500.h>
26#include <linux/mfd/abx500/ab8500.h>
27#include <linux/mfd/abx500/ab8500-gpio.h>
28#include <linux/pinctrl/pinctrl.h>
29#include <linux/pinctrl/consumer.h>
30#include <linux/pinctrl/pinmux.h>
31#include <linux/pinctrl/pinconf.h>
32#include <linux/pinctrl/pinconf-generic.h>
64a45c98 33#include <linux/pinctrl/machine.h>
0493e649
PC		 34
35#include "pinctrl-abx500.h"
61ce1356 36#include "core.h"
64a45c98 37#include "pinconf.h"
0493e649
PC		 38
39/*
40 * The AB9540 and AB8540 GPIO support are extended versions
41 * of the AB8500 GPIO support.
42 * The AB9540 supports an additional (7th) register so that
43 * more GPIO may be configured and used.
44 * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have
45 * internal pull-up and pull-down capabilities.
46 */
47
48/*
49 * GPIO registers offset
50 * Bank: 0x10
51 */
52#define AB8500_GPIO_SEL1_REG 0x00
53#define AB8500_GPIO_SEL2_REG 0x01
54#define AB8500_GPIO_SEL3_REG 0x02
55#define AB8500_GPIO_SEL4_REG 0x03
56#define AB8500_GPIO_SEL5_REG 0x04
57#define AB8500_GPIO_SEL6_REG 0x05
58#define AB9540_GPIO_SEL7_REG 0x06
59
60#define AB8500_GPIO_DIR1_REG 0x10
61#define AB8500_GPIO_DIR2_REG 0x11
62#define AB8500_GPIO_DIR3_REG 0x12
63#define AB8500_GPIO_DIR4_REG 0x13
64#define AB8500_GPIO_DIR5_REG 0x14
65#define AB8500_GPIO_DIR6_REG 0x15
66#define AB9540_GPIO_DIR7_REG 0x16
67
68#define AB8500_GPIO_OUT1_REG 0x20
69#define AB8500_GPIO_OUT2_REG 0x21
70#define AB8500_GPIO_OUT3_REG 0x22
71#define AB8500_GPIO_OUT4_REG 0x23
72#define AB8500_GPIO_OUT5_REG 0x24
73#define AB8500_GPIO_OUT6_REG 0x25
74#define AB9540_GPIO_OUT7_REG 0x26
75
76#define AB8500_GPIO_PUD1_REG 0x30
77#define AB8500_GPIO_PUD2_REG 0x31
78#define AB8500_GPIO_PUD3_REG 0x32
79#define AB8500_GPIO_PUD4_REG 0x33
80#define AB8500_GPIO_PUD5_REG 0x34
81#define AB8500_GPIO_PUD6_REG 0x35
82#define AB9540_GPIO_PUD7_REG 0x36
83
84#define AB8500_GPIO_IN1_REG 0x40
85#define AB8500_GPIO_IN2_REG 0x41
86#define AB8500_GPIO_IN3_REG 0x42
87#define AB8500_GPIO_IN4_REG 0x43
88#define AB8500_GPIO_IN5_REG 0x44
89#define AB8500_GPIO_IN6_REG 0x45
90#define AB9540_GPIO_IN7_REG 0x46
91#define AB8540_GPIO_VINSEL_REG 0x47
92#define AB8540_GPIO_PULL_UPDOWN_REG 0x48
93#define AB8500_GPIO_ALTFUN_REG 0x50
0493e649
PC		 94#define AB8540_GPIO_PULL_UPDOWN_MASK 0x03
95#define AB8540_GPIO_VINSEL_MASK 0x03
96#define AB8540_GPIOX_VBAT_START 51
97#define AB8540_GPIOX_VBAT_END 54
98
acd260b0
PC		 99#define ABX500_GPIO_INPUT 0
100#define ABX500_GPIO_OUTPUT 1
101
0493e649
PC		 102struct abx500_pinctrl {
103 struct device *dev;
104 struct pinctrl_dev *pctldev;
105 struct abx500_pinctrl_soc_data *soc;
106 struct gpio_chip chip;
107 struct ab8500 *parent;
0493e649
PC		 108 struct abx500_gpio_irq_cluster *irq_cluster;
109 int irq_cluster_size;
0493e649
PC		 110};
111
112/**
113 * to_abx500_pinctrl() - get the pointer to abx500_pinctrl
114 * @chip: Member of the structure abx500_pinctrl
115 */
116static inline struct abx500_pinctrl *to_abx500_pinctrl(struct gpio_chip *chip)
117{
118 return container_of(chip, struct abx500_pinctrl, chip);
119}
120
121static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg,
83b423c8 122 unsigned offset, bool *bit)
0493e649
PC		 123{
124 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
125 u8 pos = offset % 8;
126 u8 val;
127 int ret;
128
129 reg += offset / 8;
130 ret = abx500_get_register_interruptible(pct->dev,
131 AB8500_MISC, reg, &val);
132
133 *bit = !!(val & BIT(pos));
134
135 if (ret < 0)
136 dev_err(pct->dev,
137 "%s read reg =%x, offset=%x failed\n",
138 __func__, reg, offset);
139
140 return ret;
141}
142
143static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
83b423c8 144 unsigned offset, int val)
0493e649
PC		 145{
146 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
147 u8 pos = offset % 8;
148 int ret;
149
150 reg += offset / 8;
151 ret = abx500_mask_and_set_register_interruptible(pct->dev,
49dcf086 152 AB8500_MISC, reg, BIT(pos), val << pos);
0493e649
PC		 153 if (ret < 0)
154 dev_err(pct->dev, "%s write failed\n", __func__);
83b423c8 155
0493e649
PC		 156 return ret;
157}
83b423c8 158
0493e649
PC		 159/**
160 * abx500_gpio_get() - Get the particular GPIO value
83b423c8
LJ		 161 * @chip: Gpio device
162 * @offset: GPIO number to read
0493e649
PC		 163 */
164static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset)
165{
166 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
167 bool bit;
d8d4f7f8
PC		 168 bool is_out;
169 u8 gpio_offset = offset - 1;
0493e649
PC		 170 int ret;
171
d8d4f7f8
PC		 172 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG,
173 gpio_offset, &is_out);
174 if (ret < 0) {
175 dev_err(pct->dev, "%s failed\n", __func__);
176 return ret;
177 }
178
179 if (is_out)
180 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_OUT1_REG,
181 gpio_offset, &bit);
182 else
183 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG,
184 gpio_offset, &bit);
0493e649
PC		 185 if (ret < 0) {
186 dev_err(pct->dev, "%s failed\n", __func__);
187 return ret;
188 }
83b423c8 189
0493e649
PC		 190 return bit;
191}
192
193static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
194{
195 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
196 int ret;
197
198 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
199 if (ret < 0)
200 dev_err(pct->dev, "%s write failed\n", __func__);
201}
202
d2752ae5
PC		 203static int abx500_get_pull_updown(struct abx500_pinctrl *pct, int offset,
204 enum abx500_gpio_pull_updown *pull_updown)
0493e649
PC		 205{
206 u8 pos;
d2752ae5 207 u8 val;
0493e649
PC		 208 int ret;
209 struct pullud *pullud;
210
211 if (!pct->soc->pullud) {
212 dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
213 __func__);
214 ret = -EPERM;
215 goto out;
216 }
217
218 pullud = pct->soc->pullud;
219
220 if ((offset < pullud->first_pin)
221 || (offset > pullud->last_pin)) {
222 ret = -EINVAL;
223 goto out;
224 }
225
d2752ae5
PC		 226 ret = abx500_get_register_interruptible(pct->dev,
227 AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, &val);
228
229 pos = (offset - pullud->first_pin) << 1;
230 *pull_updown = (val >> pos) & AB8540_GPIO_PULL_UPDOWN_MASK;
231
232out:
233 if (ret < 0)
234 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
235
236 return ret;
237}
238
239static int abx500_set_pull_updown(struct abx500_pinctrl *pct,
240 int offset, enum abx500_gpio_pull_updown val)
241{
242 u8 pos;
243 int ret;
244 struct pullud *pullud;
245
246 if (!pct->soc->pullud) {
247 dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
248 __func__);
249 ret = -EPERM;
250 goto out;
251 }
252
253 pullud = pct->soc->pullud;
254
255 if ((offset < pullud->first_pin)
256 || (offset > pullud->last_pin)) {
257 ret = -EINVAL;
258 goto out;
259 }
10a8be54 260 pos = (offset - pullud->first_pin) << 1;
0493e649
PC		 261
262 ret = abx500_mask_and_set_register_interruptible(pct->dev,
263 AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG,
264 AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos);
265
266out:
267 if (ret < 0)
268 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
83b423c8 269
0493e649
PC		 270 return ret;
271}
272
8b5abd18
PC		 273static bool abx500_pullud_supported(struct gpio_chip *chip, unsigned gpio)
274{
275 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
276 struct pullud *pullud = pct->soc->pullud;
277
278 return (pullud &&
279 gpio >= pullud->first_pin &&
280 gpio <= pullud->last_pin);
281}
282
0493e649
PC		 283static int abx500_gpio_direction_output(struct gpio_chip *chip,
284 unsigned offset,
285 int val)
286{
287 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
0493e649
PC		 288 unsigned gpio;
289 int ret;
83b423c8 290
0493e649 291 /* set direction as output */
acd260b0
PC		 292 ret = abx500_gpio_set_bits(chip,
293 AB8500_GPIO_DIR1_REG,
294 offset,
295 ABX500_GPIO_OUTPUT);
0493e649
PC		 296 if (ret < 0)
297 return ret;
298
299 /* disable pull down */
acd260b0
PC		 300 ret = abx500_gpio_set_bits(chip,
301 AB8500_GPIO_PUD1_REG,
302 offset,
303 ABX500_GPIO_PULL_NONE);
0493e649
PC		 304 if (ret < 0)
305 return ret;
306
307 /* if supported, disable both pull down and pull up */
308 gpio = offset + 1;
8b5abd18 309 if (abx500_pullud_supported(chip, gpio)) {
d2752ae5 310 ret = abx500_set_pull_updown(pct,
0493e649
PC		 311 gpio,
312 ABX500_GPIO_PULL_NONE);
313 if (ret < 0)
314 return ret;
315 }
83b423c8 316
0493e649
PC		 317 /* set the output as 1 or 0 */
318 return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
319}
320
321static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
322{
323 /* set the register as input */
acd260b0
PC		 324 return abx500_gpio_set_bits(chip,
325 AB8500_GPIO_DIR1_REG,
326 offset,
327 ABX500_GPIO_INPUT);
0493e649
PC		 328}
329
330static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
331{
332 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
b9fab6e4
LJ		 333 /* The AB8500 GPIO numbers are off by one */
334 int gpio = offset + 1;
a6a16d27 335 int hwirq;
0493e649
PC		 336 int i;
337
338 for (i = 0; i < pct->irq_cluster_size; i++) {
339 struct abx500_gpio_irq_cluster *cluster =
340 &pct->irq_cluster[i];
341
a6a16d27
LJ		 342 if (gpio >= cluster->start && gpio <= cluster->end) {
343 /*
344 * The ABx500 GPIO's associated IRQs are clustered together
345 * throughout the interrupt numbers at irregular intervals.
346 * To solve this quandry, we have placed the read-in values
347 * into the cluster information table.
348 */
43a255db 349 hwirq = gpio - cluster->start + cluster->to_irq;
a6a16d27
LJ		 350 return irq_create_mapping(pct->parent->domain, hwirq);
351 }
0493e649
PC		 352 }
353
354 return -EINVAL;
355}
356
357static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
83b423c8 358 unsigned gpio, int alt_setting)
0493e649
PC		 359{
360 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
361 struct alternate_functions af = pct->soc->alternate_functions[gpio];
362 int ret;
363 int val;
364 unsigned offset;
83b423c8 365
0493e649
PC		 366 const char *modes[] = {
367 [ABX500_DEFAULT] = "default",
368 [ABX500_ALT_A] = "altA",
369 [ABX500_ALT_B] = "altB",
370 [ABX500_ALT_C] = "altC",
371 };
372
373 /* sanity check */
374 if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) ||
375 ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) ||
376 ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) {
377 dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio,
378 modes[alt_setting]);
379 return -EINVAL;
380 }
381
382 /* on ABx5xx, there is no GPIO0, so adjust the offset */
383 offset = gpio - 1;
83b423c8 384
0493e649
PC		 385 switch (alt_setting) {
386 case ABX500_DEFAULT:
387 /*
388 * for ABx5xx family, default mode is always selected by
389 * writing 0 to GPIOSELx register, except for pins which
390 * support at least ALT_B mode, default mode is selected
391 * by writing 1 to GPIOSELx register
392 */
393 val = 0;
394 if (af.alt_bit1 != UNUSED)
395 val++;
396
397 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
398 offset, val);
399 break;
83b423c8 400
0493e649
PC		 401 case ABX500_ALT_A:
402 /*
403 * for ABx5xx family, alt_a mode is always selected by
404 * writing 1 to GPIOSELx register, except for pins which
405 * support at least ALT_B mode, alt_a mode is selected
406 * by writing 0 to GPIOSELx register and 0 in ALTFUNC
407 * register
408 */
409 if (af.alt_bit1 != UNUSED) {
410 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
411 offset, 0);
412 ret = abx500_gpio_set_bits(chip,
413 AB8500_GPIO_ALTFUN_REG,
414 af.alt_bit1,
415 !!(af.alta_val && BIT(0)));
416 if (af.alt_bit2 != UNUSED)
417 ret = abx500_gpio_set_bits(chip,
418 AB8500_GPIO_ALTFUN_REG,
419 af.alt_bit2,
420 !!(af.alta_val && BIT(1)));
421 } else
422 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
423 offset, 1);
424 break;
83b423c8 425
0493e649
PC		 426 case ABX500_ALT_B:
427 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
428 offset, 0);
429 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
430 af.alt_bit1, !!(af.altb_val && BIT(0)));
431 if (af.alt_bit2 != UNUSED)
432 ret = abx500_gpio_set_bits(chip,
433 AB8500_GPIO_ALTFUN_REG,
434 af.alt_bit2,
435 !!(af.altb_val && BIT(1)));
436 break;
83b423c8 437
0493e649
PC		 438 case ABX500_ALT_C:
439 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
440 offset, 0);
441 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
442 af.alt_bit2, !!(af.altc_val && BIT(0)));
443 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
444 af.alt_bit2, !!(af.altc_val && BIT(1)));
445 break;
446
447 default:
448 dev_dbg(pct->dev, "unknow alt_setting %d\n", alt_setting);
83b423c8 449
0493e649
PC		 450 return -EINVAL;
451 }
83b423c8 452
0493e649
PC		 453 return ret;
454}
455
456static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
83b423c8 457 unsigned gpio)
0493e649
PC		 458{
459 u8 mode;
460 bool bit_mode;
461 bool alt_bit1;
462 bool alt_bit2;
463 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
464 struct alternate_functions af = pct->soc->alternate_functions[gpio];
a950cb74
LW		 465 /* on ABx5xx, there is no GPIO0, so adjust the offset */
466 unsigned offset = gpio - 1;
0493e649
PC		 467
468 /*
469 * if gpiosel_bit is set to unused,
470 * it means no GPIO or special case
471 */
472 if (af.gpiosel_bit == UNUSED)
473 return ABX500_DEFAULT;
474
475 /* read GpioSelx register */
a950cb74 476 abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8),
0493e649
PC		 477 af.gpiosel_bit, &bit_mode);
478 mode = bit_mode;
479
480 /* sanity check */
481 if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) ||
482 (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) {
483 dev_err(pct->dev,
484 "alt_bitX value not in correct range (-1 to 7)\n");
485 return -EINVAL;
486 }
83b423c8 487
0493e649
PC		 488 /* if alt_bit2 is used, alt_bit1 must be used too */
489 if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) {
490 dev_err(pct->dev,
491 "if alt_bit2 is used, alt_bit1 can't be unused\n");
492 return -EINVAL;
493 }
494
495 /* check if pin use AlternateFunction register */
6a40cdd5 496 if ((af.alt_bit1 == UNUSED) && (af.alt_bit2 == UNUSED))
0493e649
PC		 497 return mode;
498 /*
499 * if pin GPIOSEL bit is set and pin supports alternate function,
500 * it means DEFAULT mode
501 */
502 if (mode)
503 return ABX500_DEFAULT;
83b423c8 504
0493e649
PC		 505 /*
506 * pin use the AlternatFunction register
507 * read alt_bit1 value
508 */
509 abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
510 af.alt_bit1, &alt_bit1);
511
512 if (af.alt_bit2 != UNUSED)
513 /* read alt_bit2 value */
514 abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit2,
515 &alt_bit2);
516 else
517 alt_bit2 = 0;
518
519 mode = (alt_bit2 << 1) + alt_bit1;
520 if (mode == af.alta_val)
521 return ABX500_ALT_A;
522 else if (mode == af.altb_val)
523 return ABX500_ALT_B;
524 else
525 return ABX500_ALT_C;
526}
527
528#ifdef CONFIG_DEBUG_FS
529
530#include <linux/seq_file.h>
531
532static void abx500_gpio_dbg_show_one(struct seq_file *s,
83b423c8
LJ		 533 struct pinctrl_dev *pctldev,
534 struct gpio_chip *chip,
535 unsigned offset, unsigned gpio)
0493e649 536{
d2752ae5 537 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
0493e649
PC		 538 const char *label = gpiochip_is_requested(chip, offset - 1);
539 u8 gpio_offset = offset - 1;
540 int mode = -1;
541 bool is_out;
d2752ae5 542 bool pd;
ce06f407 543 enum abx500_gpio_pull_updown pud = 0;
83b423c8 544
0493e649
PC		 545 const char *modes[] = {
546 [ABX500_DEFAULT] = "default",
547 [ABX500_ALT_A] = "altA",
548 [ABX500_ALT_B] = "altB",
549 [ABX500_ALT_C] = "altC",
550 };
551
d2752ae5
PC		 552 const char *pull_up_down[] = {
553 [ABX500_GPIO_PULL_DOWN] = "pull down",
554 [ABX500_GPIO_PULL_NONE] = "pull none",
555 [ABX500_GPIO_PULL_NONE + 1] = "pull none",
556 [ABX500_GPIO_PULL_UP] = "pull up",
557 };
558
0493e649 559 abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, gpio_offset, &is_out);
d2752ae5
PC		 560
561 seq_printf(s, " gpio-%-3d (%-20.20s) %-3s",
562 gpio, label ?: "(none)",
563 is_out ? "out" : "in ");
564
565 if (!is_out) {
8b5abd18 566 if (abx500_pullud_supported(chip, offset)) {
d2752ae5
PC		 567 abx500_get_pull_updown(pct, offset, &pud);
568 seq_printf(s, " %-9s", pull_up_down[pud]);
569 } else {
570 abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG,
571 gpio_offset, &pd);
572 seq_printf(s, " %-9s", pull_up_down[pd]);
573 }
574 } else
575 seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo");
0493e649
PC		 576
577 if (pctldev)
578 mode = abx500_get_mode(pctldev, chip, offset);
579
d2752ae5 580 seq_printf(s, " %s", (mode < 0) ? "unknown" : modes[mode]);
0493e649
PC		 581}
582
583static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
584{
585 unsigned i;
586 unsigned gpio = chip->base;
587 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
588 struct pinctrl_dev *pctldev = pct->pctldev;
589
590 for (i = 0; i < chip->ngpio; i++, gpio++) {
591 /* On AB8500, there is no GPIO0, the first is the GPIO 1 */
592 abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio);
593 seq_printf(s, "\n");
594 }
595}
596
597#else
598static inline void abx500_gpio_dbg_show_one(struct seq_file *s,
83b423c8
LJ		 599 struct pinctrl_dev *pctldev,
600 struct gpio_chip *chip,
601 unsigned offset, unsigned gpio)
0493e649
PC		 602{
603}
604#define abx500_gpio_dbg_show NULL
605#endif
606
9c4154ef 607static int abx500_gpio_request(struct gpio_chip *chip, unsigned offset)
0493e649
PC		 608{
609 int gpio = chip->base + offset;
610
611 return pinctrl_request_gpio(gpio);
612}
613
9c4154ef 614static void abx500_gpio_free(struct gpio_chip *chip, unsigned offset)
0493e649
PC		 615{
616 int gpio = chip->base + offset;
617
618 pinctrl_free_gpio(gpio);
619}
620
621static struct gpio_chip abx500gpio_chip = {
622 .label = "abx500-gpio",
623 .owner = THIS_MODULE,
624 .request = abx500_gpio_request,
625 .free = abx500_gpio_free,
626 .direction_input = abx500_gpio_direction_input,
627 .get = abx500_gpio_get,
628 .direction_output = abx500_gpio_direction_output,
629 .set = abx500_gpio_set,
630 .to_irq = abx500_gpio_to_irq,
631 .dbg_show = abx500_gpio_dbg_show,
632};
633
0493e649
PC		 634static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
635{
636 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
637
638 return pct->soc->nfunctions;
639}
640
641static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev,
642 unsigned function)
643{
644 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
645
646 return pct->soc->functions[function].name;
647}
648
649static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev,
83b423c8
LJ		 650 unsigned function,
651 const char * const **groups,
652 unsigned * const num_groups)
0493e649
PC		 653{
654 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
655
656 *groups = pct->soc->functions[function].groups;
657 *num_groups = pct->soc->functions[function].ngroups;
658
659 return 0;
660}
661
0493e649 662static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
83b423c8 663 unsigned group)
0493e649
PC		 664{
665 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
666 struct gpio_chip *chip = &pct->chip;
667 const struct abx500_pingroup *g;
668 int i;
669 int ret = 0;
670
671 g = &pct->soc->groups[group];
672 if (g->altsetting < 0)
673 return -EINVAL;
674
675 dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins);
676
677 for (i = 0; i < g->npins; i++) {
678 dev_dbg(pct->dev, "setting pin %d to altsetting %d\n",
679 g->pins[i], g->altsetting);
680
0493e649
PC		 681 ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting);
682 }
83b423c8 683
0493e649
PC		 684 return ret;
685}
686
687static void abx500_pmx_disable(struct pinctrl_dev *pctldev,
83b423c8 688 unsigned function, unsigned group)
0493e649
PC		 689{
690 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
691 const struct abx500_pingroup *g;
692
693 g = &pct->soc->groups[group];
694 if (g->altsetting < 0)
695 return;
696
697 /* FIXME: poke out the mux, set the pin to some default state? */
698 dev_dbg(pct->dev, "disable group %s, %u pins\n", g->name, g->npins);
699}
700
9c4154ef 701static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev,
83b423c8
LJ		 702 struct pinctrl_gpio_range *range,
703 unsigned offset)
0493e649
PC		 704{
705 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
706 const struct abx500_pinrange *p;
707 int ret;
708 int i;
709
710 /*
711 * Different ranges have different ways to enable GPIO function on a
712 * pin, so refer back to our local range type, where we handily define
713 * what altfunc enables GPIO for a certain pin.
714 */
715 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
716 p = &pct->soc->gpio_ranges[i];
717 if ((offset >= p->offset) &&
718 (offset < (p->offset + p->npins)))
719 break;
720 }
721
722 if (i == pct->soc->gpio_num_ranges) {
723 dev_err(pct->dev, "%s failed to locate range\n", __func__);
724 return -ENODEV;
725 }
726
727 dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n",
728 p->altfunc, offset);
729
730 ret = abx500_set_mode(pct->pctldev, &pct->chip,
731 offset, p->altfunc);
732 if (ret < 0) {
733 dev_err(pct->dev, "%s setting altfunc failed\n", __func__);
734 return ret;
735 }
736
737 return ret;
738}
739
740static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev,
83b423c8
LJ		 741 struct pinctrl_gpio_range *range,
742 unsigned offset)
0493e649
PC		 743{
744}
745
022ab148 746static const struct pinmux_ops abx500_pinmux_ops = {
0493e649
PC		 747 .get_functions_count = abx500_pmx_get_funcs_cnt,
748 .get_function_name = abx500_pmx_get_func_name,
749 .get_function_groups = abx500_pmx_get_func_groups,
750 .enable = abx500_pmx_enable,
751 .disable = abx500_pmx_disable,
752 .gpio_request_enable = abx500_gpio_request_enable,
753 .gpio_disable_free = abx500_gpio_disable_free,
754};
755
756static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev)
757{
758 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
759
760 return pct->soc->ngroups;
761}
762
763static const char *abx500_get_group_name(struct pinctrl_dev *pctldev,
83b423c8 764 unsigned selector)
0493e649
PC		 765{
766 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
767
768 return pct->soc->groups[selector].name;
769}
770
771static int abx500_get_group_pins(struct pinctrl_dev *pctldev,
83b423c8
LJ		 772 unsigned selector,
773 const unsigned **pins,
774 unsigned *num_pins)
0493e649
PC		 775{
776 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
777
778 *pins = pct->soc->groups[selector].pins;
779 *num_pins = pct->soc->groups[selector].npins;
83b423c8 780
0493e649
PC		 781 return 0;
782}
783
784static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
83b423c8 785 struct seq_file *s, unsigned offset)
0493e649
PC		 786{
787 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
788 struct gpio_chip *chip = &pct->chip;
789
790 abx500_gpio_dbg_show_one(s, pctldev, chip, offset,
791 chip->base + offset - 1);
792}
793
64a45c98
PC		 794static void abx500_dt_free_map(struct pinctrl_dev *pctldev,
795 struct pinctrl_map *map, unsigned num_maps)
796{
797 int i;
798
799 for (i = 0; i < num_maps; i++)
800 if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
801 kfree(map[i].data.configs.configs);
802 kfree(map);
803}
804
805static int abx500_dt_reserve_map(struct pinctrl_map **map,
806 unsigned *reserved_maps,
807 unsigned *num_maps,
808 unsigned reserve)
809{
810 unsigned old_num = *reserved_maps;
811 unsigned new_num = *num_maps + reserve;
812 struct pinctrl_map *new_map;
813
814 if (old_num >= new_num)
815 return 0;
816
817 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
818 if (!new_map)
819 return -ENOMEM;
820
821 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
822
823 *map = new_map;
824 *reserved_maps = new_num;
825
826 return 0;
827}
828
829static int abx500_dt_add_map_mux(struct pinctrl_map **map,
830 unsigned *reserved_maps,
831 unsigned *num_maps, const char *group,
832 const char *function)
833{
834 if (*num_maps == *reserved_maps)
835 return -ENOSPC;
836
837 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
838 (*map)[*num_maps].data.mux.group = group;
839 (*map)[*num_maps].data.mux.function = function;
840 (*num_maps)++;
841
842 return 0;
843}
844
845static int abx500_dt_add_map_configs(struct pinctrl_map **map,
846 unsigned *reserved_maps,
847 unsigned *num_maps, const char *group,
848 unsigned long *configs, unsigned num_configs)
849{
850 unsigned long *dup_configs;
851
852 if (*num_maps == *reserved_maps)
853 return -ENOSPC;
854
855 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
856 GFP_KERNEL);
857 if (!dup_configs)
858 return -ENOMEM;
859
860 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
861
862 (*map)[*num_maps].data.configs.group_or_pin = group;
863 (*map)[*num_maps].data.configs.configs = dup_configs;
864 (*map)[*num_maps].data.configs.num_configs = num_configs;
865 (*num_maps)++;
866
867 return 0;
868}
869
870static const char *abx500_find_pin_name(struct pinctrl_dev *pctldev,
871 const char *pin_name)
872{
873 int i, pin_number;
874 struct abx500_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
875
876 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
877 for (i = 0; i < npct->soc->npins; i++)
878 if (npct->soc->pins[i].number == pin_number)
879 return npct->soc->pins[i].name;
880 return NULL;
881}
882
883static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
884 struct device_node *np,
885 struct pinctrl_map **map,
886 unsigned *reserved_maps,
887 unsigned *num_maps)
888{
889 int ret;
890 const char *function = NULL;
891 unsigned long *configs;
892 unsigned int nconfigs = 0;
893 bool has_config = 0;
894 unsigned reserve = 0;
895 struct property *prop;
896 const char *group, *gpio_name;
897 struct device_node *np_config;
898
899 ret = of_property_read_string(np, "ste,function", &function);
900 if (ret >= 0)
901 reserve = 1;
902
903 ret = pinconf_generic_parse_dt_config(np, &configs, &nconfigs);
904 if (nconfigs)
905 has_config = 1;
906
907 np_config = of_parse_phandle(np, "ste,config", 0);
908 if (np_config) {
909 ret = pinconf_generic_parse_dt_config(np_config, &configs,
910 &nconfigs);
911 if (ret)
912 goto exit;
913 has_config |= nconfigs;
914 }
915
916 ret = of_property_count_strings(np, "ste,pins");
917 if (ret < 0)
918 goto exit;
919
920 if (has_config)
921 reserve++;
922
923 reserve *= ret;
924
925 ret = abx500_dt_reserve_map(map, reserved_maps, num_maps, reserve);
926 if (ret < 0)
927 goto exit;
928
929 of_property_for_each_string(np, "ste,pins", prop, group) {
930 if (function) {
931 ret = abx500_dt_add_map_mux(map, reserved_maps,
932 num_maps, group, function);
933 if (ret < 0)
934 goto exit;
935 }
936 if (has_config) {
937 gpio_name = abx500_find_pin_name(pctldev, group);
938
939 ret = abx500_dt_add_map_configs(map, reserved_maps,
940 num_maps, gpio_name, configs, 1);
941 if (ret < 0)
942 goto exit;
943 }
944
945 }
946exit:
947 return ret;
948}
949
950static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev,
951 struct device_node *np_config,
952 struct pinctrl_map **map, unsigned *num_maps)
953{
954 unsigned reserved_maps;
955 struct device_node *np;
956 int ret;
957
958 reserved_maps = 0;
959 *map = NULL;
960 *num_maps = 0;
961
962 for_each_child_of_node(np_config, np) {
963 ret = abx500_dt_subnode_to_map(pctldev, np, map,
964 &reserved_maps, num_maps);
965 if (ret < 0) {
966 abx500_dt_free_map(pctldev, *map, *num_maps);
967 return ret;
968 }
969 }
970
971 return 0;
972}
973
022ab148 974static const struct pinctrl_ops abx500_pinctrl_ops = {
0493e649
PC		 975 .get_groups_count = abx500_get_groups_cnt,
976 .get_group_name = abx500_get_group_name,
977 .get_group_pins = abx500_get_group_pins,
978 .pin_dbg_show = abx500_pin_dbg_show,
64a45c98
PC		 979 .dt_node_to_map = abx500_dt_node_to_map,
980 .dt_free_map = abx500_dt_free_map,
0493e649
PC		 981};
982
9c4154ef 983static int abx500_pin_config_get(struct pinctrl_dev *pctldev,
83b423c8
LJ		 984 unsigned pin,
985 unsigned long *config)
0493e649 986{
1abeebea 987 return -ENOSYS;
0493e649
PC		 988}
989
9c4154ef 990static int abx500_pin_config_set(struct pinctrl_dev *pctldev,
83b423c8
LJ		 991 unsigned pin,
992 unsigned long config)
0493e649
PC		 993{
994 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
0493e649
PC		 995 struct gpio_chip *chip = &pct->chip;
996 unsigned offset;
61ce1356 997 int ret = -EINVAL;
0493e649
PC		 998 enum pin_config_param param = pinconf_to_config_param(config);
999 enum pin_config_param argument = pinconf_to_config_argument(config);
1000
1001 dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n",
1002 pin, config, (param == PIN_CONFIG_OUTPUT) ? "output " : "input",
1003 (param == PIN_CONFIG_OUTPUT) ? (argument ? "high" : "low") :
1004 (argument ? "pull up" : "pull down"));
83b423c8 1005
0493e649
PC		 1006 /* on ABx500, there is no GPIO0, so adjust the offset */
1007 offset = pin - 1;
1008
1009 switch (param) {
61ce1356
PC		 1010 case PIN_CONFIG_BIAS_DISABLE:
1011 ret = abx500_gpio_direction_input(chip, offset);
0493e649 1012 /*
61ce1356
PC		 1013 * Some chips only support pull down, while some actually
1014 * support both pull up and pull down. Such chips have
1015 * a "pullud" range specified for the pins that support
1016 * both features. If the pin is not within that range, we
1017 * fall back to the old bit set that only support pull down.
0493e649 1018 */
8b5abd18 1019 if (abx500_pullud_supported(chip, pin))
61ce1356
PC		 1020 ret = abx500_set_pull_updown(pct,
1021 pin,
1022 ABX500_GPIO_PULL_NONE);
1023 else
1024 /* Chip only supports pull down */
1025 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG,
1026 offset, ABX500_GPIO_PULL_NONE);
1027 break;
1028
1029 case PIN_CONFIG_BIAS_PULL_DOWN:
0493e649
PC		 1030 ret = abx500_gpio_direction_input(chip, offset);
1031 /*
61ce1356
PC		 1032 * if argument = 1 set the pull down
1033 * else clear the pull down
0493e649
PC		 1034 * Some chips only support pull down, while some actually
1035 * support both pull up and pull down. Such chips have
1036 * a "pullud" range specified for the pins that support
1037 * both features. If the pin is not within that range, we
1038 * fall back to the old bit set that only support pull down.
1039 */
8b5abd18 1040 if (abx500_pullud_supported(chip, pin))
d2752ae5 1041 ret = abx500_set_pull_updown(pct,
0493e649
PC		 1042 pin,
1043 argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE);
1044 else
1045 /* Chip only supports pull down */
1046 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG,
acd260b0
PC		 1047 offset,
1048 argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE);
0493e649 1049 break;
83b423c8 1050
9ed3cd33 1051 case PIN_CONFIG_BIAS_PULL_UP:
61ce1356 1052 ret = abx500_gpio_direction_input(chip, offset);
9ed3cd33
PC		 1053 /*
1054 * if argument = 1 set the pull up
1055 * else clear the pull up
1056 */
1057 ret = abx500_gpio_direction_input(chip, offset);
1058 /*
1059 * Some chips only support pull down, while some actually
1060 * support both pull up and pull down. Such chips have
1061 * a "pullud" range specified for the pins that support
1062 * both features. If the pin is not within that range, do
1063 * nothing
1064 */
8b5abd18 1065 if (abx500_pullud_supported(chip, pin))
d2752ae5 1066 ret = abx500_set_pull_updown(pct,
9ed3cd33
PC		 1067 pin,
1068 argument ? ABX500_GPIO_PULL_UP : ABX500_GPIO_PULL_NONE);
9ed3cd33
PC		 1069 break;
1070
0493e649
PC		 1071 case PIN_CONFIG_OUTPUT:
1072 ret = abx500_gpio_direction_output(chip, offset, argument);
83b423c8 1073
0493e649 1074 break;
83b423c8 1075
0493e649
PC		 1076 default:
1077 dev_err(chip->dev, "illegal configuration requested\n");
0493e649 1078 }
83b423c8 1079
0493e649
PC		 1080 return ret;
1081}
1082
022ab148 1083static const struct pinconf_ops abx500_pinconf_ops = {
0493e649
PC		 1084 .pin_config_get = abx500_pin_config_get,
1085 .pin_config_set = abx500_pin_config_set,
1086};
1087
1088static struct pinctrl_desc abx500_pinctrl_desc = {
1089 .name = "pinctrl-abx500",
1090 .pctlops = &abx500_pinctrl_ops,
1091 .pmxops = &abx500_pinmux_ops,
1092 .confops = &abx500_pinconf_ops,
1093 .owner = THIS_MODULE,
1094};
1095
1096static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc)
1097{
1098 unsigned int lowest = 0;
1099 unsigned int highest = 0;
1100 unsigned int npins = 0;
1101 int i;
1102
1103 /*
1104 * Compute number of GPIOs from the last SoC gpio range descriptors
1105 * These ranges may include "holes" but the GPIO number space shall
1106 * still be homogeneous, so we need to detect and account for any
1107 * such holes so that these are included in the number of GPIO pins.
1108 */
1109 for (i = 0; i < soc->gpio_num_ranges; i++) {
1110 unsigned gstart;
1111 unsigned gend;
1112 const struct abx500_pinrange *p;
1113
1114 p = &soc->gpio_ranges[i];
1115 gstart = p->offset;
1116 gend = p->offset + p->npins - 1;
1117
1118 if (i == 0) {
1119 /* First iteration, set start values */
1120 lowest = gstart;
1121 highest = gend;
1122 } else {
1123 if (gstart < lowest)
1124 lowest = gstart;
1125 if (gend > highest)
1126 highest = gend;
1127 }
1128 }
1129 /* this gives the absolute number of pins */
1130 npins = highest - lowest + 1;
1131 return npins;
1132}
1133
f30a3839
LJ		 1134static const struct of_device_id abx500_gpio_match[] = {
1135 { .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, },
1136 { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, },
1137 { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, },
1138 { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, },
e3929714 1139 { }
f30a3839
LJ		 1140};
1141
0493e649
PC		 1142static int abx500_gpio_probe(struct platform_device *pdev)
1143{
1144 struct ab8500_platform_data *abx500_pdata =
1145 dev_get_platdata(pdev->dev.parent);
f30a3839
LJ		 1146 struct abx500_gpio_platform_data *pdata = NULL;
1147 struct device_node *np = pdev->dev.of_node;
0493e649
PC		 1148 struct abx500_pinctrl *pct;
1149 const struct platform_device_id *platid = platform_get_device_id(pdev);
f30a3839 1150 unsigned int id = -1;
fa1ec996 1151 int ret, err;
0493e649
PC		 1152 int i;
1153
f30a3839
LJ		 1154 if (abx500_pdata)
1155 pdata = abx500_pdata->gpio;
f30a3839 1156
86c976e4
LJ		 1157 if (!(pdata || np)) {
1158 dev_err(&pdev->dev, "gpio dt and platform data missing\n");
1159 return -ENODEV;
0493e649
PC		 1160 }
1161
1162 pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl),
1163 GFP_KERNEL);
1164 if (pct == NULL) {
1165 dev_err(&pdev->dev,
1166 "failed to allocate memory for pct\n");
1167 return -ENOMEM;
1168 }
1169
1170 pct->dev = &pdev->dev;
1171 pct->parent = dev_get_drvdata(pdev->dev.parent);
1172 pct->chip = abx500gpio_chip;
1173 pct->chip.dev = &pdev->dev;
f30a3839 1174 pct->chip.base = (np) ? -1 : pdata->gpio_base;
0493e649 1175
86c976e4
LJ		 1176 if (platid)
1177 id = platid->driver_data;
1178 else if (np) {
1179 const struct of_device_id *match;
1180
1181 match = of_match_device(abx500_gpio_match, &pdev->dev);
1182 if (match)
1183 id = (unsigned long)match->data;
1184 }
1185
0493e649 1186 /* Poke in other ASIC variants here */
f30a3839 1187 switch (id) {
3c937993
PC		 1188 case PINCTRL_AB8500:
1189 abx500_pinctrl_ab8500_init(&pct->soc);
1190 break;
a8f96e41
PC		 1191 case PINCTRL_AB8540:
1192 abx500_pinctrl_ab8540_init(&pct->soc);
1193 break;
09dbec3f
PC		 1194 case PINCTRL_AB9540:
1195 abx500_pinctrl_ab9540_init(&pct->soc);
1196 break;
1aa2d8d4
PC		 1197 case PINCTRL_AB8505:
1198 abx500_pinctrl_ab8505_init(&pct->soc);
1199 break;
0493e649 1200 default:
2fcad12e 1201 dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id);
0493e649
PC		 1202 return -EINVAL;
1203 }
1204
1205 if (!pct->soc) {
1206 dev_err(&pdev->dev, "Invalid SOC data\n");
1207 return -EINVAL;
1208 }
1209
1210 pct->chip.ngpio = abx500_get_gpio_num(pct->soc);
1211 pct->irq_cluster = pct->soc->gpio_irq_cluster;
1212 pct->irq_cluster_size = pct->soc->ngpio_irq_cluster;
0493e649 1213
0493e649
PC		 1214 ret = gpiochip_add(&pct->chip);
1215 if (ret) {
83b423c8 1216 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
ac652d79 1217 return ret;
0493e649
PC		 1218 }
1219 dev_info(&pdev->dev, "added gpiochip\n");
1220
1221 abx500_pinctrl_desc.pins = pct->soc->pins;
1222 abx500_pinctrl_desc.npins = pct->soc->npins;
1223 pct->pctldev = pinctrl_register(&abx500_pinctrl_desc, &pdev->dev, pct);
1224 if (!pct->pctldev) {
1225 dev_err(&pdev->dev,
1226 "could not register abx500 pinctrl driver\n");
fa1ec996 1227 ret = -EINVAL;
0493e649
PC		 1228 goto out_rem_chip;
1229 }
1230 dev_info(&pdev->dev, "registered pin controller\n");
1231
1232 /* We will handle a range of GPIO pins */
1233 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
1234 const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i];
1235
1236 ret = gpiochip_add_pin_range(&pct->chip,
1237 dev_name(&pdev->dev),
1238 p->offset - 1, p->offset, p->npins);
1239 if (ret < 0)
fa1ec996 1240 goto out_rem_chip;
0493e649
PC		 1241 }
1242
1243 platform_set_drvdata(pdev, pct);
1244 dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n");
1245
1246 return 0;
1247
1248out_rem_chip:
fa1ec996
LJ		 1249 err = gpiochip_remove(&pct->chip);
1250 if (err)
0493e649 1251 dev_info(&pdev->dev, "failed to remove gpiochip\n");
ac652d79 1252
0493e649
PC		 1253 return ret;
1254}
1255
83b423c8 1256/**
0493e649 1257 * abx500_gpio_remove() - remove Ab8500-gpio driver
83b423c8 1258 * @pdev: Platform device registered
0493e649
PC		 1259 */
1260static int abx500_gpio_remove(struct platform_device *pdev)
1261{
1262 struct abx500_pinctrl *pct = platform_get_drvdata(pdev);
1263 int ret;
1264
1265 ret = gpiochip_remove(&pct->chip);
1266 if (ret < 0) {
1267 dev_err(pct->dev, "unable to remove gpiochip: %d\n",
1268 ret);
1269 return ret;
1270 }
1271
0493e649
PC		 1272 return 0;
1273}
1274
1275static const struct platform_device_id abx500_pinctrl_id[] = {
1276 { "pinctrl-ab8500", PINCTRL_AB8500 },
1277 { "pinctrl-ab8540", PINCTRL_AB8540 },
1278 { "pinctrl-ab9540", PINCTRL_AB9540 },
1279 { "pinctrl-ab8505", PINCTRL_AB8505 },
1280 { },
1281};
1282
1283static struct platform_driver abx500_gpio_driver = {
1284 .driver = {
1285 .name = "abx500-gpio",
1286 .owner = THIS_MODULE,
f30a3839 1287 .of_match_table = abx500_gpio_match,
0493e649
PC		 1288 },
1289 .probe = abx500_gpio_probe,
1290 .remove = abx500_gpio_remove,
1291 .id_table = abx500_pinctrl_id,
1292};
1293
1294static int __init abx500_gpio_init(void)
1295{
1296 return platform_driver_register(&abx500_gpio_driver);
1297}
1298core_initcall(abx500_gpio_init);
1299
1300MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>");
1301MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO");
1302MODULE_ALIAS("platform:abx500-gpio");
1303MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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