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pinctrl/lantiq: fix pin number in ltq_pmx_gpio_request_enable
[deliverable/linux.git] / drivers / pinctrl / pinctrl-abx500.c
CommitLineData
0493e649
PC		 1/*
2 * Copyright (C) ST-Ericsson SA 2013
3 *
4 * Author: Patrice Chotard <patrice.chotard@st.com>
5 * License terms: GNU General Public License (GPL) version 2
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/slab.h>
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/gpio.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
21#include <linux/bitops.h>
22#include <linux/mfd/abx500.h>
23#include <linux/mfd/abx500/ab8500.h>
24#include <linux/mfd/abx500/ab8500-gpio.h>
25#include <linux/pinctrl/pinctrl.h>
26#include <linux/pinctrl/consumer.h>
27#include <linux/pinctrl/pinmux.h>
28#include <linux/pinctrl/pinconf.h>
29#include <linux/pinctrl/pinconf-generic.h>
30
31#include "pinctrl-abx500.h"
32
33/*
34 * The AB9540 and AB8540 GPIO support are extended versions
35 * of the AB8500 GPIO support.
36 * The AB9540 supports an additional (7th) register so that
37 * more GPIO may be configured and used.
38 * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have
39 * internal pull-up and pull-down capabilities.
40 */
41
42/*
43 * GPIO registers offset
44 * Bank: 0x10
45 */
46#define AB8500_GPIO_SEL1_REG 0x00
47#define AB8500_GPIO_SEL2_REG 0x01
48#define AB8500_GPIO_SEL3_REG 0x02
49#define AB8500_GPIO_SEL4_REG 0x03
50#define AB8500_GPIO_SEL5_REG 0x04
51#define AB8500_GPIO_SEL6_REG 0x05
52#define AB9540_GPIO_SEL7_REG 0x06
53
54#define AB8500_GPIO_DIR1_REG 0x10
55#define AB8500_GPIO_DIR2_REG 0x11
56#define AB8500_GPIO_DIR3_REG 0x12
57#define AB8500_GPIO_DIR4_REG 0x13
58#define AB8500_GPIO_DIR5_REG 0x14
59#define AB8500_GPIO_DIR6_REG 0x15
60#define AB9540_GPIO_DIR7_REG 0x16
61
62#define AB8500_GPIO_OUT1_REG 0x20
63#define AB8500_GPIO_OUT2_REG 0x21
64#define AB8500_GPIO_OUT3_REG 0x22
65#define AB8500_GPIO_OUT4_REG 0x23
66#define AB8500_GPIO_OUT5_REG 0x24
67#define AB8500_GPIO_OUT6_REG 0x25
68#define AB9540_GPIO_OUT7_REG 0x26
69
70#define AB8500_GPIO_PUD1_REG 0x30
71#define AB8500_GPIO_PUD2_REG 0x31
72#define AB8500_GPIO_PUD3_REG 0x32
73#define AB8500_GPIO_PUD4_REG 0x33
74#define AB8500_GPIO_PUD5_REG 0x34
75#define AB8500_GPIO_PUD6_REG 0x35
76#define AB9540_GPIO_PUD7_REG 0x36
77
78#define AB8500_GPIO_IN1_REG 0x40
79#define AB8500_GPIO_IN2_REG 0x41
80#define AB8500_GPIO_IN3_REG 0x42
81#define AB8500_GPIO_IN4_REG 0x43
82#define AB8500_GPIO_IN5_REG 0x44
83#define AB8500_GPIO_IN6_REG 0x45
84#define AB9540_GPIO_IN7_REG 0x46
85#define AB8540_GPIO_VINSEL_REG 0x47
86#define AB8540_GPIO_PULL_UPDOWN_REG 0x48
87#define AB8500_GPIO_ALTFUN_REG 0x50
88#define AB8500_NUM_VIR_GPIO_IRQ 16
89#define AB8540_GPIO_PULL_UPDOWN_MASK 0x03
90#define AB8540_GPIO_VINSEL_MASK 0x03
91#define AB8540_GPIOX_VBAT_START 51
92#define AB8540_GPIOX_VBAT_END 54
93
94enum abx500_gpio_action {
95 NONE,
96 STARTUP,
97 SHUTDOWN,
98 MASK,
99 UNMASK
100};
101
102struct abx500_pinctrl {
103 struct device *dev;
104 struct pinctrl_dev *pctldev;
105 struct abx500_pinctrl_soc_data *soc;
106 struct gpio_chip chip;
107 struct ab8500 *parent;
108 struct mutex lock;
109 u32 irq_base;
110 enum abx500_gpio_action irq_action;
111 u16 rising;
112 u16 falling;
113 struct abx500_gpio_irq_cluster *irq_cluster;
114 int irq_cluster_size;
115 int irq_gpio_rising_offset;
116 int irq_gpio_falling_offset;
117 int irq_gpio_factor;
118};
119
120/**
121 * to_abx500_pinctrl() - get the pointer to abx500_pinctrl
122 * @chip: Member of the structure abx500_pinctrl
123 */
124static inline struct abx500_pinctrl *to_abx500_pinctrl(struct gpio_chip *chip)
125{
126 return container_of(chip, struct abx500_pinctrl, chip);
127}
128
129static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg,
83b423c8 130 unsigned offset, bool *bit)
0493e649
PC		 131{
132 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
133 u8 pos = offset % 8;
134 u8 val;
135 int ret;
136
137 reg += offset / 8;
138 ret = abx500_get_register_interruptible(pct->dev,
139 AB8500_MISC, reg, &val);
140
141 *bit = !!(val & BIT(pos));
142
143 if (ret < 0)
144 dev_err(pct->dev,
145 "%s read reg =%x, offset=%x failed\n",
146 __func__, reg, offset);
147
148 return ret;
149}
150
151static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
83b423c8 152 unsigned offset, int val)
0493e649
PC		 153{
154 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
155 u8 pos = offset % 8;
156 int ret;
157
158 reg += offset / 8;
159 ret = abx500_mask_and_set_register_interruptible(pct->dev,
49dcf086 160 AB8500_MISC, reg, BIT(pos), val << pos);
0493e649
PC		 161 if (ret < 0)
162 dev_err(pct->dev, "%s write failed\n", __func__);
83b423c8 163
0493e649
PC		 164 return ret;
165}
83b423c8 166
0493e649
PC		 167/**
168 * abx500_gpio_get() - Get the particular GPIO value
83b423c8
LJ		 169 * @chip: Gpio device
170 * @offset: GPIO number to read
0493e649
PC		 171 */
172static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset)
173{
174 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
175 bool bit;
176 int ret;
177
178 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG,
179 offset, &bit);
180 if (ret < 0) {
181 dev_err(pct->dev, "%s failed\n", __func__);
182 return ret;
183 }
83b423c8 184
0493e649
PC		 185 return bit;
186}
187
188static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
189{
190 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
191 int ret;
192
193 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
194 if (ret < 0)
195 dev_err(pct->dev, "%s write failed\n", __func__);
196}
197
198static int abx500_config_pull_updown(struct abx500_pinctrl *pct,
83b423c8 199 int offset, enum abx500_gpio_pull_updown val)
0493e649
PC		 200{
201 u8 pos;
202 int ret;
203 struct pullud *pullud;
204
205 if (!pct->soc->pullud) {
206 dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
207 __func__);
208 ret = -EPERM;
209 goto out;
210 }
211
212 pullud = pct->soc->pullud;
213
214 if ((offset < pullud->first_pin)
215 || (offset > pullud->last_pin)) {
216 ret = -EINVAL;
217 goto out;
218 }
219
220 pos = offset << 1;
221
222 ret = abx500_mask_and_set_register_interruptible(pct->dev,
223 AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG,
224 AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos);
225
226out:
227 if (ret < 0)
228 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
83b423c8 229
0493e649
PC		 230 return ret;
231}
232
233static int abx500_gpio_direction_output(struct gpio_chip *chip,
234 unsigned offset,
235 int val)
236{
237 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
238 struct pullud *pullud = pct->soc->pullud;
239 unsigned gpio;
240 int ret;
83b423c8 241
0493e649
PC		 242 /* set direction as output */
243 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 1);
244 if (ret < 0)
245 return ret;
246
247 /* disable pull down */
248 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, offset, 1);
249 if (ret < 0)
250 return ret;
251
252 /* if supported, disable both pull down and pull up */
253 gpio = offset + 1;
254 if (pullud && gpio >= pullud->first_pin && gpio <= pullud->last_pin) {
255 ret = abx500_config_pull_updown(pct,
256 gpio,
257 ABX500_GPIO_PULL_NONE);
258 if (ret < 0)
259 return ret;
260 }
83b423c8 261
0493e649
PC		 262 /* set the output as 1 or 0 */
263 return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
264}
265
266static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
267{
268 /* set the register as input */
269 return abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 0);
270}
271
272static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
273{
274 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
275 int base = pct->irq_base;
276 int i;
277
278 for (i = 0; i < pct->irq_cluster_size; i++) {
279 struct abx500_gpio_irq_cluster *cluster =
280 &pct->irq_cluster[i];
281
282 if (offset >= cluster->start && offset <= cluster->end)
283 return base + offset - cluster->start;
284
285 /* Advance by the number of gpios in this cluster */
286 base += cluster->end + cluster->offset - cluster->start + 1;
287 }
288
289 return -EINVAL;
290}
291
292static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
83b423c8 293 unsigned gpio, int alt_setting)
0493e649
PC		 294{
295 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
296 struct alternate_functions af = pct->soc->alternate_functions[gpio];
297 int ret;
298 int val;
299 unsigned offset;
83b423c8 300
0493e649
PC		 301 const char *modes[] = {
302 [ABX500_DEFAULT] = "default",
303 [ABX500_ALT_A] = "altA",
304 [ABX500_ALT_B] = "altB",
305 [ABX500_ALT_C] = "altC",
306 };
307
308 /* sanity check */
309 if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) ||
310 ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) ||
311 ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) {
312 dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio,
313 modes[alt_setting]);
314 return -EINVAL;
315 }
316
317 /* on ABx5xx, there is no GPIO0, so adjust the offset */
318 offset = gpio - 1;
83b423c8 319
0493e649
PC		 320 switch (alt_setting) {
321 case ABX500_DEFAULT:
322 /*
323 * for ABx5xx family, default mode is always selected by
324 * writing 0 to GPIOSELx register, except for pins which
325 * support at least ALT_B mode, default mode is selected
326 * by writing 1 to GPIOSELx register
327 */
328 val = 0;
329 if (af.alt_bit1 != UNUSED)
330 val++;
331
332 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
333 offset, val);
334 break;
83b423c8 335
0493e649
PC		 336 case ABX500_ALT_A:
337 /*
338 * for ABx5xx family, alt_a mode is always selected by
339 * writing 1 to GPIOSELx register, except for pins which
340 * support at least ALT_B mode, alt_a mode is selected
341 * by writing 0 to GPIOSELx register and 0 in ALTFUNC
342 * register
343 */
344 if (af.alt_bit1 != UNUSED) {
345 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
346 offset, 0);
347 ret = abx500_gpio_set_bits(chip,
348 AB8500_GPIO_ALTFUN_REG,
349 af.alt_bit1,
350 !!(af.alta_val && BIT(0)));
351 if (af.alt_bit2 != UNUSED)
352 ret = abx500_gpio_set_bits(chip,
353 AB8500_GPIO_ALTFUN_REG,
354 af.alt_bit2,
355 !!(af.alta_val && BIT(1)));
356 } else
357 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
358 offset, 1);
359 break;
83b423c8 360
0493e649
PC		 361 case ABX500_ALT_B:
362 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
363 offset, 0);
364 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
365 af.alt_bit1, !!(af.altb_val && BIT(0)));
366 if (af.alt_bit2 != UNUSED)
367 ret = abx500_gpio_set_bits(chip,
368 AB8500_GPIO_ALTFUN_REG,
369 af.alt_bit2,
370 !!(af.altb_val && BIT(1)));
371 break;
83b423c8 372
0493e649
PC		 373 case ABX500_ALT_C:
374 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
375 offset, 0);
376 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
377 af.alt_bit2, !!(af.altc_val && BIT(0)));
378 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
379 af.alt_bit2, !!(af.altc_val && BIT(1)));
380 break;
381
382 default:
383 dev_dbg(pct->dev, "unknow alt_setting %d\n", alt_setting);
83b423c8 384
0493e649
PC		 385 return -EINVAL;
386 }
83b423c8 387
0493e649
PC		 388 return ret;
389}
390
391static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
83b423c8 392 unsigned gpio)
0493e649
PC		 393{
394 u8 mode;
395 bool bit_mode;
396 bool alt_bit1;
397 bool alt_bit2;
398 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
399 struct alternate_functions af = pct->soc->alternate_functions[gpio];
400
401 /*
402 * if gpiosel_bit is set to unused,
403 * it means no GPIO or special case
404 */
405 if (af.gpiosel_bit == UNUSED)
406 return ABX500_DEFAULT;
407
408 /* read GpioSelx register */
409 abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (gpio / 8),
410 af.gpiosel_bit, &bit_mode);
411 mode = bit_mode;
412
413 /* sanity check */
414 if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) ||
415 (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) {
416 dev_err(pct->dev,
417 "alt_bitX value not in correct range (-1 to 7)\n");
418 return -EINVAL;
419 }
83b423c8 420
0493e649
PC		 421 /* if alt_bit2 is used, alt_bit1 must be used too */
422 if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) {
423 dev_err(pct->dev,
424 "if alt_bit2 is used, alt_bit1 can't be unused\n");
425 return -EINVAL;
426 }
427
428 /* check if pin use AlternateFunction register */
429 if ((af.alt_bit1 == UNUSED) && (af.alt_bit1 == UNUSED))
430 return mode;
431 /*
432 * if pin GPIOSEL bit is set and pin supports alternate function,
433 * it means DEFAULT mode
434 */
435 if (mode)
436 return ABX500_DEFAULT;
83b423c8 437
0493e649
PC		 438 /*
439 * pin use the AlternatFunction register
440 * read alt_bit1 value
441 */
442 abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
443 af.alt_bit1, &alt_bit1);
444
445 if (af.alt_bit2 != UNUSED)
446 /* read alt_bit2 value */
447 abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit2,
448 &alt_bit2);
449 else
450 alt_bit2 = 0;
451
452 mode = (alt_bit2 << 1) + alt_bit1;
453 if (mode == af.alta_val)
454 return ABX500_ALT_A;
455 else if (mode == af.altb_val)
456 return ABX500_ALT_B;
457 else
458 return ABX500_ALT_C;
459}
460
461#ifdef CONFIG_DEBUG_FS
462
463#include <linux/seq_file.h>
464
465static void abx500_gpio_dbg_show_one(struct seq_file *s,
83b423c8
LJ		 466 struct pinctrl_dev *pctldev,
467 struct gpio_chip *chip,
468 unsigned offset, unsigned gpio)
0493e649
PC		 469{
470 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
471 const char *label = gpiochip_is_requested(chip, offset - 1);
472 u8 gpio_offset = offset - 1;
473 int mode = -1;
474 bool is_out;
475 bool pull;
83b423c8 476
0493e649
PC		 477 const char *modes[] = {
478 [ABX500_DEFAULT] = "default",
479 [ABX500_ALT_A] = "altA",
480 [ABX500_ALT_B] = "altB",
481 [ABX500_ALT_C] = "altC",
482 };
483
484 abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, gpio_offset, &is_out);
485 abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, gpio_offset, &pull);
486
487 if (pctldev)
488 mode = abx500_get_mode(pctldev, chip, offset);
489
490 seq_printf(s, " gpio-%-3d (%-20.20s) %-3s %-9s %s",
491 gpio, label ?: "(none)",
492 is_out ? "out" : "in ",
493 is_out ?
494 (chip->get
495 ? (chip->get(chip, offset) ? "hi" : "lo")
496 : "? ")
497 : (pull ? "pull up" : "pull down"),
498 (mode < 0) ? "unknown" : modes[mode]);
499
500 if (label && !is_out) {
501 int irq = gpio_to_irq(gpio);
502 struct irq_desc *desc = irq_to_desc(irq);
503
504 if (irq >= 0 && desc->action) {
505 char *trigger;
506 int irq_offset = irq - pct->irq_base;
507
508 if (pct->rising & BIT(irq_offset))
509 trigger = "edge-rising";
510 else if (pct->falling & BIT(irq_offset))
511 trigger = "edge-falling";
512 else
513 trigger = "edge-undefined";
514
515 seq_printf(s, " irq-%d %s", irq, trigger);
516 }
517 }
518}
519
520static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
521{
522 unsigned i;
523 unsigned gpio = chip->base;
524 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
525 struct pinctrl_dev *pctldev = pct->pctldev;
526
527 for (i = 0; i < chip->ngpio; i++, gpio++) {
528 /* On AB8500, there is no GPIO0, the first is the GPIO 1 */
529 abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio);
530 seq_printf(s, "\n");
531 }
532}
533
534#else
535static inline void abx500_gpio_dbg_show_one(struct seq_file *s,
83b423c8
LJ		 536 struct pinctrl_dev *pctldev,
537 struct gpio_chip *chip,
538 unsigned offset, unsigned gpio)
0493e649
PC		 539{
540}
541#define abx500_gpio_dbg_show NULL
542#endif
543
544int abx500_gpio_request(struct gpio_chip *chip, unsigned offset)
545{
546 int gpio = chip->base + offset;
547
548 return pinctrl_request_gpio(gpio);
549}
550
551void abx500_gpio_free(struct gpio_chip *chip, unsigned offset)
552{
553 int gpio = chip->base + offset;
554
555 pinctrl_free_gpio(gpio);
556}
557
558static struct gpio_chip abx500gpio_chip = {
559 .label = "abx500-gpio",
560 .owner = THIS_MODULE,
561 .request = abx500_gpio_request,
562 .free = abx500_gpio_free,
563 .direction_input = abx500_gpio_direction_input,
564 .get = abx500_gpio_get,
565 .direction_output = abx500_gpio_direction_output,
566 .set = abx500_gpio_set,
567 .to_irq = abx500_gpio_to_irq,
568 .dbg_show = abx500_gpio_dbg_show,
569};
570
571static unsigned int irq_to_rising(unsigned int irq)
572{
573 struct abx500_pinctrl *pct = irq_get_chip_data(irq);
574 int offset = irq - pct->irq_base;
575 int new_irq;
576
577 new_irq = offset * pct->irq_gpio_factor
578 + pct->irq_gpio_rising_offset
579 + pct->parent->irq_base;
580
581 return new_irq;
582}
583
584static unsigned int irq_to_falling(unsigned int irq)
585{
586 struct abx500_pinctrl *pct = irq_get_chip_data(irq);
587 int offset = irq - pct->irq_base;
588 int new_irq;
589
590 new_irq = offset * pct->irq_gpio_factor
591 + pct->irq_gpio_falling_offset
592 + pct->parent->irq_base;
593 return new_irq;
594
595}
596
597static unsigned int rising_to_irq(unsigned int irq, void *dev)
598{
599 struct abx500_pinctrl *pct = dev;
600 int offset, new_irq;
601
602 offset = irq - pct->irq_gpio_rising_offset
603 - pct->parent->irq_base;
604 new_irq = (offset / pct->irq_gpio_factor)
605 + pct->irq_base;
606
607 return new_irq;
608}
609
610static unsigned int falling_to_irq(unsigned int irq, void *dev)
611{
612 struct abx500_pinctrl *pct = dev;
613 int offset, new_irq;
614
615 offset = irq - pct->irq_gpio_falling_offset
616 - pct->parent->irq_base;
617 new_irq = (offset / pct->irq_gpio_factor)
618 + pct->irq_base;
619
620 return new_irq;
621}
622
623/*
624 * IRQ handler
625 */
626
627static irqreturn_t handle_rising(int irq, void *dev)
628{
629
630 handle_nested_irq(rising_to_irq(irq , dev));
631 return IRQ_HANDLED;
632}
633
634static irqreturn_t handle_falling(int irq, void *dev)
635{
636
637 handle_nested_irq(falling_to_irq(irq, dev));
638 return IRQ_HANDLED;
639}
640
641static void abx500_gpio_irq_lock(struct irq_data *data)
642{
643 struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data);
644 mutex_lock(&pct->lock);
645}
646
647static void abx500_gpio_irq_sync_unlock(struct irq_data *data)
648{
649 struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data);
650 unsigned int irq = data->irq;
651 int offset = irq - pct->irq_base;
652 bool rising = pct->rising & BIT(offset);
653 bool falling = pct->falling & BIT(offset);
654 int ret;
655
656 switch (pct->irq_action) {
657 case STARTUP:
658 if (rising)
659 ret = request_threaded_irq(irq_to_rising(irq),
660 NULL, handle_rising,
661 IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND,
662 "abx500-gpio-r", pct);
663 if (falling)
664 ret = request_threaded_irq(irq_to_falling(irq),
665 NULL, handle_falling,
666 IRQF_TRIGGER_FALLING | IRQF_NO_SUSPEND,
667 "abx500-gpio-f", pct);
668 break;
669 case SHUTDOWN:
670 if (rising)
671 free_irq(irq_to_rising(irq), pct);
672 if (falling)
673 free_irq(irq_to_falling(irq), pct);
674 break;
675 case MASK:
676 if (rising)
677 disable_irq(irq_to_rising(irq));
678 if (falling)
679 disable_irq(irq_to_falling(irq));
680 break;
681 case UNMASK:
682 if (rising)
683 enable_irq(irq_to_rising(irq));
684 if (falling)
685 enable_irq(irq_to_falling(irq));
686 break;
687 case NONE:
688 break;
689 }
690 pct->irq_action = NONE;
691 pct->rising &= ~(BIT(offset));
692 pct->falling &= ~(BIT(offset));
693 mutex_unlock(&pct->lock);
694}
695
696
697static void abx500_gpio_irq_mask(struct irq_data *data)
698{
699 struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data);
700 pct->irq_action = MASK;
701}
702
703static void abx500_gpio_irq_unmask(struct irq_data *data)
704{
705 struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data);
706 pct->irq_action = UNMASK;
707}
708
709static int abx500_gpio_irq_set_type(struct irq_data *data, unsigned int type)
710{
711 struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data);
712 unsigned int irq = data->irq;
713 int offset = irq - pct->irq_base;
714
715 if (type == IRQ_TYPE_EDGE_BOTH) {
716 pct->rising = BIT(offset);
717 pct->falling = BIT(offset);
718 } else if (type == IRQ_TYPE_EDGE_RISING) {
719 pct->rising = BIT(offset);
720 } else {
721 pct->falling = BIT(offset);
722 }
723 return 0;
724}
725
726static unsigned int abx500_gpio_irq_startup(struct irq_data *data)
727{
728 struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data);
729 pct->irq_action = STARTUP;
730 return 0;
731}
732
733static void abx500_gpio_irq_shutdown(struct irq_data *data)
734{
735 struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data);
736 pct->irq_action = SHUTDOWN;
737}
738
739static struct irq_chip abx500_gpio_irq_chip = {
740 .name = "abx500-gpio",
741 .irq_startup = abx500_gpio_irq_startup,
742 .irq_shutdown = abx500_gpio_irq_shutdown,
743 .irq_bus_lock = abx500_gpio_irq_lock,
744 .irq_bus_sync_unlock = abx500_gpio_irq_sync_unlock,
745 .irq_mask = abx500_gpio_irq_mask,
746 .irq_unmask = abx500_gpio_irq_unmask,
747 .irq_set_type = abx500_gpio_irq_set_type,
748};
749
750static int abx500_gpio_irq_init(struct abx500_pinctrl *pct)
751{
752 u32 base = pct->irq_base;
753 int irq;
754
755 for (irq = base; irq < base + AB8500_NUM_VIR_GPIO_IRQ ; irq++) {
756 irq_set_chip_data(irq, pct);
757 irq_set_chip_and_handler(irq, &abx500_gpio_irq_chip,
758 handle_simple_irq);
759 irq_set_nested_thread(irq, 1);
760#ifdef CONFIG_ARM
761 set_irq_flags(irq, IRQF_VALID);
762#else
763 irq_set_noprobe(irq);
764#endif
765 }
766
767 return 0;
768}
769
770static void abx500_gpio_irq_remove(struct abx500_pinctrl *pct)
771{
772 int base = pct->irq_base;
773 int irq;
774
775 for (irq = base; irq < base + AB8500_NUM_VIR_GPIO_IRQ; irq++) {
776#ifdef CONFIG_ARM
777 set_irq_flags(irq, 0);
778#endif
779 irq_set_chip_and_handler(irq, NULL, NULL);
780 irq_set_chip_data(irq, NULL);
781 }
782}
783
784static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
785{
786 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
787
788 return pct->soc->nfunctions;
789}
790
791static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev,
792 unsigned function)
793{
794 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
795
796 return pct->soc->functions[function].name;
797}
798
799static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev,
83b423c8
LJ		 800 unsigned function,
801 const char * const **groups,
802 unsigned * const num_groups)
0493e649
PC		 803{
804 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
805
806 *groups = pct->soc->functions[function].groups;
807 *num_groups = pct->soc->functions[function].ngroups;
808
809 return 0;
810}
811
812static void abx500_disable_lazy_irq(struct gpio_chip *chip, unsigned gpio)
813{
814 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
815 int irq;
816 int offset;
817 bool rising;
818 bool falling;
819
820 /*
821 * check if gpio has interrupt capability and convert
822 * gpio number to irq
823 * On ABx5xx, there is no GPIO0, GPIO1 is the
824 * first one, so adjust gpio number
825 */
826 gpio--;
827 irq = gpio_to_irq(gpio + chip->base);
828 if (irq < 0)
829 return;
830
831 offset = irq - pct->irq_base;
832 rising = pct->rising & BIT(offset);
833 falling = pct->falling & BIT(offset);
834
835 /* nothing to do ?*/
836 if (!rising && !falling)
837 return;
838
839 if (rising) {
840 disable_irq(irq_to_rising(irq));
841 free_irq(irq_to_rising(irq), pct);
842 }
843 if (falling) {
844 disable_irq(irq_to_falling(irq));
845 free_irq(irq_to_falling(irq), pct);
846 }
847}
848
849static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
83b423c8 850 unsigned group)
0493e649
PC		 851{
852 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
853 struct gpio_chip *chip = &pct->chip;
854 const struct abx500_pingroup *g;
855 int i;
856 int ret = 0;
857
858 g = &pct->soc->groups[group];
859 if (g->altsetting < 0)
860 return -EINVAL;
861
862 dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins);
863
864 for (i = 0; i < g->npins; i++) {
865 dev_dbg(pct->dev, "setting pin %d to altsetting %d\n",
866 g->pins[i], g->altsetting);
867
868 abx500_disable_lazy_irq(chip, g->pins[i]);
869 ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting);
870 }
83b423c8 871
0493e649
PC		 872 return ret;
873}
874
875static void abx500_pmx_disable(struct pinctrl_dev *pctldev,
83b423c8 876 unsigned function, unsigned group)
0493e649
PC		 877{
878 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
879 const struct abx500_pingroup *g;
880
881 g = &pct->soc->groups[group];
882 if (g->altsetting < 0)
883 return;
884
885 /* FIXME: poke out the mux, set the pin to some default state? */
886 dev_dbg(pct->dev, "disable group %s, %u pins\n", g->name, g->npins);
887}
888
889int abx500_gpio_request_enable(struct pinctrl_dev *pctldev,
83b423c8
LJ		 890 struct pinctrl_gpio_range *range,
891 unsigned offset)
0493e649
PC		 892{
893 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
894 const struct abx500_pinrange *p;
895 int ret;
896 int i;
897
898 /*
899 * Different ranges have different ways to enable GPIO function on a
900 * pin, so refer back to our local range type, where we handily define
901 * what altfunc enables GPIO for a certain pin.
902 */
903 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
904 p = &pct->soc->gpio_ranges[i];
905 if ((offset >= p->offset) &&
906 (offset < (p->offset + p->npins)))
907 break;
908 }
909
910 if (i == pct->soc->gpio_num_ranges) {
911 dev_err(pct->dev, "%s failed to locate range\n", __func__);
912 return -ENODEV;
913 }
914
915 dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n",
916 p->altfunc, offset);
917
918 ret = abx500_set_mode(pct->pctldev, &pct->chip,
919 offset, p->altfunc);
920 if (ret < 0) {
921 dev_err(pct->dev, "%s setting altfunc failed\n", __func__);
922 return ret;
923 }
924
925 return ret;
926}
927
928static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev,
83b423c8
LJ		 929 struct pinctrl_gpio_range *range,
930 unsigned offset)
0493e649
PC		 931{
932}
933
934static struct pinmux_ops abx500_pinmux_ops = {
935 .get_functions_count = abx500_pmx_get_funcs_cnt,
936 .get_function_name = abx500_pmx_get_func_name,
937 .get_function_groups = abx500_pmx_get_func_groups,
938 .enable = abx500_pmx_enable,
939 .disable = abx500_pmx_disable,
940 .gpio_request_enable = abx500_gpio_request_enable,
941 .gpio_disable_free = abx500_gpio_disable_free,
942};
943
944static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev)
945{
946 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
947
948 return pct->soc->ngroups;
949}
950
951static const char *abx500_get_group_name(struct pinctrl_dev *pctldev,
83b423c8 952 unsigned selector)
0493e649
PC		 953{
954 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
955
956 return pct->soc->groups[selector].name;
957}
958
959static int abx500_get_group_pins(struct pinctrl_dev *pctldev,
83b423c8
LJ		 960 unsigned selector,
961 const unsigned **pins,
962 unsigned *num_pins)
0493e649
PC		 963{
964 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
965
966 *pins = pct->soc->groups[selector].pins;
967 *num_pins = pct->soc->groups[selector].npins;
83b423c8 968
0493e649
PC		 969 return 0;
970}
971
972static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
83b423c8 973 struct seq_file *s, unsigned offset)
0493e649
PC		 974{
975 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
976 struct gpio_chip *chip = &pct->chip;
977
978 abx500_gpio_dbg_show_one(s, pctldev, chip, offset,
979 chip->base + offset - 1);
980}
981
982static struct pinctrl_ops abx500_pinctrl_ops = {
983 .get_groups_count = abx500_get_groups_cnt,
984 .get_group_name = abx500_get_group_name,
985 .get_group_pins = abx500_get_group_pins,
986 .pin_dbg_show = abx500_pin_dbg_show,
987};
988
989int abx500_pin_config_get(struct pinctrl_dev *pctldev,
83b423c8
LJ		 990 unsigned pin,
991 unsigned long *config)
0493e649 992{
1abeebea 993 return -ENOSYS;
0493e649
PC		 994}
995
996int abx500_pin_config_set(struct pinctrl_dev *pctldev,
83b423c8
LJ		 997 unsigned pin,
998 unsigned long config)
0493e649
PC		 999{
1000 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
1001 struct pullud *pullud = pct->soc->pullud;
1002 struct gpio_chip *chip = &pct->chip;
1003 unsigned offset;
1004 int ret;
1005 enum pin_config_param param = pinconf_to_config_param(config);
1006 enum pin_config_param argument = pinconf_to_config_argument(config);
1007
1008 dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n",
1009 pin, config, (param == PIN_CONFIG_OUTPUT) ? "output " : "input",
1010 (param == PIN_CONFIG_OUTPUT) ? (argument ? "high" : "low") :
1011 (argument ? "pull up" : "pull down"));
83b423c8 1012
0493e649
PC		 1013 /* on ABx500, there is no GPIO0, so adjust the offset */
1014 offset = pin - 1;
1015
1016 switch (param) {
1017 case PIN_CONFIG_BIAS_PULL_DOWN:
1018 /*
1019 * if argument = 1 set the pull down
1020 * else clear the pull down
1021 */
1022 ret = abx500_gpio_direction_input(chip, offset);
1023 /*
1024 * Some chips only support pull down, while some actually
1025 * support both pull up and pull down. Such chips have
1026 * a "pullud" range specified for the pins that support
1027 * both features. If the pin is not within that range, we
1028 * fall back to the old bit set that only support pull down.
1029 */
1030 if (pullud &&
1031 pin >= pullud->first_pin &&
1032 pin <= pullud->last_pin)
1033 ret = abx500_config_pull_updown(pct,
1034 pin,
1035 argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE);
1036 else
1037 /* Chip only supports pull down */
1038 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG,
1039 offset, argument ? 0 : 1);
1040 break;
83b423c8 1041
0493e649
PC		 1042 case PIN_CONFIG_OUTPUT:
1043 ret = abx500_gpio_direction_output(chip, offset, argument);
83b423c8 1044
0493e649 1045 break;
83b423c8 1046
0493e649
PC		 1047 default:
1048 dev_err(chip->dev, "illegal configuration requested\n");
83b423c8 1049
0493e649
PC		 1050 return -EINVAL;
1051 }
83b423c8 1052
0493e649
PC		 1053 return ret;
1054}
1055
1056static struct pinconf_ops abx500_pinconf_ops = {
1057 .pin_config_get = abx500_pin_config_get,
1058 .pin_config_set = abx500_pin_config_set,
1059};
1060
1061static struct pinctrl_desc abx500_pinctrl_desc = {
1062 .name = "pinctrl-abx500",
1063 .pctlops = &abx500_pinctrl_ops,
1064 .pmxops = &abx500_pinmux_ops,
1065 .confops = &abx500_pinconf_ops,
1066 .owner = THIS_MODULE,
1067};
1068
1069static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc)
1070{
1071 unsigned int lowest = 0;
1072 unsigned int highest = 0;
1073 unsigned int npins = 0;
1074 int i;
1075
1076 /*
1077 * Compute number of GPIOs from the last SoC gpio range descriptors
1078 * These ranges may include "holes" but the GPIO number space shall
1079 * still be homogeneous, so we need to detect and account for any
1080 * such holes so that these are included in the number of GPIO pins.
1081 */
1082 for (i = 0; i < soc->gpio_num_ranges; i++) {
1083 unsigned gstart;
1084 unsigned gend;
1085 const struct abx500_pinrange *p;
1086
1087 p = &soc->gpio_ranges[i];
1088 gstart = p->offset;
1089 gend = p->offset + p->npins - 1;
1090
1091 if (i == 0) {
1092 /* First iteration, set start values */
1093 lowest = gstart;
1094 highest = gend;
1095 } else {
1096 if (gstart < lowest)
1097 lowest = gstart;
1098 if (gend > highest)
1099 highest = gend;
1100 }
1101 }
1102 /* this gives the absolute number of pins */
1103 npins = highest - lowest + 1;
1104 return npins;
1105}
1106
1107static int abx500_gpio_probe(struct platform_device *pdev)
1108{
1109 struct ab8500_platform_data *abx500_pdata =
1110 dev_get_platdata(pdev->dev.parent);
1111 struct abx500_gpio_platform_data *pdata;
1112 struct abx500_pinctrl *pct;
1113 const struct platform_device_id *platid = platform_get_device_id(pdev);
1114 int ret;
1115 int i;
1116
1117 pdata = abx500_pdata->gpio;
83b423c8 1118 if (!pdata) {
0493e649
PC		 1119 dev_err(&pdev->dev, "gpio platform data missing\n");
1120 return -ENODEV;
1121 }
1122
1123 pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl),
1124 GFP_KERNEL);
1125 if (pct == NULL) {
1126 dev_err(&pdev->dev,
1127 "failed to allocate memory for pct\n");
1128 return -ENOMEM;
1129 }
1130
1131 pct->dev = &pdev->dev;
1132 pct->parent = dev_get_drvdata(pdev->dev.parent);
1133 pct->chip = abx500gpio_chip;
1134 pct->chip.dev = &pdev->dev;
1135 pct->chip.base = pdata->gpio_base;
1136 pct->irq_base = pdata->irq_base;
1137
1138 /* initialize the lock */
1139 mutex_init(&pct->lock);
1140
1141 /* Poke in other ASIC variants here */
1142 switch (platid->driver_data) {
3c937993
PC		 1143 case PINCTRL_AB8500:
1144 abx500_pinctrl_ab8500_init(&pct->soc);
1145 break;
a8f96e41
PC		 1146 case PINCTRL_AB8540:
1147 abx500_pinctrl_ab8540_init(&pct->soc);
1148 break;
09dbec3f
PC		 1149 case PINCTRL_AB9540:
1150 abx500_pinctrl_ab9540_init(&pct->soc);
1151 break;
1aa2d8d4
PC		 1152 case PINCTRL_AB8505:
1153 abx500_pinctrl_ab8505_init(&pct->soc);
1154 break;
0493e649
PC		 1155 default:
1156 dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n",
1157 (int) platid->driver_data);
d41e35c3 1158 mutex_destroy(&pct->lock);
0493e649
PC		 1159 return -EINVAL;
1160 }
1161
1162 if (!pct->soc) {
1163 dev_err(&pdev->dev, "Invalid SOC data\n");
d41e35c3 1164 mutex_destroy(&pct->lock);
0493e649
PC		 1165 return -EINVAL;
1166 }
1167
1168 pct->chip.ngpio = abx500_get_gpio_num(pct->soc);
1169 pct->irq_cluster = pct->soc->gpio_irq_cluster;
1170 pct->irq_cluster_size = pct->soc->ngpio_irq_cluster;
1171 pct->irq_gpio_rising_offset = pct->soc->irq_gpio_rising_offset;
1172 pct->irq_gpio_falling_offset = pct->soc->irq_gpio_falling_offset;
1173 pct->irq_gpio_factor = pct->soc->irq_gpio_factor;
1174
1175 ret = abx500_gpio_irq_init(pct);
1176 if (ret)
1177 goto out_free;
1178 ret = gpiochip_add(&pct->chip);
1179 if (ret) {
83b423c8 1180 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
d41e35c3 1181 mutex_destroy(&pct->lock);
0493e649
PC		 1182 goto out_rem_irq;
1183 }
1184 dev_info(&pdev->dev, "added gpiochip\n");
1185
1186 abx500_pinctrl_desc.pins = pct->soc->pins;
1187 abx500_pinctrl_desc.npins = pct->soc->npins;
1188 pct->pctldev = pinctrl_register(&abx500_pinctrl_desc, &pdev->dev, pct);
1189 if (!pct->pctldev) {
1190 dev_err(&pdev->dev,
1191 "could not register abx500 pinctrl driver\n");
1192 goto out_rem_chip;
1193 }
1194 dev_info(&pdev->dev, "registered pin controller\n");
1195
1196 /* We will handle a range of GPIO pins */
1197 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
1198 const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i];
1199
1200 ret = gpiochip_add_pin_range(&pct->chip,
1201 dev_name(&pdev->dev),
1202 p->offset - 1, p->offset, p->npins);
1203 if (ret < 0)
1204 return ret;
1205 }
1206
1207 platform_set_drvdata(pdev, pct);
1208 dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n");
1209
1210 return 0;
1211
1212out_rem_chip:
1213 ret = gpiochip_remove(&pct->chip);
1214 if (ret)
1215 dev_info(&pdev->dev, "failed to remove gpiochip\n");
1216out_rem_irq:
1217 abx500_gpio_irq_remove(pct);
1218out_free:
1219 mutex_destroy(&pct->lock);
1220 return ret;
1221}
1222
83b423c8 1223/**
0493e649 1224 * abx500_gpio_remove() - remove Ab8500-gpio driver
83b423c8 1225 * @pdev: Platform device registered
0493e649
PC		 1226 */
1227static int abx500_gpio_remove(struct platform_device *pdev)
1228{
1229 struct abx500_pinctrl *pct = platform_get_drvdata(pdev);
1230 int ret;
1231
1232 ret = gpiochip_remove(&pct->chip);
1233 if (ret < 0) {
1234 dev_err(pct->dev, "unable to remove gpiochip: %d\n",
1235 ret);
1236 return ret;
1237 }
1238
1239 mutex_destroy(&pct->lock);
1240
1241 return 0;
1242}
1243
1244static const struct platform_device_id abx500_pinctrl_id[] = {
1245 { "pinctrl-ab8500", PINCTRL_AB8500 },
1246 { "pinctrl-ab8540", PINCTRL_AB8540 },
1247 { "pinctrl-ab9540", PINCTRL_AB9540 },
1248 { "pinctrl-ab8505", PINCTRL_AB8505 },
1249 { },
1250};
1251
1252static struct platform_driver abx500_gpio_driver = {
1253 .driver = {
1254 .name = "abx500-gpio",
1255 .owner = THIS_MODULE,
1256 },
1257 .probe = abx500_gpio_probe,
1258 .remove = abx500_gpio_remove,
1259 .id_table = abx500_pinctrl_id,
1260};
1261
1262static int __init abx500_gpio_init(void)
1263{
1264 return platform_driver_register(&abx500_gpio_driver);
1265}
1266core_initcall(abx500_gpio_init);
1267
1268MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>");
1269MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO");
1270MODULE_ALIAS("platform:abx500-gpio");
1271MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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