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77618084 LD |
1 | /* |
2 | * Driver for the Atmel PIO4 controller | |
3 | * | |
4 | * Copyright (C) 2015 Atmel, | |
5 | * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> | |
6 | * | |
7 | * This software is licensed under the terms of the GNU General Public | |
8 | * License version 2, as published by the Free Software Foundation, and | |
9 | * may be copied, distributed, and modified under those terms. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/clk.h> | |
80036f88 LW |
18 | #include <linux/gpio/driver.h> |
19 | /* FIXME: needed for gpio_to_irq(), get rid of this */ | |
77618084 | 20 | #include <linux/gpio.h> |
de4e882f | 21 | #include <linux/interrupt.h> |
77618084 LD |
22 | #include <linux/io.h> |
23 | #include <linux/module.h> | |
24 | #include <linux/of.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/pinctrl/pinconf.h> | |
27 | #include <linux/pinctrl/pinconf-generic.h> | |
28 | #include <linux/pinctrl/pinctrl.h> | |
29 | #include <linux/pinctrl/pinmux.h> | |
30 | #include <linux/slab.h> | |
31 | #include "core.h" | |
32 | #include "pinconf.h" | |
33 | #include "pinctrl-utils.h" | |
34 | ||
35 | /* | |
36 | * Warning: | |
37 | * In order to not introduce confusion between Atmel PIO groups and pinctrl | |
38 | * framework groups, Atmel PIO groups will be called banks, line is kept to | |
39 | * designed the pin id into this bank. | |
40 | */ | |
41 | ||
42 | #define ATMEL_PIO_MSKR 0x0000 | |
43 | #define ATMEL_PIO_CFGR 0x0004 | |
44 | #define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0) | |
45 | #define ATMEL_PIO_DIR_MASK BIT(8) | |
46 | #define ATMEL_PIO_PUEN_MASK BIT(9) | |
47 | #define ATMEL_PIO_PDEN_MASK BIT(10) | |
48 | #define ATMEL_PIO_IFEN_MASK BIT(12) | |
49 | #define ATMEL_PIO_IFSCEN_MASK BIT(13) | |
50 | #define ATMEL_PIO_OPD_MASK BIT(14) | |
51 | #define ATMEL_PIO_SCHMITT_MASK BIT(15) | |
52 | #define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24) | |
53 | #define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24) | |
54 | #define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24) | |
55 | #define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24) | |
56 | #define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24) | |
57 | #define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24) | |
58 | #define ATMEL_PIO_PDSR 0x0008 | |
59 | #define ATMEL_PIO_LOCKSR 0x000C | |
60 | #define ATMEL_PIO_SODR 0x0010 | |
61 | #define ATMEL_PIO_CODR 0x0014 | |
62 | #define ATMEL_PIO_ODSR 0x0018 | |
63 | #define ATMEL_PIO_IER 0x0020 | |
64 | #define ATMEL_PIO_IDR 0x0024 | |
65 | #define ATMEL_PIO_IMR 0x0028 | |
66 | #define ATMEL_PIO_ISR 0x002C | |
67 | #define ATMEL_PIO_IOFR 0x003C | |
68 | ||
69 | #define ATMEL_PIO_NPINS_PER_BANK 32 | |
70 | #define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK) | |
71 | #define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK) | |
72 | #define ATMEL_PIO_BANK_OFFSET 0x40 | |
73 | ||
74 | #define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff) | |
75 | #define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf) | |
76 | #define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf) | |
77 | ||
78 | struct atmel_pioctrl_data { | |
79 | unsigned nbanks; | |
80 | }; | |
81 | ||
82 | struct atmel_group { | |
83 | const char *name; | |
84 | u32 pin; | |
85 | }; | |
86 | ||
87 | struct atmel_pin { | |
88 | unsigned pin_id; | |
89 | unsigned mux; | |
90 | unsigned ioset; | |
91 | unsigned bank; | |
92 | unsigned line; | |
93 | const char *device; | |
94 | }; | |
95 | ||
96 | /** | |
97 | * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio) | |
98 | * @reg_base: base address of the controller. | |
99 | * @clk: clock of the controller. | |
100 | * @nbanks: number of PIO groups, it can vary depending on the SoC. | |
101 | * @pinctrl_dev: pinctrl device registered. | |
102 | * @groups: groups table to provide group name and pin in the group to pinctrl. | |
103 | * @group_names: group names table to provide all the group/pin names to | |
104 | * pinctrl or gpio. | |
105 | * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line | |
106 | * fields are set at probe time. Other ones are set when parsing dt | |
107 | * pinctrl. | |
108 | * @npins: number of pins. | |
109 | * @gpio_chip: gpio chip registered. | |
110 | * @irq_domain: irq domain for the gpio controller. | |
111 | * @irqs: table containing the hw irq number of the bank. The index of the | |
112 | * table is the bank id. | |
113 | * @dev: device entry for the Atmel PIO controller. | |
114 | * @node: node of the Atmel PIO controller. | |
115 | */ | |
116 | struct atmel_pioctrl { | |
117 | void __iomem *reg_base; | |
118 | struct clk *clk; | |
119 | unsigned nbanks; | |
120 | struct pinctrl_dev *pinctrl_dev; | |
121 | struct atmel_group *groups; | |
122 | const char * const *group_names; | |
123 | struct atmel_pin **pins; | |
124 | unsigned npins; | |
125 | struct gpio_chip *gpio_chip; | |
126 | struct irq_domain *irq_domain; | |
127 | int *irqs; | |
de4e882f LD |
128 | unsigned *pm_wakeup_sources; |
129 | unsigned *pm_suspend_backup; | |
77618084 LD |
130 | struct device *dev; |
131 | struct device_node *node; | |
132 | }; | |
133 | ||
134 | static const char * const atmel_functions[] = { | |
135 | "GPIO", "A", "B", "C", "D", "E", "F", "G" | |
136 | }; | |
137 | ||
138 | /* --- GPIO --- */ | |
139 | static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl, | |
140 | unsigned int bank, unsigned int reg) | |
141 | { | |
142 | return readl_relaxed(atmel_pioctrl->reg_base | |
143 | + ATMEL_PIO_BANK_OFFSET * bank + reg); | |
144 | } | |
145 | ||
146 | static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl, | |
147 | unsigned int bank, unsigned int reg, | |
148 | unsigned int val) | |
149 | { | |
150 | writel_relaxed(val, atmel_pioctrl->reg_base | |
151 | + ATMEL_PIO_BANK_OFFSET * bank + reg); | |
152 | } | |
153 | ||
154 | static void atmel_gpio_irq_ack(struct irq_data *d) | |
155 | { | |
156 | /* | |
157 | * Nothing to do, interrupt is cleared when reading the status | |
158 | * register. | |
159 | */ | |
160 | } | |
161 | ||
162 | static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type) | |
163 | { | |
164 | struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); | |
165 | struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; | |
166 | unsigned reg; | |
167 | ||
168 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, | |
169 | BIT(pin->line)); | |
170 | reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); | |
171 | reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK); | |
172 | ||
173 | switch (type) { | |
174 | case IRQ_TYPE_EDGE_RISING: | |
3fd550c6 | 175 | irq_set_handler_locked(d, handle_edge_irq); |
77618084 LD |
176 | reg |= ATMEL_PIO_CFGR_EVTSEL_RISING; |
177 | break; | |
178 | case IRQ_TYPE_EDGE_FALLING: | |
3fd550c6 | 179 | irq_set_handler_locked(d, handle_edge_irq); |
77618084 LD |
180 | reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING; |
181 | break; | |
182 | case IRQ_TYPE_EDGE_BOTH: | |
3fd550c6 | 183 | irq_set_handler_locked(d, handle_edge_irq); |
77618084 LD |
184 | reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH; |
185 | break; | |
186 | case IRQ_TYPE_LEVEL_LOW: | |
3fd550c6 | 187 | irq_set_handler_locked(d, handle_level_irq); |
77618084 LD |
188 | reg |= ATMEL_PIO_CFGR_EVTSEL_LOW; |
189 | break; | |
190 | case IRQ_TYPE_LEVEL_HIGH: | |
3fd550c6 | 191 | irq_set_handler_locked(d, handle_level_irq); |
77618084 LD |
192 | reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH; |
193 | break; | |
194 | case IRQ_TYPE_NONE: | |
195 | default: | |
196 | return -EINVAL; | |
197 | } | |
198 | ||
199 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); | |
200 | ||
201 | return 0; | |
202 | } | |
203 | ||
204 | static void atmel_gpio_irq_mask(struct irq_data *d) | |
205 | { | |
206 | struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); | |
207 | struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; | |
208 | ||
209 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR, | |
210 | BIT(pin->line)); | |
211 | } | |
212 | ||
213 | static void atmel_gpio_irq_unmask(struct irq_data *d) | |
214 | { | |
215 | struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); | |
216 | struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; | |
217 | ||
218 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER, | |
219 | BIT(pin->line)); | |
220 | } | |
221 | ||
de4e882f LD |
222 | #ifdef CONFIG_PM_SLEEP |
223 | ||
224 | static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on) | |
225 | { | |
226 | struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); | |
227 | int bank = ATMEL_PIO_BANK(d->hwirq); | |
228 | int line = ATMEL_PIO_LINE(d->hwirq); | |
229 | ||
230 | /* The gpio controller has one interrupt line per bank. */ | |
231 | irq_set_irq_wake(atmel_pioctrl->irqs[bank], on); | |
232 | ||
233 | if (on) | |
234 | atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line); | |
235 | else | |
236 | atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line)); | |
237 | ||
238 | return 0; | |
239 | } | |
240 | #else | |
241 | #define atmel_gpio_irq_set_wake NULL | |
242 | #endif /* CONFIG_PM_SLEEP */ | |
243 | ||
77618084 LD |
244 | static struct irq_chip atmel_gpio_irq_chip = { |
245 | .name = "GPIO", | |
246 | .irq_ack = atmel_gpio_irq_ack, | |
247 | .irq_mask = atmel_gpio_irq_mask, | |
248 | .irq_unmask = atmel_gpio_irq_unmask, | |
249 | .irq_set_type = atmel_gpio_irq_set_type, | |
de4e882f | 250 | .irq_set_wake = atmel_gpio_irq_set_wake, |
77618084 LD |
251 | }; |
252 | ||
89092fb0 | 253 | static void atmel_gpio_irq_handler(struct irq_desc *desc) |
77618084 | 254 | { |
89092fb0 LD |
255 | unsigned int irq = irq_desc_get_irq(desc); |
256 | struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc); | |
77618084 LD |
257 | struct irq_chip *chip = irq_desc_get_chip(desc); |
258 | unsigned long isr; | |
259 | int n, bank = -1; | |
260 | ||
261 | /* Find from which bank is the irq received. */ | |
262 | for (n = 0; n < atmel_pioctrl->nbanks; n++) { | |
263 | if (atmel_pioctrl->irqs[n] == irq) { | |
264 | bank = n; | |
265 | break; | |
266 | } | |
267 | } | |
268 | ||
269 | if (bank < 0) { | |
270 | dev_err(atmel_pioctrl->dev, | |
271 | "no bank associated to irq %u\n", irq); | |
272 | return; | |
273 | } | |
274 | ||
275 | chained_irq_enter(chip, desc); | |
276 | ||
277 | for (;;) { | |
278 | isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, | |
279 | ATMEL_PIO_ISR); | |
280 | isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, | |
281 | ATMEL_PIO_IMR); | |
282 | if (!isr) | |
283 | break; | |
284 | ||
285 | for_each_set_bit(n, &isr, BITS_PER_LONG) | |
286 | generic_handle_irq(gpio_to_irq(bank * | |
287 | ATMEL_PIO_NPINS_PER_BANK + n)); | |
288 | } | |
289 | ||
290 | chained_irq_exit(chip, desc); | |
291 | } | |
292 | ||
293 | static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
294 | { | |
80036f88 | 295 | struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); |
77618084 LD |
296 | struct atmel_pin *pin = atmel_pioctrl->pins[offset]; |
297 | unsigned reg; | |
298 | ||
299 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, | |
300 | BIT(pin->line)); | |
301 | reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); | |
302 | reg &= ~ATMEL_PIO_DIR_MASK; | |
303 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); | |
304 | ||
305 | return 0; | |
306 | } | |
307 | ||
308 | static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset) | |
309 | { | |
80036f88 | 310 | struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); |
77618084 LD |
311 | struct atmel_pin *pin = atmel_pioctrl->pins[offset]; |
312 | unsigned reg; | |
313 | ||
314 | reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR); | |
315 | ||
316 | return !!(reg & BIT(pin->line)); | |
317 | } | |
318 | ||
319 | static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | |
320 | int value) | |
321 | { | |
80036f88 | 322 | struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); |
77618084 LD |
323 | struct atmel_pin *pin = atmel_pioctrl->pins[offset]; |
324 | unsigned reg; | |
325 | ||
326 | atmel_gpio_write(atmel_pioctrl, pin->bank, | |
327 | value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, | |
328 | BIT(pin->line)); | |
329 | ||
330 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, | |
331 | BIT(pin->line)); | |
332 | reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); | |
333 | reg |= ATMEL_PIO_DIR_MASK; | |
334 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); | |
335 | ||
336 | return 0; | |
337 | } | |
338 | ||
339 | static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val) | |
340 | { | |
80036f88 | 341 | struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); |
77618084 LD |
342 | struct atmel_pin *pin = atmel_pioctrl->pins[offset]; |
343 | ||
344 | atmel_gpio_write(atmel_pioctrl, pin->bank, | |
345 | val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, | |
346 | BIT(pin->line)); | |
347 | } | |
348 | ||
349 | static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
350 | { | |
80036f88 | 351 | struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); |
77618084 LD |
352 | |
353 | return irq_find_mapping(atmel_pioctrl->irq_domain, offset); | |
354 | } | |
355 | ||
356 | static struct gpio_chip atmel_gpio_chip = { | |
357 | .direction_input = atmel_gpio_direction_input, | |
358 | .get = atmel_gpio_get, | |
359 | .direction_output = atmel_gpio_direction_output, | |
360 | .set = atmel_gpio_set, | |
361 | .to_irq = atmel_gpio_to_irq, | |
362 | .base = 0, | |
363 | }; | |
364 | ||
365 | /* --- PINCTRL --- */ | |
366 | static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev, | |
367 | unsigned pin_id) | |
368 | { | |
369 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
370 | unsigned bank = atmel_pioctrl->pins[pin_id]->bank; | |
371 | unsigned line = atmel_pioctrl->pins[pin_id]->line; | |
372 | void __iomem *addr = atmel_pioctrl->reg_base | |
373 | + bank * ATMEL_PIO_BANK_OFFSET; | |
374 | ||
375 | writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR); | |
376 | /* Have to set MSKR first, to access the right pin CFGR. */ | |
377 | wmb(); | |
378 | ||
379 | return readl_relaxed(addr + ATMEL_PIO_CFGR); | |
380 | } | |
381 | ||
382 | static void atmel_pin_config_write(struct pinctrl_dev *pctldev, | |
383 | unsigned pin_id, u32 conf) | |
384 | { | |
385 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
386 | unsigned bank = atmel_pioctrl->pins[pin_id]->bank; | |
387 | unsigned line = atmel_pioctrl->pins[pin_id]->line; | |
388 | void __iomem *addr = atmel_pioctrl->reg_base | |
389 | + bank * ATMEL_PIO_BANK_OFFSET; | |
390 | ||
391 | writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR); | |
392 | /* Have to set MSKR first, to access the right pin CFGR. */ | |
393 | wmb(); | |
394 | writel_relaxed(conf, addr + ATMEL_PIO_CFGR); | |
395 | } | |
396 | ||
397 | static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev) | |
398 | { | |
399 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
400 | ||
401 | return atmel_pioctrl->npins; | |
402 | } | |
403 | ||
404 | static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev, | |
405 | unsigned selector) | |
406 | { | |
407 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
408 | ||
409 | return atmel_pioctrl->groups[selector].name; | |
410 | } | |
411 | ||
412 | static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev, | |
413 | unsigned selector, const unsigned **pins, | |
414 | unsigned *num_pins) | |
415 | { | |
416 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
417 | ||
418 | *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin; | |
419 | *num_pins = 1; | |
420 | ||
421 | return 0; | |
422 | } | |
423 | ||
424 | struct atmel_group *atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, | |
425 | unsigned pin) | |
426 | { | |
427 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
428 | int i; | |
429 | ||
430 | for (i = 0; i < atmel_pioctrl->npins; i++) { | |
431 | struct atmel_group *grp = atmel_pioctrl->groups + i; | |
432 | ||
433 | if (grp->pin == pin) | |
434 | return grp; | |
435 | } | |
436 | ||
437 | return NULL; | |
438 | } | |
439 | ||
440 | static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev, | |
441 | struct device_node *np, | |
442 | u32 pinfunc, const char **grp_name, | |
443 | const char **func_name) | |
444 | { | |
445 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
446 | unsigned pin_id, func_id; | |
447 | struct atmel_group *grp; | |
448 | ||
449 | pin_id = ATMEL_GET_PIN_NO(pinfunc); | |
450 | func_id = ATMEL_GET_PIN_FUNC(pinfunc); | |
451 | ||
452 | if (func_id >= ARRAY_SIZE(atmel_functions)) | |
453 | return -EINVAL; | |
454 | ||
455 | *func_name = atmel_functions[func_id]; | |
456 | ||
457 | grp = atmel_pctl_find_group_by_pin(pctldev, pin_id); | |
458 | if (!grp) | |
459 | return -EINVAL; | |
460 | *grp_name = grp->name; | |
461 | ||
462 | atmel_pioctrl->pins[pin_id]->mux = func_id; | |
463 | atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc); | |
464 | /* Want the device name not the group one. */ | |
465 | if (np->parent == atmel_pioctrl->node) | |
466 | atmel_pioctrl->pins[pin_id]->device = np->name; | |
467 | else | |
468 | atmel_pioctrl->pins[pin_id]->device = np->parent->name; | |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
473 | static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev, | |
474 | struct device_node *np, | |
475 | struct pinctrl_map **map, | |
476 | unsigned *reserved_maps, | |
477 | unsigned *num_maps) | |
478 | { | |
479 | unsigned num_pins, num_configs, reserve; | |
480 | unsigned long *configs; | |
481 | struct property *pins; | |
482 | bool has_config; | |
483 | u32 pinfunc; | |
484 | int ret, i; | |
485 | ||
486 | pins = of_find_property(np, "pinmux", NULL); | |
487 | if (!pins) | |
488 | return -EINVAL; | |
489 | ||
490 | ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, | |
491 | &num_configs); | |
492 | if (ret < 0) { | |
493 | dev_err(pctldev->dev, "%s: could not parse node property\n", | |
494 | of_node_full_name(np)); | |
495 | return ret; | |
496 | } | |
497 | ||
498 | if (num_configs) | |
499 | has_config = true; | |
500 | ||
501 | num_pins = pins->length / sizeof(u32); | |
502 | if (!num_pins) { | |
503 | dev_err(pctldev->dev, "no pins found in node %s\n", | |
504 | of_node_full_name(np)); | |
e43d2b75 LD |
505 | ret = -EINVAL; |
506 | goto exit; | |
77618084 LD |
507 | } |
508 | ||
509 | /* | |
510 | * Reserve maps, at least there is a mux map and an optional conf | |
511 | * map for each pin. | |
512 | */ | |
513 | reserve = 1; | |
514 | if (has_config && num_pins >= 1) | |
515 | reserve++; | |
516 | reserve *= num_pins; | |
517 | ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, | |
518 | reserve); | |
519 | if (ret < 0) | |
e43d2b75 | 520 | goto exit; |
77618084 LD |
521 | |
522 | for (i = 0; i < num_pins; i++) { | |
523 | const char *group, *func; | |
524 | ||
525 | ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc); | |
526 | if (ret) | |
e43d2b75 | 527 | goto exit; |
77618084 LD |
528 | |
529 | ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group, | |
530 | &func); | |
531 | if (ret) | |
e43d2b75 | 532 | goto exit; |
77618084 LD |
533 | |
534 | pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps, | |
535 | group, func); | |
536 | ||
537 | if (has_config) { | |
538 | ret = pinctrl_utils_add_map_configs(pctldev, map, | |
539 | reserved_maps, num_maps, group, | |
540 | configs, num_configs, | |
541 | PIN_MAP_TYPE_CONFIGS_GROUP); | |
542 | if (ret < 0) | |
e43d2b75 | 543 | goto exit; |
77618084 LD |
544 | } |
545 | } | |
546 | ||
e43d2b75 LD |
547 | exit: |
548 | kfree(configs); | |
549 | return ret; | |
77618084 LD |
550 | } |
551 | ||
552 | static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, | |
553 | struct device_node *np_config, | |
554 | struct pinctrl_map **map, | |
555 | unsigned *num_maps) | |
556 | { | |
557 | struct device_node *np; | |
558 | unsigned reserved_maps; | |
559 | int ret; | |
560 | ||
561 | *map = NULL; | |
562 | *num_maps = 0; | |
563 | reserved_maps = 0; | |
564 | ||
565 | /* | |
566 | * If all the pins of a device have the same configuration (or no one), | |
567 | * it is useless to add a subnode, so directly parse node referenced by | |
568 | * phandle. | |
569 | */ | |
570 | ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map, | |
571 | &reserved_maps, num_maps); | |
572 | if (ret) { | |
573 | for_each_child_of_node(np_config, np) { | |
574 | ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map, | |
575 | &reserved_maps, num_maps); | |
576 | if (ret < 0) | |
577 | break; | |
578 | } | |
579 | } | |
580 | ||
581 | if (ret < 0) { | |
582 | pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); | |
583 | dev_err(pctldev->dev, "can't create maps for node %s\n", | |
584 | np_config->full_name); | |
585 | } | |
586 | ||
587 | return ret; | |
588 | } | |
589 | ||
590 | static const struct pinctrl_ops atmel_pctlops = { | |
591 | .get_groups_count = atmel_pctl_get_groups_count, | |
592 | .get_group_name = atmel_pctl_get_group_name, | |
593 | .get_group_pins = atmel_pctl_get_group_pins, | |
594 | .dt_node_to_map = atmel_pctl_dt_node_to_map, | |
595 | .dt_free_map = pinctrl_utils_dt_free_map, | |
596 | }; | |
597 | ||
598 | static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev) | |
599 | { | |
600 | return ARRAY_SIZE(atmel_functions); | |
601 | } | |
602 | ||
603 | static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev, | |
604 | unsigned selector) | |
605 | { | |
606 | return atmel_functions[selector]; | |
607 | } | |
608 | ||
609 | static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev, | |
610 | unsigned selector, | |
611 | const char * const **groups, | |
612 | unsigned * const num_groups) | |
613 | { | |
614 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
615 | ||
616 | *groups = atmel_pioctrl->group_names; | |
617 | *num_groups = atmel_pioctrl->npins; | |
618 | ||
619 | return 0; | |
620 | } | |
621 | ||
622 | static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev, | |
623 | unsigned function, | |
624 | unsigned group) | |
625 | { | |
626 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
627 | unsigned pin; | |
628 | u32 conf; | |
629 | ||
630 | dev_dbg(pctldev->dev, "enable function %s group %s\n", | |
631 | atmel_functions[function], atmel_pioctrl->groups[group].name); | |
632 | ||
633 | pin = atmel_pioctrl->groups[group].pin; | |
634 | conf = atmel_pin_config_read(pctldev, pin); | |
635 | conf &= (~ATMEL_PIO_CFGR_FUNC_MASK); | |
636 | conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK); | |
637 | dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf); | |
638 | atmel_pin_config_write(pctldev, pin, conf); | |
639 | ||
640 | return 0; | |
641 | } | |
642 | ||
643 | static const struct pinmux_ops atmel_pmxops = { | |
644 | .get_functions_count = atmel_pmx_get_functions_count, | |
645 | .get_function_name = atmel_pmx_get_function_name, | |
646 | .get_function_groups = atmel_pmx_get_function_groups, | |
647 | .set_mux = atmel_pmx_set_mux, | |
648 | }; | |
649 | ||
650 | static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev, | |
651 | unsigned group, | |
652 | unsigned long *config) | |
653 | { | |
654 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
655 | unsigned param = pinconf_to_config_param(*config), arg = 0; | |
656 | struct atmel_group *grp = atmel_pioctrl->groups + group; | |
657 | unsigned pin_id = grp->pin; | |
658 | u32 res; | |
659 | ||
660 | res = atmel_pin_config_read(pctldev, pin_id); | |
661 | ||
662 | switch (param) { | |
663 | case PIN_CONFIG_BIAS_PULL_UP: | |
664 | if (!(res & ATMEL_PIO_PUEN_MASK)) | |
665 | return -EINVAL; | |
666 | arg = 1; | |
667 | break; | |
668 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
669 | if ((res & ATMEL_PIO_PUEN_MASK) || | |
670 | (!(res & ATMEL_PIO_PDEN_MASK))) | |
671 | return -EINVAL; | |
672 | arg = 1; | |
673 | break; | |
674 | case PIN_CONFIG_BIAS_DISABLE: | |
675 | if ((res & ATMEL_PIO_PUEN_MASK) || | |
676 | ((res & ATMEL_PIO_PDEN_MASK))) | |
677 | return -EINVAL; | |
678 | arg = 1; | |
679 | break; | |
680 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
681 | if (!(res & ATMEL_PIO_OPD_MASK)) | |
682 | return -EINVAL; | |
683 | arg = 1; | |
684 | break; | |
685 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: | |
686 | if (!(res & ATMEL_PIO_SCHMITT_MASK)) | |
687 | return -EINVAL; | |
688 | arg = 1; | |
689 | break; | |
690 | default: | |
691 | return -ENOTSUPP; | |
692 | } | |
693 | ||
694 | *config = pinconf_to_config_packed(param, arg); | |
695 | return 0; | |
696 | } | |
697 | ||
698 | static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, | |
699 | unsigned group, | |
700 | unsigned long *configs, | |
701 | unsigned num_configs) | |
702 | { | |
703 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
704 | struct atmel_group *grp = atmel_pioctrl->groups + group; | |
705 | unsigned bank, pin, pin_id = grp->pin; | |
706 | u32 mask, conf = 0; | |
707 | int i; | |
708 | ||
709 | conf = atmel_pin_config_read(pctldev, pin_id); | |
710 | ||
711 | for (i = 0; i < num_configs; i++) { | |
712 | unsigned param = pinconf_to_config_param(configs[i]); | |
713 | unsigned arg = pinconf_to_config_argument(configs[i]); | |
714 | ||
715 | dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", | |
716 | __func__, pin_id, configs[i]); | |
717 | ||
718 | switch (param) { | |
719 | case PIN_CONFIG_BIAS_DISABLE: | |
720 | conf &= (~ATMEL_PIO_PUEN_MASK); | |
721 | conf &= (~ATMEL_PIO_PDEN_MASK); | |
722 | break; | |
723 | case PIN_CONFIG_BIAS_PULL_UP: | |
724 | conf |= ATMEL_PIO_PUEN_MASK; | |
5305a7b7 | 725 | conf &= (~ATMEL_PIO_PDEN_MASK); |
77618084 LD |
726 | break; |
727 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
728 | conf |= ATMEL_PIO_PDEN_MASK; | |
5305a7b7 | 729 | conf &= (~ATMEL_PIO_PUEN_MASK); |
77618084 LD |
730 | break; |
731 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
732 | if (arg == 0) | |
733 | conf &= (~ATMEL_PIO_OPD_MASK); | |
734 | else | |
735 | conf |= ATMEL_PIO_OPD_MASK; | |
736 | break; | |
737 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: | |
738 | if (arg == 0) | |
739 | conf |= ATMEL_PIO_SCHMITT_MASK; | |
740 | else | |
741 | conf &= (~ATMEL_PIO_SCHMITT_MASK); | |
742 | break; | |
743 | case PIN_CONFIG_INPUT_DEBOUNCE: | |
744 | if (arg == 0) { | |
745 | conf &= (~ATMEL_PIO_IFEN_MASK); | |
746 | conf &= (~ATMEL_PIO_IFSCEN_MASK); | |
747 | } else { | |
748 | /* | |
749 | * We don't care about the debounce value for several reasons: | |
750 | * - can't have different debounce periods inside a same group, | |
751 | * - the register to configure this period is a secure register. | |
752 | * The debouncing filter can filter a pulse with a duration of less | |
753 | * than 1/2 slow clock period. | |
754 | */ | |
755 | conf |= ATMEL_PIO_IFEN_MASK; | |
756 | conf |= ATMEL_PIO_IFSCEN_MASK; | |
757 | } | |
758 | break; | |
759 | case PIN_CONFIG_OUTPUT: | |
760 | conf |= ATMEL_PIO_DIR_MASK; | |
761 | bank = ATMEL_PIO_BANK(pin_id); | |
762 | pin = ATMEL_PIO_LINE(pin_id); | |
763 | mask = 1 << pin; | |
764 | ||
765 | if (arg == 0) { | |
766 | writel_relaxed(mask, atmel_pioctrl->reg_base + | |
767 | bank * ATMEL_PIO_BANK_OFFSET + | |
768 | ATMEL_PIO_CODR); | |
769 | } else { | |
770 | writel_relaxed(mask, atmel_pioctrl->reg_base + | |
771 | bank * ATMEL_PIO_BANK_OFFSET + | |
772 | ATMEL_PIO_SODR); | |
773 | } | |
774 | break; | |
775 | default: | |
776 | dev_warn(pctldev->dev, | |
777 | "unsupported configuration parameter: %u\n", | |
778 | param); | |
779 | continue; | |
780 | } | |
781 | } | |
782 | ||
783 | dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf); | |
784 | atmel_pin_config_write(pctldev, pin_id, conf); | |
785 | ||
786 | return 0; | |
787 | } | |
788 | ||
789 | static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev, | |
790 | struct seq_file *s, unsigned pin_id) | |
791 | { | |
792 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
793 | u32 conf; | |
794 | ||
795 | if (!atmel_pioctrl->pins[pin_id]->device) | |
796 | return; | |
797 | ||
798 | if (atmel_pioctrl->pins[pin_id]) | |
799 | seq_printf(s, " (%s, ioset %u) ", | |
800 | atmel_pioctrl->pins[pin_id]->device, | |
801 | atmel_pioctrl->pins[pin_id]->ioset); | |
802 | ||
803 | conf = atmel_pin_config_read(pctldev, pin_id); | |
804 | if (conf & ATMEL_PIO_PUEN_MASK) | |
805 | seq_printf(s, "%s ", "pull-up"); | |
806 | if (conf & ATMEL_PIO_PDEN_MASK) | |
807 | seq_printf(s, "%s ", "pull-down"); | |
808 | if (conf & ATMEL_PIO_IFEN_MASK) | |
809 | seq_printf(s, "%s ", "debounce"); | |
810 | if (conf & ATMEL_PIO_OPD_MASK) | |
811 | seq_printf(s, "%s ", "open-drain"); | |
812 | if (conf & ATMEL_PIO_SCHMITT_MASK) | |
813 | seq_printf(s, "%s ", "schmitt"); | |
814 | } | |
815 | ||
816 | static const struct pinconf_ops atmel_confops = { | |
817 | .pin_config_group_get = atmel_conf_pin_config_group_get, | |
818 | .pin_config_group_set = atmel_conf_pin_config_group_set, | |
819 | .pin_config_dbg_show = atmel_conf_pin_config_dbg_show, | |
820 | }; | |
821 | ||
822 | static struct pinctrl_desc atmel_pinctrl_desc = { | |
823 | .name = "atmel_pinctrl", | |
824 | .confops = &atmel_confops, | |
825 | .pctlops = &atmel_pctlops, | |
826 | .pmxops = &atmel_pmxops, | |
827 | }; | |
828 | ||
6be2a3a0 | 829 | static int __maybe_unused atmel_pctrl_suspend(struct device *dev) |
de4e882f LD |
830 | { |
831 | struct platform_device *pdev = to_platform_device(dev); | |
832 | struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev); | |
833 | int i; | |
834 | ||
835 | /* | |
836 | * For each bank, save IMR to restore it later and disable all GPIO | |
837 | * interrupts excepting the ones marked as wakeup sources. | |
838 | */ | |
839 | for (i = 0; i < atmel_pioctrl->nbanks; i++) { | |
840 | atmel_pioctrl->pm_suspend_backup[i] = | |
841 | atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR); | |
842 | atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR, | |
843 | ~atmel_pioctrl->pm_wakeup_sources[i]); | |
844 | } | |
845 | ||
846 | return 0; | |
847 | } | |
848 | ||
6be2a3a0 | 849 | static int __maybe_unused atmel_pctrl_resume(struct device *dev) |
de4e882f LD |
850 | { |
851 | struct platform_device *pdev = to_platform_device(dev); | |
852 | struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev); | |
853 | int i; | |
854 | ||
855 | for (i = 0; i < atmel_pioctrl->nbanks; i++) | |
856 | atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER, | |
857 | atmel_pioctrl->pm_suspend_backup[i]); | |
858 | ||
859 | return 0; | |
860 | } | |
861 | ||
862 | static const struct dev_pm_ops atmel_pctrl_pm_ops = { | |
863 | SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume) | |
864 | }; | |
865 | ||
77618084 LD |
866 | /* |
867 | * The number of banks can be different from a SoC to another one. | |
868 | * We can have up to 16 banks. | |
869 | */ | |
870 | static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = { | |
871 | .nbanks = 4, | |
872 | }; | |
873 | ||
874 | static const struct of_device_id atmel_pctrl_of_match[] = { | |
875 | { | |
876 | .compatible = "atmel,sama5d2-pinctrl", | |
877 | .data = &atmel_sama5d2_pioctrl_data, | |
878 | }, { | |
879 | /* sentinel */ | |
880 | } | |
881 | }; | |
882 | MODULE_DEVICE_TABLE(of, atmel_pctrl_of_match); | |
883 | ||
884 | static int atmel_pinctrl_probe(struct platform_device *pdev) | |
885 | { | |
886 | struct device *dev = &pdev->dev; | |
887 | struct pinctrl_pin_desc *pin_desc; | |
888 | const char **group_names; | |
889 | const struct of_device_id *match; | |
890 | int i, ret; | |
891 | struct resource *res; | |
892 | struct atmel_pioctrl *atmel_pioctrl; | |
893 | struct atmel_pioctrl_data *atmel_pioctrl_data; | |
894 | ||
895 | atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL); | |
896 | if (!atmel_pioctrl) | |
897 | return -ENOMEM; | |
898 | atmel_pioctrl->dev = dev; | |
899 | atmel_pioctrl->node = dev->of_node; | |
900 | platform_set_drvdata(pdev, atmel_pioctrl); | |
901 | ||
902 | match = of_match_node(atmel_pctrl_of_match, dev->of_node); | |
903 | if (!match) { | |
904 | dev_err(dev, "unknown compatible string\n"); | |
905 | return -ENODEV; | |
906 | } | |
907 | atmel_pioctrl_data = (struct atmel_pioctrl_data *)match->data; | |
908 | atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks; | |
909 | atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK; | |
910 | ||
911 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
912 | if (!res) { | |
913 | dev_err(dev, "unable to get atmel pinctrl resource\n"); | |
914 | return -EINVAL; | |
915 | } | |
916 | atmel_pioctrl->reg_base = devm_ioremap_resource(dev, res); | |
917 | if (IS_ERR(atmel_pioctrl->reg_base)) | |
918 | return -EINVAL; | |
919 | ||
920 | atmel_pioctrl->clk = devm_clk_get(dev, NULL); | |
921 | if (IS_ERR(atmel_pioctrl->clk)) { | |
922 | dev_err(dev, "failed to get clock\n"); | |
923 | return PTR_ERR(atmel_pioctrl->clk); | |
924 | } | |
925 | ||
926 | atmel_pioctrl->pins = devm_kzalloc(dev, sizeof(*atmel_pioctrl->pins) | |
927 | * atmel_pioctrl->npins, GFP_KERNEL); | |
928 | if (!atmel_pioctrl->pins) | |
929 | return -ENOMEM; | |
930 | ||
931 | pin_desc = devm_kzalloc(dev, sizeof(*pin_desc) | |
932 | * atmel_pioctrl->npins, GFP_KERNEL); | |
933 | if (!pin_desc) | |
934 | return -ENOMEM; | |
935 | atmel_pinctrl_desc.pins = pin_desc; | |
936 | atmel_pinctrl_desc.npins = atmel_pioctrl->npins; | |
937 | ||
938 | /* One pin is one group since a pin can achieve all functions. */ | |
939 | group_names = devm_kzalloc(dev, sizeof(*group_names) | |
940 | * atmel_pioctrl->npins, GFP_KERNEL); | |
941 | if (!group_names) | |
942 | return -ENOMEM; | |
943 | atmel_pioctrl->group_names = group_names; | |
944 | ||
945 | atmel_pioctrl->groups = devm_kzalloc(&pdev->dev, | |
946 | sizeof(*atmel_pioctrl->groups) * atmel_pioctrl->npins, | |
947 | GFP_KERNEL); | |
948 | if (!atmel_pioctrl->groups) | |
949 | return -ENOMEM; | |
950 | for (i = 0 ; i < atmel_pioctrl->npins; i++) { | |
951 | struct atmel_group *group = atmel_pioctrl->groups + i; | |
952 | unsigned bank = ATMEL_PIO_BANK(i); | |
953 | unsigned line = ATMEL_PIO_LINE(i); | |
954 | ||
955 | atmel_pioctrl->pins[i] = devm_kzalloc(dev, | |
956 | sizeof(**atmel_pioctrl->pins), GFP_KERNEL); | |
957 | if (!atmel_pioctrl->pins[i]) | |
958 | return -ENOMEM; | |
959 | ||
960 | atmel_pioctrl->pins[i]->pin_id = i; | |
961 | atmel_pioctrl->pins[i]->bank = bank; | |
962 | atmel_pioctrl->pins[i]->line = line; | |
963 | ||
964 | pin_desc[i].number = i; | |
965 | /* Pin naming convention: P(bank_name)(bank_pin_number). */ | |
966 | pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d", | |
967 | bank + 'A', line); | |
968 | ||
969 | group->name = group_names[i] = pin_desc[i].name; | |
970 | group->pin = pin_desc[i].number; | |
971 | ||
972 | dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line); | |
973 | } | |
974 | ||
975 | atmel_pioctrl->gpio_chip = &atmel_gpio_chip; | |
976 | atmel_pioctrl->gpio_chip->of_node = dev->of_node; | |
977 | atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins; | |
978 | atmel_pioctrl->gpio_chip->label = dev_name(dev); | |
58383c78 | 979 | atmel_pioctrl->gpio_chip->parent = dev; |
77618084 LD |
980 | atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names; |
981 | ||
de4e882f LD |
982 | atmel_pioctrl->pm_wakeup_sources = devm_kzalloc(dev, |
983 | sizeof(*atmel_pioctrl->pm_wakeup_sources) | |
984 | * atmel_pioctrl->nbanks, GFP_KERNEL); | |
985 | if (!atmel_pioctrl->pm_wakeup_sources) | |
986 | return -ENOMEM; | |
987 | ||
988 | atmel_pioctrl->pm_suspend_backup = devm_kzalloc(dev, | |
989 | sizeof(*atmel_pioctrl->pm_suspend_backup) | |
990 | * atmel_pioctrl->nbanks, GFP_KERNEL); | |
991 | if (!atmel_pioctrl->pm_suspend_backup) | |
992 | return -ENOMEM; | |
993 | ||
77618084 LD |
994 | atmel_pioctrl->irqs = devm_kzalloc(dev, sizeof(*atmel_pioctrl->irqs) |
995 | * atmel_pioctrl->nbanks, GFP_KERNEL); | |
996 | if (!atmel_pioctrl->irqs) | |
997 | return -ENOMEM; | |
998 | ||
999 | /* There is one controller but each bank has its own irq line. */ | |
1000 | for (i = 0; i < atmel_pioctrl->nbanks; i++) { | |
1001 | res = platform_get_resource(pdev, IORESOURCE_IRQ, i); | |
1002 | if (!res) { | |
1003 | dev_err(dev, "missing irq resource for group %c\n", | |
1004 | 'A' + i); | |
1005 | return -EINVAL; | |
1006 | } | |
1007 | atmel_pioctrl->irqs[i] = res->start; | |
1008 | irq_set_chained_handler(res->start, atmel_gpio_irq_handler); | |
1009 | irq_set_handler_data(res->start, atmel_pioctrl); | |
32844138 | 1010 | dev_dbg(dev, "bank %i: irq=%pr\n", i, res); |
77618084 LD |
1011 | } |
1012 | ||
1013 | atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node, | |
1014 | atmel_pioctrl->gpio_chip->ngpio, | |
1015 | &irq_domain_simple_ops, NULL); | |
1016 | if (!atmel_pioctrl->irq_domain) { | |
1017 | dev_err(dev, "can't add the irq domain\n"); | |
1018 | return -ENODEV; | |
1019 | } | |
1020 | atmel_pioctrl->irq_domain->name = "atmel gpio"; | |
1021 | ||
1022 | for (i = 0; i < atmel_pioctrl->npins; i++) { | |
1023 | int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i); | |
1024 | ||
1025 | irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip, | |
1026 | handle_simple_irq); | |
1027 | irq_set_chip_data(irq, atmel_pioctrl); | |
1028 | dev_dbg(dev, | |
1029 | "atmel gpio irq domain: hwirq: %d, linux irq: %d\n", | |
1030 | i, irq); | |
1031 | } | |
1032 | ||
1033 | ret = clk_prepare_enable(atmel_pioctrl->clk); | |
1034 | if (ret) { | |
1035 | dev_err(dev, "failed to prepare and enable clock\n"); | |
1036 | goto clk_prepare_enable_error; | |
1037 | } | |
1038 | ||
1039 | atmel_pioctrl->pinctrl_dev = pinctrl_register(&atmel_pinctrl_desc, | |
1040 | &pdev->dev, | |
1041 | atmel_pioctrl); | |
1042 | if (!atmel_pioctrl->pinctrl_dev) { | |
1043 | dev_err(dev, "pinctrl registration failed\n"); | |
1044 | goto pinctrl_register_error; | |
1045 | } | |
1046 | ||
80036f88 | 1047 | ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl); |
77618084 LD |
1048 | if (ret) { |
1049 | dev_err(dev, "failed to add gpiochip\n"); | |
1050 | goto gpiochip_add_error; | |
1051 | } | |
1052 | ||
1053 | ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev), | |
1054 | 0, 0, atmel_pioctrl->gpio_chip->ngpio); | |
1055 | if (ret) { | |
1056 | dev_err(dev, "failed to add gpio pin range\n"); | |
1057 | goto gpiochip_add_pin_range_error; | |
1058 | } | |
1059 | ||
1060 | dev_info(&pdev->dev, "atmel pinctrl initialized\n"); | |
1061 | ||
1062 | return 0; | |
1063 | ||
1064 | clk_prepare_enable_error: | |
1065 | irq_domain_remove(atmel_pioctrl->irq_domain); | |
1066 | pinctrl_register_error: | |
1067 | clk_disable_unprepare(atmel_pioctrl->clk); | |
1068 | gpiochip_add_error: | |
1069 | pinctrl_unregister(atmel_pioctrl->pinctrl_dev); | |
1070 | gpiochip_add_pin_range_error: | |
1071 | gpiochip_remove(atmel_pioctrl->gpio_chip); | |
1072 | ||
1073 | return ret; | |
1074 | } | |
1075 | ||
1076 | int atmel_pinctrl_remove(struct platform_device *pdev) | |
1077 | { | |
1078 | struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev); | |
1079 | ||
1080 | irq_domain_remove(atmel_pioctrl->irq_domain); | |
1081 | clk_disable_unprepare(atmel_pioctrl->clk); | |
1082 | pinctrl_unregister(atmel_pioctrl->pinctrl_dev); | |
1083 | gpiochip_remove(atmel_pioctrl->gpio_chip); | |
1084 | ||
1085 | return 0; | |
1086 | } | |
1087 | ||
1088 | static struct platform_driver atmel_pinctrl_driver = { | |
1089 | .driver = { | |
1090 | .name = "pinctrl-at91-pio4", | |
1091 | .of_match_table = atmel_pctrl_of_match, | |
de4e882f | 1092 | .pm = &atmel_pctrl_pm_ops, |
77618084 LD |
1093 | }, |
1094 | .probe = atmel_pinctrl_probe, | |
1095 | .remove = atmel_pinctrl_remove, | |
1096 | }; | |
1097 | module_platform_driver(atmel_pinctrl_driver); | |
1098 | ||
1099 | MODULE_AUTHOR(Ludovic Desroches <ludovic.desroches@atmel.com>); | |
1100 | MODULE_DESCRIPTION("Atmel PIO4 pinctrl driver"); | |
1101 | MODULE_LICENSE("GPL v2"); |