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Merge tag 'for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux...
[deliverable/linux.git] / drivers / pinctrl / pinctrl-at91.c
CommitLineData
6732ae5c
JCPV		 1/*
2 * at91 pinctrl driver based on at91 pinmux core
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Under GPLv2 only
7 */
8
9#include <linux/clk.h>
10#include <linux/err.h>
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/slab.h>
18#include <linux/interrupt.h>
6732ae5c
JCPV		 19#include <linux/io.h>
20#include <linux/gpio.h>
6732ae5c
JCPV		 21#include <linux/pinctrl/machine.h>
22#include <linux/pinctrl/pinconf.h>
23#include <linux/pinctrl/pinctrl.h>
24#include <linux/pinctrl/pinmux.h>
25/* Since we request GPIOs from ourself */
26#include <linux/pinctrl/consumer.h>
27
c654b6bf 28#include "pinctrl-at91.h"
6732ae5c
JCPV		 29#include "core.h"
30
94daf85e 31#define MAX_GPIO_BANKS 5
6732ae5c
JCPV		 32#define MAX_NB_GPIO_PER_BANK 32
33
34struct at91_pinctrl_mux_ops;
35
36struct at91_gpio_chip {
37 struct gpio_chip chip;
38 struct pinctrl_gpio_range range;
39 struct at91_gpio_chip *next; /* Bank sharing same clock */
40 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
41 int pioc_virq; /* PIO bank Linux virtual interrupt */
42 int pioc_idx; /* PIO bank index */
43 void __iomem *regbase; /* PIO bank virtual address */
44 struct clk *clock; /* associated clock */
6732ae5c
JCPV		 45 struct at91_pinctrl_mux_ops *ops; /* ops */
46};
47
48#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
49
50static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
51
52static int gpio_banks;
53
525fae21 54#define PULL_UP (1 << 0)
6732ae5c 55#define MULTI_DRIVE (1 << 1)
7ebd7a3a
JCPV		 56#define DEGLITCH (1 << 2)
57#define PULL_DOWN (1 << 3)
58#define DIS_SCHMIT (1 << 4)
4334ac2d
MR		 59#define DRIVE_STRENGTH_SHIFT 5
60#define DRIVE_STRENGTH_MASK 0x3
61#define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
7ebd7a3a
JCPV		 62#define DEBOUNCE (1 << 16)
63#define DEBOUNCE_VAL_SHIFT 17
64#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
6732ae5c 65
4334ac2d
MR		 66/**
67 * These defines will translated the dt binding settings to our internal
68 * settings. They are not necessarily the same value as the register setting.
69 * The actual drive strength current of low, medium and high must be looked up
70 * from the corresponding device datasheet. This value is different for pins
71 * that are even in the same banks. It is also dependent on VCC.
72 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
73 * strength when there is no dt config for it.
74 */
75#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
76#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
77#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
78#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
79
6732ae5c
JCPV		 80/**
81 * struct at91_pmx_func - describes AT91 pinmux functions
82 * @name: the name of this specific function
83 * @groups: corresponding pin groups
84 * @ngroups: the number of groups
85 */
86struct at91_pmx_func {
87 const char *name;
88 const char **groups;
89 unsigned ngroups;
90};
91
92enum at91_mux {
93 AT91_MUX_GPIO = 0,
94 AT91_MUX_PERIPH_A = 1,
95 AT91_MUX_PERIPH_B = 2,
96 AT91_MUX_PERIPH_C = 3,
97 AT91_MUX_PERIPH_D = 4,
98};
99
100/**
101 * struct at91_pmx_pin - describes an At91 pin mux
102 * @bank: the bank of the pin
103 * @pin: the pin number in the @bank
104 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
105 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
106 */
107struct at91_pmx_pin {
108 uint32_t bank;
109 uint32_t pin;
110 enum at91_mux mux;
111 unsigned long conf;
112};
113
114/**
115 * struct at91_pin_group - describes an At91 pin group
116 * @name: the name of this specific pin group
117 * @pins_conf: the mux mode for each pin in this group. The size of this
118 * array is the same as pins.
119 * @pins: an array of discrete physical pins used in this group, taken
120 * from the driver-local pin enumeration space
121 * @npins: the number of pins in this group array, i.e. the number of
122 * elements in .pins so we can iterate over that array
123 */
124struct at91_pin_group {
125 const char *name;
126 struct at91_pmx_pin *pins_conf;
127 unsigned int *pins;
128 unsigned npins;
129};
130
131/**
c2eb9e7f 132 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
6732ae5c
JCPV		 133 * on new IP with support for periph C and D the way to mux in
134 * periph A and B has changed
135 * So provide the right call back
136 * if not present means the IP does not support it
137 * @get_periph: return the periph mode configured
138 * @mux_A_periph: mux as periph A
139 * @mux_B_periph: mux as periph B
140 * @mux_C_periph: mux as periph C
141 * @mux_D_periph: mux as periph D
7ebd7a3a
JCPV		 142 * @get_deglitch: get deglitch status
143 * @set_deglitch: enable/disable deglitch
144 * @get_debounce: get debounce status
145 * @set_debounce: enable/disable debounce
146 * @get_pulldown: get pulldown status
147 * @set_pulldown: enable/disable pulldown
148 * @get_schmitt_trig: get schmitt trigger status
149 * @disable_schmitt_trig: disable schmitt trigger
6732ae5c
JCPV		 150 * @irq_type: return irq type
151 */
152struct at91_pinctrl_mux_ops {
153 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
154 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
155 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
156 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
157 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
7ebd7a3a 158 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
77966ad7 159 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
7ebd7a3a 160 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
77966ad7 161 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
7ebd7a3a 162 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
77966ad7 163 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
7ebd7a3a
JCPV		 164 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
165 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
4334ac2d
MR		 166 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
167 void (*set_drivestrength)(void __iomem *pio, unsigned pin,
168 u32 strength);
6732ae5c
JCPV		 169 /* irq */
170 int (*irq_type)(struct irq_data *d, unsigned type);
171};
172
173static int gpio_irq_type(struct irq_data *d, unsigned type);
174static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
175
176struct at91_pinctrl {
177 struct device *dev;
178 struct pinctrl_dev *pctl;
179
a0b957f3 180 int nactive_banks;
6732ae5c
JCPV		 181
182 uint32_t *mux_mask;
183 int nmux;
184
185 struct at91_pmx_func *functions;
186 int nfunctions;
187
188 struct at91_pin_group *groups;
189 int ngroups;
190
191 struct at91_pinctrl_mux_ops *ops;
192};
193
194static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name(
195 const struct at91_pinctrl *info,
196 const char *name)
197{
198 const struct at91_pin_group *grp = NULL;
199 int i;
200
201 for (i = 0; i < info->ngroups; i++) {
202 if (strcmp(info->groups[i].name, name))
203 continue;
204
205 grp = &info->groups[i];
206 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
207 break;
208 }
209
210 return grp;
211}
212
213static int at91_get_groups_count(struct pinctrl_dev *pctldev)
214{
215 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
216
217 return info->ngroups;
218}
219
220static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
221 unsigned selector)
222{
223 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
224
225 return info->groups[selector].name;
226}
227
228static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
229 const unsigned **pins,
230 unsigned *npins)
231{
232 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
233
234 if (selector >= info->ngroups)
235 return -EINVAL;
236
237 *pins = info->groups[selector].pins;
238 *npins = info->groups[selector].npins;
239
240 return 0;
241}
242
243static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
244 unsigned offset)
245{
246 seq_printf(s, "%s", dev_name(pctldev->dev));
247}
248
249static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
250 struct device_node *np,
251 struct pinctrl_map **map, unsigned *num_maps)
252{
253 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
254 const struct at91_pin_group *grp;
255 struct pinctrl_map *new_map;
256 struct device_node *parent;
257 int map_num = 1;
258 int i;
6732ae5c
JCPV		 259
260 /*
61e310a1 261 * first find the group of this node and check if we need to create
6732ae5c
JCPV		 262 * config maps for pins
263 */
264 grp = at91_pinctrl_find_group_by_name(info, np->name);
265 if (!grp) {
266 dev_err(info->dev, "unable to find group for node %s\n",
267 np->name);
268 return -EINVAL;
269 }
270
271 map_num += grp->npins;
272 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL);
273 if (!new_map)
274 return -ENOMEM;
275
276 *map = new_map;
277 *num_maps = map_num;
278
279 /* create mux map */
280 parent = of_get_parent(np);
281 if (!parent) {
c62b2b34 282 devm_kfree(pctldev->dev, new_map);
6732ae5c
JCPV		 283 return -EINVAL;
284 }
285 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
286 new_map[0].data.mux.function = parent->name;
287 new_map[0].data.mux.group = np->name;
288 of_node_put(parent);
289
290 /* create config map */
291 new_map++;
292 for (i = 0; i < grp->npins; i++) {
6732ae5c
JCPV		 293 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
294 new_map[i].data.configs.group_or_pin =
295 pin_get_name(pctldev, grp->pins[i]);
296 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
297 new_map[i].data.configs.num_configs = 1;
298 }
299
300 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
301 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
302
303 return 0;
304}
305
306static void at91_dt_free_map(struct pinctrl_dev *pctldev,
307 struct pinctrl_map *map, unsigned num_maps)
308{
309}
310
022ab148 311static const struct pinctrl_ops at91_pctrl_ops = {
6732ae5c
JCPV		 312 .get_groups_count = at91_get_groups_count,
313 .get_group_name = at91_get_group_name,
314 .get_group_pins = at91_get_group_pins,
315 .pin_dbg_show = at91_pin_dbg_show,
316 .dt_node_to_map = at91_dt_node_to_map,
317 .dt_free_map = at91_dt_free_map,
318};
319
3c93600d 320static void __iomem *pin_to_controller(struct at91_pinctrl *info,
6732ae5c
JCPV		 321 unsigned int bank)
322{
323 return gpio_chips[bank]->regbase;
324}
325
326static inline int pin_to_bank(unsigned pin)
327{
328 return pin /= MAX_NB_GPIO_PER_BANK;
329}
330
331static unsigned pin_to_mask(unsigned int pin)
332{
333 return 1 << pin;
334}
335
4334ac2d
MR		 336static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
337{
338 /* return the shift value for a pin for "two bit" per pin registers,
339 * i.e. drive strength */
340 return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
341 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
342}
343
344static unsigned sama5d3_get_drive_register(unsigned int pin)
345{
346 /* drive strength is split between two registers
347 * with two bits per pin */
348 return (pin >= MAX_NB_GPIO_PER_BANK/2)
349 ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
350}
351
352static unsigned at91sam9x5_get_drive_register(unsigned int pin)
353{
354 /* drive strength is split between two registers
355 * with two bits per pin */
356 return (pin >= MAX_NB_GPIO_PER_BANK/2)
357 ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
358}
359
6732ae5c
JCPV		 360static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
361{
362 writel_relaxed(mask, pio + PIO_IDR);
363}
364
365static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
366{
05d3534a 367 return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
6732ae5c
JCPV		 368}
369
370static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
371{
3d784273
WY		 372 if (on)
373 writel_relaxed(mask, pio + PIO_PPDDR);
374
6732ae5c
JCPV		 375 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
376}
377
378static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
379{
380 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
381}
382
383static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
384{
385 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
386}
387
388static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
389{
390 writel_relaxed(mask, pio + PIO_ASR);
391}
392
393static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
394{
395 writel_relaxed(mask, pio + PIO_BSR);
396}
397
398static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
399{
400
401 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
402 pio + PIO_ABCDSR1);
403 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
404 pio + PIO_ABCDSR2);
405}
406
407static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
408{
409 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
410 pio + PIO_ABCDSR1);
411 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
412 pio + PIO_ABCDSR2);
413}
414
415static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
416{
417 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
418 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
419}
420
421static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
422{
423 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
424 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
425}
426
427static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
428{
429 unsigned select;
430
431 if (readl_relaxed(pio + PIO_PSR) & mask)
432 return AT91_MUX_GPIO;
433
434 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
435 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
436
437 return select + 1;
438}
439
440static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
441{
442 unsigned select;
443
444 if (readl_relaxed(pio + PIO_PSR) & mask)
445 return AT91_MUX_GPIO;
446
447 select = readl_relaxed(pio + PIO_ABSR) & mask;
448
449 return select + 1;
450}
451
7ebd7a3a
JCPV		 452static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
453{
454 return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1;
455}
456
457static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
458{
459 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
460}
461
c8dba02e
BB		 462static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
463{
464 if ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1)
465 return !((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1);
466
467 return false;
468}
469
7ebd7a3a
JCPV		 470static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
471{
472 if (is_on)
473 __raw_writel(mask, pio + PIO_IFSCDR);
474 at91_mux_set_deglitch(pio, mask, is_on);
475}
476
477static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
478{
479 *div = __raw_readl(pio + PIO_SCDR);
480
c8dba02e
BB		 481 return ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) &&
482 ((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1);
7ebd7a3a
JCPV		 483}
484
485static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
486 bool is_on, u32 div)
487{
488 if (is_on) {
489 __raw_writel(mask, pio + PIO_IFSCER);
490 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
491 __raw_writel(mask, pio + PIO_IFER);
c8dba02e
BB		 492 } else
493 __raw_writel(mask, pio + PIO_IFSCDR);
7ebd7a3a
JCPV		 494}
495
496static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
497{
05d3534a 498 return !((__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1);
7ebd7a3a
JCPV		 499}
500
501static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
502{
3d784273
WY		 503 if (is_on)
504 __raw_writel(mask, pio + PIO_PUDR);
505
7ebd7a3a
JCPV		 506 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
507}
508
509static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
510{
511 __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
512}
513
514static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
515{
516 return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1;
517}
518
4334ac2d
MR		 519static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
520{
521 unsigned tmp = __raw_readl(reg);
522
523 tmp = tmp >> two_bit_pin_value_shift_amount(pin);
524
525 return tmp & DRIVE_STRENGTH_MASK;
526}
527
528static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
529 unsigned pin)
530{
531 unsigned tmp = read_drive_strength(pio +
532 sama5d3_get_drive_register(pin), pin);
533
534 /* SAMA5 strength is 1:1 with our defines,
535 * except 0 is equivalent to low per datasheet */
536 if (!tmp)
537 tmp = DRIVE_STRENGTH_LOW;
538
539 return tmp;
540}
541
542static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
543 unsigned pin)
544{
545 unsigned tmp = read_drive_strength(pio +
546 at91sam9x5_get_drive_register(pin), pin);
547
548 /* strength is inverse in SAM9x5s hardware with the pinctrl defines
549 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
550 tmp = DRIVE_STRENGTH_HI - tmp;
551
552 return tmp;
553}
554
555static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
556{
557 unsigned tmp = __raw_readl(reg);
558 unsigned shift = two_bit_pin_value_shift_amount(pin);
559
560 tmp &= ~(DRIVE_STRENGTH_MASK << shift);
561 tmp |= strength << shift;
562
563 __raw_writel(tmp, reg);
564}
565
566static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
567 u32 setting)
568{
569 /* do nothing if setting is zero */
570 if (!setting)
571 return;
572
573 /* strength is 1 to 1 with setting for SAMA5 */
574 set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
575}
576
577static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
578 u32 setting)
579{
580 /* do nothing if setting is zero */
581 if (!setting)
582 return;
583
584 /* strength is inverse on SAM9x5s with our defines
585 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
586 setting = DRIVE_STRENGTH_HI - setting;
587
588 set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
589 setting);
590}
591
6732ae5c
JCPV		 592static struct at91_pinctrl_mux_ops at91rm9200_ops = {
593 .get_periph = at91_mux_get_periph,
594 .mux_A_periph = at91_mux_set_A_periph,
595 .mux_B_periph = at91_mux_set_B_periph,
7ebd7a3a
JCPV		 596 .get_deglitch = at91_mux_get_deglitch,
597 .set_deglitch = at91_mux_set_deglitch,
6732ae5c
JCPV		 598 .irq_type = gpio_irq_type,
599};
600
601static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
602 .get_periph = at91_mux_pio3_get_periph,
603 .mux_A_periph = at91_mux_pio3_set_A_periph,
604 .mux_B_periph = at91_mux_pio3_set_B_periph,
605 .mux_C_periph = at91_mux_pio3_set_C_periph,
606 .mux_D_periph = at91_mux_pio3_set_D_periph,
c8dba02e 607 .get_deglitch = at91_mux_pio3_get_deglitch,
7ebd7a3a
JCPV		 608 .set_deglitch = at91_mux_pio3_set_deglitch,
609 .get_debounce = at91_mux_pio3_get_debounce,
610 .set_debounce = at91_mux_pio3_set_debounce,
611 .get_pulldown = at91_mux_pio3_get_pulldown,
612 .set_pulldown = at91_mux_pio3_set_pulldown,
613 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
614 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
4334ac2d
MR		 615 .get_drivestrength = at91_mux_sam9x5_get_drivestrength,
616 .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
617 .irq_type = alt_gpio_irq_type,
618};
619
620static struct at91_pinctrl_mux_ops sama5d3_ops = {
621 .get_periph = at91_mux_pio3_get_periph,
622 .mux_A_periph = at91_mux_pio3_set_A_periph,
623 .mux_B_periph = at91_mux_pio3_set_B_periph,
624 .mux_C_periph = at91_mux_pio3_set_C_periph,
625 .mux_D_periph = at91_mux_pio3_set_D_periph,
626 .get_deglitch = at91_mux_pio3_get_deglitch,
627 .set_deglitch = at91_mux_pio3_set_deglitch,
628 .get_debounce = at91_mux_pio3_get_debounce,
629 .set_debounce = at91_mux_pio3_set_debounce,
630 .get_pulldown = at91_mux_pio3_get_pulldown,
631 .set_pulldown = at91_mux_pio3_set_pulldown,
632 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
633 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
634 .get_drivestrength = at91_mux_sama5d3_get_drivestrength,
635 .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
6732ae5c
JCPV		 636 .irq_type = alt_gpio_irq_type,
637};
638
639static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
640{
641 if (pin->mux) {
4b6fe45a 642 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n",
6732ae5c
JCPV		 643 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
644 } else {
4b6fe45a 645 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n",
6732ae5c
JCPV		 646 pin->bank + 'A', pin->pin, pin->conf);
647 }
648}
649
3c93600d 650static int pin_check_config(struct at91_pinctrl *info, const char *name,
6732ae5c
JCPV		 651 int index, const struct at91_pmx_pin *pin)
652{
653 int mux;
654
655 /* check if it's a valid config */
a0b957f3 656 if (pin->bank >= gpio_banks) {
6732ae5c 657 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
a0b957f3 658 name, index, pin->bank, gpio_banks);
6732ae5c
JCPV		 659 return -EINVAL;
660 }
661
a0b957f3
JCPV		 662 if (!gpio_chips[pin->bank]) {
663 dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n",
664 name, index, pin->bank);
665 return -ENXIO;
666 }
667
6732ae5c
JCPV		 668 if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
669 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
670 name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
671 return -EINVAL;
672 }
673
674 if (!pin->mux)
675 return 0;
676
677 mux = pin->mux - 1;
678
679 if (mux >= info->nmux) {
680 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
681 name, index, mux, info->nmux);
682 return -EINVAL;
683 }
684
685 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
686 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
687 name, index, mux, pin->bank + 'A', pin->pin);
688 return -EINVAL;
689 }
690
691 return 0;
692}
693
694static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
695{
696 writel_relaxed(mask, pio + PIO_PDR);
697}
698
699static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
700{
701 writel_relaxed(mask, pio + PIO_PER);
702 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
703}
704
03e9f0ca
LW		 705static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
706 unsigned group)
6732ae5c
JCPV		 707{
708 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
709 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
710 const struct at91_pmx_pin *pin;
711 uint32_t npins = info->groups[group].npins;
712 int i, ret;
713 unsigned mask;
714 void __iomem *pio;
715
716 dev_dbg(info->dev, "enable function %s group %s\n",
717 info->functions[selector].name, info->groups[group].name);
718
719 /* first check that all the pins of the group are valid with a valid
61e310a1 720 * parameter */
6732ae5c
JCPV		 721 for (i = 0; i < npins; i++) {
722 pin = &pins_conf[i];
723 ret = pin_check_config(info, info->groups[group].name, i, pin);
724 if (ret)
725 return ret;
726 }
727
728 for (i = 0; i < npins; i++) {
729 pin = &pins_conf[i];
730 at91_pin_dbg(info->dev, pin);
731 pio = pin_to_controller(info, pin->bank);
732 mask = pin_to_mask(pin->pin);
733 at91_mux_disable_interrupt(pio, mask);
3c93600d 734 switch (pin->mux) {
6732ae5c
JCPV		 735 case AT91_MUX_GPIO:
736 at91_mux_gpio_enable(pio, mask, 1);
737 break;
738 case AT91_MUX_PERIPH_A:
739 info->ops->mux_A_periph(pio, mask);
740 break;
741 case AT91_MUX_PERIPH_B:
742 info->ops->mux_B_periph(pio, mask);
743 break;
744 case AT91_MUX_PERIPH_C:
745 if (!info->ops->mux_C_periph)
746 return -EINVAL;
747 info->ops->mux_C_periph(pio, mask);
748 break;
749 case AT91_MUX_PERIPH_D:
750 if (!info->ops->mux_D_periph)
751 return -EINVAL;
752 info->ops->mux_D_periph(pio, mask);
753 break;
754 }
755 if (pin->mux)
756 at91_mux_gpio_disable(pio, mask);
757 }
758
759 return 0;
760}
761
6732ae5c
JCPV		 762static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
763{
764 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
765
766 return info->nfunctions;
767}
768
769static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
770 unsigned selector)
771{
772 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
773
774 return info->functions[selector].name;
775}
776
777static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
778 const char * const **groups,
779 unsigned * const num_groups)
780{
781 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
782
783 *groups = info->functions[selector].groups;
784 *num_groups = info->functions[selector].ngroups;
785
786 return 0;
787}
788
f6f94f66
AL		 789static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
790 struct pinctrl_gpio_range *range,
791 unsigned offset)
6732ae5c
JCPV		 792{
793 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
794 struct at91_gpio_chip *at91_chip;
795 struct gpio_chip *chip;
796 unsigned mask;
797
798 if (!range) {
799 dev_err(npct->dev, "invalid range\n");
800 return -EINVAL;
801 }
802 if (!range->gc) {
803 dev_err(npct->dev, "missing GPIO chip in range\n");
804 return -EINVAL;
805 }
806 chip = range->gc;
807 at91_chip = container_of(chip, struct at91_gpio_chip, chip);
808
809 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
810
811 mask = 1 << (offset - chip->base);
812
813 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
814 offset, 'A' + range->id, offset - chip->base, mask);
815
816 writel_relaxed(mask, at91_chip->regbase + PIO_PER);
817
818 return 0;
819}
820
f6f94f66
AL		 821static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
822 struct pinctrl_gpio_range *range,
823 unsigned offset)
6732ae5c
JCPV		 824{
825 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
826
827 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
828 /* Set the pin to some default state, GPIO is usually default */
829}
830
022ab148 831static const struct pinmux_ops at91_pmx_ops = {
6732ae5c
JCPV		 832 .get_functions_count = at91_pmx_get_funcs_count,
833 .get_function_name = at91_pmx_get_func_name,
834 .get_function_groups = at91_pmx_get_groups,
03e9f0ca 835 .set_mux = at91_pmx_set,
6732ae5c
JCPV		 836 .gpio_request_enable = at91_gpio_request_enable,
837 .gpio_disable_free = at91_gpio_disable_free,
838};
839
840static int at91_pinconf_get(struct pinctrl_dev *pctldev,
841 unsigned pin_id, unsigned long *config)
842{
843 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
844 void __iomem *pio;
845 unsigned pin;
7ebd7a3a 846 int div;
6732ae5c 847
1292e693
AB		 848 *config = 0;
849 dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
6732ae5c
JCPV		 850 pio = pin_to_controller(info, pin_to_bank(pin_id));
851 pin = pin_id % MAX_NB_GPIO_PER_BANK;
852
853 if (at91_mux_get_multidrive(pio, pin))
854 *config |= MULTI_DRIVE;
855
856 if (at91_mux_get_pullup(pio, pin))
857 *config |= PULL_UP;
858
7ebd7a3a
JCPV		 859 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
860 *config |= DEGLITCH;
861 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
862 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
863 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
864 *config |= PULL_DOWN;
865 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
866 *config |= DIS_SCHMIT;
4334ac2d
MR		 867 if (info->ops->get_drivestrength)
868 *config |= (info->ops->get_drivestrength(pio, pin)
869 << DRIVE_STRENGTH_SHIFT);
7ebd7a3a 870
6732ae5c
JCPV		 871 return 0;
872}
873
874static int at91_pinconf_set(struct pinctrl_dev *pctldev,
03b054e9
SY		 875 unsigned pin_id, unsigned long *configs,
876 unsigned num_configs)
6732ae5c
JCPV		 877{
878 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
879 unsigned mask;
880 void __iomem *pio;
03b054e9
SY		 881 int i;
882 unsigned long config;
4334ac2d 883 unsigned pin;
03b054e9
SY		 884
885 for (i = 0; i < num_configs; i++) {
886 config = configs[i];
887
888 dev_dbg(info->dev,
889 "%s:%d, pin_id=%d, config=0x%lx",
890 __func__, __LINE__, pin_id, config);
891 pio = pin_to_controller(info, pin_to_bank(pin_id));
4334ac2d
MR		 892 pin = pin_id % MAX_NB_GPIO_PER_BANK;
893 mask = pin_to_mask(pin);
03b054e9
SY		 894
895 if (config & PULL_UP && config & PULL_DOWN)
896 return -EINVAL;
897
898 at91_mux_set_pullup(pio, mask, config & PULL_UP);
899 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
900 if (info->ops->set_deglitch)
901 info->ops->set_deglitch(pio, mask, config & DEGLITCH);
902 if (info->ops->set_debounce)
903 info->ops->set_debounce(pio, mask, config & DEBOUNCE,
7ebd7a3a 904 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
03b054e9
SY		 905 if (info->ops->set_pulldown)
906 info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
907 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
908 info->ops->disable_schmitt_trig(pio, mask);
4334ac2d
MR		 909 if (info->ops->set_drivestrength)
910 info->ops->set_drivestrength(pio, pin,
911 (config & DRIVE_STRENGTH)
912 >> DRIVE_STRENGTH_SHIFT);
03b054e9
SY		 913
914 } /* for each config */
7ebd7a3a 915
6732ae5c
JCPV		 916 return 0;
917}
918
4d9b8a8e
AB		 919#define DBG_SHOW_FLAG(flag) do { \
920 if (config & flag) { \
921 if (num_conf) \
922 seq_puts(s, "|"); \
923 seq_puts(s, #flag); \
924 num_conf++; \
925 } \
926} while (0)
927
4334ac2d
MR		 928#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
929 if ((config & mask) == flag) { \
930 if (num_conf) \
931 seq_puts(s, "|"); \
932 seq_puts(s, #flag); \
933 num_conf++; \
934 } \
935} while (0)
936
6732ae5c
JCPV		 937static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
938 struct seq_file *s, unsigned pin_id)
939{
4d9b8a8e 940 unsigned long config;
445d2026 941 int val, num_conf = 0;
4d9b8a8e 942
445d2026 943 at91_pinconf_get(pctldev, pin_id, &config);
4d9b8a8e
AB		 944
945 DBG_SHOW_FLAG(MULTI_DRIVE);
946 DBG_SHOW_FLAG(PULL_UP);
947 DBG_SHOW_FLAG(PULL_DOWN);
948 DBG_SHOW_FLAG(DIS_SCHMIT);
949 DBG_SHOW_FLAG(DEGLITCH);
4334ac2d
MR		 950 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
951 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
952 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
4d9b8a8e
AB		 953 DBG_SHOW_FLAG(DEBOUNCE);
954 if (config & DEBOUNCE) {
955 val = config >> DEBOUNCE_VAL_SHIFT;
956 seq_printf(s, "(%d)", val);
957 }
6732ae5c 958
4d9b8a8e 959 return;
6732ae5c
JCPV		 960}
961
962static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
963 struct seq_file *s, unsigned group)
964{
965}
966
022ab148 967static const struct pinconf_ops at91_pinconf_ops = {
6732ae5c
JCPV		 968 .pin_config_get = at91_pinconf_get,
969 .pin_config_set = at91_pinconf_set,
970 .pin_config_dbg_show = at91_pinconf_dbg_show,
971 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
972};
973
974static struct pinctrl_desc at91_pinctrl_desc = {
975 .pctlops = &at91_pctrl_ops,
976 .pmxops = &at91_pmx_ops,
977 .confops = &at91_pinconf_ops,
978 .owner = THIS_MODULE,
979};
980
981static const char *gpio_compat = "atmel,at91rm9200-gpio";
982
150632b0
GKH		 983static void at91_pinctrl_child_count(struct at91_pinctrl *info,
984 struct device_node *np)
6732ae5c
JCPV		 985{
986 struct device_node *child;
987
988 for_each_child_of_node(np, child) {
989 if (of_device_is_compatible(child, gpio_compat)) {
a0b957f3
JCPV		 990 if (of_device_is_available(child))
991 info->nactive_banks++;
6732ae5c
JCPV		 992 } else {
993 info->nfunctions++;
994 info->ngroups += of_get_child_count(child);
995 }
996 }
997}
998
150632b0
GKH		 999static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
1000 struct device_node *np)
6732ae5c
JCPV		 1001{
1002 int ret = 0;
1003 int size;
1164d73a 1004 const __be32 *list;
6732ae5c
JCPV		 1005
1006 list = of_get_property(np, "atmel,mux-mask", &size);
1007 if (!list) {
1008 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1009 return -EINVAL;
1010 }
1011
1012 size /= sizeof(*list);
a0b957f3
JCPV		 1013 if (!size || size % gpio_banks) {
1014 dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks);
6732ae5c
JCPV		 1015 return -EINVAL;
1016 }
a0b957f3 1017 info->nmux = size / gpio_banks;
6732ae5c
JCPV		 1018
1019 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
1020 if (!info->mux_mask) {
1021 dev_err(info->dev, "could not alloc mux_mask\n");
1022 return -ENOMEM;
1023 }
1024
1025 ret = of_property_read_u32_array(np, "atmel,mux-mask",
1026 info->mux_mask, size);
1027 if (ret)
1028 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1029 return ret;
1030}
1031
150632b0
GKH		 1032static int at91_pinctrl_parse_groups(struct device_node *np,
1033 struct at91_pin_group *grp,
1034 struct at91_pinctrl *info, u32 index)
6732ae5c
JCPV		 1035{
1036 struct at91_pmx_pin *pin;
1037 int size;
1164d73a 1038 const __be32 *list;
6732ae5c
JCPV		 1039 int i, j;
1040
1041 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1042
1043 /* Initialise group */
1044 grp->name = np->name;
1045
1046 /*
1047 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
1048 * do sanity check and calculate pins number
1049 */
1050 list = of_get_property(np, "atmel,pins", &size);
1051 /* we do not check return since it's safe node passed down */
1052 size /= sizeof(*list);
1053 if (!size || size % 4) {
1054 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1055 return -EINVAL;
1056 }
1057
1058 grp->npins = size / 4;
1059 pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin),
1060 GFP_KERNEL);
1061 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1062 GFP_KERNEL);
1063 if (!grp->pins_conf || !grp->pins)
1064 return -ENOMEM;
1065
1066 for (i = 0, j = 0; i < size; i += 4, j++) {
1067 pin->bank = be32_to_cpu(*list++);
1068 pin->pin = be32_to_cpu(*list++);
1069 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
1070 pin->mux = be32_to_cpu(*list++);
1071 pin->conf = be32_to_cpu(*list++);
1072
1073 at91_pin_dbg(info->dev, pin);
1074 pin++;
1075 }
1076
1077 return 0;
1078}
1079
150632b0
GKH		 1080static int at91_pinctrl_parse_functions(struct device_node *np,
1081 struct at91_pinctrl *info, u32 index)
6732ae5c
JCPV		 1082{
1083 struct device_node *child;
1084 struct at91_pmx_func *func;
1085 struct at91_pin_group *grp;
1086 int ret;
1087 static u32 grp_index;
1088 u32 i = 0;
1089
1090 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1091
1092 func = &info->functions[index];
1093
1094 /* Initialise function */
1095 func->name = np->name;
1096 func->ngroups = of_get_child_count(np);
ca7162ad 1097 if (func->ngroups == 0) {
6732ae5c
JCPV		 1098 dev_err(info->dev, "no groups defined\n");
1099 return -EINVAL;
1100 }
1101 func->groups = devm_kzalloc(info->dev,
1102 func->ngroups * sizeof(char *), GFP_KERNEL);
1103 if (!func->groups)
1104 return -ENOMEM;
1105
1106 for_each_child_of_node(np, child) {
1107 func->groups[i] = child->name;
1108 grp = &info->groups[grp_index++];
1109 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
1110 if (ret)
1111 return ret;
1112 }
1113
1114 return 0;
1115}
1116
150632b0 1117static struct of_device_id at91_pinctrl_of_match[] = {
4334ac2d 1118 { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
6732ae5c
JCPV		 1119 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
1120 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
1121 { /* sentinel */ }
1122};
1123
150632b0
GKH		 1124static int at91_pinctrl_probe_dt(struct platform_device *pdev,
1125 struct at91_pinctrl *info)
6732ae5c
JCPV		 1126{
1127 int ret = 0;
1128 int i, j;
1129 uint32_t *tmp;
1130 struct device_node *np = pdev->dev.of_node;
1131 struct device_node *child;
1132
1133 if (!np)
1134 return -ENODEV;
1135
1136 info->dev = &pdev->dev;
3c93600d 1137 info->ops = (struct at91_pinctrl_mux_ops *)
6732ae5c
JCPV		 1138 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
1139 at91_pinctrl_child_count(info, np);
1140
a0b957f3 1141 if (gpio_banks < 1) {
61e310a1 1142 dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
6732ae5c
JCPV		 1143 return -EINVAL;
1144 }
1145
1146 ret = at91_pinctrl_mux_mask(info, np);
1147 if (ret)
1148 return ret;
1149
1150 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
1151
1152 dev_dbg(&pdev->dev, "mux-mask\n");
1153 tmp = info->mux_mask;
a0b957f3 1154 for (i = 0; i < gpio_banks; i++) {
6732ae5c
JCPV		 1155 for (j = 0; j < info->nmux; j++, tmp++) {
1156 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
1157 }
1158 }
1159
1160 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1161 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1162 info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func),
1163 GFP_KERNEL);
1164 if (!info->functions)
1165 return -ENOMEM;
1166
1167 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group),
1168 GFP_KERNEL);
1169 if (!info->groups)
1170 return -ENOMEM;
1171
a0b957f3 1172 dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks);
6732ae5c
JCPV		 1173 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1174 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1175
1176 i = 0;
1177
1178 for_each_child_of_node(np, child) {
1179 if (of_device_is_compatible(child, gpio_compat))
1180 continue;
1181 ret = at91_pinctrl_parse_functions(child, info, i++);
1182 if (ret) {
1183 dev_err(&pdev->dev, "failed to parse function\n");
1184 return ret;
1185 }
1186 }
1187
1188 return 0;
1189}
1190
150632b0 1191static int at91_pinctrl_probe(struct platform_device *pdev)
6732ae5c
JCPV		 1192{
1193 struct at91_pinctrl *info;
1194 struct pinctrl_pin_desc *pdesc;
a0b957f3 1195 int ret, i, j, k, ngpio_chips_enabled = 0;
6732ae5c
JCPV		 1196
1197 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1198 if (!info)
1199 return -ENOMEM;
1200
1201 ret = at91_pinctrl_probe_dt(pdev, info);
1202 if (ret)
1203 return ret;
1204
1205 /*
1206 * We need all the GPIO drivers to probe FIRST, or we will not be able
1207 * to obtain references to the struct gpio_chip * for them, and we
1208 * need this to proceed.
1209 */
a0b957f3
JCPV		 1210 for (i = 0; i < gpio_banks; i++)
1211 if (gpio_chips[i])
1212 ngpio_chips_enabled++;
1213
1214 if (ngpio_chips_enabled < info->nactive_banks) {
1215 dev_warn(&pdev->dev,
1216 "All GPIO chips are not registered yet (%d/%d)\n",
1217 ngpio_chips_enabled, info->nactive_banks);
1218 devm_kfree(&pdev->dev, info);
1219 return -EPROBE_DEFER;
6732ae5c
JCPV		 1220 }
1221
1222 at91_pinctrl_desc.name = dev_name(&pdev->dev);
a0b957f3 1223 at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK;
6732ae5c
JCPV		 1224 at91_pinctrl_desc.pins = pdesc =
1225 devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL);
1226
1227 if (!at91_pinctrl_desc.pins)
1228 return -ENOMEM;
1229
a0b957f3 1230 for (i = 0, k = 0; i < gpio_banks; i++) {
6732ae5c
JCPV		 1231 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1232 pdesc->number = k;
1233 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1234 pdesc++;
1235 }
1236 }
1237
1238 platform_set_drvdata(pdev, info);
1239 info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info);
1240
1241 if (!info->pctl) {
1242 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1243 ret = -EINVAL;
1244 goto err;
1245 }
1246
1247 /* We will handle a range of GPIO pins */
a0b957f3
JCPV		 1248 for (i = 0; i < gpio_banks; i++)
1249 if (gpio_chips[i])
1250 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
6732ae5c
JCPV		 1251
1252 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1253
1254 return 0;
1255
1256err:
1257 return ret;
1258}
1259
150632b0 1260static int at91_pinctrl_remove(struct platform_device *pdev)
6732ae5c
JCPV		 1261{
1262 struct at91_pinctrl *info = platform_get_drvdata(pdev);
1263
1264 pinctrl_unregister(info->pctl);
1265
1266 return 0;
1267}
1268
1269static int at91_gpio_request(struct gpio_chip *chip, unsigned offset)
1270{
1271 /*
1272 * Map back to global GPIO space and request muxing, the direction
1273 * parameter does not matter for this controller.
1274 */
1275 int gpio = chip->base + offset;
1276 int bank = chip->base / chip->ngpio;
1277
1278 dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__,
1279 'A' + bank, offset, gpio);
1280
1281 return pinctrl_request_gpio(gpio);
1282}
1283
1284static void at91_gpio_free(struct gpio_chip *chip, unsigned offset)
1285{
1286 int gpio = chip->base + offset;
1287
1288 pinctrl_free_gpio(gpio);
1289}
1290
8af584b8
RG		 1291static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1292{
1293 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1294 void __iomem *pio = at91_gpio->regbase;
1295 unsigned mask = 1 << offset;
1296 u32 osr;
1297
1298 osr = readl_relaxed(pio + PIO_OSR);
1299 return !(osr & mask);
1300}
1301
6732ae5c
JCPV		 1302static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1303{
1304 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1305 void __iomem *pio = at91_gpio->regbase;
1306 unsigned mask = 1 << offset;
1307
1308 writel_relaxed(mask, pio + PIO_ODR);
1309 return 0;
1310}
1311
1312static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1313{
1314 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1315 void __iomem *pio = at91_gpio->regbase;
1316 unsigned mask = 1 << offset;
1317 u32 pdsr;
1318
1319 pdsr = readl_relaxed(pio + PIO_PDSR);
1320 return (pdsr & mask) != 0;
1321}
1322
1323static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1324 int val)
1325{
1326 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1327 void __iomem *pio = at91_gpio->regbase;
1328 unsigned mask = 1 << offset;
1329
1330 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1331}
1332
1333static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1334 int val)
1335{
1336 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1337 void __iomem *pio = at91_gpio->regbase;
1338 unsigned mask = 1 << offset;
1339
1340 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1341 writel_relaxed(mask, pio + PIO_OER);
1342
1343 return 0;
1344}
1345
6732ae5c
JCPV		 1346#ifdef CONFIG_DEBUG_FS
1347static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1348{
1349 enum at91_mux mode;
1350 int i;
1351 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1352 void __iomem *pio = at91_gpio->regbase;
1353
1354 for (i = 0; i < chip->ngpio; i++) {
47f22716 1355 unsigned mask = pin_to_mask(i);
6732ae5c 1356 const char *gpio_label;
6732ae5c
JCPV		 1357
1358 gpio_label = gpiochip_is_requested(chip, i);
1359 if (!gpio_label)
1360 continue;
1361 mode = at91_gpio->ops->get_periph(pio, mask);
1362 seq_printf(s, "[%s] GPIO%s%d: ",
1363 gpio_label, chip->label, i);
1364 if (mode == AT91_MUX_GPIO) {
853b6bf0
MC		 1365 seq_printf(s, "[gpio] ");
1366 seq_printf(s, "%s ",
1367 readl_relaxed(pio + PIO_OSR) & mask ?
1368 "output" : "input");
1369 seq_printf(s, "%s\n",
1370 readl_relaxed(pio + PIO_PDSR) & mask ?
1371 "set" : "clear");
6732ae5c
JCPV		 1372 } else {
1373 seq_printf(s, "[periph %c]\n",
1374 mode + 'A' - 1);
1375 }
1376 }
1377}
1378#else
1379#define at91_gpio_dbg_show NULL
1380#endif
1381
1382/* Several AIC controller irqs are dispatched through this GPIO handler.
1383 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1384 * at91_set_gpio_input() then maybe enable its glitch filter.
1385 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1386 * handler.
1387 * First implementation always triggers on rising and falling edges
1388 * whereas the newer PIO3 can be additionally configured to trigger on
1389 * level, edge with any polarity.
1390 *
1391 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1392 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1393 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1394 */
1395
1396static void gpio_irq_mask(struct irq_data *d)
1397{
1398 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1399 void __iomem *pio = at91_gpio->regbase;
1400 unsigned mask = 1 << d->hwirq;
1401
1402 if (pio)
1403 writel_relaxed(mask, pio + PIO_IDR);
1404}
1405
1406static void gpio_irq_unmask(struct irq_data *d)
1407{
1408 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1409 void __iomem *pio = at91_gpio->regbase;
1410 unsigned mask = 1 << d->hwirq;
1411
1412 if (pio)
1413 writel_relaxed(mask, pio + PIO_IER);
1414}
1415
1416static int gpio_irq_type(struct irq_data *d, unsigned type)
1417{
1418 switch (type) {
1419 case IRQ_TYPE_NONE:
1420 case IRQ_TYPE_EDGE_BOTH:
1421 return 0;
1422 default:
1423 return -EINVAL;
1424 }
1425}
1426
1427/* Alternate irq type for PIO3 support */
1428static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1429{
1430 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1431 void __iomem *pio = at91_gpio->regbase;
1432 unsigned mask = 1 << d->hwirq;
1433
1434 switch (type) {
1435 case IRQ_TYPE_EDGE_RISING:
b0dcfd87 1436 __irq_set_handler_locked(d->irq, handle_simple_irq);
6732ae5c
JCPV		 1437 writel_relaxed(mask, pio + PIO_ESR);
1438 writel_relaxed(mask, pio + PIO_REHLSR);
1439 break;
1440 case IRQ_TYPE_EDGE_FALLING:
b0dcfd87 1441 __irq_set_handler_locked(d->irq, handle_simple_irq);
6732ae5c
JCPV		 1442 writel_relaxed(mask, pio + PIO_ESR);
1443 writel_relaxed(mask, pio + PIO_FELLSR);
1444 break;
1445 case IRQ_TYPE_LEVEL_LOW:
b0dcfd87 1446 __irq_set_handler_locked(d->irq, handle_level_irq);
6732ae5c
JCPV		 1447 writel_relaxed(mask, pio + PIO_LSR);
1448 writel_relaxed(mask, pio + PIO_FELLSR);
1449 break;
1450 case IRQ_TYPE_LEVEL_HIGH:
b0dcfd87 1451 __irq_set_handler_locked(d->irq, handle_level_irq);
6732ae5c
JCPV		 1452 writel_relaxed(mask, pio + PIO_LSR);
1453 writel_relaxed(mask, pio + PIO_REHLSR);
1454 break;
1455 case IRQ_TYPE_EDGE_BOTH:
1456 /*
1457 * disable additional interrupt modes:
1458 * fall back to default behavior
1459 */
b0dcfd87 1460 __irq_set_handler_locked(d->irq, handle_simple_irq);
6732ae5c
JCPV		 1461 writel_relaxed(mask, pio + PIO_AIMDR);
1462 return 0;
1463 case IRQ_TYPE_NONE:
1464 default:
1465 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
1466 return -EINVAL;
1467 }
1468
1469 /* enable additional interrupt modes */
1470 writel_relaxed(mask, pio + PIO_AIMER);
1471
1472 return 0;
1473}
1474
80cc3732
AS		 1475static void gpio_irq_ack(struct irq_data *d)
1476{
1477 /* the interrupt is already cleared before by reading ISR */
1478}
1479
bd873373 1480static int gpio_irq_request_res(struct irq_data *d)
94e69207
JJH		 1481{
1482 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1483 unsigned pin = d->hwirq;
1484 int ret;
1485
e3a2e878 1486 ret = gpiochip_lock_as_irq(&at91_gpio->chip, pin);
bd873373 1487 if (ret)
94e69207
JJH		 1488 dev_err(at91_gpio->chip.dev, "unable to lock pind %lu IRQ\n",
1489 d->hwirq);
bd873373
BB		 1490
1491 return ret;
94e69207
JJH		 1492}
1493
bd873373 1494static void gpio_irq_release_res(struct irq_data *d)
94e69207
JJH		 1495{
1496 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1497 unsigned pin = d->hwirq;
1498
e3a2e878 1499 gpiochip_unlock_as_irq(&at91_gpio->chip, pin);
94e69207
JJH		 1500}
1501
6732ae5c 1502#ifdef CONFIG_PM
647f8d94
LD		 1503
1504static u32 wakeups[MAX_GPIO_BANKS];
1505static u32 backups[MAX_GPIO_BANKS];
1506
6732ae5c
JCPV		 1507static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1508{
1509 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1510 unsigned bank = at91_gpio->pioc_idx;
647f8d94 1511 unsigned mask = 1 << d->hwirq;
6732ae5c
JCPV		 1512
1513 if (unlikely(bank >= MAX_GPIO_BANKS))
1514 return -EINVAL;
1515
647f8d94
LD		 1516 if (state)
1517 wakeups[bank] |= mask;
1518 else
1519 wakeups[bank] &= ~mask;
1520
6732ae5c
JCPV		 1521 irq_set_irq_wake(at91_gpio->pioc_virq, state);
1522
1523 return 0;
1524}
647f8d94
LD		 1525
1526void at91_pinctrl_gpio_suspend(void)
1527{
1528 int i;
1529
1530 for (i = 0; i < gpio_banks; i++) {
1531 void __iomem *pio;
1532
1533 if (!gpio_chips[i])
1534 continue;
1535
1536 pio = gpio_chips[i]->regbase;
1537
1538 backups[i] = __raw_readl(pio + PIO_IMR);
1539 __raw_writel(backups[i], pio + PIO_IDR);
1540 __raw_writel(wakeups[i], pio + PIO_IER);
1541
795f9953
BB		 1542 if (!wakeups[i])
1543 clk_disable_unprepare(gpio_chips[i]->clock);
1544 else
647f8d94
LD		 1545 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
1546 'A'+i, wakeups[i]);
647f8d94
LD		 1547 }
1548}
1549
1550void at91_pinctrl_gpio_resume(void)
1551{
1552 int i;
1553
1554 for (i = 0; i < gpio_banks; i++) {
1555 void __iomem *pio;
1556
1557 if (!gpio_chips[i])
1558 continue;
1559
1560 pio = gpio_chips[i]->regbase;
1561
37ef1d92
BB		 1562 if (!wakeups[i])
1563 clk_prepare_enable(gpio_chips[i]->clock);
647f8d94
LD		 1564
1565 __raw_writel(wakeups[i], pio + PIO_IDR);
1566 __raw_writel(backups[i], pio + PIO_IER);
1567 }
1568}
1569
6732ae5c
JCPV		 1570#else
1571#define gpio_irq_set_wake NULL
647f8d94 1572#endif /* CONFIG_PM */
6732ae5c
JCPV		 1573
1574static struct irq_chip gpio_irqchip = {
1575 .name = "GPIO",
80cc3732 1576 .irq_ack = gpio_irq_ack,
bd873373
BB		 1577 .irq_request_resources = gpio_irq_request_res,
1578 .irq_release_resources = gpio_irq_release_res,
6732ae5c
JCPV		 1579 .irq_disable = gpio_irq_mask,
1580 .irq_mask = gpio_irq_mask,
1581 .irq_unmask = gpio_irq_unmask,
1582 /* .irq_set_type is set dynamically */
1583 .irq_set_wake = gpio_irq_set_wake,
1584};
1585
1586static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1587{
80cc3732
AS		 1588 struct irq_chip *chip = irq_get_chip(irq);
1589 struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
1590 struct at91_gpio_chip *at91_gpio = container_of(gpio_chip,
1591 struct at91_gpio_chip, chip);
1592
6732ae5c
JCPV		 1593 void __iomem *pio = at91_gpio->regbase;
1594 unsigned long isr;
1595 int n;
1596
1597 chained_irq_enter(chip, desc);
1598 for (;;) {
1599 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
c2eb9e7f 1600 * When there are none pending, we're finished unless we need
6732ae5c
JCPV		 1601 * to process multiple banks (like ID_PIOCDE on sam9263).
1602 */
1603 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1604 if (!isr) {
1605 if (!at91_gpio->next)
1606 break;
1607 at91_gpio = at91_gpio->next;
1608 pio = at91_gpio->regbase;
cccb0c3e 1609 gpio_chip = &at91_gpio->chip;
6732ae5c
JCPV		 1610 continue;
1611 }
1612
05daa16a 1613 for_each_set_bit(n, &isr, BITS_PER_LONG) {
80cc3732
AS		 1614 generic_handle_irq(irq_find_mapping(
1615 gpio_chip->irqdomain, n));
6732ae5c
JCPV		 1616 }
1617 }
1618 chained_irq_exit(chip, desc);
1619 /* now it may re-trigger */
1620}
1621
834e1678 1622static int at91_gpio_of_irq_setup(struct platform_device *pdev,
6732ae5c
JCPV		 1623 struct at91_gpio_chip *at91_gpio)
1624{
a0b957f3 1625 struct gpio_chip *gpiochip_prev = NULL;
cccb0c3e 1626 struct at91_gpio_chip *prev = NULL;
6732ae5c 1627 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
a0b957f3 1628 int ret, i;
6732ae5c
JCPV		 1629
1630 at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1631
1632 /* Setup proper .irq_set_type function */
1633 gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type;
1634
1635 /* Disable irqs of this PIO controller */
1636 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1637
80cc3732
AS		 1638 /*
1639 * Let the generic code handle this edge IRQ, the the chained
1640 * handler will perform the actual work of handling the parent
1641 * interrupt.
1642 */
1643 ret = gpiochip_irqchip_add(&at91_gpio->chip,
1644 &gpio_irqchip,
1645 0,
1646 handle_edge_irq,
1647 IRQ_TYPE_EDGE_BOTH);
834e1678
PG		 1648 if (ret) {
1649 dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n",
6732ae5c 1650 at91_gpio->pioc_idx);
834e1678
PG		 1651 return ret;
1652 }
6732ae5c 1653
cccb0c3e
AS		 1654 /* The top level handler handles one bank of GPIOs, except
1655 * on some SoC it can handle up to three...
1656 * We only set up the handler for the first of the list.
1657 */
a0b957f3
JCPV		 1658 gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
1659 if (!gpiochip_prev) {
1660 /* Then register the chain on the parent IRQ */
1661 gpiochip_set_chained_irqchip(&at91_gpio->chip,
1662 &gpio_irqchip,
1663 at91_gpio->pioc_virq,
1664 gpio_irq_handler);
cccb0c3e 1665 return 0;
a0b957f3 1666 }
cccb0c3e 1667
a0b957f3 1668 prev = container_of(gpiochip_prev, struct at91_gpio_chip, chip);
6732ae5c 1669
a0b957f3
JCPV		 1670 /* we can only have 2 banks before */
1671 for (i = 0; i < 2; i++) {
1672 if (prev->next) {
1673 prev = prev->next;
1674 } else {
1675 prev->next = at91_gpio;
1676 return 0;
1677 }
1678 }
1679
1680 return -EINVAL;
6732ae5c
JCPV		 1681}
1682
1683/* This structure is replicated for each GPIO block allocated at probe time */
1684static struct gpio_chip at91_gpio_template = {
1685 .request = at91_gpio_request,
1686 .free = at91_gpio_free,
8af584b8 1687 .get_direction = at91_gpio_get_direction,
6732ae5c
JCPV		 1688 .direction_input = at91_gpio_direction_input,
1689 .get = at91_gpio_get,
1690 .direction_output = at91_gpio_direction_output,
1691 .set = at91_gpio_set,
6732ae5c 1692 .dbg_show = at91_gpio_dbg_show,
9fb1f39e 1693 .can_sleep = false,
6732ae5c
JCPV		 1694 .ngpio = MAX_NB_GPIO_PER_BANK,
1695};
1696
150632b0 1697static struct of_device_id at91_gpio_of_match[] = {
6732ae5c
JCPV		 1698 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1699 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1700 { /* sentinel */ }
1701};
1702
150632b0 1703static int at91_gpio_probe(struct platform_device *pdev)
6732ae5c
JCPV		 1704{
1705 struct device_node *np = pdev->dev.of_node;
1706 struct resource *res;
1707 struct at91_gpio_chip *at91_chip = NULL;
1708 struct gpio_chip *chip;
1709 struct pinctrl_gpio_range *range;
1710 int ret = 0;
32b01a36 1711 int irq, i;
6732ae5c
JCPV		 1712 int alias_idx = of_alias_get_id(np, "gpio");
1713 uint32_t ngpio;
32b01a36 1714 char **names;
6732ae5c
JCPV		 1715
1716 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1717 if (gpio_chips[alias_idx]) {
1718 ret = -EBUSY;
1719 goto err;
1720 }
1721
6732ae5c
JCPV		 1722 irq = platform_get_irq(pdev, 0);
1723 if (irq < 0) {
1724 ret = irq;
1725 goto err;
1726 }
1727
1728 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1729 if (!at91_chip) {
1730 ret = -ENOMEM;
1731 goto err;
1732 }
1733
f50b9e12 1734 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9e0c1fb2
TR		 1735 at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
1736 if (IS_ERR(at91_chip->regbase)) {
1737 ret = PTR_ERR(at91_chip->regbase);
6732ae5c
JCPV		 1738 goto err;
1739 }
1740
3c93600d 1741 at91_chip->ops = (struct at91_pinctrl_mux_ops *)
6732ae5c
JCPV		 1742 of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1743 at91_chip->pioc_virq = irq;
1744 at91_chip->pioc_idx = alias_idx;
1745
02b837ff 1746 at91_chip->clock = devm_clk_get(&pdev->dev, NULL);
6732ae5c
JCPV		 1747 if (IS_ERR(at91_chip->clock)) {
1748 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
70e41974 1749 ret = PTR_ERR(at91_chip->clock);
6732ae5c
JCPV		 1750 goto err;
1751 }
1752
70e41974
PG		 1753 ret = clk_prepare(at91_chip->clock);
1754 if (ret)
1755 goto clk_prepare_err;
6732ae5c
JCPV		 1756
1757 /* enable PIO controller's clock */
70e41974
PG		 1758 ret = clk_enable(at91_chip->clock);
1759 if (ret) {
6732ae5c 1760 dev_err(&pdev->dev, "failed to enable clock, ignoring.\n");
70e41974 1761 goto clk_enable_err;
6732ae5c
JCPV		 1762 }
1763
1764 at91_chip->chip = at91_gpio_template;
1765
1766 chip = &at91_chip->chip;
1767 chip->of_node = np;
1768 chip->label = dev_name(&pdev->dev);
1769 chip->dev = &pdev->dev;
1770 chip->owner = THIS_MODULE;
1771 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1772
1773 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1774 if (ngpio >= MAX_NB_GPIO_PER_BANK)
1775 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1776 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1777 else
1778 chip->ngpio = ngpio;
1779 }
1780
3c93600d
SK		 1781 names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio,
1782 GFP_KERNEL);
32b01a36
JCPV		 1783
1784 if (!names) {
1785 ret = -ENOMEM;
70e41974 1786 goto clk_enable_err;
32b01a36
JCPV		 1787 }
1788
1789 for (i = 0; i < chip->ngpio; i++)
1790 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1791
3c93600d 1792 chip->names = (const char *const *)names;
32b01a36 1793
6732ae5c
JCPV		 1794 range = &at91_chip->range;
1795 range->name = chip->label;
1796 range->id = alias_idx;
1797 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1798
1799 range->npins = chip->ngpio;
1800 range->gc = chip;
1801
1802 ret = gpiochip_add(chip);
1803 if (ret)
70e41974 1804 goto gpiochip_add_err;
6732ae5c
JCPV		 1805
1806 gpio_chips[alias_idx] = at91_chip;
1807 gpio_banks = max(gpio_banks, alias_idx + 1);
1808
834e1678
PG		 1809 ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1810 if (ret)
1811 goto irq_setup_err;
6732ae5c
JCPV		 1812
1813 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1814
1815 return 0;
1816
834e1678
PG		 1817irq_setup_err:
1818 gpiochip_remove(chip);
70e41974
PG		 1819gpiochip_add_err:
1820 clk_disable(at91_chip->clock);
1821clk_enable_err:
6732ae5c 1822 clk_unprepare(at91_chip->clock);
70e41974 1823clk_prepare_err:
6732ae5c
JCPV		 1824err:
1825 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1826
1827 return ret;
1828}
1829
1830static struct platform_driver at91_gpio_driver = {
1831 .driver = {
1832 .name = "gpio-at91",
606fca94 1833 .of_match_table = at91_gpio_of_match,
6732ae5c
JCPV		 1834 },
1835 .probe = at91_gpio_probe,
1836};
1837
1838static struct platform_driver at91_pinctrl_driver = {
1839 .driver = {
1840 .name = "pinctrl-at91",
606fca94 1841 .of_match_table = at91_pinctrl_of_match,
6732ae5c
JCPV		 1842 },
1843 .probe = at91_pinctrl_probe,
150632b0 1844 .remove = at91_pinctrl_remove,
6732ae5c
JCPV		 1845};
1846
1847static int __init at91_pinctrl_init(void)
1848{
1849 int ret;
1850
1851 ret = platform_driver_register(&at91_gpio_driver);
1852 if (ret)
1853 return ret;
1854 return platform_driver_register(&at91_pinctrl_driver);
1855}
1856arch_initcall(at91_pinctrl_init);
1857
1858static void __exit at91_pinctrl_exit(void)
1859{
1860 platform_driver_unregister(&at91_pinctrl_driver);
1861}
1862
1863module_exit(at91_pinctrl_exit);
1864MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>");
1865MODULE_DESCRIPTION("Atmel AT91 pinctrl driver");
1866MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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