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pinctrl: st: remove gpiochip in failure cases
[deliverable/linux.git] / drivers / pinctrl / pinctrl-at91.c
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6732ae5c
JCPV		 1/*
2 * at91 pinctrl driver based on at91 pinmux core
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Under GPLv2 only
7 */
8
9#include <linux/clk.h>
10#include <linux/err.h>
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/slab.h>
18#include <linux/interrupt.h>
6732ae5c
JCPV		 19#include <linux/io.h>
20#include <linux/gpio.h>
6732ae5c
JCPV		 21#include <linux/pinctrl/machine.h>
22#include <linux/pinctrl/pinconf.h>
23#include <linux/pinctrl/pinctrl.h>
24#include <linux/pinctrl/pinmux.h>
25/* Since we request GPIOs from ourself */
26#include <linux/pinctrl/consumer.h>
27
6732ae5c
JCPV		 28#include <mach/hardware.h>
29#include <mach/at91_pio.h>
30
31#include "core.h"
32
94daf85e 33#define MAX_GPIO_BANKS 5
6732ae5c
JCPV		 34#define MAX_NB_GPIO_PER_BANK 32
35
36struct at91_pinctrl_mux_ops;
37
38struct at91_gpio_chip {
39 struct gpio_chip chip;
40 struct pinctrl_gpio_range range;
41 struct at91_gpio_chip *next; /* Bank sharing same clock */
42 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
43 int pioc_virq; /* PIO bank Linux virtual interrupt */
44 int pioc_idx; /* PIO bank index */
45 void __iomem *regbase; /* PIO bank virtual address */
46 struct clk *clock; /* associated clock */
6732ae5c
JCPV		 47 struct at91_pinctrl_mux_ops *ops; /* ops */
48};
49
50#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
51
52static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
53
54static int gpio_banks;
55
525fae21 56#define PULL_UP (1 << 0)
6732ae5c 57#define MULTI_DRIVE (1 << 1)
7ebd7a3a
JCPV		 58#define DEGLITCH (1 << 2)
59#define PULL_DOWN (1 << 3)
60#define DIS_SCHMIT (1 << 4)
4334ac2d
MR		 61#define DRIVE_STRENGTH_SHIFT 5
62#define DRIVE_STRENGTH_MASK 0x3
63#define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
7ebd7a3a
JCPV		 64#define DEBOUNCE (1 << 16)
65#define DEBOUNCE_VAL_SHIFT 17
66#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
6732ae5c 67
4334ac2d
MR		 68/**
69 * These defines will translated the dt binding settings to our internal
70 * settings. They are not necessarily the same value as the register setting.
71 * The actual drive strength current of low, medium and high must be looked up
72 * from the corresponding device datasheet. This value is different for pins
73 * that are even in the same banks. It is also dependent on VCC.
74 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
75 * strength when there is no dt config for it.
76 */
77#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
78#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
79#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
80#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
81
6732ae5c
JCPV		 82/**
83 * struct at91_pmx_func - describes AT91 pinmux functions
84 * @name: the name of this specific function
85 * @groups: corresponding pin groups
86 * @ngroups: the number of groups
87 */
88struct at91_pmx_func {
89 const char *name;
90 const char **groups;
91 unsigned ngroups;
92};
93
94enum at91_mux {
95 AT91_MUX_GPIO = 0,
96 AT91_MUX_PERIPH_A = 1,
97 AT91_MUX_PERIPH_B = 2,
98 AT91_MUX_PERIPH_C = 3,
99 AT91_MUX_PERIPH_D = 4,
100};
101
102/**
103 * struct at91_pmx_pin - describes an At91 pin mux
104 * @bank: the bank of the pin
105 * @pin: the pin number in the @bank
106 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
107 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
108 */
109struct at91_pmx_pin {
110 uint32_t bank;
111 uint32_t pin;
112 enum at91_mux mux;
113 unsigned long conf;
114};
115
116/**
117 * struct at91_pin_group - describes an At91 pin group
118 * @name: the name of this specific pin group
119 * @pins_conf: the mux mode for each pin in this group. The size of this
120 * array is the same as pins.
121 * @pins: an array of discrete physical pins used in this group, taken
122 * from the driver-local pin enumeration space
123 * @npins: the number of pins in this group array, i.e. the number of
124 * elements in .pins so we can iterate over that array
125 */
126struct at91_pin_group {
127 const char *name;
128 struct at91_pmx_pin *pins_conf;
129 unsigned int *pins;
130 unsigned npins;
131};
132
133/**
c2eb9e7f 134 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
6732ae5c
JCPV		 135 * on new IP with support for periph C and D the way to mux in
136 * periph A and B has changed
137 * So provide the right call back
138 * if not present means the IP does not support it
139 * @get_periph: return the periph mode configured
140 * @mux_A_periph: mux as periph A
141 * @mux_B_periph: mux as periph B
142 * @mux_C_periph: mux as periph C
143 * @mux_D_periph: mux as periph D
7ebd7a3a
JCPV		 144 * @get_deglitch: get deglitch status
145 * @set_deglitch: enable/disable deglitch
146 * @get_debounce: get debounce status
147 * @set_debounce: enable/disable debounce
148 * @get_pulldown: get pulldown status
149 * @set_pulldown: enable/disable pulldown
150 * @get_schmitt_trig: get schmitt trigger status
151 * @disable_schmitt_trig: disable schmitt trigger
6732ae5c
JCPV		 152 * @irq_type: return irq type
153 */
154struct at91_pinctrl_mux_ops {
155 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
156 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
157 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
158 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
159 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
7ebd7a3a 160 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
77966ad7 161 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
7ebd7a3a 162 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
77966ad7 163 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
7ebd7a3a 164 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
77966ad7 165 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
7ebd7a3a
JCPV		 166 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
167 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
4334ac2d
MR		 168 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
169 void (*set_drivestrength)(void __iomem *pio, unsigned pin,
170 u32 strength);
6732ae5c
JCPV		 171 /* irq */
172 int (*irq_type)(struct irq_data *d, unsigned type);
173};
174
175static int gpio_irq_type(struct irq_data *d, unsigned type);
176static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
177
178struct at91_pinctrl {
179 struct device *dev;
180 struct pinctrl_dev *pctl;
181
182 int nbanks;
183
184 uint32_t *mux_mask;
185 int nmux;
186
187 struct at91_pmx_func *functions;
188 int nfunctions;
189
190 struct at91_pin_group *groups;
191 int ngroups;
192
193 struct at91_pinctrl_mux_ops *ops;
194};
195
196static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name(
197 const struct at91_pinctrl *info,
198 const char *name)
199{
200 const struct at91_pin_group *grp = NULL;
201 int i;
202
203 for (i = 0; i < info->ngroups; i++) {
204 if (strcmp(info->groups[i].name, name))
205 continue;
206
207 grp = &info->groups[i];
208 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
209 break;
210 }
211
212 return grp;
213}
214
215static int at91_get_groups_count(struct pinctrl_dev *pctldev)
216{
217 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
218
219 return info->ngroups;
220}
221
222static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
223 unsigned selector)
224{
225 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
226
227 return info->groups[selector].name;
228}
229
230static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
231 const unsigned **pins,
232 unsigned *npins)
233{
234 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
235
236 if (selector >= info->ngroups)
237 return -EINVAL;
238
239 *pins = info->groups[selector].pins;
240 *npins = info->groups[selector].npins;
241
242 return 0;
243}
244
245static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
246 unsigned offset)
247{
248 seq_printf(s, "%s", dev_name(pctldev->dev));
249}
250
251static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
252 struct device_node *np,
253 struct pinctrl_map **map, unsigned *num_maps)
254{
255 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
256 const struct at91_pin_group *grp;
257 struct pinctrl_map *new_map;
258 struct device_node *parent;
259 int map_num = 1;
260 int i;
6732ae5c
JCPV		 261
262 /*
61e310a1 263 * first find the group of this node and check if we need to create
6732ae5c
JCPV		 264 * config maps for pins
265 */
266 grp = at91_pinctrl_find_group_by_name(info, np->name);
267 if (!grp) {
268 dev_err(info->dev, "unable to find group for node %s\n",
269 np->name);
270 return -EINVAL;
271 }
272
273 map_num += grp->npins;
274 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL);
275 if (!new_map)
276 return -ENOMEM;
277
278 *map = new_map;
279 *num_maps = map_num;
280
281 /* create mux map */
282 parent = of_get_parent(np);
283 if (!parent) {
c62b2b34 284 devm_kfree(pctldev->dev, new_map);
6732ae5c
JCPV		 285 return -EINVAL;
286 }
287 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
288 new_map[0].data.mux.function = parent->name;
289 new_map[0].data.mux.group = np->name;
290 of_node_put(parent);
291
292 /* create config map */
293 new_map++;
294 for (i = 0; i < grp->npins; i++) {
6732ae5c
JCPV		 295 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
296 new_map[i].data.configs.group_or_pin =
297 pin_get_name(pctldev, grp->pins[i]);
298 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
299 new_map[i].data.configs.num_configs = 1;
300 }
301
302 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
303 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
304
305 return 0;
306}
307
308static void at91_dt_free_map(struct pinctrl_dev *pctldev,
309 struct pinctrl_map *map, unsigned num_maps)
310{
311}
312
022ab148 313static const struct pinctrl_ops at91_pctrl_ops = {
6732ae5c
JCPV		 314 .get_groups_count = at91_get_groups_count,
315 .get_group_name = at91_get_group_name,
316 .get_group_pins = at91_get_group_pins,
317 .pin_dbg_show = at91_pin_dbg_show,
318 .dt_node_to_map = at91_dt_node_to_map,
319 .dt_free_map = at91_dt_free_map,
320};
321
3c93600d 322static void __iomem *pin_to_controller(struct at91_pinctrl *info,
6732ae5c
JCPV		 323 unsigned int bank)
324{
325 return gpio_chips[bank]->regbase;
326}
327
328static inline int pin_to_bank(unsigned pin)
329{
330 return pin /= MAX_NB_GPIO_PER_BANK;
331}
332
333static unsigned pin_to_mask(unsigned int pin)
334{
335 return 1 << pin;
336}
337
4334ac2d
MR		 338static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
339{
340 /* return the shift value for a pin for "two bit" per pin registers,
341 * i.e. drive strength */
342 return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
343 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
344}
345
346static unsigned sama5d3_get_drive_register(unsigned int pin)
347{
348 /* drive strength is split between two registers
349 * with two bits per pin */
350 return (pin >= MAX_NB_GPIO_PER_BANK/2)
351 ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
352}
353
354static unsigned at91sam9x5_get_drive_register(unsigned int pin)
355{
356 /* drive strength is split between two registers
357 * with two bits per pin */
358 return (pin >= MAX_NB_GPIO_PER_BANK/2)
359 ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
360}
361
6732ae5c
JCPV		 362static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
363{
364 writel_relaxed(mask, pio + PIO_IDR);
365}
366
367static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
368{
05d3534a 369 return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
6732ae5c
JCPV		 370}
371
372static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
373{
374 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
375}
376
377static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
378{
379 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
380}
381
382static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
383{
384 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
385}
386
387static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
388{
389 writel_relaxed(mask, pio + PIO_ASR);
390}
391
392static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
393{
394 writel_relaxed(mask, pio + PIO_BSR);
395}
396
397static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
398{
399
400 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
401 pio + PIO_ABCDSR1);
402 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
403 pio + PIO_ABCDSR2);
404}
405
406static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
407{
408 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
409 pio + PIO_ABCDSR1);
410 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
411 pio + PIO_ABCDSR2);
412}
413
414static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
415{
416 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
417 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
418}
419
420static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
421{
422 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
423 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
424}
425
426static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
427{
428 unsigned select;
429
430 if (readl_relaxed(pio + PIO_PSR) & mask)
431 return AT91_MUX_GPIO;
432
433 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
434 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
435
436 return select + 1;
437}
438
439static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
440{
441 unsigned select;
442
443 if (readl_relaxed(pio + PIO_PSR) & mask)
444 return AT91_MUX_GPIO;
445
446 select = readl_relaxed(pio + PIO_ABSR) & mask;
447
448 return select + 1;
449}
450
7ebd7a3a
JCPV		 451static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
452{
453 return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1;
454}
455
456static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
457{
458 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
459}
460
c8dba02e
BB		 461static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
462{
463 if ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1)
464 return !((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1);
465
466 return false;
467}
468
7ebd7a3a
JCPV		 469static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
470{
471 if (is_on)
472 __raw_writel(mask, pio + PIO_IFSCDR);
473 at91_mux_set_deglitch(pio, mask, is_on);
474}
475
476static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
477{
478 *div = __raw_readl(pio + PIO_SCDR);
479
c8dba02e
BB		 480 return ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) &&
481 ((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1);
7ebd7a3a
JCPV		 482}
483
484static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
485 bool is_on, u32 div)
486{
487 if (is_on) {
488 __raw_writel(mask, pio + PIO_IFSCER);
489 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
490 __raw_writel(mask, pio + PIO_IFER);
c8dba02e
BB		 491 } else
492 __raw_writel(mask, pio + PIO_IFSCDR);
7ebd7a3a
JCPV		 493}
494
495static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
496{
05d3534a 497 return !((__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1);
7ebd7a3a
JCPV		 498}
499
500static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
501{
502 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
503}
504
505static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
506{
507 __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
508}
509
510static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
511{
512 return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1;
513}
514
4334ac2d
MR		 515static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
516{
517 unsigned tmp = __raw_readl(reg);
518
519 tmp = tmp >> two_bit_pin_value_shift_amount(pin);
520
521 return tmp & DRIVE_STRENGTH_MASK;
522}
523
524static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
525 unsigned pin)
526{
527 unsigned tmp = read_drive_strength(pio +
528 sama5d3_get_drive_register(pin), pin);
529
530 /* SAMA5 strength is 1:1 with our defines,
531 * except 0 is equivalent to low per datasheet */
532 if (!tmp)
533 tmp = DRIVE_STRENGTH_LOW;
534
535 return tmp;
536}
537
538static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
539 unsigned pin)
540{
541 unsigned tmp = read_drive_strength(pio +
542 at91sam9x5_get_drive_register(pin), pin);
543
544 /* strength is inverse in SAM9x5s hardware with the pinctrl defines
545 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
546 tmp = DRIVE_STRENGTH_HI - tmp;
547
548 return tmp;
549}
550
551static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
552{
553 unsigned tmp = __raw_readl(reg);
554 unsigned shift = two_bit_pin_value_shift_amount(pin);
555
556 tmp &= ~(DRIVE_STRENGTH_MASK << shift);
557 tmp |= strength << shift;
558
559 __raw_writel(tmp, reg);
560}
561
562static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
563 u32 setting)
564{
565 /* do nothing if setting is zero */
566 if (!setting)
567 return;
568
569 /* strength is 1 to 1 with setting for SAMA5 */
570 set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
571}
572
573static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
574 u32 setting)
575{
576 /* do nothing if setting is zero */
577 if (!setting)
578 return;
579
580 /* strength is inverse on SAM9x5s with our defines
581 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
582 setting = DRIVE_STRENGTH_HI - setting;
583
584 set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
585 setting);
586}
587
6732ae5c
JCPV		 588static struct at91_pinctrl_mux_ops at91rm9200_ops = {
589 .get_periph = at91_mux_get_periph,
590 .mux_A_periph = at91_mux_set_A_periph,
591 .mux_B_periph = at91_mux_set_B_periph,
7ebd7a3a
JCPV		 592 .get_deglitch = at91_mux_get_deglitch,
593 .set_deglitch = at91_mux_set_deglitch,
6732ae5c
JCPV		 594 .irq_type = gpio_irq_type,
595};
596
597static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
598 .get_periph = at91_mux_pio3_get_periph,
599 .mux_A_periph = at91_mux_pio3_set_A_periph,
600 .mux_B_periph = at91_mux_pio3_set_B_periph,
601 .mux_C_periph = at91_mux_pio3_set_C_periph,
602 .mux_D_periph = at91_mux_pio3_set_D_periph,
c8dba02e 603 .get_deglitch = at91_mux_pio3_get_deglitch,
7ebd7a3a
JCPV		 604 .set_deglitch = at91_mux_pio3_set_deglitch,
605 .get_debounce = at91_mux_pio3_get_debounce,
606 .set_debounce = at91_mux_pio3_set_debounce,
607 .get_pulldown = at91_mux_pio3_get_pulldown,
608 .set_pulldown = at91_mux_pio3_set_pulldown,
609 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
610 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
4334ac2d
MR		 611 .get_drivestrength = at91_mux_sam9x5_get_drivestrength,
612 .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
613 .irq_type = alt_gpio_irq_type,
614};
615
616static struct at91_pinctrl_mux_ops sama5d3_ops = {
617 .get_periph = at91_mux_pio3_get_periph,
618 .mux_A_periph = at91_mux_pio3_set_A_periph,
619 .mux_B_periph = at91_mux_pio3_set_B_periph,
620 .mux_C_periph = at91_mux_pio3_set_C_periph,
621 .mux_D_periph = at91_mux_pio3_set_D_periph,
622 .get_deglitch = at91_mux_pio3_get_deglitch,
623 .set_deglitch = at91_mux_pio3_set_deglitch,
624 .get_debounce = at91_mux_pio3_get_debounce,
625 .set_debounce = at91_mux_pio3_set_debounce,
626 .get_pulldown = at91_mux_pio3_get_pulldown,
627 .set_pulldown = at91_mux_pio3_set_pulldown,
628 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
629 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
630 .get_drivestrength = at91_mux_sama5d3_get_drivestrength,
631 .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
6732ae5c
JCPV		 632 .irq_type = alt_gpio_irq_type,
633};
634
635static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
636{
637 if (pin->mux) {
638 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n",
639 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
640 } else {
641 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n",
642 pin->bank + 'A', pin->pin, pin->conf);
643 }
644}
645
3c93600d 646static int pin_check_config(struct at91_pinctrl *info, const char *name,
6732ae5c
JCPV		 647 int index, const struct at91_pmx_pin *pin)
648{
649 int mux;
650
651 /* check if it's a valid config */
652 if (pin->bank >= info->nbanks) {
653 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
654 name, index, pin->bank, info->nbanks);
655 return -EINVAL;
656 }
657
658 if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
659 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
660 name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
661 return -EINVAL;
662 }
663
664 if (!pin->mux)
665 return 0;
666
667 mux = pin->mux - 1;
668
669 if (mux >= info->nmux) {
670 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
671 name, index, mux, info->nmux);
672 return -EINVAL;
673 }
674
675 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
676 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
677 name, index, mux, pin->bank + 'A', pin->pin);
678 return -EINVAL;
679 }
680
681 return 0;
682}
683
684static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
685{
686 writel_relaxed(mask, pio + PIO_PDR);
687}
688
689static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
690{
691 writel_relaxed(mask, pio + PIO_PER);
692 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
693}
694
03e9f0ca
LW		 695static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
696 unsigned group)
6732ae5c
JCPV		 697{
698 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
699 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
700 const struct at91_pmx_pin *pin;
701 uint32_t npins = info->groups[group].npins;
702 int i, ret;
703 unsigned mask;
704 void __iomem *pio;
705
706 dev_dbg(info->dev, "enable function %s group %s\n",
707 info->functions[selector].name, info->groups[group].name);
708
709 /* first check that all the pins of the group are valid with a valid
61e310a1 710 * parameter */
6732ae5c
JCPV		 711 for (i = 0; i < npins; i++) {
712 pin = &pins_conf[i];
713 ret = pin_check_config(info, info->groups[group].name, i, pin);
714 if (ret)
715 return ret;
716 }
717
718 for (i = 0; i < npins; i++) {
719 pin = &pins_conf[i];
720 at91_pin_dbg(info->dev, pin);
721 pio = pin_to_controller(info, pin->bank);
722 mask = pin_to_mask(pin->pin);
723 at91_mux_disable_interrupt(pio, mask);
3c93600d 724 switch (pin->mux) {
6732ae5c
JCPV		 725 case AT91_MUX_GPIO:
726 at91_mux_gpio_enable(pio, mask, 1);
727 break;
728 case AT91_MUX_PERIPH_A:
729 info->ops->mux_A_periph(pio, mask);
730 break;
731 case AT91_MUX_PERIPH_B:
732 info->ops->mux_B_periph(pio, mask);
733 break;
734 case AT91_MUX_PERIPH_C:
735 if (!info->ops->mux_C_periph)
736 return -EINVAL;
737 info->ops->mux_C_periph(pio, mask);
738 break;
739 case AT91_MUX_PERIPH_D:
740 if (!info->ops->mux_D_periph)
741 return -EINVAL;
742 info->ops->mux_D_periph(pio, mask);
743 break;
744 }
745 if (pin->mux)
746 at91_mux_gpio_disable(pio, mask);
747 }
748
749 return 0;
750}
751
6732ae5c
JCPV		 752static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
753{
754 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
755
756 return info->nfunctions;
757}
758
759static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
760 unsigned selector)
761{
762 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
763
764 return info->functions[selector].name;
765}
766
767static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
768 const char * const **groups,
769 unsigned * const num_groups)
770{
771 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
772
773 *groups = info->functions[selector].groups;
774 *num_groups = info->functions[selector].ngroups;
775
776 return 0;
777}
778
f6f94f66
AL		 779static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
780 struct pinctrl_gpio_range *range,
781 unsigned offset)
6732ae5c
JCPV		 782{
783 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
784 struct at91_gpio_chip *at91_chip;
785 struct gpio_chip *chip;
786 unsigned mask;
787
788 if (!range) {
789 dev_err(npct->dev, "invalid range\n");
790 return -EINVAL;
791 }
792 if (!range->gc) {
793 dev_err(npct->dev, "missing GPIO chip in range\n");
794 return -EINVAL;
795 }
796 chip = range->gc;
797 at91_chip = container_of(chip, struct at91_gpio_chip, chip);
798
799 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
800
801 mask = 1 << (offset - chip->base);
802
803 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
804 offset, 'A' + range->id, offset - chip->base, mask);
805
806 writel_relaxed(mask, at91_chip->regbase + PIO_PER);
807
808 return 0;
809}
810
f6f94f66
AL		 811static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
812 struct pinctrl_gpio_range *range,
813 unsigned offset)
6732ae5c
JCPV		 814{
815 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
816
817 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
818 /* Set the pin to some default state, GPIO is usually default */
819}
820
022ab148 821static const struct pinmux_ops at91_pmx_ops = {
6732ae5c
JCPV		 822 .get_functions_count = at91_pmx_get_funcs_count,
823 .get_function_name = at91_pmx_get_func_name,
824 .get_function_groups = at91_pmx_get_groups,
03e9f0ca 825 .set_mux = at91_pmx_set,
6732ae5c
JCPV		 826 .gpio_request_enable = at91_gpio_request_enable,
827 .gpio_disable_free = at91_gpio_disable_free,
828};
829
830static int at91_pinconf_get(struct pinctrl_dev *pctldev,
831 unsigned pin_id, unsigned long *config)
832{
833 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
834 void __iomem *pio;
835 unsigned pin;
7ebd7a3a 836 int div;
6732ae5c 837
1292e693
AB		 838 *config = 0;
839 dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
6732ae5c
JCPV		 840 pio = pin_to_controller(info, pin_to_bank(pin_id));
841 pin = pin_id % MAX_NB_GPIO_PER_BANK;
842
843 if (at91_mux_get_multidrive(pio, pin))
844 *config |= MULTI_DRIVE;
845
846 if (at91_mux_get_pullup(pio, pin))
847 *config |= PULL_UP;
848
7ebd7a3a
JCPV		 849 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
850 *config |= DEGLITCH;
851 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
852 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
853 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
854 *config |= PULL_DOWN;
855 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
856 *config |= DIS_SCHMIT;
4334ac2d
MR		 857 if (info->ops->get_drivestrength)
858 *config |= (info->ops->get_drivestrength(pio, pin)
859 << DRIVE_STRENGTH_SHIFT);
7ebd7a3a 860
6732ae5c
JCPV		 861 return 0;
862}
863
864static int at91_pinconf_set(struct pinctrl_dev *pctldev,
03b054e9
SY		 865 unsigned pin_id, unsigned long *configs,
866 unsigned num_configs)
6732ae5c
JCPV		 867{
868 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
869 unsigned mask;
870 void __iomem *pio;
03b054e9
SY		 871 int i;
872 unsigned long config;
4334ac2d 873 unsigned pin;
03b054e9
SY		 874
875 for (i = 0; i < num_configs; i++) {
876 config = configs[i];
877
878 dev_dbg(info->dev,
879 "%s:%d, pin_id=%d, config=0x%lx",
880 __func__, __LINE__, pin_id, config);
881 pio = pin_to_controller(info, pin_to_bank(pin_id));
4334ac2d
MR		 882 pin = pin_id % MAX_NB_GPIO_PER_BANK;
883 mask = pin_to_mask(pin);
03b054e9
SY		 884
885 if (config & PULL_UP && config & PULL_DOWN)
886 return -EINVAL;
887
888 at91_mux_set_pullup(pio, mask, config & PULL_UP);
889 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
890 if (info->ops->set_deglitch)
891 info->ops->set_deglitch(pio, mask, config & DEGLITCH);
892 if (info->ops->set_debounce)
893 info->ops->set_debounce(pio, mask, config & DEBOUNCE,
7ebd7a3a 894 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
03b054e9
SY		 895 if (info->ops->set_pulldown)
896 info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
897 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
898 info->ops->disable_schmitt_trig(pio, mask);
4334ac2d
MR		 899 if (info->ops->set_drivestrength)
900 info->ops->set_drivestrength(pio, pin,
901 (config & DRIVE_STRENGTH)
902 >> DRIVE_STRENGTH_SHIFT);
03b054e9
SY		 903
904 } /* for each config */
7ebd7a3a 905
6732ae5c
JCPV		 906 return 0;
907}
908
4d9b8a8e
AB		 909#define DBG_SHOW_FLAG(flag) do { \
910 if (config & flag) { \
911 if (num_conf) \
912 seq_puts(s, "|"); \
913 seq_puts(s, #flag); \
914 num_conf++; \
915 } \
916} while (0)
917
4334ac2d
MR		 918#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
919 if ((config & mask) == flag) { \
920 if (num_conf) \
921 seq_puts(s, "|"); \
922 seq_puts(s, #flag); \
923 num_conf++; \
924 } \
925} while (0)
926
6732ae5c
JCPV		 927static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
928 struct seq_file *s, unsigned pin_id)
929{
4d9b8a8e 930 unsigned long config;
445d2026 931 int val, num_conf = 0;
4d9b8a8e 932
445d2026 933 at91_pinconf_get(pctldev, pin_id, &config);
4d9b8a8e
AB		 934
935 DBG_SHOW_FLAG(MULTI_DRIVE);
936 DBG_SHOW_FLAG(PULL_UP);
937 DBG_SHOW_FLAG(PULL_DOWN);
938 DBG_SHOW_FLAG(DIS_SCHMIT);
939 DBG_SHOW_FLAG(DEGLITCH);
4334ac2d
MR		 940 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
941 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
942 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
4d9b8a8e
AB		 943 DBG_SHOW_FLAG(DEBOUNCE);
944 if (config & DEBOUNCE) {
945 val = config >> DEBOUNCE_VAL_SHIFT;
946 seq_printf(s, "(%d)", val);
947 }
6732ae5c 948
4d9b8a8e 949 return;
6732ae5c
JCPV		 950}
951
952static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
953 struct seq_file *s, unsigned group)
954{
955}
956
022ab148 957static const struct pinconf_ops at91_pinconf_ops = {
6732ae5c
JCPV		 958 .pin_config_get = at91_pinconf_get,
959 .pin_config_set = at91_pinconf_set,
960 .pin_config_dbg_show = at91_pinconf_dbg_show,
961 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
962};
963
964static struct pinctrl_desc at91_pinctrl_desc = {
965 .pctlops = &at91_pctrl_ops,
966 .pmxops = &at91_pmx_ops,
967 .confops = &at91_pinconf_ops,
968 .owner = THIS_MODULE,
969};
970
971static const char *gpio_compat = "atmel,at91rm9200-gpio";
972
150632b0
GKH		 973static void at91_pinctrl_child_count(struct at91_pinctrl *info,
974 struct device_node *np)
6732ae5c
JCPV		 975{
976 struct device_node *child;
977
978 for_each_child_of_node(np, child) {
979 if (of_device_is_compatible(child, gpio_compat)) {
980 info->nbanks++;
981 } else {
982 info->nfunctions++;
983 info->ngroups += of_get_child_count(child);
984 }
985 }
986}
987
150632b0
GKH		 988static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
989 struct device_node *np)
6732ae5c
JCPV		 990{
991 int ret = 0;
992 int size;
1164d73a 993 const __be32 *list;
6732ae5c
JCPV		 994
995 list = of_get_property(np, "atmel,mux-mask", &size);
996 if (!list) {
997 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
998 return -EINVAL;
999 }
1000
1001 size /= sizeof(*list);
1002 if (!size || size % info->nbanks) {
1003 dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks);
1004 return -EINVAL;
1005 }
1006 info->nmux = size / info->nbanks;
1007
1008 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
1009 if (!info->mux_mask) {
1010 dev_err(info->dev, "could not alloc mux_mask\n");
1011 return -ENOMEM;
1012 }
1013
1014 ret = of_property_read_u32_array(np, "atmel,mux-mask",
1015 info->mux_mask, size);
1016 if (ret)
1017 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1018 return ret;
1019}
1020
150632b0
GKH		 1021static int at91_pinctrl_parse_groups(struct device_node *np,
1022 struct at91_pin_group *grp,
1023 struct at91_pinctrl *info, u32 index)
6732ae5c
JCPV		 1024{
1025 struct at91_pmx_pin *pin;
1026 int size;
1164d73a 1027 const __be32 *list;
6732ae5c
JCPV		 1028 int i, j;
1029
1030 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1031
1032 /* Initialise group */
1033 grp->name = np->name;
1034
1035 /*
1036 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
1037 * do sanity check and calculate pins number
1038 */
1039 list = of_get_property(np, "atmel,pins", &size);
1040 /* we do not check return since it's safe node passed down */
1041 size /= sizeof(*list);
1042 if (!size || size % 4) {
1043 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1044 return -EINVAL;
1045 }
1046
1047 grp->npins = size / 4;
1048 pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin),
1049 GFP_KERNEL);
1050 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1051 GFP_KERNEL);
1052 if (!grp->pins_conf || !grp->pins)
1053 return -ENOMEM;
1054
1055 for (i = 0, j = 0; i < size; i += 4, j++) {
1056 pin->bank = be32_to_cpu(*list++);
1057 pin->pin = be32_to_cpu(*list++);
1058 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
1059 pin->mux = be32_to_cpu(*list++);
1060 pin->conf = be32_to_cpu(*list++);
1061
1062 at91_pin_dbg(info->dev, pin);
1063 pin++;
1064 }
1065
1066 return 0;
1067}
1068
150632b0
GKH		 1069static int at91_pinctrl_parse_functions(struct device_node *np,
1070 struct at91_pinctrl *info, u32 index)
6732ae5c
JCPV		 1071{
1072 struct device_node *child;
1073 struct at91_pmx_func *func;
1074 struct at91_pin_group *grp;
1075 int ret;
1076 static u32 grp_index;
1077 u32 i = 0;
1078
1079 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1080
1081 func = &info->functions[index];
1082
1083 /* Initialise function */
1084 func->name = np->name;
1085 func->ngroups = of_get_child_count(np);
ca7162ad 1086 if (func->ngroups == 0) {
6732ae5c
JCPV		 1087 dev_err(info->dev, "no groups defined\n");
1088 return -EINVAL;
1089 }
1090 func->groups = devm_kzalloc(info->dev,
1091 func->ngroups * sizeof(char *), GFP_KERNEL);
1092 if (!func->groups)
1093 return -ENOMEM;
1094
1095 for_each_child_of_node(np, child) {
1096 func->groups[i] = child->name;
1097 grp = &info->groups[grp_index++];
1098 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
1099 if (ret)
1100 return ret;
1101 }
1102
1103 return 0;
1104}
1105
150632b0 1106static struct of_device_id at91_pinctrl_of_match[] = {
4334ac2d 1107 { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
6732ae5c
JCPV		 1108 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
1109 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
1110 { /* sentinel */ }
1111};
1112
150632b0
GKH		 1113static int at91_pinctrl_probe_dt(struct platform_device *pdev,
1114 struct at91_pinctrl *info)
6732ae5c
JCPV		 1115{
1116 int ret = 0;
1117 int i, j;
1118 uint32_t *tmp;
1119 struct device_node *np = pdev->dev.of_node;
1120 struct device_node *child;
1121
1122 if (!np)
1123 return -ENODEV;
1124
1125 info->dev = &pdev->dev;
3c93600d 1126 info->ops = (struct at91_pinctrl_mux_ops *)
6732ae5c
JCPV		 1127 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
1128 at91_pinctrl_child_count(info, np);
1129
1130 if (info->nbanks < 1) {
61e310a1 1131 dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
6732ae5c
JCPV		 1132 return -EINVAL;
1133 }
1134
1135 ret = at91_pinctrl_mux_mask(info, np);
1136 if (ret)
1137 return ret;
1138
1139 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
1140
1141 dev_dbg(&pdev->dev, "mux-mask\n");
1142 tmp = info->mux_mask;
1143 for (i = 0; i < info->nbanks; i++) {
1144 for (j = 0; j < info->nmux; j++, tmp++) {
1145 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
1146 }
1147 }
1148
1149 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1150 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1151 info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func),
1152 GFP_KERNEL);
1153 if (!info->functions)
1154 return -ENOMEM;
1155
1156 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group),
1157 GFP_KERNEL);
1158 if (!info->groups)
1159 return -ENOMEM;
1160
1161 dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks);
1162 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1163 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1164
1165 i = 0;
1166
1167 for_each_child_of_node(np, child) {
1168 if (of_device_is_compatible(child, gpio_compat))
1169 continue;
1170 ret = at91_pinctrl_parse_functions(child, info, i++);
1171 if (ret) {
1172 dev_err(&pdev->dev, "failed to parse function\n");
1173 return ret;
1174 }
1175 }
1176
1177 return 0;
1178}
1179
150632b0 1180static int at91_pinctrl_probe(struct platform_device *pdev)
6732ae5c
JCPV		 1181{
1182 struct at91_pinctrl *info;
1183 struct pinctrl_pin_desc *pdesc;
3c93600d 1184 int ret, i, j, k;
6732ae5c
JCPV		 1185
1186 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1187 if (!info)
1188 return -ENOMEM;
1189
1190 ret = at91_pinctrl_probe_dt(pdev, info);
1191 if (ret)
1192 return ret;
1193
1194 /*
1195 * We need all the GPIO drivers to probe FIRST, or we will not be able
1196 * to obtain references to the struct gpio_chip * for them, and we
1197 * need this to proceed.
1198 */
1199 for (i = 0; i < info->nbanks; i++) {
1200 if (!gpio_chips[i]) {
1201 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1202 devm_kfree(&pdev->dev, info);
1203 return -EPROBE_DEFER;
1204 }
1205 }
1206
1207 at91_pinctrl_desc.name = dev_name(&pdev->dev);
1208 at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK;
1209 at91_pinctrl_desc.pins = pdesc =
1210 devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL);
1211
1212 if (!at91_pinctrl_desc.pins)
1213 return -ENOMEM;
1214
1215 for (i = 0 , k = 0; i < info->nbanks; i++) {
1216 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1217 pdesc->number = k;
1218 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1219 pdesc++;
1220 }
1221 }
1222
1223 platform_set_drvdata(pdev, info);
1224 info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info);
1225
1226 if (!info->pctl) {
1227 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1228 ret = -EINVAL;
1229 goto err;
1230 }
1231
1232 /* We will handle a range of GPIO pins */
1233 for (i = 0; i < info->nbanks; i++)
1234 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1235
1236 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1237
1238 return 0;
1239
1240err:
1241 return ret;
1242}
1243
150632b0 1244static int at91_pinctrl_remove(struct platform_device *pdev)
6732ae5c
JCPV		 1245{
1246 struct at91_pinctrl *info = platform_get_drvdata(pdev);
1247
1248 pinctrl_unregister(info->pctl);
1249
1250 return 0;
1251}
1252
1253static int at91_gpio_request(struct gpio_chip *chip, unsigned offset)
1254{
1255 /*
1256 * Map back to global GPIO space and request muxing, the direction
1257 * parameter does not matter for this controller.
1258 */
1259 int gpio = chip->base + offset;
1260 int bank = chip->base / chip->ngpio;
1261
1262 dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__,
1263 'A' + bank, offset, gpio);
1264
1265 return pinctrl_request_gpio(gpio);
1266}
1267
1268static void at91_gpio_free(struct gpio_chip *chip, unsigned offset)
1269{
1270 int gpio = chip->base + offset;
1271
1272 pinctrl_free_gpio(gpio);
1273}
1274
8af584b8
RG		 1275static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1276{
1277 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1278 void __iomem *pio = at91_gpio->regbase;
1279 unsigned mask = 1 << offset;
1280 u32 osr;
1281
1282 osr = readl_relaxed(pio + PIO_OSR);
1283 return !(osr & mask);
1284}
1285
6732ae5c
JCPV		 1286static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1287{
1288 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1289 void __iomem *pio = at91_gpio->regbase;
1290 unsigned mask = 1 << offset;
1291
1292 writel_relaxed(mask, pio + PIO_ODR);
1293 return 0;
1294}
1295
1296static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1297{
1298 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1299 void __iomem *pio = at91_gpio->regbase;
1300 unsigned mask = 1 << offset;
1301 u32 pdsr;
1302
1303 pdsr = readl_relaxed(pio + PIO_PDSR);
1304 return (pdsr & mask) != 0;
1305}
1306
1307static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1308 int val)
1309{
1310 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1311 void __iomem *pio = at91_gpio->regbase;
1312 unsigned mask = 1 << offset;
1313
1314 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1315}
1316
1317static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1318 int val)
1319{
1320 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1321 void __iomem *pio = at91_gpio->regbase;
1322 unsigned mask = 1 << offset;
1323
1324 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1325 writel_relaxed(mask, pio + PIO_OER);
1326
1327 return 0;
1328}
1329
6732ae5c
JCPV		 1330#ifdef CONFIG_DEBUG_FS
1331static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1332{
1333 enum at91_mux mode;
1334 int i;
1335 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1336 void __iomem *pio = at91_gpio->regbase;
1337
1338 for (i = 0; i < chip->ngpio; i++) {
47f22716 1339 unsigned mask = pin_to_mask(i);
6732ae5c
JCPV		 1340 const char *gpio_label;
1341 u32 pdsr;
1342
1343 gpio_label = gpiochip_is_requested(chip, i);
1344 if (!gpio_label)
1345 continue;
1346 mode = at91_gpio->ops->get_periph(pio, mask);
1347 seq_printf(s, "[%s] GPIO%s%d: ",
1348 gpio_label, chip->label, i);
1349 if (mode == AT91_MUX_GPIO) {
1350 pdsr = readl_relaxed(pio + PIO_PDSR);
1351
1352 seq_printf(s, "[gpio] %s\n",
1353 pdsr & mask ?
1354 "set" : "clear");
1355 } else {
1356 seq_printf(s, "[periph %c]\n",
1357 mode + 'A' - 1);
1358 }
1359 }
1360}
1361#else
1362#define at91_gpio_dbg_show NULL
1363#endif
1364
1365/* Several AIC controller irqs are dispatched through this GPIO handler.
1366 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1367 * at91_set_gpio_input() then maybe enable its glitch filter.
1368 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1369 * handler.
1370 * First implementation always triggers on rising and falling edges
1371 * whereas the newer PIO3 can be additionally configured to trigger on
1372 * level, edge with any polarity.
1373 *
1374 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1375 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1376 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1377 */
1378
1379static void gpio_irq_mask(struct irq_data *d)
1380{
1381 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1382 void __iomem *pio = at91_gpio->regbase;
1383 unsigned mask = 1 << d->hwirq;
1384
1385 if (pio)
1386 writel_relaxed(mask, pio + PIO_IDR);
1387}
1388
1389static void gpio_irq_unmask(struct irq_data *d)
1390{
1391 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1392 void __iomem *pio = at91_gpio->regbase;
1393 unsigned mask = 1 << d->hwirq;
1394
1395 if (pio)
1396 writel_relaxed(mask, pio + PIO_IER);
1397}
1398
1399static int gpio_irq_type(struct irq_data *d, unsigned type)
1400{
1401 switch (type) {
1402 case IRQ_TYPE_NONE:
1403 case IRQ_TYPE_EDGE_BOTH:
1404 return 0;
1405 default:
1406 return -EINVAL;
1407 }
1408}
1409
1410/* Alternate irq type for PIO3 support */
1411static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1412{
1413 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1414 void __iomem *pio = at91_gpio->regbase;
1415 unsigned mask = 1 << d->hwirq;
1416
1417 switch (type) {
1418 case IRQ_TYPE_EDGE_RISING:
b0dcfd87 1419 __irq_set_handler_locked(d->irq, handle_simple_irq);
6732ae5c
JCPV		 1420 writel_relaxed(mask, pio + PIO_ESR);
1421 writel_relaxed(mask, pio + PIO_REHLSR);
1422 break;
1423 case IRQ_TYPE_EDGE_FALLING:
b0dcfd87 1424 __irq_set_handler_locked(d->irq, handle_simple_irq);
6732ae5c
JCPV		 1425 writel_relaxed(mask, pio + PIO_ESR);
1426 writel_relaxed(mask, pio + PIO_FELLSR);
1427 break;
1428 case IRQ_TYPE_LEVEL_LOW:
b0dcfd87 1429 __irq_set_handler_locked(d->irq, handle_level_irq);
6732ae5c
JCPV		 1430 writel_relaxed(mask, pio + PIO_LSR);
1431 writel_relaxed(mask, pio + PIO_FELLSR);
1432 break;
1433 case IRQ_TYPE_LEVEL_HIGH:
b0dcfd87 1434 __irq_set_handler_locked(d->irq, handle_level_irq);
6732ae5c
JCPV		 1435 writel_relaxed(mask, pio + PIO_LSR);
1436 writel_relaxed(mask, pio + PIO_REHLSR);
1437 break;
1438 case IRQ_TYPE_EDGE_BOTH:
1439 /*
1440 * disable additional interrupt modes:
1441 * fall back to default behavior
1442 */
b0dcfd87 1443 __irq_set_handler_locked(d->irq, handle_simple_irq);
6732ae5c
JCPV		 1444 writel_relaxed(mask, pio + PIO_AIMDR);
1445 return 0;
1446 case IRQ_TYPE_NONE:
1447 default:
1448 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
1449 return -EINVAL;
1450 }
1451
1452 /* enable additional interrupt modes */
1453 writel_relaxed(mask, pio + PIO_AIMER);
1454
1455 return 0;
1456}
1457
80cc3732
AS		 1458static void gpio_irq_ack(struct irq_data *d)
1459{
1460 /* the interrupt is already cleared before by reading ISR */
1461}
1462
94e69207
JJH		 1463static unsigned int gpio_irq_startup(struct irq_data *d)
1464{
1465 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1466 unsigned pin = d->hwirq;
1467 int ret;
1468
1469 ret = gpio_lock_as_irq(&at91_gpio->chip, pin);
1470 if (ret) {
1471 dev_err(at91_gpio->chip.dev, "unable to lock pind %lu IRQ\n",
1472 d->hwirq);
1473 return ret;
1474 }
1475 gpio_irq_unmask(d);
1476 return 0;
1477}
1478
1479static void gpio_irq_shutdown(struct irq_data *d)
1480{
1481 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1482 unsigned pin = d->hwirq;
1483
1484 gpio_irq_mask(d);
1485 gpio_unlock_as_irq(&at91_gpio->chip, pin);
1486}
1487
6732ae5c 1488#ifdef CONFIG_PM
647f8d94
LD		 1489
1490static u32 wakeups[MAX_GPIO_BANKS];
1491static u32 backups[MAX_GPIO_BANKS];
1492
6732ae5c
JCPV		 1493static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1494{
1495 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1496 unsigned bank = at91_gpio->pioc_idx;
647f8d94 1497 unsigned mask = 1 << d->hwirq;
6732ae5c
JCPV		 1498
1499 if (unlikely(bank >= MAX_GPIO_BANKS))
1500 return -EINVAL;
1501
647f8d94
LD		 1502 if (state)
1503 wakeups[bank] |= mask;
1504 else
1505 wakeups[bank] &= ~mask;
1506
6732ae5c
JCPV		 1507 irq_set_irq_wake(at91_gpio->pioc_virq, state);
1508
1509 return 0;
1510}
647f8d94
LD		 1511
1512void at91_pinctrl_gpio_suspend(void)
1513{
1514 int i;
1515
1516 for (i = 0; i < gpio_banks; i++) {
1517 void __iomem *pio;
1518
1519 if (!gpio_chips[i])
1520 continue;
1521
1522 pio = gpio_chips[i]->regbase;
1523
1524 backups[i] = __raw_readl(pio + PIO_IMR);
1525 __raw_writel(backups[i], pio + PIO_IDR);
1526 __raw_writel(wakeups[i], pio + PIO_IER);
1527
795f9953
BB		 1528 if (!wakeups[i])
1529 clk_disable_unprepare(gpio_chips[i]->clock);
1530 else
647f8d94
LD		 1531 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
1532 'A'+i, wakeups[i]);
647f8d94
LD		 1533 }
1534}
1535
1536void at91_pinctrl_gpio_resume(void)
1537{
1538 int i;
1539
1540 for (i = 0; i < gpio_banks; i++) {
1541 void __iomem *pio;
1542
1543 if (!gpio_chips[i])
1544 continue;
1545
1546 pio = gpio_chips[i]->regbase;
1547
37ef1d92
BB		 1548 if (!wakeups[i])
1549 clk_prepare_enable(gpio_chips[i]->clock);
647f8d94
LD		 1550
1551 __raw_writel(wakeups[i], pio + PIO_IDR);
1552 __raw_writel(backups[i], pio + PIO_IER);
1553 }
1554}
1555
6732ae5c
JCPV		 1556#else
1557#define gpio_irq_set_wake NULL
647f8d94 1558#endif /* CONFIG_PM */
6732ae5c
JCPV		 1559
1560static struct irq_chip gpio_irqchip = {
1561 .name = "GPIO",
80cc3732 1562 .irq_ack = gpio_irq_ack,
94e69207
JJH		 1563 .irq_startup = gpio_irq_startup,
1564 .irq_shutdown = gpio_irq_shutdown,
6732ae5c
JCPV		 1565 .irq_disable = gpio_irq_mask,
1566 .irq_mask = gpio_irq_mask,
1567 .irq_unmask = gpio_irq_unmask,
1568 /* .irq_set_type is set dynamically */
1569 .irq_set_wake = gpio_irq_set_wake,
1570};
1571
1572static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1573{
80cc3732
AS		 1574 struct irq_chip *chip = irq_get_chip(irq);
1575 struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
1576 struct at91_gpio_chip *at91_gpio = container_of(gpio_chip,
1577 struct at91_gpio_chip, chip);
1578
6732ae5c
JCPV		 1579 void __iomem *pio = at91_gpio->regbase;
1580 unsigned long isr;
1581 int n;
1582
1583 chained_irq_enter(chip, desc);
1584 for (;;) {
1585 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
c2eb9e7f 1586 * When there are none pending, we're finished unless we need
6732ae5c
JCPV		 1587 * to process multiple banks (like ID_PIOCDE on sam9263).
1588 */
1589 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1590 if (!isr) {
1591 if (!at91_gpio->next)
1592 break;
1593 at91_gpio = at91_gpio->next;
1594 pio = at91_gpio->regbase;
cccb0c3e 1595 gpio_chip = &at91_gpio->chip;
6732ae5c
JCPV		 1596 continue;
1597 }
1598
05daa16a 1599 for_each_set_bit(n, &isr, BITS_PER_LONG) {
80cc3732
AS		 1600 generic_handle_irq(irq_find_mapping(
1601 gpio_chip->irqdomain, n));
6732ae5c
JCPV		 1602 }
1603 }
1604 chained_irq_exit(chip, desc);
1605 /* now it may re-trigger */
1606}
1607
834e1678 1608static int at91_gpio_of_irq_setup(struct platform_device *pdev,
6732ae5c
JCPV		 1609 struct at91_gpio_chip *at91_gpio)
1610{
cccb0c3e 1611 struct at91_gpio_chip *prev = NULL;
6732ae5c 1612 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
80cc3732 1613 int ret;
6732ae5c
JCPV		 1614
1615 at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1616
1617 /* Setup proper .irq_set_type function */
1618 gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type;
1619
1620 /* Disable irqs of this PIO controller */
1621 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1622
80cc3732
AS		 1623 /*
1624 * Let the generic code handle this edge IRQ, the the chained
1625 * handler will perform the actual work of handling the parent
1626 * interrupt.
1627 */
1628 ret = gpiochip_irqchip_add(&at91_gpio->chip,
1629 &gpio_irqchip,
1630 0,
1631 handle_edge_irq,
1632 IRQ_TYPE_EDGE_BOTH);
834e1678
PG		 1633 if (ret) {
1634 dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n",
6732ae5c 1635 at91_gpio->pioc_idx);
834e1678
PG		 1636 return ret;
1637 }
6732ae5c 1638
cccb0c3e
AS		 1639 /* Setup chained handler */
1640 if (at91_gpio->pioc_idx)
1641 prev = gpio_chips[at91_gpio->pioc_idx - 1];
1642
1643 /* The top level handler handles one bank of GPIOs, except
1644 * on some SoC it can handle up to three...
1645 * We only set up the handler for the first of the list.
1646 */
1647 if (prev && prev->next == at91_gpio)
1648 return 0;
1649
80cc3732
AS		 1650 /* Then register the chain on the parent IRQ */
1651 gpiochip_set_chained_irqchip(&at91_gpio->chip,
1652 &gpio_irqchip,
1653 at91_gpio->pioc_virq,
1654 gpio_irq_handler);
6732ae5c
JCPV		 1655
1656 return 0;
1657}
1658
1659/* This structure is replicated for each GPIO block allocated at probe time */
1660static struct gpio_chip at91_gpio_template = {
1661 .request = at91_gpio_request,
1662 .free = at91_gpio_free,
8af584b8 1663 .get_direction = at91_gpio_get_direction,
6732ae5c
JCPV		 1664 .direction_input = at91_gpio_direction_input,
1665 .get = at91_gpio_get,
1666 .direction_output = at91_gpio_direction_output,
1667 .set = at91_gpio_set,
6732ae5c 1668 .dbg_show = at91_gpio_dbg_show,
9fb1f39e 1669 .can_sleep = false,
6732ae5c
JCPV		 1670 .ngpio = MAX_NB_GPIO_PER_BANK,
1671};
1672
150632b0 1673static void at91_gpio_probe_fixup(void)
6732ae5c
JCPV		 1674{
1675 unsigned i;
1676 struct at91_gpio_chip *at91_gpio, *last = NULL;
1677
1678 for (i = 0; i < gpio_banks; i++) {
1679 at91_gpio = gpio_chips[i];
1680
1681 /*
1682 * GPIO controller are grouped on some SoC:
1683 * PIOC, PIOD and PIOE can share the same IRQ line
1684 */
1685 if (last && last->pioc_virq == at91_gpio->pioc_virq)
1686 last->next = at91_gpio;
1687 last = at91_gpio;
1688 }
1689}
1690
150632b0 1691static struct of_device_id at91_gpio_of_match[] = {
6732ae5c
JCPV		 1692 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1693 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1694 { /* sentinel */ }
1695};
1696
150632b0 1697static int at91_gpio_probe(struct platform_device *pdev)
6732ae5c
JCPV		 1698{
1699 struct device_node *np = pdev->dev.of_node;
1700 struct resource *res;
1701 struct at91_gpio_chip *at91_chip = NULL;
1702 struct gpio_chip *chip;
1703 struct pinctrl_gpio_range *range;
1704 int ret = 0;
32b01a36 1705 int irq, i;
6732ae5c
JCPV		 1706 int alias_idx = of_alias_get_id(np, "gpio");
1707 uint32_t ngpio;
32b01a36 1708 char **names;
6732ae5c
JCPV		 1709
1710 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1711 if (gpio_chips[alias_idx]) {
1712 ret = -EBUSY;
1713 goto err;
1714 }
1715
6732ae5c
JCPV		 1716 irq = platform_get_irq(pdev, 0);
1717 if (irq < 0) {
1718 ret = irq;
1719 goto err;
1720 }
1721
1722 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1723 if (!at91_chip) {
1724 ret = -ENOMEM;
1725 goto err;
1726 }
1727
f50b9e12 1728 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9e0c1fb2
TR		 1729 at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
1730 if (IS_ERR(at91_chip->regbase)) {
1731 ret = PTR_ERR(at91_chip->regbase);
6732ae5c
JCPV		 1732 goto err;
1733 }
1734
3c93600d 1735 at91_chip->ops = (struct at91_pinctrl_mux_ops *)
6732ae5c
JCPV		 1736 of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1737 at91_chip->pioc_virq = irq;
1738 at91_chip->pioc_idx = alias_idx;
1739
02b837ff 1740 at91_chip->clock = devm_clk_get(&pdev->dev, NULL);
6732ae5c
JCPV		 1741 if (IS_ERR(at91_chip->clock)) {
1742 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
70e41974 1743 ret = PTR_ERR(at91_chip->clock);
6732ae5c
JCPV		 1744 goto err;
1745 }
1746
70e41974
PG		 1747 ret = clk_prepare(at91_chip->clock);
1748 if (ret)
1749 goto clk_prepare_err;
6732ae5c
JCPV		 1750
1751 /* enable PIO controller's clock */
70e41974
PG		 1752 ret = clk_enable(at91_chip->clock);
1753 if (ret) {
6732ae5c 1754 dev_err(&pdev->dev, "failed to enable clock, ignoring.\n");
70e41974 1755 goto clk_enable_err;
6732ae5c
JCPV		 1756 }
1757
1758 at91_chip->chip = at91_gpio_template;
1759
1760 chip = &at91_chip->chip;
1761 chip->of_node = np;
1762 chip->label = dev_name(&pdev->dev);
1763 chip->dev = &pdev->dev;
1764 chip->owner = THIS_MODULE;
1765 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1766
1767 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1768 if (ngpio >= MAX_NB_GPIO_PER_BANK)
1769 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1770 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1771 else
1772 chip->ngpio = ngpio;
1773 }
1774
3c93600d
SK		 1775 names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio,
1776 GFP_KERNEL);
32b01a36
JCPV		 1777
1778 if (!names) {
1779 ret = -ENOMEM;
70e41974 1780 goto clk_enable_err;
32b01a36
JCPV		 1781 }
1782
1783 for (i = 0; i < chip->ngpio; i++)
1784 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1785
3c93600d 1786 chip->names = (const char *const *)names;
32b01a36 1787
6732ae5c
JCPV		 1788 range = &at91_chip->range;
1789 range->name = chip->label;
1790 range->id = alias_idx;
1791 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1792
1793 range->npins = chip->ngpio;
1794 range->gc = chip;
1795
1796 ret = gpiochip_add(chip);
1797 if (ret)
70e41974 1798 goto gpiochip_add_err;
6732ae5c
JCPV		 1799
1800 gpio_chips[alias_idx] = at91_chip;
1801 gpio_banks = max(gpio_banks, alias_idx + 1);
1802
1803 at91_gpio_probe_fixup();
1804
834e1678
PG		 1805 ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1806 if (ret)
1807 goto irq_setup_err;
6732ae5c
JCPV		 1808
1809 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1810
1811 return 0;
1812
834e1678
PG		 1813irq_setup_err:
1814 gpiochip_remove(chip);
70e41974
PG		 1815gpiochip_add_err:
1816 clk_disable(at91_chip->clock);
1817clk_enable_err:
6732ae5c 1818 clk_unprepare(at91_chip->clock);
70e41974 1819clk_prepare_err:
6732ae5c
JCPV		 1820err:
1821 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1822
1823 return ret;
1824}
1825
1826static struct platform_driver at91_gpio_driver = {
1827 .driver = {
1828 .name = "gpio-at91",
1829 .owner = THIS_MODULE,
606fca94 1830 .of_match_table = at91_gpio_of_match,
6732ae5c
JCPV		 1831 },
1832 .probe = at91_gpio_probe,
1833};
1834
1835static struct platform_driver at91_pinctrl_driver = {
1836 .driver = {
1837 .name = "pinctrl-at91",
1838 .owner = THIS_MODULE,
606fca94 1839 .of_match_table = at91_pinctrl_of_match,
6732ae5c
JCPV		 1840 },
1841 .probe = at91_pinctrl_probe,
150632b0 1842 .remove = at91_pinctrl_remove,
6732ae5c
JCPV		 1843};
1844
1845static int __init at91_pinctrl_init(void)
1846{
1847 int ret;
1848
1849 ret = platform_driver_register(&at91_gpio_driver);
1850 if (ret)
1851 return ret;
1852 return platform_driver_register(&at91_pinctrl_driver);
1853}
1854arch_initcall(at91_pinctrl_init);
1855
1856static void __exit at91_pinctrl_exit(void)
1857{
1858 platform_driver_unregister(&at91_pinctrl_driver);
1859}
1860
1861module_exit(at91_pinctrl_exit);
1862MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>");
1863MODULE_DESCRIPTION("Atmel AT91 pinctrl driver");
1864MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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