[deliverable/linux.git] / drivers / pinctrl / pinctrl-baytrail.c

/*
 * Pinctrl GPIO driver for Intel Baytrail
 * Copyright (c) 2012-2013, Intel Corporation.
 *
 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/bitops.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/irqdomain.h>
#include <linux/acpi.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <linux/pinctrl/pinctrl.h>

/* memory mapped register offsets */
#define BYT_CONF0_REG		0x000
#define BYT_CONF1_REG		0x004
#define BYT_VAL_REG		0x008
#define BYT_DFT_REG		0x00c
#define BYT_INT_STAT_REG	0x800

/* BYT_CONF0_REG register bits */
#define BYT_IODEN		BIT(31)
#define BYT_TRIG_NEG		BIT(26)
#define BYT_TRIG_POS		BIT(25)
#define BYT_TRIG_LVL		BIT(24)
#define BYT_PULL_STR_SHIFT	9
#define BYT_PULL_STR_MASK	(3 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_STR_2K		(0 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_STR_10K	(1 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_STR_20K	(2 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_STR_40K	(3 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_ASSIGN_SHIFT	7
#define BYT_PULL_ASSIGN_MASK	(3 << BYT_PULL_ASSIGN_SHIFT)
#define BYT_PULL_ASSIGN_UP	(1 << BYT_PULL_ASSIGN_SHIFT)
#define BYT_PULL_ASSIGN_DOWN	(2 << BYT_PULL_ASSIGN_SHIFT)
#define BYT_PIN_MUX		0x07

/* BYT_VAL_REG register bits */
#define BYT_INPUT_EN		BIT(2)  /* 0: input enabled (active low)*/
#define BYT_OUTPUT_EN		BIT(1)  /* 0: output enabled (active low)*/
#define BYT_LEVEL		BIT(0)

#define BYT_DIR_MASK		(BIT(1) | BIT(2))
#define BYT_TRIG_MASK		(BIT(26) | BIT(25) | BIT(24))

#define BYT_NGPIO_SCORE		102
#define BYT_NGPIO_NCORE		28
#define BYT_NGPIO_SUS		44

#define BYT_SCORE_ACPI_UID	"1"
#define BYT_NCORE_ACPI_UID	"2"
#define BYT_SUS_ACPI_UID	"3"

/*
 * Baytrail gpio controller consist of three separate sub-controllers called
 * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
 *
 * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
 * _not_ correspond to the first gpio register at controller's gpio base.
 * There is no logic or pattern in mapping gpio numbers to registers (pads) so
 * each sub-controller needs to have its own mapping table
 */

/* score_pins[gpio_nr] = pad_nr */

static unsigned const score_pins[BYT_NGPIO_SCORE] = {
	85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
	36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
	54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
	52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
	95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
	86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
	80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
	2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
	31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
	24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
	97, 100,
};

static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
	19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
	14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
	3, 6, 10, 13, 2, 5, 9, 7,
};

static unsigned const sus_pins[BYT_NGPIO_SUS] = {
	29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
	18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
	0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
	26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
	52, 53, 59, 40,
};

static struct pinctrl_gpio_range byt_ranges[] = {
	{
		.name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */
		.npins = BYT_NGPIO_SCORE,
		.pins = score_pins,
	},
	{
		.name = BYT_NCORE_ACPI_UID,
		.npins = BYT_NGPIO_NCORE,
		.pins = ncore_pins,
	},
	{
		.name = BYT_SUS_ACPI_UID,
		.npins = BYT_NGPIO_SUS,
		.pins = sus_pins,
	},
	{
	},
};

struct byt_gpio {
	struct gpio_chip		chip;
	struct irq_domain		*domain;
	struct platform_device		*pdev;
	spinlock_t			lock;
	void __iomem			*reg_base;
	struct pinctrl_gpio_range	*range;
};

#define to_byt_gpio(c)	container_of(c, struct byt_gpio, chip)

static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
				 int reg)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	u32 reg_offset;

	if (reg == BYT_INT_STAT_REG)
		reg_offset = (offset / 32) * 4;
	else
		reg_offset = vg->range->pins[offset] * 16;

	return vg->reg_base + reg_offset + reg;
}

static bool is_special_pin(struct byt_gpio *vg, unsigned offset)
{
	/* SCORE pin 92-93 */
	if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) &&
		offset >= 92 && offset <= 93)
		return true;

	/* SUS pin 11-21 */
	if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) &&
		offset >= 11 && offset <= 21)
		return true;

	return false;
}

static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
	u32 value;
	bool special;

	/*
	 * In most cases, func pin mux 000 means GPIO function.
	 * But, some pins may have func pin mux 001 represents
	 * GPIO function. Only allow user to export pin with
	 * func pin mux preset as GPIO function by BIOS/FW.
	 */
	value = readl(reg) & BYT_PIN_MUX;
	special = is_special_pin(vg, offset);
	if ((special && value != 1) || (!special && value)) {
		dev_err(&vg->pdev->dev,
			"pin %u cannot be used as GPIO.\n", offset);
		return -EINVAL;
	}

	pm_runtime_get(&vg->pdev->dev);

	return 0;
}

static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
	u32 value;

	/* clear interrupt triggering */
	value = readl(reg);
	value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
	writel(value, reg);

	pm_runtime_put(&vg->pdev->dev);
}

static int byt_irq_type(struct irq_data *d, unsigned type)
{
	struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
	u32 offset = irqd_to_hwirq(d);
	u32 value;
	unsigned long flags;
	void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);

	if (offset >= vg->chip.ngpio)
		return -EINVAL;

	spin_lock_irqsave(&vg->lock, flags);
	value = readl(reg);

	/* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
	 * are used to indicate high and low level triggering
	 */
	value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);

	switch (type) {
	case IRQ_TYPE_LEVEL_HIGH:
		value |= BYT_TRIG_LVL;
	case IRQ_TYPE_EDGE_RISING:
		value |= BYT_TRIG_POS;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		value |= BYT_TRIG_LVL;
	case IRQ_TYPE_EDGE_FALLING:
		value |= BYT_TRIG_NEG;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
		break;
	}
	writel(value, reg);

	spin_unlock_irqrestore(&vg->lock, flags);

	return 0;
}

static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	return readl(reg) & BYT_LEVEL;
}

static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	unsigned long flags;
	u32 old_val;

	spin_lock_irqsave(&vg->lock, flags);

	old_val = readl(reg);

	if (value)
		writel(old_val | BYT_LEVEL, reg);
	else
		writel(old_val & ~BYT_LEVEL, reg);

	spin_unlock_irqrestore(&vg->lock, flags);
}

static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	unsigned long flags;
	u32 value;

	spin_lock_irqsave(&vg->lock, flags);

	value = readl(reg) | BYT_DIR_MASK;
	value &= ~BYT_INPUT_EN;		/* active low */
	writel(value, reg);

	spin_unlock_irqrestore(&vg->lock, flags);

	return 0;
}

static int byt_gpio_direction_output(struct gpio_chip *chip,
				     unsigned gpio, int value)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
	unsigned long flags;
	u32 reg_val;

	spin_lock_irqsave(&vg->lock, flags);

	reg_val = readl(reg) | BYT_DIR_MASK;
	reg_val &= ~BYT_OUTPUT_EN;

	if (value)
		writel(reg_val | BYT_LEVEL, reg);
	else
		writel(reg_val & ~BYT_LEVEL, reg);

	spin_unlock_irqrestore(&vg->lock, flags);

	return 0;
}

static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	int i;
	unsigned long flags;
	u32 conf0, val, offs;

	spin_lock_irqsave(&vg->lock, flags);

	for (i = 0; i < vg->chip.ngpio; i++) {
		const char *pull_str = NULL;
		const char *pull = NULL;
		const char *label;
		offs = vg->range->pins[i] * 16;
		conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
		val = readl(vg->reg_base + offs + BYT_VAL_REG);

		label = gpiochip_is_requested(chip, i);
		if (!label)
			label = "Unrequested";

		switch (conf0 & BYT_PULL_ASSIGN_MASK) {
		case BYT_PULL_ASSIGN_UP:
			pull = "up";
			break;
		case BYT_PULL_ASSIGN_DOWN:
			pull = "down";
			break;
		}

		switch (conf0 & BYT_PULL_STR_MASK) {
		case BYT_PULL_STR_2K:
			pull_str = "2k";
			break;
		case BYT_PULL_STR_10K:
			pull_str = "10k";
			break;
		case BYT_PULL_STR_20K:
			pull_str = "20k";
			break;
		case BYT_PULL_STR_40K:
			pull_str = "40k";
			break;
		}

		seq_printf(s,
			   " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
			   i,
			   label,
			   val & BYT_INPUT_EN ? "  " : "in",
			   val & BYT_OUTPUT_EN ? "   " : "out",
			   val & BYT_LEVEL ? "hi" : "lo",
			   vg->range->pins[i], offs,
			   conf0 & 0x7,
			   conf0 & BYT_TRIG_NEG ? " fall" : "     ",
			   conf0 & BYT_TRIG_POS ? " rise" : "     ",
			   conf0 & BYT_TRIG_LVL ? " level" : "      ");

		if (pull && pull_str)
			seq_printf(s, " %-4s %-3s", pull, pull_str);
		else
			seq_puts(s, "          ");

		if (conf0 & BYT_IODEN)
			seq_puts(s, " open-drain");

		seq_puts(s, "\n");
	}
	spin_unlock_irqrestore(&vg->lock, flags);
}

static int byt_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	return irq_create_mapping(vg->domain, offset);
}

static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
	struct irq_data *data = irq_desc_get_irq_data(desc);
	struct byt_gpio *vg = irq_data_get_irq_handler_data(data);
	struct irq_chip *chip = irq_data_get_irq_chip(data);
	u32 base, pin, mask;
	void __iomem *reg;
	u32 pending;
	unsigned virq;
	int looplimit = 0;

	/* check from GPIO controller which pin triggered the interrupt */
	for (base = 0; base < vg->chip.ngpio; base += 32) {

		reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);

		while ((pending = readl(reg))) {
			pin = __ffs(pending);
			mask = BIT(pin);
			/* Clear before handling so we can't lose an edge */
			writel(mask, reg);

			virq = irq_find_mapping(vg->domain, base + pin);
			generic_handle_irq(virq);

			/* In case bios or user sets triggering incorretly a pin
			 * might remain in "interrupt triggered" state.
			 */
			if (looplimit++ > 32) {
				dev_err(&vg->pdev->dev,
					"Gpio %d interrupt flood, disabling\n",
					base + pin);

				reg = byt_gpio_reg(&vg->chip, base + pin,
						   BYT_CONF0_REG);
				mask = readl(reg);
				mask &= ~(BYT_TRIG_NEG | BYT_TRIG_POS |
					  BYT_TRIG_LVL);
				writel(mask, reg);
				mask = readl(reg); /* flush */
				break;
			}
		}
	}
	chip->irq_eoi(data);
}

static void byt_irq_unmask(struct irq_data *d)
{
}

static void byt_irq_mask(struct irq_data *d)
{
}

static int byt_irq_reqres(struct irq_data *d)
{
	struct byt_gpio *vg = irq_data_get_irq_chip_data(d);

	if (gpio_lock_as_irq(&vg->chip, irqd_to_hwirq(d))) {
		dev_err(vg->chip.dev,
			"unable to lock HW IRQ %lu for IRQ\n",
			irqd_to_hwirq(d));
		return -EINVAL;
	}
	return 0;
}

static void byt_irq_relres(struct irq_data *d)
{
	struct byt_gpio *vg = irq_data_get_irq_chip_data(d);

	gpio_unlock_as_irq(&vg->chip, irqd_to_hwirq(d));
}

static struct irq_chip byt_irqchip = {
	.name = "BYT-GPIO",
	.irq_mask = byt_irq_mask,
	.irq_unmask = byt_irq_unmask,
	.irq_set_type = byt_irq_type,
	.irq_request_resources = byt_irq_reqres,
	.irq_release_resources = byt_irq_relres,
};

static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
{
	void __iomem *reg;
	u32 base, value;

	/* clear interrupt status trigger registers */
	for (base = 0; base < vg->chip.ngpio; base += 32) {
		reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
		writel(0xffffffff, reg);
		/* make sure trigger bits are cleared, if not then a pin
		   might be misconfigured in bios */
		value = readl(reg);
		if (value)
			dev_err(&vg->pdev->dev,
				"GPIO interrupt error, pins misconfigured\n");
	}
}

static int byt_gpio_irq_map(struct irq_domain *d, unsigned int virq,
			    irq_hw_number_t hw)
{
	struct byt_gpio *vg = d->host_data;

	irq_set_chip_and_handler_name(virq, &byt_irqchip, handle_simple_irq,
				      "demux");
	irq_set_chip_data(virq, vg);
	irq_set_irq_type(virq, IRQ_TYPE_NONE);

	return 0;
}

static const struct irq_domain_ops byt_gpio_irq_ops = {
	.map = byt_gpio_irq_map,
};

static int byt_gpio_probe(struct platform_device *pdev)
{
	struct byt_gpio *vg;
	struct gpio_chip *gc;
	struct resource *mem_rc, *irq_rc;
	struct device *dev = &pdev->dev;
	struct acpi_device *acpi_dev;
	struct pinctrl_gpio_range *range;
	acpi_handle handle = ACPI_HANDLE(dev);
	unsigned hwirq;
	int ret;

	if (acpi_bus_get_device(handle, &acpi_dev))
		return -ENODEV;

	vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL);
	if (!vg) {
		dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n");
		return -ENOMEM;
	}

	for (range = byt_ranges; range->name; range++) {
		if (!strcmp(acpi_dev->pnp.unique_id, range->name)) {
			vg->chip.ngpio = range->npins;
			vg->range = range;
			break;
		}
	}

	if (!vg->chip.ngpio || !vg->range)
		return -ENODEV;

	vg->pdev = pdev;
	platform_set_drvdata(pdev, vg);

	mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	vg->reg_base = devm_ioremap_resource(dev, mem_rc);
	if (IS_ERR(vg->reg_base))
		return PTR_ERR(vg->reg_base);

	spin_lock_init(&vg->lock);

	gc = &vg->chip;
	gc->label = dev_name(&pdev->dev);
	gc->owner = THIS_MODULE;
	gc->request = byt_gpio_request;
	gc->free = byt_gpio_free;
	gc->direction_input = byt_gpio_direction_input;
	gc->direction_output = byt_gpio_direction_output;
	gc->get = byt_gpio_get;
	gc->set = byt_gpio_set;
	gc->dbg_show = byt_gpio_dbg_show;
	gc->base = -1;
	gc->can_sleep = false;
	gc->dev = dev;

	/* set up interrupts  */
	irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (irq_rc && irq_rc->start) {
		hwirq = irq_rc->start;
		gc->to_irq = byt_gpio_to_irq;

		vg->domain = irq_domain_add_linear(NULL, gc->ngpio,
						   &byt_gpio_irq_ops, vg);
		if (!vg->domain)
			return -ENXIO;

		byt_gpio_irq_init_hw(vg);

		irq_set_handler_data(hwirq, vg);
		irq_set_chained_handler(hwirq, byt_gpio_irq_handler);
	}

	ret = gpiochip_add(gc);
	if (ret) {
		dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
		return ret;
	}

	pm_runtime_enable(dev);

	return 0;
}

static int byt_gpio_runtime_suspend(struct device *dev)
{
	return 0;
}

static int byt_gpio_runtime_resume(struct device *dev)
{
	return 0;
}

static const struct dev_pm_ops byt_gpio_pm_ops = {
	.runtime_suspend = byt_gpio_runtime_suspend,
	.runtime_resume = byt_gpio_runtime_resume,
};

static const struct acpi_device_id byt_gpio_acpi_match[] = {
	{ "INT33B2", 0 },
	{ "INT33FC", 0 },
	{ }
};
MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);

static int byt_gpio_remove(struct platform_device *pdev)
{
	struct byt_gpio *vg = platform_get_drvdata(pdev);
	int err;

	pm_runtime_disable(&pdev->dev);
	err = gpiochip_remove(&vg->chip);
	if (err)
		dev_warn(&pdev->dev, "failed to remove gpio_chip.\n");

	return 0;
}

static struct platform_driver byt_gpio_driver = {
	.probe          = byt_gpio_probe,
	.remove         = byt_gpio_remove,
	.driver         = {
		.name   = "byt_gpio",
		.owner  = THIS_MODULE,
		.pm	= &byt_gpio_pm_ops,
		.acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
	},
};

static int __init byt_gpio_init(void)
{
	return platform_driver_register(&byt_gpio_driver);
}

subsys_initcall(byt_gpio_init);
Commit	Line	Data
a5d811bb MN	1	/*
	2	* Pinctrl GPIO driver for Intel Baytrail
	3	* Copyright (c) 2012-2013, Intel Corporation.
	4	*
	5	* Author: Mathias Nyman <mathias.nyman@linux.intel.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program; if not, write to the Free Software Foundation, Inc.,
	18	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	19	*
	20	*/
	21
	22	#include <linux/kernel.h>
	23	#include <linux/module.h>
	24	#include <linux/init.h>
	25	#include <linux/types.h>
	26	#include <linux/bitops.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/irq.h>
	29	#include <linux/gpio.h>
	30	#include <linux/irqdomain.h>
	31	#include <linux/acpi.h>
a5d811bb MN	32	#include <linux/platform_device.h>
	33	#include <linux/seq_file.h>
	34	#include <linux/io.h>
	35	#include <linux/pm_runtime.h>
	36	#include <linux/pinctrl/pinctrl.h>
	37
	38	/* memory mapped register offsets */
	39	#define BYT_CONF0_REG 0x000
	40	#define BYT_CONF1_REG 0x004
	41	#define BYT_VAL_REG 0x008
	42	#define BYT_DFT_REG 0x00c
	43	#define BYT_INT_STAT_REG 0x800
	44
	45	/* BYT_CONF0_REG register bits */
3ff95885	46	#define BYT_IODEN BIT(31)
a5d811bb MN	47	#define BYT_TRIG_NEG BIT(26)
	48	#define BYT_TRIG_POS BIT(25)
	49	#define BYT_TRIG_LVL BIT(24)
3ff95885 MW	50	#define BYT_PULL_STR_SHIFT 9
	51	#define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT)
	52	#define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
	53	#define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
	54	#define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
	55	#define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
	56	#define BYT_PULL_ASSIGN_SHIFT 7
	57	#define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT)
	58	#define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
	59	#define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
a5d811bb MN	60	#define BYT_PIN_MUX 0x07
	61
	62	/* BYT_VAL_REG register bits */
	63	#define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
	64	#define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
	65	#define BYT_LEVEL BIT(0)
	66
	67	#define BYT_DIR_MASK (BIT(1) \| BIT(2))
	68	#define BYT_TRIG_MASK (BIT(26) \| BIT(25) \| BIT(24))
	69
	70	#define BYT_NGPIO_SCORE 102
	71	#define BYT_NGPIO_NCORE 28
	72	#define BYT_NGPIO_SUS 44
	73
42bd0070 CKH	74	#define BYT_SCORE_ACPI_UID "1"
	75	#define BYT_NCORE_ACPI_UID "2"
	76	#define BYT_SUS_ACPI_UID "3"
	77
a5d811bb MN	78	/*
	79	* Baytrail gpio controller consist of three separate sub-controllers called
	80	* SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
	81	*
	82	* GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
	83	* _not_ correspond to the first gpio register at controller's gpio base.
	84	* There is no logic or pattern in mapping gpio numbers to registers (pads) so
	85	* each sub-controller needs to have its own mapping table
	86	*/
	87
	88	/* score_pins[gpio_nr] = pad_nr */
	89
	90	static unsigned const score_pins[BYT_NGPIO_SCORE] = {
	91	85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
	92	36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
	93	54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
	94	52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
	95	95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
	96	86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
	97	80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
	98	2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
	99	31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
	100	24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
	101	97, 100,
	102	};
	103
	104	static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
	105	19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
	106	14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
	107	3, 6, 10, 13, 2, 5, 9, 7,
	108	};
	109
	110	static unsigned const sus_pins[BYT_NGPIO_SUS] = {
	111	29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
	112	18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
	113	0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
	114	26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
	115	52, 53, 59, 40,
	116	};
	117
	118	static struct pinctrl_gpio_range byt_ranges[] = {
	119	{
42bd0070	120	.name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */
a5d811bb MN	121	.npins = BYT_NGPIO_SCORE,
	122	.pins = score_pins,
	123	},
	124	{
42bd0070	125	.name = BYT_NCORE_ACPI_UID,
a5d811bb MN	126	.npins = BYT_NGPIO_NCORE,
	127	.pins = ncore_pins,
	128	},
	129	{
42bd0070	130	.name = BYT_SUS_ACPI_UID,
a5d811bb MN	131	.npins = BYT_NGPIO_SUS,
	132	.pins = sus_pins,
	133	},
	134	{
	135	},
	136	};
	137
	138	struct byt_gpio {
	139	struct gpio_chip chip;
	140	struct irq_domain *domain;
	141	struct platform_device *pdev;
	142	spinlock_t lock;
	143	void __iomem *reg_base;
	144	struct pinctrl_gpio_range *range;
	145	};
	146
17e52464 AS	147	#define to_byt_gpio(c) container_of(c, struct byt_gpio, chip)
17e52464 AS	148
a5d811bb MN	149	static void __iomem byt_gpio_reg(struct gpio_chip chip, unsigned offset,
	150	int reg)
	151	{
17e52464	152	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb	153	u32 reg_offset;
a5d811bb MN	154
	155	if (reg == BYT_INT_STAT_REG)
	156	reg_offset = (offset / 32) * 4;
	157	else
	158	reg_offset = vg->range->pins[offset] * 16;
	159
9c5b6557	160	return vg->reg_base + reg_offset + reg;
a5d811bb MN	161	}
a5d811bb MN	162
42bd0070 CKH	163	static bool is_special_pin(struct byt_gpio *vg, unsigned offset)
	164	{
	165	/* SCORE pin 92-93 */
	166	if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) &&
	167	offset >= 92 && offset <= 93)
	168	return true;
	169
	170	/* SUS pin 11-21 */
	171	if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) &&
	172	offset >= 11 && offset <= 21)
	173	return true;
	174
	175	return false;
	176	}
	177
a5d811bb MN	178	static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
a5d811bb MN	179	{
17e52464	180	struct byt_gpio *vg = to_byt_gpio(chip);
42bd0070 CKH	181	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
	182	u32 value;
	183	bool special;
	184
	185	/*
	186	* In most cases, func pin mux 000 means GPIO function.
	187	* But, some pins may have func pin mux 001 represents
	188	* GPIO function. Only allow user to export pin with
	189	* func pin mux preset as GPIO function by BIOS/FW.
	190	*/
	191	value = readl(reg) & BYT_PIN_MUX;
	192	special = is_special_pin(vg, offset);
	193	if ((special && value != 1) \|\| (!special && value)) {
	194	dev_err(&vg->pdev->dev,
	195	"pin %u cannot be used as GPIO.\n", offset);
	196	return -EINVAL;
	197	}
a5d811bb MN	198
	199	pm_runtime_get(&vg->pdev->dev);
	200
	201	return 0;
	202	}
	203
	204	static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
	205	{
17e52464	206	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb MN	207	void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
	208	u32 value;
	209
	210	/* clear interrupt triggering */
	211	value = readl(reg);
	212	value &= ~(BYT_TRIG_POS \| BYT_TRIG_NEG \| BYT_TRIG_LVL);
	213	writel(value, reg);
	214
	215	pm_runtime_put(&vg->pdev->dev);
	216	}
	217
	218	static int byt_irq_type(struct irq_data *d, unsigned type)
	219	{
	220	struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
	221	u32 offset = irqd_to_hwirq(d);
	222	u32 value;
	223	unsigned long flags;
	224	void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
	225
	226	if (offset >= vg->chip.ngpio)
	227	return -EINVAL;
	228
	229	spin_lock_irqsave(&vg->lock, flags);
	230	value = readl(reg);
	231
	232	/* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
	233	* are used to indicate high and low level triggering
	234	*/
	235	value &= ~(BYT_TRIG_POS \| BYT_TRIG_NEG \| BYT_TRIG_LVL);
	236
	237	switch (type) {
	238	case IRQ_TYPE_LEVEL_HIGH:
	239	value \|= BYT_TRIG_LVL;
	240	case IRQ_TYPE_EDGE_RISING:
	241	value \|= BYT_TRIG_POS;
	242	break;
	243	case IRQ_TYPE_LEVEL_LOW:
	244	value \|= BYT_TRIG_LVL;
	245	case IRQ_TYPE_EDGE_FALLING:
	246	value \|= BYT_TRIG_NEG;
	247	break;
	248	case IRQ_TYPE_EDGE_BOTH:
	249	value \|= (BYT_TRIG_NEG \| BYT_TRIG_POS);
	250	break;
	251	}
	252	writel(value, reg);
	253
	254	spin_unlock_irqrestore(&vg->lock, flags);
	255
	256	return 0;
	257	}
	258
	259	static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
	260	{
	261	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	262	return readl(reg) & BYT_LEVEL;
	263	}
	264
	265	static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	266	{
17e52464	267	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb MN	268	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	269	unsigned long flags;
	270	u32 old_val;
	271
	272	spin_lock_irqsave(&vg->lock, flags);
	273
	274	old_val = readl(reg);
	275
	276	if (value)
	277	writel(old_val \| BYT_LEVEL, reg);
	278	else
	279	writel(old_val & ~BYT_LEVEL, reg);
	280
	281	spin_unlock_irqrestore(&vg->lock, flags);
	282	}
	283
	284	static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	285	{
17e52464	286	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb MN	287	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	288	unsigned long flags;
	289	u32 value;
	290
	291	spin_lock_irqsave(&vg->lock, flags);
	292
	293	value = readl(reg) \| BYT_DIR_MASK;
496940c1	294	value &= ~BYT_INPUT_EN; /* active low */
a5d811bb MN	295	writel(value, reg);
	296
	297	spin_unlock_irqrestore(&vg->lock, flags);
	298
	299	return 0;
	300	}
	301
	302	static int byt_gpio_direction_output(struct gpio_chip *chip,
	303	unsigned gpio, int value)
	304	{
17e52464	305	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb MN	306	void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
	307	unsigned long flags;
	308	u32 reg_val;
	309
	310	spin_lock_irqsave(&vg->lock, flags);
	311
496940c1 AS	312	reg_val = readl(reg) \| BYT_DIR_MASK;
	313	reg_val &= ~BYT_OUTPUT_EN;
	314
	315	if (value)
	316	writel(reg_val \| BYT_LEVEL, reg);
	317	else
	318	writel(reg_val & ~BYT_LEVEL, reg);
a5d811bb MN	319
	320	spin_unlock_irqrestore(&vg->lock, flags);
	321
	322	return 0;
	323	}
	324
	325	static void byt_gpio_dbg_show(struct seq_file s, struct gpio_chip chip)
	326	{
17e52464	327	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb MN	328	int i;
	329	unsigned long flags;
	330	u32 conf0, val, offs;
	331
	332	spin_lock_irqsave(&vg->lock, flags);
	333
	334	for (i = 0; i < vg->chip.ngpio; i++) {
3ff95885 MW	335	const char *pull_str = NULL;
3ff95885 MW	336	const char *pull = NULL;
a4d8d6da	337	const char *label;
a5d811bb MN	338	offs = vg->range->pins[i] * 16;
	339	conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
	340	val = readl(vg->reg_base + offs + BYT_VAL_REG);
	341
a4d8d6da MN	342	label = gpiochip_is_requested(chip, i);
	343	if (!label)
	344	label = "Unrequested";
	345
3ff95885 MW	346	switch (conf0 & BYT_PULL_ASSIGN_MASK) {
	347	case BYT_PULL_ASSIGN_UP:
	348	pull = "up";
	349	break;
	350	case BYT_PULL_ASSIGN_DOWN:
	351	pull = "down";
	352	break;
	353	}
	354
	355	switch (conf0 & BYT_PULL_STR_MASK) {
	356	case BYT_PULL_STR_2K:
	357	pull_str = "2k";
	358	break;
	359	case BYT_PULL_STR_10K:
	360	pull_str = "10k";
	361	break;
	362	case BYT_PULL_STR_20K:
	363	pull_str = "20k";
	364	break;
	365	case BYT_PULL_STR_40K:
	366	pull_str = "40k";
	367	break;
	368	}
	369
a5d811bb	370	seq_printf(s,
3ff95885	371	" gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
a5d811bb	372	i,
a4d8d6da	373	label,
a5d811bb MN	374	val & BYT_INPUT_EN ? " " : "in",
	375	val & BYT_OUTPUT_EN ? " " : "out",
	376	val & BYT_LEVEL ? "hi" : "lo",
	377	vg->range->pins[i], offs,
	378	conf0 & 0x7,
3ff95885 MW	379	conf0 & BYT_TRIG_NEG ? " fall" : " ",
	380	conf0 & BYT_TRIG_POS ? " rise" : " ",
	381	conf0 & BYT_TRIG_LVL ? " level" : " ");
	382
	383	if (pull && pull_str)
	384	seq_printf(s, " %-4s %-3s", pull, pull_str);
	385	else
	386	seq_puts(s, " ");
	387
	388	if (conf0 & BYT_IODEN)
	389	seq_puts(s, " open-drain");
	390
	391	seq_puts(s, "\n");
a5d811bb MN	392	}
	393	spin_unlock_irqrestore(&vg->lock, flags);
	394	}
	395
	396	static int byt_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
	397	{
17e52464	398	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb MN	399	return irq_create_mapping(vg->domain, offset);
	400	}
	401
	402	static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
	403	{
	404	struct irq_data *data = irq_desc_get_irq_data(desc);
	405	struct byt_gpio *vg = irq_data_get_irq_handler_data(data);
	406	struct irq_chip *chip = irq_data_get_irq_chip(data);
	407	u32 base, pin, mask;
	408	void __iomem *reg;
	409	u32 pending;
	410	unsigned virq;
	411	int looplimit = 0;
	412
	413	/* check from GPIO controller which pin triggered the interrupt */
	414	for (base = 0; base < vg->chip.ngpio; base += 32) {
	415
	416	reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
	417
	418	while ((pending = readl(reg))) {
	419	pin = __ffs(pending);
	420	mask = BIT(pin);
	421	/* Clear before handling so we can't lose an edge */
	422	writel(mask, reg);
	423
	424	virq = irq_find_mapping(vg->domain, base + pin);
	425	generic_handle_irq(virq);
	426
	427	/* In case bios or user sets triggering incorretly a pin
	428	* might remain in "interrupt triggered" state.
	429	*/
	430	if (looplimit++ > 32) {
	431	dev_err(&vg->pdev->dev,
	432	"Gpio %d interrupt flood, disabling\n",
	433	base + pin);
	434
	435	reg = byt_gpio_reg(&vg->chip, base + pin,
	436	BYT_CONF0_REG);
	437	mask = readl(reg);
	438	mask &= ~(BYT_TRIG_NEG \| BYT_TRIG_POS \|
	439	BYT_TRIG_LVL);
	440	writel(mask, reg);
	441	mask = readl(reg); /* flush */
	442	break;
	443	}
	444	}
	445	}
	446	chip->irq_eoi(data);
	447	}
	448
	449	static void byt_irq_unmask(struct irq_data *d)
	450	{
	451	}
	452
	453	static void byt_irq_mask(struct irq_data *d)
	454	{
	455	}
	456
57ef0428	457	static int byt_irq_reqres(struct irq_data *d)
1d2d8ce6 LW	458	{
	459	struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
	460
57ef0428	461	if (gpio_lock_as_irq(&vg->chip, irqd_to_hwirq(d))) {
1d2d8ce6 LW	462	dev_err(vg->chip.dev,
	463	"unable to lock HW IRQ %lu for IRQ\n",
	464	irqd_to_hwirq(d));
57ef0428 LW	465	return -EINVAL;
57ef0428 LW	466	}
1d2d8ce6 LW	467	return 0;
	468	}
	469
57ef0428	470	static void byt_irq_relres(struct irq_data *d)
1d2d8ce6 LW	471	{
	472	struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
	473
1d2d8ce6 LW	474	gpio_unlock_as_irq(&vg->chip, irqd_to_hwirq(d));
	475	}
	476
a5d811bb MN	477	static struct irq_chip byt_irqchip = {
	478	.name = "BYT-GPIO",
	479	.irq_mask = byt_irq_mask,
	480	.irq_unmask = byt_irq_unmask,
	481	.irq_set_type = byt_irq_type,
57ef0428 LW	482	.irq_request_resources = byt_irq_reqres,
57ef0428 LW	483	.irq_release_resources = byt_irq_relres,
a5d811bb MN	484	};
	485
	486	static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
	487	{
	488	void __iomem *reg;
	489	u32 base, value;
	490
	491	/* clear interrupt status trigger registers */
	492	for (base = 0; base < vg->chip.ngpio; base += 32) {
	493	reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
	494	writel(0xffffffff, reg);
	495	/* make sure trigger bits are cleared, if not then a pin
	496	might be misconfigured in bios */
	497	value = readl(reg);
	498	if (value)
	499	dev_err(&vg->pdev->dev,
	500	"GPIO interrupt error, pins misconfigured\n");
	501	}
	502	}
	503
	504	static int byt_gpio_irq_map(struct irq_domain *d, unsigned int virq,
	505	irq_hw_number_t hw)
	506	{
	507	struct byt_gpio *vg = d->host_data;
	508
	509	irq_set_chip_and_handler_name(virq, &byt_irqchip, handle_simple_irq,
	510	"demux");
	511	irq_set_chip_data(virq, vg);
	512	irq_set_irq_type(virq, IRQ_TYPE_NONE);
	513
	514	return 0;
	515	}
	516
	517	static const struct irq_domain_ops byt_gpio_irq_ops = {
	518	.map = byt_gpio_irq_map,
	519	};
	520
	521	static int byt_gpio_probe(struct platform_device *pdev)
	522	{
	523	struct byt_gpio *vg;
	524	struct gpio_chip *gc;
	525	struct resource mem_rc, irq_rc;
	526	struct device *dev = &pdev->dev;
	527	struct acpi_device *acpi_dev;
	528	struct pinctrl_gpio_range *range;
	529	acpi_handle handle = ACPI_HANDLE(dev);
	530	unsigned hwirq;
	531	int ret;
	532
	533	if (acpi_bus_get_device(handle, &acpi_dev))
	534	return -ENODEV;
	535
	536	vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL);
	537	if (!vg) {
	538	dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n");
	539	return -ENOMEM;
	540	}
	541
	542	for (range = byt_ranges; range->name; range++) {
	543	if (!strcmp(acpi_dev->pnp.unique_id, range->name)) {
	544	vg->chip.ngpio = range->npins;
	545	vg->range = range;
	546	break;
	547	}
548	}
549
550	if (!vg->chip.ngpio \|\| !vg->range)
551	return -ENODEV;
552
553	vg->pdev = pdev;
554	platform_set_drvdata(pdev, vg);
555
556	mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
557	vg->reg_base = devm_ioremap_resource(dev, mem_rc);
558	if (IS_ERR(vg->reg_base))
559	return PTR_ERR(vg->reg_base);
560
561	spin_lock_init(&vg->lock);
562
563	gc = &vg->chip;
564	gc->label = dev_name(&pdev->dev);
565	gc->owner = THIS_MODULE;
566	gc->request = byt_gpio_request;
567	gc->free = byt_gpio_free;
568	gc->direction_input = byt_gpio_direction_input;
569	gc->direction_output = byt_gpio_direction_output;
570	gc->get = byt_gpio_get;
571	gc->set = byt_gpio_set;
572	gc->dbg_show = byt_gpio_dbg_show;
573	gc->base = -1;
9fb1f39e	574	gc->can_sleep = false;
a5d811bb MN	575	gc->dev = dev;
a5d811bb MN	576
a5d811bb MN	577	/* set up interrupts */
	578	irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	579	if (irq_rc && irq_rc->start) {
	580	hwirq = irq_rc->start;
	581	gc->to_irq = byt_gpio_to_irq;
	582
	583	vg->domain = irq_domain_add_linear(NULL, gc->ngpio,
	584	&byt_gpio_irq_ops, vg);
	585	if (!vg->domain)
	586	return -ENXIO;
	587
	588	byt_gpio_irq_init_hw(vg);
	589
	590	irq_set_handler_data(hwirq, vg);
	591	irq_set_chained_handler(hwirq, byt_gpio_irq_handler);
a5d811bb MN	592	}
a5d811bb MN	593
605a7bca JY	594	ret = gpiochip_add(gc);
	595	if (ret) {
	596	dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
	597	return ret;
	598	}
	599
a5d811bb MN	600	pm_runtime_enable(dev);
	601
	602	return 0;
	603	}
	604
	605	static int byt_gpio_runtime_suspend(struct device *dev)
	606	{
	607	return 0;
	608	}
	609
	610	static int byt_gpio_runtime_resume(struct device *dev)
	611	{
	612	return 0;
	613	}
	614
	615	static const struct dev_pm_ops byt_gpio_pm_ops = {
	616	.runtime_suspend = byt_gpio_runtime_suspend,
	617	.runtime_resume = byt_gpio_runtime_resume,
	618	};
	619
	620	static const struct acpi_device_id byt_gpio_acpi_match[] = {
	621	{ "INT33B2", 0 },
20482d32	622	{ "INT33FC", 0 },
a5d811bb MN	623	{ }
	624	};
	625	MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
	626
	627	static int byt_gpio_remove(struct platform_device *pdev)
	628	{
	629	struct byt_gpio *vg = platform_get_drvdata(pdev);
	630	int err;
ec243320	631
a5d811bb MN	632	pm_runtime_disable(&pdev->dev);
	633	err = gpiochip_remove(&vg->chip);
	634	if (err)
	635	dev_warn(&pdev->dev, "failed to remove gpio_chip.\n");
	636
	637	return 0;
	638	}
	639
	640	static struct platform_driver byt_gpio_driver = {
	641	.probe = byt_gpio_probe,
	642	.remove = byt_gpio_remove,
	643	.driver = {
	644	.name = "byt_gpio",
	645	.owner = THIS_MODULE,
	646	.pm = &byt_gpio_pm_ops,
	647	.acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
	648	},
	649	};
	650
	651	static int __init byt_gpio_init(void)
	652	{
	653	return platform_driver_register(&byt_gpio_driver);
	654	}
	655
	656	subsys_initcall(byt_gpio_init);