[deliverable/linux.git] / drivers / pinctrl / pinctrl-baytrail.c

/*
 * Pinctrl GPIO driver for Intel Baytrail
 * Copyright (c) 2012-2013, Intel Corporation.
 *
 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/bitops.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/irqdomain.h>
#include <linux/acpi.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <linux/pinctrl/pinctrl.h>

/* memory mapped register offsets */
#define BYT_CONF0_REG		0x000
#define BYT_CONF1_REG		0x004
#define BYT_VAL_REG		0x008
#define BYT_DFT_REG		0x00c
#define BYT_INT_STAT_REG	0x800

/* BYT_CONF0_REG register bits */
#define BYT_IODEN		BIT(31)
#define BYT_DIRECT_IRQ_EN	BIT(27)
#define BYT_TRIG_NEG		BIT(26)
#define BYT_TRIG_POS		BIT(25)
#define BYT_TRIG_LVL		BIT(24)
#define BYT_PULL_STR_SHIFT	9
#define BYT_PULL_STR_MASK	(3 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_STR_2K		(0 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_STR_10K	(1 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_STR_20K	(2 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_STR_40K	(3 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_ASSIGN_SHIFT	7
#define BYT_PULL_ASSIGN_MASK	(3 << BYT_PULL_ASSIGN_SHIFT)
#define BYT_PULL_ASSIGN_UP	(1 << BYT_PULL_ASSIGN_SHIFT)
#define BYT_PULL_ASSIGN_DOWN	(2 << BYT_PULL_ASSIGN_SHIFT)
#define BYT_PIN_MUX		0x07

/* BYT_VAL_REG register bits */
#define BYT_INPUT_EN		BIT(2)  /* 0: input enabled (active low)*/
#define BYT_OUTPUT_EN		BIT(1)  /* 0: output enabled (active low)*/
#define BYT_LEVEL		BIT(0)

#define BYT_DIR_MASK		(BIT(1) | BIT(2))
#define BYT_TRIG_MASK		(BIT(26) | BIT(25) | BIT(24))

#define BYT_NGPIO_SCORE		102
#define BYT_NGPIO_NCORE		28
#define BYT_NGPIO_SUS		44

#define BYT_SCORE_ACPI_UID	"1"
#define BYT_NCORE_ACPI_UID	"2"
#define BYT_SUS_ACPI_UID	"3"

/*
 * Baytrail gpio controller consist of three separate sub-controllers called
 * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
 *
 * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
 * _not_ correspond to the first gpio register at controller's gpio base.
 * There is no logic or pattern in mapping gpio numbers to registers (pads) so
 * each sub-controller needs to have its own mapping table
 */

/* score_pins[gpio_nr] = pad_nr */

static unsigned const score_pins[BYT_NGPIO_SCORE] = {
	85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
	36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
	54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
	52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
	95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
	86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
	80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
	2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
	31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
	24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
	97, 100,
};

static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
	19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
	14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
	3, 6, 10, 13, 2, 5, 9, 7,
};

static unsigned const sus_pins[BYT_NGPIO_SUS] = {
	29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
	18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
	0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
	26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
	52, 53, 59, 40,
};

static struct pinctrl_gpio_range byt_ranges[] = {
	{
		.name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */
		.npins = BYT_NGPIO_SCORE,
		.pins = score_pins,
	},
	{
		.name = BYT_NCORE_ACPI_UID,
		.npins = BYT_NGPIO_NCORE,
		.pins = ncore_pins,
	},
	{
		.name = BYT_SUS_ACPI_UID,
		.npins = BYT_NGPIO_SUS,
		.pins = sus_pins,
	},
	{
	},
};

struct byt_gpio {
	struct gpio_chip		chip;
	struct irq_domain		*domain;
	struct platform_device		*pdev;
	spinlock_t			lock;
	void __iomem			*reg_base;
	struct pinctrl_gpio_range	*range;
};

#define to_byt_gpio(c)	container_of(c, struct byt_gpio, chip)

static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
				 int reg)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	u32 reg_offset;

	if (reg == BYT_INT_STAT_REG)
		reg_offset = (offset / 32) * 4;
	else
		reg_offset = vg->range->pins[offset] * 16;

	return vg->reg_base + reg_offset + reg;
}

static bool is_special_pin(struct byt_gpio *vg, unsigned offset)
{
	/* SCORE pin 92-93 */
	if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) &&
		offset >= 92 && offset <= 93)
		return true;

	/* SUS pin 11-21 */
	if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) &&
		offset >= 11 && offset <= 21)
		return true;

	return false;
}

static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
	u32 value;
	bool special;

	/*
	 * In most cases, func pin mux 000 means GPIO function.
	 * But, some pins may have func pin mux 001 represents
	 * GPIO function. Only allow user to export pin with
	 * func pin mux preset as GPIO function by BIOS/FW.
	 */
	value = readl(reg) & BYT_PIN_MUX;
	special = is_special_pin(vg, offset);
	if ((special && value != 1) || (!special && value)) {
		dev_err(&vg->pdev->dev,
			"pin %u cannot be used as GPIO.\n", offset);
		return -EINVAL;
	}

	pm_runtime_get(&vg->pdev->dev);

	return 0;
}

static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
	u32 value;

	/* clear interrupt triggering */
	value = readl(reg);
	value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
	writel(value, reg);

	pm_runtime_put(&vg->pdev->dev);
}

static int byt_irq_type(struct irq_data *d, unsigned type)
{
	struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
	u32 offset = irqd_to_hwirq(d);
	u32 value;
	unsigned long flags;
	void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);

	if (offset >= vg->chip.ngpio)
		return -EINVAL;

	spin_lock_irqsave(&vg->lock, flags);
	value = readl(reg);

	/* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
	 * are used to indicate high and low level triggering
	 */
	value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);

	switch (type) {
	case IRQ_TYPE_LEVEL_HIGH:
		value |= BYT_TRIG_LVL;
	case IRQ_TYPE_EDGE_RISING:
		value |= BYT_TRIG_POS;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		value |= BYT_TRIG_LVL;
	case IRQ_TYPE_EDGE_FALLING:
		value |= BYT_TRIG_NEG;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
		break;
	}
	writel(value, reg);

	spin_unlock_irqrestore(&vg->lock, flags);

	return 0;
}

static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	return readl(reg) & BYT_LEVEL;
}

static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	unsigned long flags;
	u32 old_val;

	spin_lock_irqsave(&vg->lock, flags);

	old_val = readl(reg);

	if (value)
		writel(old_val | BYT_LEVEL, reg);
	else
		writel(old_val & ~BYT_LEVEL, reg);

	spin_unlock_irqrestore(&vg->lock, flags);
}

static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	unsigned long flags;
	u32 value;

	spin_lock_irqsave(&vg->lock, flags);

	value = readl(reg) | BYT_DIR_MASK;
	value &= ~BYT_INPUT_EN;		/* active low */
	writel(value, reg);

	spin_unlock_irqrestore(&vg->lock, flags);

	return 0;
}

static int byt_gpio_direction_output(struct gpio_chip *chip,
				     unsigned gpio, int value)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	void __iomem *conf_reg = byt_gpio_reg(chip, gpio, BYT_CONF0_REG);
	void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
	unsigned long flags;
	u32 reg_val;

	spin_lock_irqsave(&vg->lock, flags);

	/*
	 * Before making any direction modifications, do a check if gpio
	 * is set for direct IRQ.  On baytrail, setting GPIO to output does
	 * not make sense, so let's at least warn the caller before they shoot
	 * themselves in the foot.
	 */
	WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
		"Potential Error: Setting GPIO with direct_irq_en to output");

	reg_val = readl(reg) | BYT_DIR_MASK;
	reg_val &= ~BYT_OUTPUT_EN;

	if (value)
		writel(reg_val | BYT_LEVEL, reg);
	else
		writel(reg_val & ~BYT_LEVEL, reg);

	spin_unlock_irqrestore(&vg->lock, flags);

	return 0;
}

static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	int i;
	unsigned long flags;
	u32 conf0, val, offs;

	spin_lock_irqsave(&vg->lock, flags);

	for (i = 0; i < vg->chip.ngpio; i++) {
		const char *pull_str = NULL;
		const char *pull = NULL;
		const char *label;
		offs = vg->range->pins[i] * 16;
		conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
		val = readl(vg->reg_base + offs + BYT_VAL_REG);

		label = gpiochip_is_requested(chip, i);
		if (!label)
			label = "Unrequested";

		switch (conf0 & BYT_PULL_ASSIGN_MASK) {
		case BYT_PULL_ASSIGN_UP:
			pull = "up";
			break;
		case BYT_PULL_ASSIGN_DOWN:
			pull = "down";
			break;
		}

		switch (conf0 & BYT_PULL_STR_MASK) {
		case BYT_PULL_STR_2K:
			pull_str = "2k";
			break;
		case BYT_PULL_STR_10K:
			pull_str = "10k";
			break;
		case BYT_PULL_STR_20K:
			pull_str = "20k";
			break;
		case BYT_PULL_STR_40K:
			pull_str = "40k";
			break;
		}

		seq_printf(s,
			   " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
			   i,
			   label,
			   val & BYT_INPUT_EN ? "  " : "in",
			   val & BYT_OUTPUT_EN ? "   " : "out",
			   val & BYT_LEVEL ? "hi" : "lo",
			   vg->range->pins[i], offs,
			   conf0 & 0x7,
			   conf0 & BYT_TRIG_NEG ? " fall" : "     ",
			   conf0 & BYT_TRIG_POS ? " rise" : "     ",
			   conf0 & BYT_TRIG_LVL ? " level" : "      ");

		if (pull && pull_str)
			seq_printf(s, " %-4s %-3s", pull, pull_str);
		else
			seq_puts(s, "          ");

		if (conf0 & BYT_IODEN)
			seq_puts(s, " open-drain");

		seq_puts(s, "\n");
	}
	spin_unlock_irqrestore(&vg->lock, flags);
}

static int byt_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	return irq_create_mapping(vg->domain, offset);
}

static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
	struct irq_data *data = irq_desc_get_irq_data(desc);
	struct byt_gpio *vg = irq_data_get_irq_handler_data(data);
	struct irq_chip *chip = irq_data_get_irq_chip(data);
	u32 base, pin, mask;
	void __iomem *reg;
	u32 pending;
	unsigned virq;
	int looplimit = 0;

	/* check from GPIO controller which pin triggered the interrupt */
	for (base = 0; base < vg->chip.ngpio; base += 32) {

		reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);

		while ((pending = readl(reg))) {
			pin = __ffs(pending);
			mask = BIT(pin);
			/* Clear before handling so we can't lose an edge */
			writel(mask, reg);

			virq = irq_find_mapping(vg->domain, base + pin);
			generic_handle_irq(virq);

			/* In case bios or user sets triggering incorretly a pin
			 * might remain in "interrupt triggered" state.
			 */
			if (looplimit++ > 32) {
				dev_err(&vg->pdev->dev,
					"Gpio %d interrupt flood, disabling\n",
					base + pin);

				reg = byt_gpio_reg(&vg->chip, base + pin,
						   BYT_CONF0_REG);
				mask = readl(reg);
				mask &= ~(BYT_TRIG_NEG | BYT_TRIG_POS |
					  BYT_TRIG_LVL);
				writel(mask, reg);
				mask = readl(reg); /* flush */
				break;
			}
		}
	}
	chip->irq_eoi(data);
}

static void byt_irq_unmask(struct irq_data *d)
{
}

static void byt_irq_mask(struct irq_data *d)
{
}

static int byt_irq_reqres(struct irq_data *d)
{
	struct byt_gpio *vg = irq_data_get_irq_chip_data(d);

	if (gpio_lock_as_irq(&vg->chip, irqd_to_hwirq(d))) {
		dev_err(vg->chip.dev,
			"unable to lock HW IRQ %lu for IRQ\n",
			irqd_to_hwirq(d));
		return -EINVAL;
	}
	return 0;
}

static void byt_irq_relres(struct irq_data *d)
{
	struct byt_gpio *vg = irq_data_get_irq_chip_data(d);

	gpio_unlock_as_irq(&vg->chip, irqd_to_hwirq(d));
}

static struct irq_chip byt_irqchip = {
	.name = "BYT-GPIO",
	.irq_mask = byt_irq_mask,
	.irq_unmask = byt_irq_unmask,
	.irq_set_type = byt_irq_type,
	.irq_request_resources = byt_irq_reqres,
	.irq_release_resources = byt_irq_relres,
};

static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
{
	void __iomem *reg;
	u32 base, value;

	/* clear interrupt status trigger registers */
	for (base = 0; base < vg->chip.ngpio; base += 32) {
		reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
		writel(0xffffffff, reg);
		/* make sure trigger bits are cleared, if not then a pin
		   might be misconfigured in bios */
		value = readl(reg);
		if (value)
			dev_err(&vg->pdev->dev,
				"GPIO interrupt error, pins misconfigured\n");
	}
}

static int byt_gpio_irq_map(struct irq_domain *d, unsigned int virq,
			    irq_hw_number_t hw)
{
	struct byt_gpio *vg = d->host_data;

	irq_set_chip_and_handler_name(virq, &byt_irqchip, handle_simple_irq,
				      "demux");
	irq_set_chip_data(virq, vg);
	irq_set_irq_type(virq, IRQ_TYPE_NONE);

	return 0;
}

static const struct irq_domain_ops byt_gpio_irq_ops = {
	.map = byt_gpio_irq_map,
};

static int byt_gpio_probe(struct platform_device *pdev)
{
	struct byt_gpio *vg;
	struct gpio_chip *gc;
	struct resource *mem_rc, *irq_rc;
	struct device *dev = &pdev->dev;
	struct acpi_device *acpi_dev;
	struct pinctrl_gpio_range *range;
	acpi_handle handle = ACPI_HANDLE(dev);
	unsigned hwirq;
	int ret;

	if (acpi_bus_get_device(handle, &acpi_dev))
		return -ENODEV;

	vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL);
	if (!vg) {
		dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n");
		return -ENOMEM;
	}

	for (range = byt_ranges; range->name; range++) {
		if (!strcmp(acpi_dev->pnp.unique_id, range->name)) {
			vg->chip.ngpio = range->npins;
			vg->range = range;
			break;
		}
	}

	if (!vg->chip.ngpio || !vg->range)
		return -ENODEV;

	vg->pdev = pdev;
	platform_set_drvdata(pdev, vg);

	mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	vg->reg_base = devm_ioremap_resource(dev, mem_rc);
	if (IS_ERR(vg->reg_base))
		return PTR_ERR(vg->reg_base);

	spin_lock_init(&vg->lock);

	gc = &vg->chip;
	gc->label = dev_name(&pdev->dev);
	gc->owner = THIS_MODULE;
	gc->request = byt_gpio_request;
	gc->free = byt_gpio_free;
	gc->direction_input = byt_gpio_direction_input;
	gc->direction_output = byt_gpio_direction_output;
	gc->get = byt_gpio_get;
	gc->set = byt_gpio_set;
	gc->dbg_show = byt_gpio_dbg_show;
	gc->base = -1;
	gc->can_sleep = false;
	gc->dev = dev;

	/* set up interrupts  */
	irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (irq_rc && irq_rc->start) {
		hwirq = irq_rc->start;
		gc->to_irq = byt_gpio_to_irq;

		vg->domain = irq_domain_add_linear(NULL, gc->ngpio,
						   &byt_gpio_irq_ops, vg);
		if (!vg->domain)
			return -ENXIO;

		byt_gpio_irq_init_hw(vg);

		irq_set_handler_data(hwirq, vg);
		irq_set_chained_handler(hwirq, byt_gpio_irq_handler);
	}

	ret = gpiochip_add(gc);
	if (ret) {
		dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
		return ret;
	}

	pm_runtime_enable(dev);

	return 0;
}

static int byt_gpio_runtime_suspend(struct device *dev)
{
	return 0;
}

static int byt_gpio_runtime_resume(struct device *dev)
{
	return 0;
}

static const struct dev_pm_ops byt_gpio_pm_ops = {
	.runtime_suspend = byt_gpio_runtime_suspend,
	.runtime_resume = byt_gpio_runtime_resume,
};

static const struct acpi_device_id byt_gpio_acpi_match[] = {
	{ "INT33B2", 0 },
	{ "INT33FC", 0 },
	{ }
};
MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);

static int byt_gpio_remove(struct platform_device *pdev)
{
	struct byt_gpio *vg = platform_get_drvdata(pdev);

	pm_runtime_disable(&pdev->dev);
	gpiochip_remove(&vg->chip);

	return 0;
}

static struct platform_driver byt_gpio_driver = {
	.probe          = byt_gpio_probe,
	.remove         = byt_gpio_remove,
	.driver         = {
		.name   = "byt_gpio",
		.owner  = THIS_MODULE,
		.pm	= &byt_gpio_pm_ops,
		.acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
	},
};

static int __init byt_gpio_init(void)
{
	return platform_driver_register(&byt_gpio_driver);
}

subsys_initcall(byt_gpio_init);
Commit	Line	Data
a5d811bb MN	1	/*
	2	* Pinctrl GPIO driver for Intel Baytrail
	3	* Copyright (c) 2012-2013, Intel Corporation.
	4	*
	5	* Author: Mathias Nyman <mathias.nyman@linux.intel.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program; if not, write to the Free Software Foundation, Inc.,
	18	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	19	*
	20	*/
	21
	22	#include <linux/kernel.h>
	23	#include <linux/module.h>
	24	#include <linux/init.h>
	25	#include <linux/types.h>
	26	#include <linux/bitops.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/irq.h>
	29	#include <linux/gpio.h>
	30	#include <linux/irqdomain.h>
	31	#include <linux/acpi.h>
a5d811bb MN	32	#include <linux/platform_device.h>
	33	#include <linux/seq_file.h>
	34	#include <linux/io.h>
	35	#include <linux/pm_runtime.h>
	36	#include <linux/pinctrl/pinctrl.h>
	37
	38	/* memory mapped register offsets */
	39	#define BYT_CONF0_REG 0x000
	40	#define BYT_CONF1_REG 0x004
	41	#define BYT_VAL_REG 0x008
	42	#define BYT_DFT_REG 0x00c
	43	#define BYT_INT_STAT_REG 0x800
	44
	45	/* BYT_CONF0_REG register bits */
3ff95885	46	#define BYT_IODEN BIT(31)
ff998356	47	#define BYT_DIRECT_IRQ_EN BIT(27)
a5d811bb MN	48	#define BYT_TRIG_NEG BIT(26)
	49	#define BYT_TRIG_POS BIT(25)
	50	#define BYT_TRIG_LVL BIT(24)
3ff95885 MW	51	#define BYT_PULL_STR_SHIFT 9
	52	#define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT)
	53	#define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
	54	#define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
	55	#define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
	56	#define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
	57	#define BYT_PULL_ASSIGN_SHIFT 7
	58	#define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT)
	59	#define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
	60	#define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
a5d811bb MN	61	#define BYT_PIN_MUX 0x07
	62
	63	/* BYT_VAL_REG register bits */
	64	#define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
	65	#define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
	66	#define BYT_LEVEL BIT(0)
	67
	68	#define BYT_DIR_MASK (BIT(1) \| BIT(2))
	69	#define BYT_TRIG_MASK (BIT(26) \| BIT(25) \| BIT(24))
	70
	71	#define BYT_NGPIO_SCORE 102
	72	#define BYT_NGPIO_NCORE 28
	73	#define BYT_NGPIO_SUS 44
	74
42bd0070 CKH	75	#define BYT_SCORE_ACPI_UID "1"
	76	#define BYT_NCORE_ACPI_UID "2"
	77	#define BYT_SUS_ACPI_UID "3"
	78
a5d811bb MN	79	/*
	80	* Baytrail gpio controller consist of three separate sub-controllers called
	81	* SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
	82	*
	83	* GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
	84	* _not_ correspond to the first gpio register at controller's gpio base.
	85	* There is no logic or pattern in mapping gpio numbers to registers (pads) so
	86	* each sub-controller needs to have its own mapping table
	87	*/
	88
	89	/* score_pins[gpio_nr] = pad_nr */
	90
	91	static unsigned const score_pins[BYT_NGPIO_SCORE] = {
	92	85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
	93	36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
	94	54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
	95	52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
	96	95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
	97	86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
	98	80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
	99	2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
	100	31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
	101	24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
	102	97, 100,
	103	};
	104
	105	static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
	106	19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
	107	14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
	108	3, 6, 10, 13, 2, 5, 9, 7,
	109	};
	110
	111	static unsigned const sus_pins[BYT_NGPIO_SUS] = {
	112	29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
	113	18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
	114	0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
	115	26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
	116	52, 53, 59, 40,
	117	};
	118
	119	static struct pinctrl_gpio_range byt_ranges[] = {
	120	{
42bd0070	121	.name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */
a5d811bb MN	122	.npins = BYT_NGPIO_SCORE,
	123	.pins = score_pins,
	124	},
	125	{
42bd0070	126	.name = BYT_NCORE_ACPI_UID,
a5d811bb MN	127	.npins = BYT_NGPIO_NCORE,
	128	.pins = ncore_pins,
	129	},
	130	{
42bd0070	131	.name = BYT_SUS_ACPI_UID,
a5d811bb MN	132	.npins = BYT_NGPIO_SUS,
	133	.pins = sus_pins,
	134	},
	135	{
	136	},
	137	};
	138
	139	struct byt_gpio {
	140	struct gpio_chip chip;
	141	struct irq_domain *domain;
	142	struct platform_device *pdev;
	143	spinlock_t lock;
	144	void __iomem *reg_base;
	145	struct pinctrl_gpio_range *range;
	146	};
	147
17e52464 AS	148	#define to_byt_gpio(c) container_of(c, struct byt_gpio, chip)
17e52464 AS	149
a5d811bb MN	150	static void __iomem byt_gpio_reg(struct gpio_chip chip, unsigned offset,
	151	int reg)
	152	{
17e52464	153	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb	154	u32 reg_offset;
a5d811bb MN	155
	156	if (reg == BYT_INT_STAT_REG)
	157	reg_offset = (offset / 32) * 4;
	158	else
	159	reg_offset = vg->range->pins[offset] * 16;
	160
9c5b6557	161	return vg->reg_base + reg_offset + reg;
a5d811bb MN	162	}
a5d811bb MN	163
42bd0070 CKH	164	static bool is_special_pin(struct byt_gpio *vg, unsigned offset)
	165	{
	166	/* SCORE pin 92-93 */
	167	if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) &&
	168	offset >= 92 && offset <= 93)
	169	return true;
	170
	171	/* SUS pin 11-21 */
	172	if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) &&
	173	offset >= 11 && offset <= 21)
	174	return true;
	175
	176	return false;
	177	}
	178
a5d811bb MN	179	static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
a5d811bb MN	180	{
17e52464	181	struct byt_gpio *vg = to_byt_gpio(chip);
42bd0070 CKH	182	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
	183	u32 value;
	184	bool special;
	185
	186	/*
	187	* In most cases, func pin mux 000 means GPIO function.
	188	* But, some pins may have func pin mux 001 represents
	189	* GPIO function. Only allow user to export pin with
	190	* func pin mux preset as GPIO function by BIOS/FW.
	191	*/
	192	value = readl(reg) & BYT_PIN_MUX;
	193	special = is_special_pin(vg, offset);
	194	if ((special && value != 1) \|\| (!special && value)) {
	195	dev_err(&vg->pdev->dev,
	196	"pin %u cannot be used as GPIO.\n", offset);
	197	return -EINVAL;
	198	}
a5d811bb MN	199
	200	pm_runtime_get(&vg->pdev->dev);
	201
	202	return 0;
	203	}
	204
	205	static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
	206	{
17e52464	207	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb MN	208	void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
	209	u32 value;
	210
	211	/* clear interrupt triggering */
	212	value = readl(reg);
	213	value &= ~(BYT_TRIG_POS \| BYT_TRIG_NEG \| BYT_TRIG_LVL);
	214	writel(value, reg);
	215
	216	pm_runtime_put(&vg->pdev->dev);
	217	}
	218
	219	static int byt_irq_type(struct irq_data *d, unsigned type)
	220	{
	221	struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
	222	u32 offset = irqd_to_hwirq(d);
	223	u32 value;
	224	unsigned long flags;
	225	void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
	226
	227	if (offset >= vg->chip.ngpio)
	228	return -EINVAL;
	229
	230	spin_lock_irqsave(&vg->lock, flags);
	231	value = readl(reg);
	232
	233	/* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
	234	* are used to indicate high and low level triggering
	235	*/
	236	value &= ~(BYT_TRIG_POS \| BYT_TRIG_NEG \| BYT_TRIG_LVL);
	237
	238	switch (type) {
	239	case IRQ_TYPE_LEVEL_HIGH:
	240	value \|= BYT_TRIG_LVL;
	241	case IRQ_TYPE_EDGE_RISING:
	242	value \|= BYT_TRIG_POS;
	243	break;
	244	case IRQ_TYPE_LEVEL_LOW:
	245	value \|= BYT_TRIG_LVL;
	246	case IRQ_TYPE_EDGE_FALLING:
	247	value \|= BYT_TRIG_NEG;
	248	break;
	249	case IRQ_TYPE_EDGE_BOTH:
	250	value \|= (BYT_TRIG_NEG \| BYT_TRIG_POS);
	251	break;
	252	}
	253	writel(value, reg);
	254
	255	spin_unlock_irqrestore(&vg->lock, flags);
	256
	257	return 0;
	258	}
	259
	260	static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
	261	{
	262	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	263	return readl(reg) & BYT_LEVEL;
	264	}
	265
	266	static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	267	{
17e52464	268	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb MN	269	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	270	unsigned long flags;
	271	u32 old_val;
	272
	273	spin_lock_irqsave(&vg->lock, flags);
	274
	275	old_val = readl(reg);
	276
	277	if (value)
	278	writel(old_val \| BYT_LEVEL, reg);
	279	else
	280	writel(old_val & ~BYT_LEVEL, reg);
	281
	282	spin_unlock_irqrestore(&vg->lock, flags);
	283	}
	284
	285	static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	286	{
17e52464	287	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb MN	288	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	289	unsigned long flags;
	290	u32 value;
	291
	292	spin_lock_irqsave(&vg->lock, flags);
	293
	294	value = readl(reg) \| BYT_DIR_MASK;
496940c1	295	value &= ~BYT_INPUT_EN; /* active low */
a5d811bb MN	296	writel(value, reg);
	297
	298	spin_unlock_irqrestore(&vg->lock, flags);
	299
	300	return 0;
	301	}
	302
	303	static int byt_gpio_direction_output(struct gpio_chip *chip,
	304	unsigned gpio, int value)
	305	{
17e52464	306	struct byt_gpio *vg = to_byt_gpio(chip);
ff998356	307	void __iomem *conf_reg = byt_gpio_reg(chip, gpio, BYT_CONF0_REG);
a5d811bb MN	308	void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
	309	unsigned long flags;
	310	u32 reg_val;
	311
	312	spin_lock_irqsave(&vg->lock, flags);
	313
ff998356 EE	314	/*
	315	* Before making any direction modifications, do a check if gpio
	316	* is set for direct IRQ. On baytrail, setting GPIO to output does
	317	* not make sense, so let's at least warn the caller before they shoot
	318	* themselves in the foot.
	319	*/
	320	WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
	321	"Potential Error: Setting GPIO with direct_irq_en to output");
	322
496940c1 AS	323	reg_val = readl(reg) \| BYT_DIR_MASK;
	324	reg_val &= ~BYT_OUTPUT_EN;
	325
	326	if (value)
	327	writel(reg_val \| BYT_LEVEL, reg);
	328	else
	329	writel(reg_val & ~BYT_LEVEL, reg);
a5d811bb MN	330
	331	spin_unlock_irqrestore(&vg->lock, flags);
	332
	333	return 0;
	334	}
	335
	336	static void byt_gpio_dbg_show(struct seq_file s, struct gpio_chip chip)
	337	{
17e52464	338	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb MN	339	int i;
	340	unsigned long flags;
	341	u32 conf0, val, offs;
	342
	343	spin_lock_irqsave(&vg->lock, flags);
	344
	345	for (i = 0; i < vg->chip.ngpio; i++) {
3ff95885 MW	346	const char *pull_str = NULL;
3ff95885 MW	347	const char *pull = NULL;
a4d8d6da	348	const char *label;
a5d811bb MN	349	offs = vg->range->pins[i] * 16;
	350	conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
	351	val = readl(vg->reg_base + offs + BYT_VAL_REG);
	352
a4d8d6da MN	353	label = gpiochip_is_requested(chip, i);
	354	if (!label)
	355	label = "Unrequested";
	356
3ff95885 MW	357	switch (conf0 & BYT_PULL_ASSIGN_MASK) {
	358	case BYT_PULL_ASSIGN_UP:
	359	pull = "up";
	360	break;
	361	case BYT_PULL_ASSIGN_DOWN:
	362	pull = "down";
	363	break;
	364	}
	365
	366	switch (conf0 & BYT_PULL_STR_MASK) {
	367	case BYT_PULL_STR_2K:
	368	pull_str = "2k";
	369	break;
	370	case BYT_PULL_STR_10K:
	371	pull_str = "10k";
	372	break;
	373	case BYT_PULL_STR_20K:
	374	pull_str = "20k";
	375	break;
	376	case BYT_PULL_STR_40K:
	377	pull_str = "40k";
	378	break;
	379	}
	380
a5d811bb	381	seq_printf(s,
3ff95885	382	" gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
a5d811bb	383	i,
a4d8d6da	384	label,
a5d811bb MN	385	val & BYT_INPUT_EN ? " " : "in",
	386	val & BYT_OUTPUT_EN ? " " : "out",
	387	val & BYT_LEVEL ? "hi" : "lo",
	388	vg->range->pins[i], offs,
	389	conf0 & 0x7,
3ff95885 MW	390	conf0 & BYT_TRIG_NEG ? " fall" : " ",
	391	conf0 & BYT_TRIG_POS ? " rise" : " ",
	392	conf0 & BYT_TRIG_LVL ? " level" : " ");
	393
	394	if (pull && pull_str)
	395	seq_printf(s, " %-4s %-3s", pull, pull_str);
	396	else
	397	seq_puts(s, " ");
	398
	399	if (conf0 & BYT_IODEN)
	400	seq_puts(s, " open-drain");
	401
	402	seq_puts(s, "\n");
a5d811bb MN	403	}
	404	spin_unlock_irqrestore(&vg->lock, flags);
	405	}
	406
	407	static int byt_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
	408	{
17e52464	409	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb MN	410	return irq_create_mapping(vg->domain, offset);
	411	}
	412
	413	static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
	414	{
	415	struct irq_data *data = irq_desc_get_irq_data(desc);
	416	struct byt_gpio *vg = irq_data_get_irq_handler_data(data);
	417	struct irq_chip *chip = irq_data_get_irq_chip(data);
	418	u32 base, pin, mask;
	419	void __iomem *reg;
	420	u32 pending;
	421	unsigned virq;
	422	int looplimit = 0;
	423
	424	/* check from GPIO controller which pin triggered the interrupt */
	425	for (base = 0; base < vg->chip.ngpio; base += 32) {
	426
	427	reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
	428
	429	while ((pending = readl(reg))) {
	430	pin = __ffs(pending);
	431	mask = BIT(pin);
	432	/* Clear before handling so we can't lose an edge */
	433	writel(mask, reg);
	434
	435	virq = irq_find_mapping(vg->domain, base + pin);
	436	generic_handle_irq(virq);
	437
	438	/* In case bios or user sets triggering incorretly a pin
	439	* might remain in "interrupt triggered" state.
	440	*/
	441	if (looplimit++ > 32) {
	442	dev_err(&vg->pdev->dev,
	443	"Gpio %d interrupt flood, disabling\n",
	444	base + pin);
	445
	446	reg = byt_gpio_reg(&vg->chip, base + pin,
	447	BYT_CONF0_REG);
	448	mask = readl(reg);
	449	mask &= ~(BYT_TRIG_NEG \| BYT_TRIG_POS \|
	450	BYT_TRIG_LVL);
	451	writel(mask, reg);
	452	mask = readl(reg); /* flush */
	453	break;
	454	}
	455	}
	456	}
	457	chip->irq_eoi(data);
	458	}
	459
	460	static void byt_irq_unmask(struct irq_data *d)
	461	{
	462	}
	463
	464	static void byt_irq_mask(struct irq_data *d)
	465	{
	466	}
	467
57ef0428	468	static int byt_irq_reqres(struct irq_data *d)
1d2d8ce6 LW	469	{
	470	struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
	471
57ef0428	472	if (gpio_lock_as_irq(&vg->chip, irqd_to_hwirq(d))) {
1d2d8ce6 LW	473	dev_err(vg->chip.dev,
	474	"unable to lock HW IRQ %lu for IRQ\n",
	475	irqd_to_hwirq(d));
57ef0428 LW	476	return -EINVAL;
57ef0428 LW	477	}
1d2d8ce6 LW	478	return 0;
	479	}
	480
57ef0428	481	static void byt_irq_relres(struct irq_data *d)
1d2d8ce6 LW	482	{
	483	struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
	484
1d2d8ce6 LW	485	gpio_unlock_as_irq(&vg->chip, irqd_to_hwirq(d));
	486	}
	487
a5d811bb MN	488	static struct irq_chip byt_irqchip = {
	489	.name = "BYT-GPIO",
	490	.irq_mask = byt_irq_mask,
	491	.irq_unmask = byt_irq_unmask,
	492	.irq_set_type = byt_irq_type,
57ef0428 LW	493	.irq_request_resources = byt_irq_reqres,
57ef0428 LW	494	.irq_release_resources = byt_irq_relres,
a5d811bb MN	495	};
	496
	497	static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
	498	{
	499	void __iomem *reg;
	500	u32 base, value;
	501
	502	/* clear interrupt status trigger registers */
	503	for (base = 0; base < vg->chip.ngpio; base += 32) {
	504	reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
	505	writel(0xffffffff, reg);
	506	/* make sure trigger bits are cleared, if not then a pin
	507	might be misconfigured in bios */
	508	value = readl(reg);
	509	if (value)
	510	dev_err(&vg->pdev->dev,
	511	"GPIO interrupt error, pins misconfigured\n");
	512	}
	513	}
	514
	515	static int byt_gpio_irq_map(struct irq_domain *d, unsigned int virq,
	516	irq_hw_number_t hw)
	517	{
	518	struct byt_gpio *vg = d->host_data;
	519
	520	irq_set_chip_and_handler_name(virq, &byt_irqchip, handle_simple_irq,
	521	"demux");
	522	irq_set_chip_data(virq, vg);
	523	irq_set_irq_type(virq, IRQ_TYPE_NONE);
	524
	525	return 0;
	526	}
	527
	528	static const struct irq_domain_ops byt_gpio_irq_ops = {
	529	.map = byt_gpio_irq_map,
	530	};
	531
	532	static int byt_gpio_probe(struct platform_device *pdev)
	533	{
	534	struct byt_gpio *vg;
	535	struct gpio_chip *gc;
	536	struct resource mem_rc, irq_rc;
	537	struct device *dev = &pdev->dev;
	538	struct acpi_device *acpi_dev;
	539	struct pinctrl_gpio_range *range;
	540	acpi_handle handle = ACPI_HANDLE(dev);
	541	unsigned hwirq;
	542	int ret;
	543
	544	if (acpi_bus_get_device(handle, &acpi_dev))
	545	return -ENODEV;
	546
	547	vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL);
	548	if (!vg) {
	549	dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n");
	550	return -ENOMEM;
	551	}
	552
	553	for (range = byt_ranges; range->name; range++) {
	554	if (!strcmp(acpi_dev->pnp.unique_id, range->name)) {
	555	vg->chip.ngpio = range->npins;
	556	vg->range = range;
	557	break;
	558	}
559	}
560
561	if (!vg->chip.ngpio \|\| !vg->range)
562	return -ENODEV;
563
564	vg->pdev = pdev;
565	platform_set_drvdata(pdev, vg);
566
567	mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
568	vg->reg_base = devm_ioremap_resource(dev, mem_rc);
569	if (IS_ERR(vg->reg_base))
570	return PTR_ERR(vg->reg_base);
571
572	spin_lock_init(&vg->lock);
573
574	gc = &vg->chip;
575	gc->label = dev_name(&pdev->dev);
576	gc->owner = THIS_MODULE;
577	gc->request = byt_gpio_request;
578	gc->free = byt_gpio_free;
579	gc->direction_input = byt_gpio_direction_input;
580	gc->direction_output = byt_gpio_direction_output;
581	gc->get = byt_gpio_get;
582	gc->set = byt_gpio_set;
583	gc->dbg_show = byt_gpio_dbg_show;
584	gc->base = -1;
9fb1f39e	585	gc->can_sleep = false;
a5d811bb MN	586	gc->dev = dev;
a5d811bb MN	587
a5d811bb MN	588	/* set up interrupts */
	589	irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	590	if (irq_rc && irq_rc->start) {
	591	hwirq = irq_rc->start;
	592	gc->to_irq = byt_gpio_to_irq;
	593
	594	vg->domain = irq_domain_add_linear(NULL, gc->ngpio,
	595	&byt_gpio_irq_ops, vg);
	596	if (!vg->domain)
	597	return -ENXIO;
	598
	599	byt_gpio_irq_init_hw(vg);
	600
	601	irq_set_handler_data(hwirq, vg);
	602	irq_set_chained_handler(hwirq, byt_gpio_irq_handler);
a5d811bb MN	603	}
a5d811bb MN	604
605a7bca JY	605	ret = gpiochip_add(gc);
	606	if (ret) {
	607	dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
	608	return ret;
	609	}
	610
a5d811bb MN	611	pm_runtime_enable(dev);
	612
	613	return 0;
	614	}
	615
	616	static int byt_gpio_runtime_suspend(struct device *dev)
	617	{
	618	return 0;
	619	}
	620
	621	static int byt_gpio_runtime_resume(struct device *dev)
	622	{
	623	return 0;
	624	}
	625
	626	static const struct dev_pm_ops byt_gpio_pm_ops = {
	627	.runtime_suspend = byt_gpio_runtime_suspend,
	628	.runtime_resume = byt_gpio_runtime_resume,
	629	};
	630
	631	static const struct acpi_device_id byt_gpio_acpi_match[] = {
	632	{ "INT33B2", 0 },
20482d32	633	{ "INT33FC", 0 },
a5d811bb MN	634	{ }
	635	};
	636	MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
	637
	638	static int byt_gpio_remove(struct platform_device *pdev)
	639	{
	640	struct byt_gpio *vg = platform_get_drvdata(pdev);
ec243320	641
a5d811bb	642	pm_runtime_disable(&pdev->dev);
b4e7c55d	643	gpiochip_remove(&vg->chip);
a5d811bb MN	644
	645	return 0;
	646	}
	647
	648	static struct platform_driver byt_gpio_driver = {
	649	.probe = byt_gpio_probe,
	650	.remove = byt_gpio_remove,
	651	.driver = {
	652	.name = "byt_gpio",
	653	.owner = THIS_MODULE,
	654	.pm = &byt_gpio_pm_ops,
	655	.acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
	656	},
	657	};
	658
	659	static int __init byt_gpio_init(void)
	660	{
	661	return platform_driver_register(&byt_gpio_driver);
	662	}
	663
	664	subsys_initcall(byt_gpio_init);