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Merge tag 'v3.8-rc7' into regulator-core
[deliverable/linux.git] / drivers / pinctrl / pinctrl-exynos.c
CommitLineData
43b169db
TA		 1/*
2 * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2012 Linaro Ltd
7 * http://www.linaro.org
8 *
9 * Author: Thomas Abraham <thomas.ab@samsung.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This file contains the Samsung Exynos specific information required by the
17 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
18 * external gpio and wakeup interrupt support.
19 */
20
21#include <linux/module.h>
22#include <linux/device.h>
23#include <linux/interrupt.h>
24#include <linux/irqdomain.h>
25#include <linux/irq.h>
26#include <linux/of_irq.h>
27#include <linux/io.h>
28#include <linux/slab.h>
29#include <linux/err.h>
30
31#include <asm/mach/irq.h>
32
33#include "pinctrl-samsung.h"
34#include "pinctrl-exynos.h"
35
36/* list of external wakeup controllers supported */
37static const struct of_device_id exynos_wkup_irq_ids[] = {
38 { .compatible = "samsung,exynos4210-wakeup-eint", },
afa538c2 39 { }
43b169db
TA		 40};
41
42static void exynos_gpio_irq_unmask(struct irq_data *irqd)
43{
595be726
TF		 44 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
45 struct samsung_pinctrl_drv_data *d = bank->drvdata;
46 unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset;
43b169db
TA		 47 unsigned long mask;
48
49 mask = readl(d->virt_base + reg_mask);
595be726 50 mask &= ~(1 << irqd->hwirq);
43b169db
TA		 51 writel(mask, d->virt_base + reg_mask);
52}
53
54static void exynos_gpio_irq_mask(struct irq_data *irqd)
55{
595be726
TF		 56 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
57 struct samsung_pinctrl_drv_data *d = bank->drvdata;
58 unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset;
43b169db
TA		 59 unsigned long mask;
60
61 mask = readl(d->virt_base + reg_mask);
595be726 62 mask |= 1 << irqd->hwirq;
43b169db
TA		 63 writel(mask, d->virt_base + reg_mask);
64}
65
66static void exynos_gpio_irq_ack(struct irq_data *irqd)
67{
595be726
TF		 68 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
69 struct samsung_pinctrl_drv_data *d = bank->drvdata;
70 unsigned long reg_pend = d->ctrl->geint_pend + bank->eint_offset;
43b169db 71
595be726 72 writel(1 << irqd->hwirq, d->virt_base + reg_pend);
43b169db
TA		 73}
74
75static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
76{
595be726
TF		 77 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
78 struct samsung_pinctrl_drv_data *d = bank->drvdata;
43b169db 79 struct samsung_pin_ctrl *ctrl = d->ctrl;
595be726
TF		 80 unsigned int pin = irqd->hwirq;
81 unsigned int shift = EXYNOS_EINT_CON_LEN * pin;
43b169db 82 unsigned int con, trig_type;
595be726 83 unsigned long reg_con = ctrl->geint_con + bank->eint_offset;
ee2f573c 84 unsigned int mask;
43b169db
TA		 85
86 switch (type) {
87 case IRQ_TYPE_EDGE_RISING:
88 trig_type = EXYNOS_EINT_EDGE_RISING;
89 break;
90 case IRQ_TYPE_EDGE_FALLING:
91 trig_type = EXYNOS_EINT_EDGE_FALLING;
92 break;
93 case IRQ_TYPE_EDGE_BOTH:
94 trig_type = EXYNOS_EINT_EDGE_BOTH;
95 break;
96 case IRQ_TYPE_LEVEL_HIGH:
97 trig_type = EXYNOS_EINT_LEVEL_HIGH;
98 break;
99 case IRQ_TYPE_LEVEL_LOW:
100 trig_type = EXYNOS_EINT_LEVEL_LOW;
101 break;
102 default:
103 pr_err("unsupported external interrupt type\n");
104 return -EINVAL;
105 }
106
107 if (type & IRQ_TYPE_EDGE_BOTH)
108 __irq_set_handler_locked(irqd->irq, handle_edge_irq);
109 else
110 __irq_set_handler_locked(irqd->irq, handle_level_irq);
111
112 con = readl(d->virt_base + reg_con);
113 con &= ~(EXYNOS_EINT_CON_MASK << shift);
114 con |= trig_type << shift;
115 writel(con, d->virt_base + reg_con);
ee2f573c
TF		 116
117 reg_con = bank->pctl_offset;
595be726 118 shift = pin * bank->func_width;
ee2f573c
TF		 119 mask = (1 << bank->func_width) - 1;
120
121 con = readl(d->virt_base + reg_con);
122 con &= ~(mask << shift);
123 con |= EXYNOS_EINT_FUNC << shift;
124 writel(con, d->virt_base + reg_con);
125
43b169db
TA		 126 return 0;
127}
128
129/*
130 * irq_chip for gpio interrupts.
131 */
132static struct irq_chip exynos_gpio_irq_chip = {
133 .name = "exynos_gpio_irq_chip",
134 .irq_unmask = exynos_gpio_irq_unmask,
135 .irq_mask = exynos_gpio_irq_mask,
136 .irq_ack = exynos_gpio_irq_ack,
137 .irq_set_type = exynos_gpio_irq_set_type,
138};
139
43b169db
TA		 140static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
141 irq_hw_number_t hw)
142{
595be726 143 struct samsung_pin_bank *b = h->host_data;
43b169db 144
595be726 145 irq_set_chip_data(virq, b);
43b169db
TA		 146 irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip,
147 handle_level_irq);
148 set_irq_flags(virq, IRQF_VALID);
149 return 0;
150}
151
43b169db
TA		 152/*
153 * irq domain callbacks for external gpio interrupt controller.
154 */
155static const struct irq_domain_ops exynos_gpio_irqd_ops = {
156 .map = exynos_gpio_irq_map,
43b169db
TA		 157 .xlate = irq_domain_xlate_twocell,
158};
159
160static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
161{
162 struct samsung_pinctrl_drv_data *d = data;
163 struct samsung_pin_ctrl *ctrl = d->ctrl;
164 struct samsung_pin_bank *bank = ctrl->pin_banks;
165 unsigned int svc, group, pin, virq;
166
167 svc = readl(d->virt_base + ctrl->svc);
168 group = EXYNOS_SVC_GROUP(svc);
169 pin = svc & EXYNOS_SVC_NUM_MASK;
170
171 if (!group)
172 return IRQ_HANDLED;
173 bank += (group - 1);
174
595be726 175 virq = irq_linear_revmap(bank->irq_domain, pin);
43b169db
TA		 176 if (!virq)
177 return IRQ_NONE;
178 generic_handle_irq(virq);
179 return IRQ_HANDLED;
180}
181
182/*
183 * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
184 * @d: driver data of samsung pinctrl driver.
185 */
186static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
187{
595be726 188 struct samsung_pin_bank *bank;
43b169db
TA		 189 struct device *dev = d->dev;
190 unsigned int ret;
595be726 191 unsigned int i;
43b169db
TA		 192
193 if (!d->irq) {
194 dev_err(dev, "irq number not available\n");
195 return -EINVAL;
196 }
197
198 ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
199 0, dev_name(dev), d);
200 if (ret) {
201 dev_err(dev, "irq request failed\n");
202 return -ENXIO;
203 }
204
595be726
TF		 205 bank = d->ctrl->pin_banks;
206 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
207 if (bank->eint_type != EINT_TYPE_GPIO)
208 continue;
209 bank->irq_domain = irq_domain_add_linear(bank->of_node,
210 bank->nr_pins, &exynos_gpio_irqd_ops, bank);
211 if (!bank->irq_domain) {
212 dev_err(dev, "gpio irq domain add failed\n");
213 return -ENXIO;
214 }
43b169db
TA		 215 }
216
217 return 0;
218}
219
220static void exynos_wkup_irq_unmask(struct irq_data *irqd)
221{
a04b07c0
TF		 222 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
223 struct samsung_pinctrl_drv_data *d = b->drvdata;
224 unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
43b169db
TA		 225 unsigned long mask;
226
227 mask = readl(d->virt_base + reg_mask);
a04b07c0 228 mask &= ~(1 << irqd->hwirq);
43b169db
TA		 229 writel(mask, d->virt_base + reg_mask);
230}
231
232static void exynos_wkup_irq_mask(struct irq_data *irqd)
233{
a04b07c0
TF		 234 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
235 struct samsung_pinctrl_drv_data *d = b->drvdata;
236 unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
43b169db
TA		 237 unsigned long mask;
238
239 mask = readl(d->virt_base + reg_mask);
a04b07c0 240 mask |= 1 << irqd->hwirq;
43b169db
TA		 241 writel(mask, d->virt_base + reg_mask);
242}
243
244static void exynos_wkup_irq_ack(struct irq_data *irqd)
245{
a04b07c0
TF		 246 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
247 struct samsung_pinctrl_drv_data *d = b->drvdata;
248 unsigned long pend = d->ctrl->weint_pend + b->eint_offset;
43b169db 249
a04b07c0 250 writel(1 << irqd->hwirq, d->virt_base + pend);
43b169db
TA		 251}
252
253static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
254{
a04b07c0
TF		 255 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
256 struct samsung_pinctrl_drv_data *d = bank->drvdata;
257 unsigned int pin = irqd->hwirq;
258 unsigned long reg_con = d->ctrl->weint_con + bank->eint_offset;
43b169db
TA		 259 unsigned long shift = EXYNOS_EINT_CON_LEN * pin;
260 unsigned long con, trig_type;
22b9ba03 261 unsigned int mask;
43b169db
TA		 262
263 switch (type) {
264 case IRQ_TYPE_EDGE_RISING:
265 trig_type = EXYNOS_EINT_EDGE_RISING;
266 break;
267 case IRQ_TYPE_EDGE_FALLING:
268 trig_type = EXYNOS_EINT_EDGE_FALLING;
269 break;
270 case IRQ_TYPE_EDGE_BOTH:
271 trig_type = EXYNOS_EINT_EDGE_BOTH;
272 break;
273 case IRQ_TYPE_LEVEL_HIGH:
274 trig_type = EXYNOS_EINT_LEVEL_HIGH;
275 break;
276 case IRQ_TYPE_LEVEL_LOW:
277 trig_type = EXYNOS_EINT_LEVEL_LOW;
278 break;
279 default:
280 pr_err("unsupported external interrupt type\n");
281 return -EINVAL;
282 }
283
284 if (type & IRQ_TYPE_EDGE_BOTH)
285 __irq_set_handler_locked(irqd->irq, handle_edge_irq);
286 else
287 __irq_set_handler_locked(irqd->irq, handle_level_irq);
288
289 con = readl(d->virt_base + reg_con);
290 con &= ~(EXYNOS_EINT_CON_MASK << shift);
291 con |= trig_type << shift;
292 writel(con, d->virt_base + reg_con);
22b9ba03
TF		 293
294 reg_con = bank->pctl_offset;
295 shift = pin * bank->func_width;
296 mask = (1 << bank->func_width) - 1;
297
298 con = readl(d->virt_base + reg_con);
299 con &= ~(mask << shift);
300 con |= EXYNOS_EINT_FUNC << shift;
301 writel(con, d->virt_base + reg_con);
302
43b169db
TA		 303 return 0;
304}
305
306/*
307 * irq_chip for wakeup interrupts
308 */
309static struct irq_chip exynos_wkup_irq_chip = {
310 .name = "exynos_wkup_irq_chip",
311 .irq_unmask = exynos_wkup_irq_unmask,
312 .irq_mask = exynos_wkup_irq_mask,
313 .irq_ack = exynos_wkup_irq_ack,
314 .irq_set_type = exynos_wkup_irq_set_type,
315};
316
317/* interrupt handler for wakeup interrupts 0..15 */
318static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
319{
320 struct exynos_weint_data *eintd = irq_get_handler_data(irq);
a04b07c0 321 struct samsung_pin_bank *bank = eintd->bank;
43b169db
TA		 322 struct irq_chip *chip = irq_get_chip(irq);
323 int eint_irq;
324
325 chained_irq_enter(chip, desc);
326 chip->irq_mask(&desc->irq_data);
327
328 if (chip->irq_ack)
329 chip->irq_ack(&desc->irq_data);
330
a04b07c0 331 eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq);
43b169db
TA		 332 generic_handle_irq(eint_irq);
333 chip->irq_unmask(&desc->irq_data);
334 chained_irq_exit(chip, desc);
335}
336
a04b07c0
TF		 337static inline void exynos_irq_demux_eint(unsigned long pend,
338 struct irq_domain *domain)
43b169db
TA		 339{
340 unsigned int irq;
341
342 while (pend) {
343 irq = fls(pend) - 1;
a04b07c0 344 generic_handle_irq(irq_find_mapping(domain, irq));
43b169db
TA		 345 pend &= ~(1 << irq);
346 }
347}
348
349/* interrupt handler for wakeup interrupt 16 */
350static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
351{
352 struct irq_chip *chip = irq_get_chip(irq);
a04b07c0
TF		 353 struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq);
354 struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata;
355 struct samsung_pin_ctrl *ctrl = d->ctrl;
43b169db 356 unsigned long pend;
de59049b 357 unsigned long mask;
a04b07c0 358 int i;
43b169db
TA		 359
360 chained_irq_enter(chip, desc);
a04b07c0
TF		 361
362 for (i = 0; i < eintd->nr_banks; ++i) {
363 struct samsung_pin_bank *b = eintd->banks[i];
364 pend = readl(d->virt_base + ctrl->weint_pend + b->eint_offset);
365 mask = readl(d->virt_base + ctrl->weint_mask + b->eint_offset);
366 exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
367 }
368
43b169db
TA		 369 chained_irq_exit(chip, desc);
370}
371
372static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
373 irq_hw_number_t hw)
374{
375 irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip, handle_level_irq);
376 irq_set_chip_data(virq, h->host_data);
377 set_irq_flags(virq, IRQF_VALID);
378 return 0;
379}
380
381/*
382 * irq domain callbacks for external wakeup interrupt controller.
383 */
384static const struct irq_domain_ops exynos_wkup_irqd_ops = {
385 .map = exynos_wkup_irq_map,
386 .xlate = irq_domain_xlate_twocell,
387};
388
389/*
390 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
391 * @d: driver data of samsung pinctrl driver.
392 */
393static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
394{
395 struct device *dev = d->dev;
c3ad056b
TF		 396 struct device_node *wkup_np = NULL;
397 struct device_node *np;
a04b07c0 398 struct samsung_pin_bank *bank;
43b169db 399 struct exynos_weint_data *weint_data;
a04b07c0
TF		 400 struct exynos_muxed_weint_data *muxed_data;
401 unsigned int muxed_banks = 0;
402 unsigned int i;
43b169db
TA		 403 int idx, irq;
404
c3ad056b
TF		 405 for_each_child_of_node(dev->of_node, np) {
406 if (of_match_node(exynos_wkup_irq_ids, np)) {
407 wkup_np = np;
408 break;
409 }
43b169db 410 }
c3ad056b
TF		 411 if (!wkup_np)
412 return -ENODEV;
43b169db 413
a04b07c0
TF		 414 bank = d->ctrl->pin_banks;
415 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
416 if (bank->eint_type != EINT_TYPE_WKUP)
417 continue;
43b169db 418
a04b07c0
TF		 419 bank->irq_domain = irq_domain_add_linear(bank->of_node,
420 bank->nr_pins, &exynos_wkup_irqd_ops, bank);
421 if (!bank->irq_domain) {
422 dev_err(dev, "wkup irq domain add failed\n");
423 return -ENXIO;
424 }
43b169db 425
a04b07c0
TF		 426 if (!of_find_property(bank->of_node, "interrupts", NULL)) {
427 bank->eint_type = EINT_TYPE_WKUP_MUX;
428 ++muxed_banks;
429 continue;
430 }
43b169db 431
a04b07c0
TF		 432 weint_data = devm_kzalloc(dev, bank->nr_pins
433 * sizeof(*weint_data), GFP_KERNEL);
434 if (!weint_data) {
435 dev_err(dev, "could not allocate memory for weint_data\n");
436 return -ENOMEM;
437 }
43b169db 438
a04b07c0
TF		 439 for (idx = 0; idx < bank->nr_pins; ++idx) {
440 irq = irq_of_parse_and_map(bank->of_node, idx);
441 if (!irq) {
442 dev_err(dev, "irq number for eint-%s-%d not found\n",
443 bank->name, idx);
444 continue;
445 }
446 weint_data[idx].irq = idx;
447 weint_data[idx].bank = bank;
43b169db
TA		 448 irq_set_handler_data(irq, &weint_data[idx]);
449 irq_set_chained_handler(irq, exynos_irq_eint0_15);
43b169db
TA		 450 }
451 }
a04b07c0
TF		 452
453 if (!muxed_banks)
454 return 0;
455
456 irq = irq_of_parse_and_map(wkup_np, 0);
457 if (!irq) {
458 dev_err(dev, "irq number for muxed EINTs not found\n");
459 return 0;
460 }
461
462 muxed_data = devm_kzalloc(dev, sizeof(*muxed_data)
463 + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL);
464 if (!muxed_data) {
465 dev_err(dev, "could not allocate memory for muxed_data\n");
466 return -ENOMEM;
467 }
468
469 irq_set_chained_handler(irq, exynos_irq_demux_eint16_31);
470 irq_set_handler_data(irq, muxed_data);
471
472 bank = d->ctrl->pin_banks;
473 idx = 0;
474 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
475 if (bank->eint_type != EINT_TYPE_WKUP_MUX)
476 continue;
477
478 muxed_data->banks[idx++] = bank;
479 }
480 muxed_data->nr_banks = muxed_banks;
481
43b169db
TA		 482 return 0;
483}
484
485/* pin banks of exynos4210 pin-controller 0 */
486static struct samsung_pin_bank exynos4210_pin_banks0[] = {
1b6056d6
TF		 487 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
488 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
489 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
490 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
491 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
492 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
493 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
494 EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
495 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
496 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
497 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
498 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
499 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
500 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
501 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
502 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
43b169db
TA		 503};
504
505/* pin banks of exynos4210 pin-controller 1 */
506static struct samsung_pin_bank exynos4210_pin_banks1[] = {
1b6056d6
TF		 507 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
508 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
509 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
510 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
511 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
512 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
513 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
514 EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
515 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
40ba6227
TF		 516 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
517 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
518 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
519 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
520 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
521 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
522 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
a04b07c0
TF		 523 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
524 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
525 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
526 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
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TA		 527};
528
529/* pin banks of exynos4210 pin-controller 2 */
530static struct samsung_pin_bank exynos4210_pin_banks2[] = {
40ba6227 531 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
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TA		 532};
533
534/*
535 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
536 * three gpio/pin-mux/pinconfig controllers.
537 */
538struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
539 {
540 /* pin-controller instance 0 data */
541 .pin_banks = exynos4210_pin_banks0,
542 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
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TA		 543 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
544 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
545 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
546 .svc = EXYNOS_SVC_OFFSET,
547 .eint_gpio_init = exynos_eint_gpio_init,
548 .label = "exynos4210-gpio-ctrl0",
549 }, {
550 /* pin-controller instance 1 data */
551 .pin_banks = exynos4210_pin_banks1,
552 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
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TA		 553 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
554 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
555 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
556 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
557 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
558 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
559 .svc = EXYNOS_SVC_OFFSET,
560 .eint_gpio_init = exynos_eint_gpio_init,
561 .eint_wkup_init = exynos_eint_wkup_init,
562 .label = "exynos4210-gpio-ctrl1",
563 }, {
564 /* pin-controller instance 2 data */
565 .pin_banks = exynos4210_pin_banks2,
566 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),
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TA		 567 .label = "exynos4210-gpio-ctrl2",
568 },
569};
6edc794a
TF		 570
571/* pin banks of exynos4x12 pin-controller 0 */
572static struct samsung_pin_bank exynos4x12_pin_banks0[] = {
573 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
574 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
575 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
576 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
577 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
578 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
579 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
580 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
581 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
582 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
583 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
584 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
585 EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
586};
587
588/* pin banks of exynos4x12 pin-controller 1 */
589static struct samsung_pin_bank exynos4x12_pin_banks1[] = {
590 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
591 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
592 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
593 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
594 EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
595 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
596 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
597 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
598 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
599 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
600 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
601 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
602 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
603 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
604 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
605 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
606 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
607 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
608 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
609 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
610 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
611 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
612 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
613};
614
615/* pin banks of exynos4x12 pin-controller 2 */
616static struct samsung_pin_bank exynos4x12_pin_banks2[] = {
617 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
618};
619
620/* pin banks of exynos4x12 pin-controller 3 */
621static struct samsung_pin_bank exynos4x12_pin_banks3[] = {
622 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
623 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
624 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
625 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
626 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
627};
628
629/*
630 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
631 * four gpio/pin-mux/pinconfig controllers.
632 */
633struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
634 {
635 /* pin-controller instance 0 data */
636 .pin_banks = exynos4x12_pin_banks0,
637 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0),
638 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
639 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
640 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
641 .svc = EXYNOS_SVC_OFFSET,
642 .eint_gpio_init = exynos_eint_gpio_init,
643 .label = "exynos4x12-gpio-ctrl0",
644 }, {
645 /* pin-controller instance 1 data */
646 .pin_banks = exynos4x12_pin_banks1,
647 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1),
648 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
649 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
650 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
651 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
652 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
653 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
654 .svc = EXYNOS_SVC_OFFSET,
655 .eint_gpio_init = exynos_eint_gpio_init,
656 .eint_wkup_init = exynos_eint_wkup_init,
657 .label = "exynos4x12-gpio-ctrl1",
658 }, {
659 /* pin-controller instance 2 data */
660 .pin_banks = exynos4x12_pin_banks2,
661 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2),
662 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
663 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
664 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
665 .svc = EXYNOS_SVC_OFFSET,
666 .eint_gpio_init = exynos_eint_gpio_init,
667 .label = "exynos4x12-gpio-ctrl2",
668 }, {
669 /* pin-controller instance 3 data */
670 .pin_banks = exynos4x12_pin_banks3,
671 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3),
672 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
673 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
674 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
675 .svc = EXYNOS_SVC_OFFSET,
676 .eint_gpio_init = exynos_eint_gpio_init,
677 .label = "exynos4x12-gpio-ctrl3",
678 },
679};
Linux kernel - Deliverables
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