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43b169db TA |
1 | /* |
2 | * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support. | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * Copyright (c) 2012 Linaro Ltd | |
7 | * http://www.linaro.org | |
8 | * | |
9 | * Author: Thomas Abraham <thomas.ab@samsung.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This file contains the Samsung Exynos specific information required by the | |
17 | * the Samsung pinctrl/gpiolib driver. It also includes the implementation of | |
18 | * external gpio and wakeup interrupt support. | |
19 | */ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/irqdomain.h> | |
25 | #include <linux/irq.h> | |
de88cbb7 | 26 | #include <linux/irqchip/chained_irq.h> |
43b169db TA |
27 | #include <linux/of_irq.h> |
28 | #include <linux/io.h> | |
29 | #include <linux/slab.h> | |
19846950 | 30 | #include <linux/spinlock.h> |
43b169db TA |
31 | #include <linux/err.h> |
32 | ||
43b169db TA |
33 | #include "pinctrl-samsung.h" |
34 | #include "pinctrl-exynos.h" | |
35 | ||
499147c9 TF |
36 | |
37 | static struct samsung_pin_bank_type bank_type_off = { | |
38 | .fld_width = { 4, 1, 2, 2, 2, 2, }, | |
43fc9e7f | 39 | .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, |
499147c9 TF |
40 | }; |
41 | ||
42 | static struct samsung_pin_bank_type bank_type_alive = { | |
43 | .fld_width = { 4, 1, 2, 2, }, | |
43fc9e7f | 44 | .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, |
499147c9 TF |
45 | }; |
46 | ||
43b169db TA |
47 | /* list of external wakeup controllers supported */ |
48 | static const struct of_device_id exynos_wkup_irq_ids[] = { | |
49 | { .compatible = "samsung,exynos4210-wakeup-eint", }, | |
afa538c2 | 50 | { } |
43b169db TA |
51 | }; |
52 | ||
5ace03fb | 53 | static void exynos_gpio_irq_mask(struct irq_data *irqd) |
43b169db | 54 | { |
595be726 TF |
55 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
56 | struct samsung_pinctrl_drv_data *d = bank->drvdata; | |
57 | unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; | |
43b169db | 58 | unsigned long mask; |
5ae8cf79 DA |
59 | unsigned long flags; |
60 | ||
61 | spin_lock_irqsave(&bank->slock, flags); | |
43b169db TA |
62 | |
63 | mask = readl(d->virt_base + reg_mask); | |
5ace03fb | 64 | mask |= 1 << irqd->hwirq; |
43b169db | 65 | writel(mask, d->virt_base + reg_mask); |
5ae8cf79 DA |
66 | |
67 | spin_unlock_irqrestore(&bank->slock, flags); | |
43b169db TA |
68 | } |
69 | ||
5ace03fb DA |
70 | static void exynos_gpio_irq_ack(struct irq_data *irqd) |
71 | { | |
72 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); | |
73 | struct samsung_pinctrl_drv_data *d = bank->drvdata; | |
74 | unsigned long reg_pend = d->ctrl->geint_pend + bank->eint_offset; | |
75 | ||
76 | writel(1 << irqd->hwirq, d->virt_base + reg_pend); | |
77 | } | |
78 | ||
79 | static void exynos_gpio_irq_unmask(struct irq_data *irqd) | |
43b169db | 80 | { |
595be726 TF |
81 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
82 | struct samsung_pinctrl_drv_data *d = bank->drvdata; | |
83 | unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; | |
43b169db | 84 | unsigned long mask; |
5ae8cf79 DA |
85 | unsigned long flags; |
86 | ||
87 | spin_lock_irqsave(&bank->slock, flags); | |
43b169db TA |
88 | |
89 | mask = readl(d->virt_base + reg_mask); | |
5ace03fb | 90 | mask &= ~(1 << irqd->hwirq); |
43b169db | 91 | writel(mask, d->virt_base + reg_mask); |
5ae8cf79 DA |
92 | |
93 | spin_unlock_irqrestore(&bank->slock, flags); | |
43b169db TA |
94 | } |
95 | ||
43b169db TA |
96 | static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) |
97 | { | |
595be726 | 98 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
499147c9 | 99 | struct samsung_pin_bank_type *bank_type = bank->type; |
595be726 | 100 | struct samsung_pinctrl_drv_data *d = bank->drvdata; |
43b169db | 101 | struct samsung_pin_ctrl *ctrl = d->ctrl; |
595be726 TF |
102 | unsigned int pin = irqd->hwirq; |
103 | unsigned int shift = EXYNOS_EINT_CON_LEN * pin; | |
43b169db | 104 | unsigned int con, trig_type; |
595be726 | 105 | unsigned long reg_con = ctrl->geint_con + bank->eint_offset; |
19846950 | 106 | unsigned long flags; |
ee2f573c | 107 | unsigned int mask; |
43b169db TA |
108 | |
109 | switch (type) { | |
110 | case IRQ_TYPE_EDGE_RISING: | |
111 | trig_type = EXYNOS_EINT_EDGE_RISING; | |
112 | break; | |
113 | case IRQ_TYPE_EDGE_FALLING: | |
114 | trig_type = EXYNOS_EINT_EDGE_FALLING; | |
115 | break; | |
116 | case IRQ_TYPE_EDGE_BOTH: | |
117 | trig_type = EXYNOS_EINT_EDGE_BOTH; | |
118 | break; | |
119 | case IRQ_TYPE_LEVEL_HIGH: | |
120 | trig_type = EXYNOS_EINT_LEVEL_HIGH; | |
121 | break; | |
122 | case IRQ_TYPE_LEVEL_LOW: | |
123 | trig_type = EXYNOS_EINT_LEVEL_LOW; | |
124 | break; | |
125 | default: | |
126 | pr_err("unsupported external interrupt type\n"); | |
127 | return -EINVAL; | |
128 | } | |
129 | ||
130 | if (type & IRQ_TYPE_EDGE_BOTH) | |
131 | __irq_set_handler_locked(irqd->irq, handle_edge_irq); | |
132 | else | |
133 | __irq_set_handler_locked(irqd->irq, handle_level_irq); | |
134 | ||
135 | con = readl(d->virt_base + reg_con); | |
136 | con &= ~(EXYNOS_EINT_CON_MASK << shift); | |
137 | con |= trig_type << shift; | |
138 | writel(con, d->virt_base + reg_con); | |
ee2f573c | 139 | |
43fc9e7f | 140 | reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; |
499147c9 TF |
141 | shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC]; |
142 | mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; | |
ee2f573c | 143 | |
19846950 TF |
144 | spin_lock_irqsave(&bank->slock, flags); |
145 | ||
ee2f573c TF |
146 | con = readl(d->virt_base + reg_con); |
147 | con &= ~(mask << shift); | |
148 | con |= EXYNOS_EINT_FUNC << shift; | |
149 | writel(con, d->virt_base + reg_con); | |
150 | ||
19846950 TF |
151 | spin_unlock_irqrestore(&bank->slock, flags); |
152 | ||
43b169db TA |
153 | return 0; |
154 | } | |
155 | ||
156 | /* | |
157 | * irq_chip for gpio interrupts. | |
158 | */ | |
159 | static struct irq_chip exynos_gpio_irq_chip = { | |
160 | .name = "exynos_gpio_irq_chip", | |
161 | .irq_unmask = exynos_gpio_irq_unmask, | |
162 | .irq_mask = exynos_gpio_irq_mask, | |
163 | .irq_ack = exynos_gpio_irq_ack, | |
164 | .irq_set_type = exynos_gpio_irq_set_type, | |
165 | }; | |
166 | ||
43b169db TA |
167 | static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq, |
168 | irq_hw_number_t hw) | |
169 | { | |
595be726 | 170 | struct samsung_pin_bank *b = h->host_data; |
43b169db | 171 | |
595be726 | 172 | irq_set_chip_data(virq, b); |
43b169db TA |
173 | irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip, |
174 | handle_level_irq); | |
175 | set_irq_flags(virq, IRQF_VALID); | |
176 | return 0; | |
177 | } | |
178 | ||
43b169db TA |
179 | /* |
180 | * irq domain callbacks for external gpio interrupt controller. | |
181 | */ | |
182 | static const struct irq_domain_ops exynos_gpio_irqd_ops = { | |
183 | .map = exynos_gpio_irq_map, | |
43b169db TA |
184 | .xlate = irq_domain_xlate_twocell, |
185 | }; | |
186 | ||
187 | static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) | |
188 | { | |
189 | struct samsung_pinctrl_drv_data *d = data; | |
190 | struct samsung_pin_ctrl *ctrl = d->ctrl; | |
191 | struct samsung_pin_bank *bank = ctrl->pin_banks; | |
192 | unsigned int svc, group, pin, virq; | |
193 | ||
194 | svc = readl(d->virt_base + ctrl->svc); | |
195 | group = EXYNOS_SVC_GROUP(svc); | |
196 | pin = svc & EXYNOS_SVC_NUM_MASK; | |
197 | ||
198 | if (!group) | |
199 | return IRQ_HANDLED; | |
200 | bank += (group - 1); | |
201 | ||
595be726 | 202 | virq = irq_linear_revmap(bank->irq_domain, pin); |
43b169db TA |
203 | if (!virq) |
204 | return IRQ_NONE; | |
205 | generic_handle_irq(virq); | |
206 | return IRQ_HANDLED; | |
207 | } | |
208 | ||
7ccbc60c TF |
209 | struct exynos_eint_gpio_save { |
210 | u32 eint_con; | |
211 | u32 eint_fltcon0; | |
212 | u32 eint_fltcon1; | |
213 | }; | |
214 | ||
43b169db TA |
215 | /* |
216 | * exynos_eint_gpio_init() - setup handling of external gpio interrupts. | |
217 | * @d: driver data of samsung pinctrl driver. | |
218 | */ | |
219 | static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) | |
220 | { | |
595be726 | 221 | struct samsung_pin_bank *bank; |
43b169db | 222 | struct device *dev = d->dev; |
7ccbc60c TF |
223 | int ret; |
224 | int i; | |
43b169db TA |
225 | |
226 | if (!d->irq) { | |
227 | dev_err(dev, "irq number not available\n"); | |
228 | return -EINVAL; | |
229 | } | |
230 | ||
231 | ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq, | |
232 | 0, dev_name(dev), d); | |
233 | if (ret) { | |
234 | dev_err(dev, "irq request failed\n"); | |
235 | return -ENXIO; | |
236 | } | |
237 | ||
595be726 TF |
238 | bank = d->ctrl->pin_banks; |
239 | for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { | |
240 | if (bank->eint_type != EINT_TYPE_GPIO) | |
241 | continue; | |
242 | bank->irq_domain = irq_domain_add_linear(bank->of_node, | |
243 | bank->nr_pins, &exynos_gpio_irqd_ops, bank); | |
244 | if (!bank->irq_domain) { | |
245 | dev_err(dev, "gpio irq domain add failed\n"); | |
7ccbc60c TF |
246 | ret = -ENXIO; |
247 | goto err_domains; | |
248 | } | |
249 | ||
250 | bank->soc_priv = devm_kzalloc(d->dev, | |
251 | sizeof(struct exynos_eint_gpio_save), GFP_KERNEL); | |
252 | if (!bank->soc_priv) { | |
253 | irq_domain_remove(bank->irq_domain); | |
254 | ret = -ENOMEM; | |
255 | goto err_domains; | |
595be726 | 256 | } |
43b169db TA |
257 | } |
258 | ||
259 | return 0; | |
7ccbc60c TF |
260 | |
261 | err_domains: | |
262 | for (--i, --bank; i >= 0; --i, --bank) { | |
263 | if (bank->eint_type != EINT_TYPE_GPIO) | |
264 | continue; | |
265 | irq_domain_remove(bank->irq_domain); | |
266 | } | |
267 | ||
268 | return ret; | |
43b169db TA |
269 | } |
270 | ||
5ace03fb | 271 | static void exynos_wkup_irq_mask(struct irq_data *irqd) |
43b169db | 272 | { |
a04b07c0 TF |
273 | struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); |
274 | struct samsung_pinctrl_drv_data *d = b->drvdata; | |
275 | unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset; | |
43b169db | 276 | unsigned long mask; |
5ae8cf79 DA |
277 | unsigned long flags; |
278 | ||
279 | spin_lock_irqsave(&b->slock, flags); | |
43b169db TA |
280 | |
281 | mask = readl(d->virt_base + reg_mask); | |
5ace03fb | 282 | mask |= 1 << irqd->hwirq; |
43b169db | 283 | writel(mask, d->virt_base + reg_mask); |
5ae8cf79 DA |
284 | |
285 | spin_unlock_irqrestore(&b->slock, flags); | |
43b169db TA |
286 | } |
287 | ||
5ace03fb DA |
288 | static void exynos_wkup_irq_ack(struct irq_data *irqd) |
289 | { | |
290 | struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); | |
291 | struct samsung_pinctrl_drv_data *d = b->drvdata; | |
292 | unsigned long pend = d->ctrl->weint_pend + b->eint_offset; | |
293 | ||
294 | writel(1 << irqd->hwirq, d->virt_base + pend); | |
295 | } | |
296 | ||
297 | static void exynos_wkup_irq_unmask(struct irq_data *irqd) | |
43b169db | 298 | { |
a04b07c0 TF |
299 | struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); |
300 | struct samsung_pinctrl_drv_data *d = b->drvdata; | |
301 | unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset; | |
43b169db | 302 | unsigned long mask; |
5ae8cf79 DA |
303 | unsigned long flags; |
304 | ||
305 | spin_lock_irqsave(&b->slock, flags); | |
43b169db TA |
306 | |
307 | mask = readl(d->virt_base + reg_mask); | |
5ace03fb | 308 | mask &= ~(1 << irqd->hwirq); |
43b169db | 309 | writel(mask, d->virt_base + reg_mask); |
5ae8cf79 DA |
310 | |
311 | spin_unlock_irqrestore(&b->slock, flags); | |
43b169db TA |
312 | } |
313 | ||
43b169db TA |
314 | static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type) |
315 | { | |
a04b07c0 | 316 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
499147c9 | 317 | struct samsung_pin_bank_type *bank_type = bank->type; |
a04b07c0 TF |
318 | struct samsung_pinctrl_drv_data *d = bank->drvdata; |
319 | unsigned int pin = irqd->hwirq; | |
320 | unsigned long reg_con = d->ctrl->weint_con + bank->eint_offset; | |
43b169db TA |
321 | unsigned long shift = EXYNOS_EINT_CON_LEN * pin; |
322 | unsigned long con, trig_type; | |
19846950 | 323 | unsigned long flags; |
22b9ba03 | 324 | unsigned int mask; |
43b169db TA |
325 | |
326 | switch (type) { | |
327 | case IRQ_TYPE_EDGE_RISING: | |
328 | trig_type = EXYNOS_EINT_EDGE_RISING; | |
329 | break; | |
330 | case IRQ_TYPE_EDGE_FALLING: | |
331 | trig_type = EXYNOS_EINT_EDGE_FALLING; | |
332 | break; | |
333 | case IRQ_TYPE_EDGE_BOTH: | |
334 | trig_type = EXYNOS_EINT_EDGE_BOTH; | |
335 | break; | |
336 | case IRQ_TYPE_LEVEL_HIGH: | |
337 | trig_type = EXYNOS_EINT_LEVEL_HIGH; | |
338 | break; | |
339 | case IRQ_TYPE_LEVEL_LOW: | |
340 | trig_type = EXYNOS_EINT_LEVEL_LOW; | |
341 | break; | |
342 | default: | |
343 | pr_err("unsupported external interrupt type\n"); | |
344 | return -EINVAL; | |
345 | } | |
346 | ||
347 | if (type & IRQ_TYPE_EDGE_BOTH) | |
348 | __irq_set_handler_locked(irqd->irq, handle_edge_irq); | |
349 | else | |
350 | __irq_set_handler_locked(irqd->irq, handle_level_irq); | |
351 | ||
352 | con = readl(d->virt_base + reg_con); | |
353 | con &= ~(EXYNOS_EINT_CON_MASK << shift); | |
354 | con |= trig_type << shift; | |
355 | writel(con, d->virt_base + reg_con); | |
22b9ba03 | 356 | |
43fc9e7f | 357 | reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; |
499147c9 TF |
358 | shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC]; |
359 | mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; | |
22b9ba03 | 360 | |
19846950 TF |
361 | spin_lock_irqsave(&bank->slock, flags); |
362 | ||
22b9ba03 TF |
363 | con = readl(d->virt_base + reg_con); |
364 | con &= ~(mask << shift); | |
365 | con |= EXYNOS_EINT_FUNC << shift; | |
366 | writel(con, d->virt_base + reg_con); | |
367 | ||
19846950 TF |
368 | spin_unlock_irqrestore(&bank->slock, flags); |
369 | ||
43b169db TA |
370 | return 0; |
371 | } | |
372 | ||
ad350cd9 TF |
373 | static u32 exynos_eint_wake_mask = 0xffffffff; |
374 | ||
375 | u32 exynos_get_eint_wake_mask(void) | |
376 | { | |
377 | return exynos_eint_wake_mask; | |
378 | } | |
379 | ||
380 | static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) | |
381 | { | |
382 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); | |
383 | unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); | |
384 | ||
385 | pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq); | |
386 | ||
387 | if (!on) | |
388 | exynos_eint_wake_mask |= bit; | |
389 | else | |
390 | exynos_eint_wake_mask &= ~bit; | |
391 | ||
392 | return 0; | |
393 | } | |
394 | ||
43b169db TA |
395 | /* |
396 | * irq_chip for wakeup interrupts | |
397 | */ | |
398 | static struct irq_chip exynos_wkup_irq_chip = { | |
399 | .name = "exynos_wkup_irq_chip", | |
400 | .irq_unmask = exynos_wkup_irq_unmask, | |
401 | .irq_mask = exynos_wkup_irq_mask, | |
402 | .irq_ack = exynos_wkup_irq_ack, | |
403 | .irq_set_type = exynos_wkup_irq_set_type, | |
ad350cd9 | 404 | .irq_set_wake = exynos_wkup_irq_set_wake, |
43b169db TA |
405 | }; |
406 | ||
407 | /* interrupt handler for wakeup interrupts 0..15 */ | |
408 | static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc) | |
409 | { | |
410 | struct exynos_weint_data *eintd = irq_get_handler_data(irq); | |
a04b07c0 | 411 | struct samsung_pin_bank *bank = eintd->bank; |
43b169db TA |
412 | struct irq_chip *chip = irq_get_chip(irq); |
413 | int eint_irq; | |
414 | ||
415 | chained_irq_enter(chip, desc); | |
416 | chip->irq_mask(&desc->irq_data); | |
417 | ||
418 | if (chip->irq_ack) | |
419 | chip->irq_ack(&desc->irq_data); | |
420 | ||
a04b07c0 | 421 | eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq); |
43b169db TA |
422 | generic_handle_irq(eint_irq); |
423 | chip->irq_unmask(&desc->irq_data); | |
424 | chained_irq_exit(chip, desc); | |
425 | } | |
426 | ||
a04b07c0 TF |
427 | static inline void exynos_irq_demux_eint(unsigned long pend, |
428 | struct irq_domain *domain) | |
43b169db TA |
429 | { |
430 | unsigned int irq; | |
431 | ||
432 | while (pend) { | |
433 | irq = fls(pend) - 1; | |
a04b07c0 | 434 | generic_handle_irq(irq_find_mapping(domain, irq)); |
43b169db TA |
435 | pend &= ~(1 << irq); |
436 | } | |
437 | } | |
438 | ||
439 | /* interrupt handler for wakeup interrupt 16 */ | |
440 | static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) | |
441 | { | |
442 | struct irq_chip *chip = irq_get_chip(irq); | |
a04b07c0 TF |
443 | struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq); |
444 | struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata; | |
445 | struct samsung_pin_ctrl *ctrl = d->ctrl; | |
43b169db | 446 | unsigned long pend; |
de59049b | 447 | unsigned long mask; |
a04b07c0 | 448 | int i; |
43b169db TA |
449 | |
450 | chained_irq_enter(chip, desc); | |
a04b07c0 TF |
451 | |
452 | for (i = 0; i < eintd->nr_banks; ++i) { | |
453 | struct samsung_pin_bank *b = eintd->banks[i]; | |
454 | pend = readl(d->virt_base + ctrl->weint_pend + b->eint_offset); | |
455 | mask = readl(d->virt_base + ctrl->weint_mask + b->eint_offset); | |
456 | exynos_irq_demux_eint(pend & ~mask, b->irq_domain); | |
457 | } | |
458 | ||
43b169db TA |
459 | chained_irq_exit(chip, desc); |
460 | } | |
461 | ||
462 | static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq, | |
463 | irq_hw_number_t hw) | |
464 | { | |
465 | irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip, handle_level_irq); | |
466 | irq_set_chip_data(virq, h->host_data); | |
467 | set_irq_flags(virq, IRQF_VALID); | |
468 | return 0; | |
469 | } | |
470 | ||
471 | /* | |
472 | * irq domain callbacks for external wakeup interrupt controller. | |
473 | */ | |
474 | static const struct irq_domain_ops exynos_wkup_irqd_ops = { | |
475 | .map = exynos_wkup_irq_map, | |
476 | .xlate = irq_domain_xlate_twocell, | |
477 | }; | |
478 | ||
479 | /* | |
480 | * exynos_eint_wkup_init() - setup handling of external wakeup interrupts. | |
481 | * @d: driver data of samsung pinctrl driver. | |
482 | */ | |
483 | static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) | |
484 | { | |
485 | struct device *dev = d->dev; | |
c3ad056b TF |
486 | struct device_node *wkup_np = NULL; |
487 | struct device_node *np; | |
a04b07c0 | 488 | struct samsung_pin_bank *bank; |
43b169db | 489 | struct exynos_weint_data *weint_data; |
a04b07c0 TF |
490 | struct exynos_muxed_weint_data *muxed_data; |
491 | unsigned int muxed_banks = 0; | |
492 | unsigned int i; | |
43b169db TA |
493 | int idx, irq; |
494 | ||
c3ad056b TF |
495 | for_each_child_of_node(dev->of_node, np) { |
496 | if (of_match_node(exynos_wkup_irq_ids, np)) { | |
497 | wkup_np = np; | |
498 | break; | |
499 | } | |
43b169db | 500 | } |
c3ad056b TF |
501 | if (!wkup_np) |
502 | return -ENODEV; | |
43b169db | 503 | |
a04b07c0 TF |
504 | bank = d->ctrl->pin_banks; |
505 | for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { | |
506 | if (bank->eint_type != EINT_TYPE_WKUP) | |
507 | continue; | |
43b169db | 508 | |
a04b07c0 TF |
509 | bank->irq_domain = irq_domain_add_linear(bank->of_node, |
510 | bank->nr_pins, &exynos_wkup_irqd_ops, bank); | |
511 | if (!bank->irq_domain) { | |
512 | dev_err(dev, "wkup irq domain add failed\n"); | |
513 | return -ENXIO; | |
514 | } | |
43b169db | 515 | |
a04b07c0 TF |
516 | if (!of_find_property(bank->of_node, "interrupts", NULL)) { |
517 | bank->eint_type = EINT_TYPE_WKUP_MUX; | |
518 | ++muxed_banks; | |
519 | continue; | |
520 | } | |
43b169db | 521 | |
a04b07c0 TF |
522 | weint_data = devm_kzalloc(dev, bank->nr_pins |
523 | * sizeof(*weint_data), GFP_KERNEL); | |
524 | if (!weint_data) { | |
525 | dev_err(dev, "could not allocate memory for weint_data\n"); | |
526 | return -ENOMEM; | |
527 | } | |
43b169db | 528 | |
a04b07c0 TF |
529 | for (idx = 0; idx < bank->nr_pins; ++idx) { |
530 | irq = irq_of_parse_and_map(bank->of_node, idx); | |
531 | if (!irq) { | |
532 | dev_err(dev, "irq number for eint-%s-%d not found\n", | |
533 | bank->name, idx); | |
534 | continue; | |
535 | } | |
536 | weint_data[idx].irq = idx; | |
537 | weint_data[idx].bank = bank; | |
43b169db TA |
538 | irq_set_handler_data(irq, &weint_data[idx]); |
539 | irq_set_chained_handler(irq, exynos_irq_eint0_15); | |
43b169db TA |
540 | } |
541 | } | |
a04b07c0 TF |
542 | |
543 | if (!muxed_banks) | |
544 | return 0; | |
545 | ||
546 | irq = irq_of_parse_and_map(wkup_np, 0); | |
547 | if (!irq) { | |
548 | dev_err(dev, "irq number for muxed EINTs not found\n"); | |
549 | return 0; | |
550 | } | |
551 | ||
552 | muxed_data = devm_kzalloc(dev, sizeof(*muxed_data) | |
553 | + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL); | |
554 | if (!muxed_data) { | |
555 | dev_err(dev, "could not allocate memory for muxed_data\n"); | |
556 | return -ENOMEM; | |
557 | } | |
558 | ||
559 | irq_set_chained_handler(irq, exynos_irq_demux_eint16_31); | |
560 | irq_set_handler_data(irq, muxed_data); | |
561 | ||
562 | bank = d->ctrl->pin_banks; | |
563 | idx = 0; | |
564 | for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { | |
565 | if (bank->eint_type != EINT_TYPE_WKUP_MUX) | |
566 | continue; | |
567 | ||
568 | muxed_data->banks[idx++] = bank; | |
569 | } | |
570 | muxed_data->nr_banks = muxed_banks; | |
571 | ||
43b169db TA |
572 | return 0; |
573 | } | |
574 | ||
7ccbc60c TF |
575 | static void exynos_pinctrl_suspend_bank( |
576 | struct samsung_pinctrl_drv_data *drvdata, | |
577 | struct samsung_pin_bank *bank) | |
578 | { | |
579 | struct exynos_eint_gpio_save *save = bank->soc_priv; | |
580 | void __iomem *regs = drvdata->virt_base; | |
581 | ||
582 | save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET | |
583 | + bank->eint_offset); | |
584 | save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET | |
585 | + 2 * bank->eint_offset); | |
586 | save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET | |
587 | + 2 * bank->eint_offset + 4); | |
588 | ||
589 | pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); | |
590 | pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); | |
591 | pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); | |
592 | } | |
593 | ||
594 | static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) | |
595 | { | |
596 | struct samsung_pin_ctrl *ctrl = drvdata->ctrl; | |
597 | struct samsung_pin_bank *bank = ctrl->pin_banks; | |
598 | int i; | |
599 | ||
600 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) | |
601 | if (bank->eint_type == EINT_TYPE_GPIO) | |
602 | exynos_pinctrl_suspend_bank(drvdata, bank); | |
603 | } | |
604 | ||
605 | static void exynos_pinctrl_resume_bank( | |
606 | struct samsung_pinctrl_drv_data *drvdata, | |
607 | struct samsung_pin_bank *bank) | |
608 | { | |
609 | struct exynos_eint_gpio_save *save = bank->soc_priv; | |
610 | void __iomem *regs = drvdata->virt_base; | |
611 | ||
612 | pr_debug("%s: con %#010x => %#010x\n", bank->name, | |
613 | readl(regs + EXYNOS_GPIO_ECON_OFFSET | |
614 | + bank->eint_offset), save->eint_con); | |
615 | pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, | |
616 | readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET | |
617 | + 2 * bank->eint_offset), save->eint_fltcon0); | |
618 | pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, | |
619 | readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET | |
620 | + 2 * bank->eint_offset + 4), save->eint_fltcon1); | |
621 | ||
622 | writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET | |
623 | + bank->eint_offset); | |
624 | writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET | |
625 | + 2 * bank->eint_offset); | |
626 | writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET | |
627 | + 2 * bank->eint_offset + 4); | |
628 | } | |
629 | ||
630 | static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) | |
631 | { | |
632 | struct samsung_pin_ctrl *ctrl = drvdata->ctrl; | |
633 | struct samsung_pin_bank *bank = ctrl->pin_banks; | |
634 | int i; | |
635 | ||
636 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) | |
637 | if (bank->eint_type == EINT_TYPE_GPIO) | |
638 | exynos_pinctrl_resume_bank(drvdata, bank); | |
639 | } | |
640 | ||
43b169db TA |
641 | /* pin banks of exynos4210 pin-controller 0 */ |
642 | static struct samsung_pin_bank exynos4210_pin_banks0[] = { | |
1b6056d6 TF |
643 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), |
644 | EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), | |
645 | EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), | |
646 | EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), | |
647 | EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), | |
648 | EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), | |
649 | EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), | |
650 | EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c), | |
651 | EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20), | |
652 | EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24), | |
653 | EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28), | |
654 | EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c), | |
655 | EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), | |
656 | EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), | |
657 | EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), | |
658 | EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), | |
43b169db TA |
659 | }; |
660 | ||
661 | /* pin banks of exynos4210 pin-controller 1 */ | |
662 | static struct samsung_pin_bank exynos4210_pin_banks1[] = { | |
1b6056d6 TF |
663 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00), |
664 | EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04), | |
665 | EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), | |
666 | EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), | |
667 | EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), | |
668 | EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), | |
669 | EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18), | |
670 | EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c), | |
671 | EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), | |
40ba6227 TF |
672 | EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), |
673 | EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), | |
674 | EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), | |
675 | EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), | |
676 | EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), | |
677 | EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), | |
678 | EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), | |
a04b07c0 TF |
679 | EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), |
680 | EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), | |
681 | EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), | |
682 | EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), | |
43b169db TA |
683 | }; |
684 | ||
685 | /* pin banks of exynos4210 pin-controller 2 */ | |
686 | static struct samsung_pin_bank exynos4210_pin_banks2[] = { | |
40ba6227 | 687 | EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"), |
43b169db TA |
688 | }; |
689 | ||
690 | /* | |
691 | * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes | |
692 | * three gpio/pin-mux/pinconfig controllers. | |
693 | */ | |
694 | struct samsung_pin_ctrl exynos4210_pin_ctrl[] = { | |
695 | { | |
696 | /* pin-controller instance 0 data */ | |
697 | .pin_banks = exynos4210_pin_banks0, | |
698 | .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0), | |
43b169db TA |
699 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, |
700 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
701 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
702 | .svc = EXYNOS_SVC_OFFSET, | |
703 | .eint_gpio_init = exynos_eint_gpio_init, | |
7ccbc60c TF |
704 | .suspend = exynos_pinctrl_suspend, |
705 | .resume = exynos_pinctrl_resume, | |
43b169db TA |
706 | .label = "exynos4210-gpio-ctrl0", |
707 | }, { | |
708 | /* pin-controller instance 1 data */ | |
709 | .pin_banks = exynos4210_pin_banks1, | |
710 | .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1), | |
43b169db TA |
711 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, |
712 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
713 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
714 | .weint_con = EXYNOS_WKUP_ECON_OFFSET, | |
715 | .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, | |
716 | .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, | |
717 | .svc = EXYNOS_SVC_OFFSET, | |
718 | .eint_gpio_init = exynos_eint_gpio_init, | |
719 | .eint_wkup_init = exynos_eint_wkup_init, | |
7ccbc60c TF |
720 | .suspend = exynos_pinctrl_suspend, |
721 | .resume = exynos_pinctrl_resume, | |
43b169db TA |
722 | .label = "exynos4210-gpio-ctrl1", |
723 | }, { | |
724 | /* pin-controller instance 2 data */ | |
725 | .pin_banks = exynos4210_pin_banks2, | |
726 | .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2), | |
43b169db TA |
727 | .label = "exynos4210-gpio-ctrl2", |
728 | }, | |
729 | }; | |
6edc794a TF |
730 | |
731 | /* pin banks of exynos4x12 pin-controller 0 */ | |
732 | static struct samsung_pin_bank exynos4x12_pin_banks0[] = { | |
733 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), | |
734 | EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), | |
735 | EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), | |
736 | EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), | |
737 | EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), | |
738 | EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), | |
739 | EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), | |
740 | EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), | |
741 | EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), | |
742 | EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), | |
743 | EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), | |
744 | EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40), | |
745 | EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44), | |
746 | }; | |
747 | ||
748 | /* pin banks of exynos4x12 pin-controller 1 */ | |
749 | static struct samsung_pin_bank exynos4x12_pin_banks1[] = { | |
750 | EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), | |
751 | EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), | |
752 | EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), | |
753 | EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), | |
754 | EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18), | |
755 | EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c), | |
756 | EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), | |
757 | EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), | |
758 | EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), | |
759 | EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c), | |
760 | EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30), | |
761 | EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34), | |
762 | EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), | |
763 | EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), | |
764 | EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), | |
765 | EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), | |
766 | EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), | |
767 | EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), | |
768 | EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), | |
769 | EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), | |
770 | EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), | |
771 | EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), | |
772 | EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), | |
773 | }; | |
774 | ||
775 | /* pin banks of exynos4x12 pin-controller 2 */ | |
776 | static struct samsung_pin_bank exynos4x12_pin_banks2[] = { | |
777 | EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), | |
778 | }; | |
779 | ||
780 | /* pin banks of exynos4x12 pin-controller 3 */ | |
781 | static struct samsung_pin_bank exynos4x12_pin_banks3[] = { | |
782 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), | |
783 | EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), | |
784 | EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08), | |
785 | EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c), | |
786 | EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10), | |
787 | }; | |
788 | ||
789 | /* | |
790 | * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes | |
791 | * four gpio/pin-mux/pinconfig controllers. | |
792 | */ | |
793 | struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = { | |
794 | { | |
795 | /* pin-controller instance 0 data */ | |
796 | .pin_banks = exynos4x12_pin_banks0, | |
797 | .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0), | |
798 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
799 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
800 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
801 | .svc = EXYNOS_SVC_OFFSET, | |
802 | .eint_gpio_init = exynos_eint_gpio_init, | |
7ccbc60c TF |
803 | .suspend = exynos_pinctrl_suspend, |
804 | .resume = exynos_pinctrl_resume, | |
6edc794a TF |
805 | .label = "exynos4x12-gpio-ctrl0", |
806 | }, { | |
807 | /* pin-controller instance 1 data */ | |
808 | .pin_banks = exynos4x12_pin_banks1, | |
809 | .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1), | |
810 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
811 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
812 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
813 | .weint_con = EXYNOS_WKUP_ECON_OFFSET, | |
814 | .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, | |
815 | .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, | |
816 | .svc = EXYNOS_SVC_OFFSET, | |
817 | .eint_gpio_init = exynos_eint_gpio_init, | |
818 | .eint_wkup_init = exynos_eint_wkup_init, | |
7ccbc60c TF |
819 | .suspend = exynos_pinctrl_suspend, |
820 | .resume = exynos_pinctrl_resume, | |
6edc794a TF |
821 | .label = "exynos4x12-gpio-ctrl1", |
822 | }, { | |
823 | /* pin-controller instance 2 data */ | |
824 | .pin_banks = exynos4x12_pin_banks2, | |
825 | .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2), | |
826 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
827 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
828 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
829 | .svc = EXYNOS_SVC_OFFSET, | |
830 | .eint_gpio_init = exynos_eint_gpio_init, | |
7ccbc60c TF |
831 | .suspend = exynos_pinctrl_suspend, |
832 | .resume = exynos_pinctrl_resume, | |
6edc794a TF |
833 | .label = "exynos4x12-gpio-ctrl2", |
834 | }, { | |
835 | /* pin-controller instance 3 data */ | |
836 | .pin_banks = exynos4x12_pin_banks3, | |
837 | .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3), | |
838 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
839 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
840 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
841 | .svc = EXYNOS_SVC_OFFSET, | |
842 | .eint_gpio_init = exynos_eint_gpio_init, | |
7ccbc60c TF |
843 | .suspend = exynos_pinctrl_suspend, |
844 | .resume = exynos_pinctrl_resume, | |
6edc794a TF |
845 | .label = "exynos4x12-gpio-ctrl3", |
846 | }, | |
847 | }; | |
f67faf48 TA |
848 | |
849 | /* pin banks of exynos5250 pin-controller 0 */ | |
850 | static struct samsung_pin_bank exynos5250_pin_banks0[] = { | |
851 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), | |
852 | EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), | |
853 | EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), | |
854 | EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), | |
855 | EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), | |
856 | EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), | |
857 | EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), | |
858 | EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), | |
859 | EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20), | |
860 | EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24), | |
861 | EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28), | |
862 | EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c), | |
863 | EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30), | |
864 | EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34), | |
865 | EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"), | |
866 | EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"), | |
867 | EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"), | |
868 | EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"), | |
869 | EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"), | |
870 | EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"), | |
871 | EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"), | |
872 | EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), | |
873 | EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), | |
874 | EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), | |
875 | EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), | |
876 | }; | |
877 | ||
878 | /* pin banks of exynos5250 pin-controller 1 */ | |
879 | static struct samsung_pin_bank exynos5250_pin_banks1[] = { | |
880 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), | |
881 | EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), | |
882 | EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08), | |
883 | EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c), | |
884 | EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), | |
885 | EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), | |
886 | EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), | |
887 | EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c), | |
888 | EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20), | |
889 | }; | |
890 | ||
891 | /* pin banks of exynos5250 pin-controller 2 */ | |
892 | static struct samsung_pin_bank exynos5250_pin_banks2[] = { | |
893 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), | |
894 | EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), | |
895 | EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), | |
896 | EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), | |
897 | EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), | |
898 | }; | |
899 | ||
900 | /* pin banks of exynos5250 pin-controller 3 */ | |
901 | static struct samsung_pin_bank exynos5250_pin_banks3[] = { | |
902 | EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), | |
903 | }; | |
904 | ||
905 | /* | |
906 | * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes | |
907 | * four gpio/pin-mux/pinconfig controllers. | |
908 | */ | |
909 | struct samsung_pin_ctrl exynos5250_pin_ctrl[] = { | |
910 | { | |
911 | /* pin-controller instance 0 data */ | |
912 | .pin_banks = exynos5250_pin_banks0, | |
913 | .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0), | |
914 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
915 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
916 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
917 | .weint_con = EXYNOS_WKUP_ECON_OFFSET, | |
918 | .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, | |
919 | .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, | |
920 | .svc = EXYNOS_SVC_OFFSET, | |
921 | .eint_gpio_init = exynos_eint_gpio_init, | |
922 | .eint_wkup_init = exynos_eint_wkup_init, | |
7ccbc60c TF |
923 | .suspend = exynos_pinctrl_suspend, |
924 | .resume = exynos_pinctrl_resume, | |
f67faf48 TA |
925 | .label = "exynos5250-gpio-ctrl0", |
926 | }, { | |
927 | /* pin-controller instance 1 data */ | |
928 | .pin_banks = exynos5250_pin_banks1, | |
929 | .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1), | |
930 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
931 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
932 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
933 | .svc = EXYNOS_SVC_OFFSET, | |
934 | .eint_gpio_init = exynos_eint_gpio_init, | |
7ccbc60c TF |
935 | .suspend = exynos_pinctrl_suspend, |
936 | .resume = exynos_pinctrl_resume, | |
f67faf48 TA |
937 | .label = "exynos5250-gpio-ctrl1", |
938 | }, { | |
939 | /* pin-controller instance 2 data */ | |
940 | .pin_banks = exynos5250_pin_banks2, | |
941 | .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2), | |
942 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
943 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
944 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
945 | .svc = EXYNOS_SVC_OFFSET, | |
946 | .eint_gpio_init = exynos_eint_gpio_init, | |
7ccbc60c TF |
947 | .suspend = exynos_pinctrl_suspend, |
948 | .resume = exynos_pinctrl_resume, | |
f67faf48 TA |
949 | .label = "exynos5250-gpio-ctrl2", |
950 | }, { | |
951 | /* pin-controller instance 3 data */ | |
952 | .pin_banks = exynos5250_pin_banks3, | |
953 | .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3), | |
954 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
955 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
956 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
957 | .svc = EXYNOS_SVC_OFFSET, | |
958 | .eint_gpio_init = exynos_eint_gpio_init, | |
7ccbc60c TF |
959 | .suspend = exynos_pinctrl_suspend, |
960 | .resume = exynos_pinctrl_resume, | |
f67faf48 TA |
961 | .label = "exynos5250-gpio-ctrl3", |
962 | }, | |
963 | }; |