[deliverable/linux.git] / drivers / pinctrl / pinctrl-imx.c

/*
 * Core driver for the imx pin controller
 *
 * Copyright (C) 2012 Freescale Semiconductor, Inc.
 * Copyright (C) 2012 Linaro Ltd.
 *
 * Author: Dong Aisheng <dong.aisheng@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>

#include "core.h"
#include "pinctrl-imx.h"

#define IMX_PMX_DUMP(info, p, m, c, n)			\
{							\
	int i, j;					\
	printk(KERN_DEBUG "Format: Pin Mux Config\n");	\
	for (i = 0; i < n; i++) {			\
		j = p[i];				\
		printk(KERN_DEBUG "%s %d 0x%lx\n",	\
			info->pins[j].name,		\
			m[i], c[i]);			\
	}						\
}

/* The bits in CONFIG cell defined in binding doc*/
#define IMX_NO_PAD_CTL	0x80000000	/* no pin config need */
#define IMX_PAD_SION 0x40000000		/* set SION */

/**
 * @dev: a pointer back to containing device
 * @base: the offset to the controller in virtual memory
 */
struct imx_pinctrl {
	struct device *dev;
	struct pinctrl_dev *pctl;
	void __iomem *base;
	const struct imx_pinctrl_soc_info *info;
};

static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
				const struct imx_pinctrl_soc_info *info,
				const char *name)
{
	const struct imx_pin_group *grp = NULL;
	int i;

	for (i = 0; i < info->ngroups; i++) {
		if (!strcmp(info->groups[i].name, name)) {
			grp = &info->groups[i];
			break;
		}
	}

	return grp;
}

static int imx_get_groups_count(struct pinctrl_dev *pctldev)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	return info->ngroups;
}

static const char *imx_get_group_name(struct pinctrl_dev *pctldev,
				       unsigned selector)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	return info->groups[selector].name;
}

static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
			       const unsigned **pins,
			       unsigned *npins)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	if (selector >= info->ngroups)
		return -EINVAL;

	*pins = info->groups[selector].pins;
	*npins = info->groups[selector].npins;

	return 0;
}

static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
		   unsigned offset)
{
	seq_printf(s, "%s", dev_name(pctldev->dev));
}

static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
			struct device_node *np,
			struct pinctrl_map **map, unsigned *num_maps)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	const struct imx_pin_group *grp;
	struct pinctrl_map *new_map;
	struct device_node *parent;
	int map_num = 1;
	int i, j;

	/*
	 * first find the group of this node and check if we need create
	 * config maps for pins
	 */
	grp = imx_pinctrl_find_group_by_name(info, np->name);
	if (!grp) {
		dev_err(info->dev, "unable to find group for node %s\n",
			np->name);
		return -EINVAL;
	}

	for (i = 0; i < grp->npins; i++) {
		if (!(grp->configs[i] & IMX_NO_PAD_CTL))
			map_num++;
	}

	new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
	if (!new_map)
		return -ENOMEM;

	*map = new_map;
	*num_maps = map_num;

	/* create mux map */
	parent = of_get_parent(np);
	if (!parent) {
		kfree(new_map);
		return -EINVAL;
	}
	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
	new_map[0].data.mux.function = parent->name;
	new_map[0].data.mux.group = np->name;
	of_node_put(parent);

	/* create config map */
	new_map++;
	for (i = j = 0; i < grp->npins; i++) {
		if (!(grp->configs[i] & IMX_NO_PAD_CTL)) {
			new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
			new_map[j].data.configs.group_or_pin =
					pin_get_name(pctldev, grp->pins[i]);
			new_map[j].data.configs.configs = &grp->configs[i];
			new_map[j].data.configs.num_configs = 1;
			j++;
		}
	}

	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
		(*map)->data.mux.function, (*map)->data.mux.group, map_num);

	return 0;
}

static void imx_dt_free_map(struct pinctrl_dev *pctldev,
				struct pinctrl_map *map, unsigned num_maps)
{
	kfree(map);
}

static const struct pinctrl_ops imx_pctrl_ops = {
	.get_groups_count = imx_get_groups_count,
	.get_group_name = imx_get_group_name,
	.get_group_pins = imx_get_group_pins,
	.pin_dbg_show = imx_pin_dbg_show,
	.dt_node_to_map = imx_dt_node_to_map,
	.dt_free_map = imx_dt_free_map,

};

static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
			   unsigned group)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	const struct imx_pin_reg *pin_reg;
	const unsigned *pins, *mux, *input_val;
	u16 *input_reg;
	unsigned int npins, pin_id;
	int i;

	/*
	 * Configure the mux mode for each pin in the group for a specific
	 * function.
	 */
	pins = info->groups[group].pins;
	npins = info->groups[group].npins;
	mux = info->groups[group].mux_mode;
	input_val = info->groups[group].input_val;
	input_reg = info->groups[group].input_reg;

	WARN_ON(!pins || !npins || !mux || !input_val || !input_reg);

	dev_dbg(ipctl->dev, "enable function %s group %s\n",
		info->functions[selector].name, info->groups[group].name);

	for (i = 0; i < npins; i++) {
		pin_id = pins[i];
		pin_reg = &info->pin_regs[pin_id];

		if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) {
			dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
				info->pins[pin_id].name);
			return -EINVAL;
		}

		if (info->flags & SHARE_MUX_CONF_REG) {
			u32 reg;
			reg = readl(ipctl->base + pin_reg->mux_reg);
			reg &= ~(0x7 << 20);
			reg |= (mux[i] << 20);
			writel(reg, ipctl->base + pin_reg->mux_reg);
		} else {
			writel(mux[i], ipctl->base + pin_reg->mux_reg);
		}
		dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
			pin_reg->mux_reg, mux[i]);

		/* some pins also need select input setting, set it if found */
		if (input_reg[i]) {
			writel(input_val[i], ipctl->base + input_reg[i]);
			dev_dbg(ipctl->dev,
				"==>select_input: offset 0x%x val 0x%x\n",
				input_reg[i], input_val[i]);
		}
	}

	return 0;
}

static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	return info->nfunctions;
}

static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev,
					  unsigned selector)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	return info->functions[selector].name;
}

static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
			       const char * const **groups,
			       unsigned * const num_groups)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	*groups = info->functions[selector].groups;
	*num_groups = info->functions[selector].num_groups;

	return 0;
}

static const struct pinmux_ops imx_pmx_ops = {
	.get_functions_count = imx_pmx_get_funcs_count,
	.get_function_name = imx_pmx_get_func_name,
	.get_function_groups = imx_pmx_get_groups,
	.enable = imx_pmx_enable,
};

static int imx_pinconf_get(struct pinctrl_dev *pctldev,
			     unsigned pin_id, unsigned long *config)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];

	if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
		dev_err(info->dev, "Pin(%s) does not support config function\n",
			info->pins[pin_id].name);
		return -EINVAL;
	}

	*config = readl(ipctl->base + pin_reg->conf_reg);

	if (info->flags & SHARE_MUX_CONF_REG)
		*config &= 0xffff;

	return 0;
}

static int imx_pinconf_set(struct pinctrl_dev *pctldev,
			     unsigned pin_id, unsigned long config)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];

	if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
		dev_err(info->dev, "Pin(%s) does not support config function\n",
			info->pins[pin_id].name);
		return -EINVAL;
	}

	dev_dbg(ipctl->dev, "pinconf set pin %s\n",
		info->pins[pin_id].name);

	if (info->flags & SHARE_MUX_CONF_REG) {
		u32 reg;
		reg = readl(ipctl->base + pin_reg->conf_reg);
		reg &= ~0xffff;
		reg |= config;
		writel(reg, ipctl->base + pin_reg->conf_reg);
	} else {
		writel(config, ipctl->base + pin_reg->conf_reg);
	}
	dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
		pin_reg->conf_reg, config);

	return 0;
}

static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
				   struct seq_file *s, unsigned pin_id)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
	unsigned long config;

	if (!pin_reg || !pin_reg->conf_reg) {
		seq_printf(s, "N/A");
		return;
	}

	config = readl(ipctl->base + pin_reg->conf_reg);
	seq_printf(s, "0x%lx", config);
}

static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
					 struct seq_file *s, unsigned group)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	struct imx_pin_group *grp;
	unsigned long config;
	const char *name;
	int i, ret;

	if (group > info->ngroups)
		return;

	seq_printf(s, "\n");
	grp = &info->groups[group];
	for (i = 0; i < grp->npins; i++) {
		name = pin_get_name(pctldev, grp->pins[i]);
		ret = imx_pinconf_get(pctldev, grp->pins[i], &config);
		if (ret)
			return;
		seq_printf(s, "%s: 0x%lx", name, config);
	}
}

static const struct pinconf_ops imx_pinconf_ops = {
	.pin_config_get = imx_pinconf_get,
	.pin_config_set = imx_pinconf_set,
	.pin_config_dbg_show = imx_pinconf_dbg_show,
	.pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
};

static struct pinctrl_desc imx_pinctrl_desc = {
	.pctlops = &imx_pctrl_ops,
	.pmxops = &imx_pmx_ops,
	.confops = &imx_pinconf_ops,
	.owner = THIS_MODULE,
};

/*
 * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
 * 1 u32 CONFIG, so 24 types in total for each pin.
 */
#define FSL_PIN_SIZE 24
#define SHARE_FSL_PIN_SIZE 20

static int imx_pinctrl_parse_groups(struct device_node *np,
				    struct imx_pin_group *grp,
				    struct imx_pinctrl_soc_info *info,
				    u32 index)
{
	int size, pin_size;
	const __be32 *list;
	int i;
	u32 config;

	dev_dbg(info->dev, "group(%d): %s\n", index, np->name);

	if (info->flags & SHARE_MUX_CONF_REG)
		pin_size = SHARE_FSL_PIN_SIZE;
	else
		pin_size = FSL_PIN_SIZE;
	/* Initialise group */
	grp->name = np->name;

	/*
	 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
	 * do sanity check and calculate pins number
	 */
	list = of_get_property(np, "fsl,pins", &size);
	/* we do not check return since it's safe node passed down */
	if (!size || size % pin_size) {
		dev_err(info->dev, "Invalid fsl,pins property\n");
		return -EINVAL;
	}

	grp->npins = size / pin_size;
	grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
				GFP_KERNEL);
	grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
				GFP_KERNEL);
	grp->input_reg = devm_kzalloc(info->dev, grp->npins * sizeof(u16),
				GFP_KERNEL);
	grp->input_val = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
				GFP_KERNEL);
	grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long),
				GFP_KERNEL);
	for (i = 0; i < grp->npins; i++) {
		u32 mux_reg = be32_to_cpu(*list++);
		u32 conf_reg;
		unsigned int pin_id;
		struct imx_pin_reg *pin_reg;

		if (info->flags & SHARE_MUX_CONF_REG)
			conf_reg = mux_reg;
		else
			conf_reg = be32_to_cpu(*list++);

		pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
		pin_reg = &info->pin_regs[pin_id];
		grp->pins[i] = pin_id;
		pin_reg->mux_reg = mux_reg;
		pin_reg->conf_reg = conf_reg;
		grp->input_reg[i] = be32_to_cpu(*list++);
		grp->mux_mode[i] = be32_to_cpu(*list++);
		grp->input_val[i] = be32_to_cpu(*list++);

		/* SION bit is in mux register */
		config = be32_to_cpu(*list++);
		if (config & IMX_PAD_SION)
			grp->mux_mode[i] |= IOMUXC_CONFIG_SION;
		grp->configs[i] = config & ~IMX_PAD_SION;
	}

#ifdef DEBUG
	IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins);
#endif

	return 0;
}

static int imx_pinctrl_parse_functions(struct device_node *np,
				       struct imx_pinctrl_soc_info *info,
				       u32 index)
{
	struct device_node *child;
	struct imx_pmx_func *func;
	struct imx_pin_group *grp;
	int ret;
	static u32 grp_index;
	u32 i = 0;

	dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);

	func = &info->functions[index];

	/* Initialise function */
	func->name = np->name;
	func->num_groups = of_get_child_count(np);
	if (func->num_groups <= 0) {
		dev_err(info->dev, "no groups defined\n");
		return -EINVAL;
	}
	func->groups = devm_kzalloc(info->dev,
			func->num_groups * sizeof(char *), GFP_KERNEL);

	for_each_child_of_node(np, child) {
		func->groups[i] = child->name;
		grp = &info->groups[grp_index++];
		ret = imx_pinctrl_parse_groups(child, grp, info, i++);
		if (ret)
			return ret;
	}

	return 0;
}

static int imx_pinctrl_probe_dt(struct platform_device *pdev,
				struct imx_pinctrl_soc_info *info)
{
	struct device_node *np = pdev->dev.of_node;
	struct device_node *child;
	int ret;
	u32 nfuncs = 0;
	u32 i = 0;

	if (!np)
		return -ENODEV;

	nfuncs = of_get_child_count(np);
	if (nfuncs <= 0) {
		dev_err(&pdev->dev, "no functions defined\n");
		return -EINVAL;
	}

	info->nfunctions = nfuncs;
	info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
					GFP_KERNEL);
	if (!info->functions)
		return -ENOMEM;

	info->ngroups = 0;
	for_each_child_of_node(np, child)
		info->ngroups += of_get_child_count(child);
	info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
					GFP_KERNEL);
	if (!info->groups)
		return -ENOMEM;

	for_each_child_of_node(np, child) {
		ret = imx_pinctrl_parse_functions(child, info, i++);
		if (ret) {
			dev_err(&pdev->dev, "failed to parse function\n");
			return ret;
		}
	}

	return 0;
}

int imx_pinctrl_probe(struct platform_device *pdev,
		      struct imx_pinctrl_soc_info *info)
{
	struct imx_pinctrl *ipctl;
	struct resource *res;
	int ret;

	if (!info || !info->pins || !info->npins) {
		dev_err(&pdev->dev, "wrong pinctrl info\n");
		return -EINVAL;
	}
	info->dev = &pdev->dev;

	/* Create state holders etc for this driver */
	ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
	if (!ipctl)
		return -ENOMEM;

	info->pin_regs = devm_kzalloc(&pdev->dev, sizeof(*info->pin_regs) *
				      info->npins, GFP_KERNEL);
	if (!info->pin_regs)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENOENT;

	ipctl->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(ipctl->base))
		return PTR_ERR(ipctl->base);

	imx_pinctrl_desc.name = dev_name(&pdev->dev);
	imx_pinctrl_desc.pins = info->pins;
	imx_pinctrl_desc.npins = info->npins;

	ret = imx_pinctrl_probe_dt(pdev, info);
	if (ret) {
		dev_err(&pdev->dev, "fail to probe dt properties\n");
		return ret;
	}

	ipctl->info = info;
	ipctl->dev = info->dev;
	platform_set_drvdata(pdev, ipctl);
	ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
	if (!ipctl->pctl) {
		dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
		return -EINVAL;
	}

	dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");

	return 0;
}

int imx_pinctrl_remove(struct platform_device *pdev)
{
	struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);

	pinctrl_unregister(ipctl->pctl);

	return 0;
}
Commit	Line	Data
ae75ff81 DA	1	/*
	2	* Core driver for the imx pin controller
	3	*
	4	* Copyright (C) 2012 Freescale Semiconductor, Inc.
	5	* Copyright (C) 2012 Linaro Ltd.
	6	*
	7	* Author: Dong Aisheng <dong.aisheng@linaro.org>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*/
	14
	15	#include <linux/err.h>
	16	#include <linux/init.h>
	17	#include <linux/io.h>
	18	#include <linux/module.h>
	19	#include <linux/of.h>
	20	#include <linux/of_device.h>
	21	#include <linux/pinctrl/machine.h>
	22	#include <linux/pinctrl/pinconf.h>
	23	#include <linux/pinctrl/pinctrl.h>
	24	#include <linux/pinctrl/pinmux.h>
	25	#include <linux/slab.h>
	26
	27	#include "core.h"
	28	#include "pinctrl-imx.h"
	29
3a86a5f8 DN	30	#define IMX_PMX_DUMP(info, p, m, c, n) \
	31	{ \
	32	int i, j; \
	33	printk(KERN_DEBUG "Format: Pin Mux Config\n"); \
	34	for (i = 0; i < n; i++) { \
	35	j = p[i]; \
	36	printk(KERN_DEBUG "%s %d 0x%lx\n", \
	37	info->pins[j].name, \
	38	m[i], c[i]); \
	39	} \
ae75ff81 DA	40	}
	41
	42	/* The bits in CONFIG cell defined in binding doc*/
	43	#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
	44	#define IMX_PAD_SION 0x40000000 /* set SION */
	45
	46	/**
	47	* @dev: a pointer back to containing device
	48	* @base: the offset to the controller in virtual memory
	49	*/
	50	struct imx_pinctrl {
	51	struct device *dev;
	52	struct pinctrl_dev *pctl;
	53	void __iomem *base;
	54	const struct imx_pinctrl_soc_info *info;
	55	};
	56
ae75ff81 DA	57	static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
	58	const struct imx_pinctrl_soc_info *info,
	59	const char *name)
	60	{
	61	const struct imx_pin_group *grp = NULL;
	62	int i;
	63
	64	for (i = 0; i < info->ngroups; i++) {
	65	if (!strcmp(info->groups[i].name, name)) {
	66	grp = &info->groups[i];
	67	break;
	68	}
	69	}
	70
	71	return grp;
	72	}
	73
	74	static int imx_get_groups_count(struct pinctrl_dev *pctldev)
	75	{
	76	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	77	const struct imx_pinctrl_soc_info *info = ipctl->info;
	78
	79	return info->ngroups;
	80	}
	81
	82	static const char imx_get_group_name(struct pinctrl_dev pctldev,
	83	unsigned selector)
	84	{
	85	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	86	const struct imx_pinctrl_soc_info *info = ipctl->info;
	87
	88	return info->groups[selector].name;
	89	}
	90
	91	static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
	92	const unsigned **pins,
	93	unsigned *npins)
	94	{
	95	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	96	const struct imx_pinctrl_soc_info *info = ipctl->info;
	97
	98	if (selector >= info->ngroups)
	99	return -EINVAL;
	100
	101	*pins = info->groups[selector].pins;
	102	*npins = info->groups[selector].npins;
	103
	104	return 0;
	105	}
	106
	107	static void imx_pin_dbg_show(struct pinctrl_dev pctldev, struct seq_file s,
	108	unsigned offset)
	109	{
	110	seq_printf(s, "%s", dev_name(pctldev->dev));
	111	}
	112
	113	static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
	114	struct device_node *np,
	115	struct pinctrl_map *map, unsigned num_maps)
	116	{
	117	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	118	const struct imx_pinctrl_soc_info *info = ipctl->info;
	119	const struct imx_pin_group *grp;
	120	struct pinctrl_map *new_map;
121	struct device_node *parent;
122	int map_num = 1;
18071610	123	int i, j;
ae75ff81 DA	124
	125	/*
	126	* first find the group of this node and check if we need create
	127	* config maps for pins
	128	*/
	129	grp = imx_pinctrl_find_group_by_name(info, np->name);
	130	if (!grp) {
	131	dev_err(info->dev, "unable to find group for node %s\n",
	132	np->name);
	133	return -EINVAL;
	134	}
	135
	136	for (i = 0; i < grp->npins; i++) {
	137	if (!(grp->configs[i] & IMX_NO_PAD_CTL))
	138	map_num++;
	139	}
	140
	141	new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
	142	if (!new_map)
	143	return -ENOMEM;
	144
	145	*map = new_map;
	146	*num_maps = map_num;
	147
	148	/* create mux map */
	149	parent = of_get_parent(np);
c71157c5 DN	150	if (!parent) {
c71157c5 DN	151	kfree(new_map);
ae75ff81	152	return -EINVAL;
c71157c5	153	}
ae75ff81 DA	154	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
	155	new_map[0].data.mux.function = parent->name;
	156	new_map[0].data.mux.group = np->name;
	157	of_node_put(parent);
	158
	159	/* create config map */
	160	new_map++;
18071610	161	for (i = j = 0; i < grp->npins; i++) {
ae75ff81	162	if (!(grp->configs[i] & IMX_NO_PAD_CTL)) {
18071610 HW	163	new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
18071610 HW	164	new_map[j].data.configs.group_or_pin =
ae75ff81	165	pin_get_name(pctldev, grp->pins[i]);
18071610 HW	166	new_map[j].data.configs.configs = &grp->configs[i];
	167	new_map[j].data.configs.num_configs = 1;
	168	j++;
ae75ff81 DA	169	}
	170	}
	171
	172	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
67695f2e	173	(map)->data.mux.function, (map)->data.mux.group, map_num);
ae75ff81 DA	174
	175	return 0;
	176	}
	177
	178	static void imx_dt_free_map(struct pinctrl_dev *pctldev,
	179	struct pinctrl_map *map, unsigned num_maps)
	180	{
3a86a5f8	181	kfree(map);
ae75ff81 DA	182	}
ae75ff81 DA	183
022ab148	184	static const struct pinctrl_ops imx_pctrl_ops = {
ae75ff81 DA	185	.get_groups_count = imx_get_groups_count,
	186	.get_group_name = imx_get_group_name,
	187	.get_group_pins = imx_get_group_pins,
	188	.pin_dbg_show = imx_pin_dbg_show,
	189	.dt_node_to_map = imx_dt_node_to_map,
	190	.dt_free_map = imx_dt_free_map,
	191
	192	};
	193
	194	static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
	195	unsigned group)
	196	{
	197	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	198	const struct imx_pinctrl_soc_info *info = ipctl->info;
	199	const struct imx_pin_reg *pin_reg;
e1641531 SG	200	const unsigned pins, mux, *input_val;
e1641531 SG	201	u16 *input_reg;
ae75ff81 DA	202	unsigned int npins, pin_id;
	203	int i;
	204
	205	/*
	206	* Configure the mux mode for each pin in the group for a specific
	207	* function.
	208	*/
	209	pins = info->groups[group].pins;
	210	npins = info->groups[group].npins;
	211	mux = info->groups[group].mux_mode;
e1641531 SG	212	input_val = info->groups[group].input_val;
e1641531 SG	213	input_reg = info->groups[group].input_reg;
ae75ff81	214
e1641531	215	WARN_ON(!pins \|\| !npins \|\| !mux \|\| !input_val \|\| !input_reg);
ae75ff81 DA	216
	217	dev_dbg(ipctl->dev, "enable function %s group %s\n",
	218	info->functions[selector].name, info->groups[group].name);
	219
	220	for (i = 0; i < npins; i++) {
	221	pin_id = pins[i];
e1641531	222	pin_reg = &info->pin_regs[pin_id];
ae75ff81	223
bf5a5309	224	if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) {
ae75ff81 DA	225	dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
	226	info->pins[pin_id].name);
	227	return -EINVAL;
	228	}
	229
bf5a5309 JL	230	if (info->flags & SHARE_MUX_CONF_REG) {
	231	u32 reg;
	232	reg = readl(ipctl->base + pin_reg->mux_reg);
	233	reg &= ~(0x7 << 20);
	234	reg \|= (mux[i] << 20);
	235	writel(reg, ipctl->base + pin_reg->mux_reg);
	236	} else {
	237	writel(mux[i], ipctl->base + pin_reg->mux_reg);
	238	}
ae75ff81 DA	239	dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
	240	pin_reg->mux_reg, mux[i]);
	241
	242	/* some pins also need select input setting, set it if found */
e1641531 SG	243	if (input_reg[i]) {
e1641531 SG	244	writel(input_val[i], ipctl->base + input_reg[i]);
ae75ff81 DA	245	dev_dbg(ipctl->dev,
ae75ff81 DA	246	"==>select_input: offset 0x%x val 0x%x\n",
e1641531	247	input_reg[i], input_val[i]);
ae75ff81 DA	248	}
	249	}
	250
	251	return 0;
	252	}
	253
ae75ff81 DA	254	static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
	255	{
	256	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	257	const struct imx_pinctrl_soc_info *info = ipctl->info;
	258
	259	return info->nfunctions;
	260	}
	261
	262	static const char imx_pmx_get_func_name(struct pinctrl_dev pctldev,
	263	unsigned selector)
	264	{
	265	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	266	const struct imx_pinctrl_soc_info *info = ipctl->info;
	267
	268	return info->functions[selector].name;
	269	}
	270
	271	static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
	272	const char * const **groups,
	273	unsigned * const num_groups)
	274	{
	275	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	276	const struct imx_pinctrl_soc_info *info = ipctl->info;
	277
	278	*groups = info->functions[selector].groups;
	279	*num_groups = info->functions[selector].num_groups;
	280
	281	return 0;
	282	}
	283
022ab148	284	static const struct pinmux_ops imx_pmx_ops = {
ae75ff81 DA	285	.get_functions_count = imx_pmx_get_funcs_count,
	286	.get_function_name = imx_pmx_get_func_name,
	287	.get_function_groups = imx_pmx_get_groups,
	288	.enable = imx_pmx_enable,
ae75ff81 DA	289	};
	290
	291	static int imx_pinconf_get(struct pinctrl_dev *pctldev,
	292	unsigned pin_id, unsigned long *config)
	293	{
	294	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	295	const struct imx_pinctrl_soc_info *info = ipctl->info;
e1641531	296	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
ae75ff81	297
bf5a5309	298	if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
ae75ff81 DA	299	dev_err(info->dev, "Pin(%s) does not support config function\n",
	300	info->pins[pin_id].name);
	301	return -EINVAL;
	302	}
	303
	304	*config = readl(ipctl->base + pin_reg->conf_reg);
	305
bf5a5309 JL	306	if (info->flags & SHARE_MUX_CONF_REG)
	307	*config &= 0xffff;
	308
ae75ff81 DA	309	return 0;
	310	}
	311
	312	static int imx_pinconf_set(struct pinctrl_dev *pctldev,
	313	unsigned pin_id, unsigned long config)
	314	{
	315	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	316	const struct imx_pinctrl_soc_info *info = ipctl->info;
e1641531	317	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
ae75ff81	318
bf5a5309	319	if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
ae75ff81 DA	320	dev_err(info->dev, "Pin(%s) does not support config function\n",
	321	info->pins[pin_id].name);
	322	return -EINVAL;
	323	}
	324
	325	dev_dbg(ipctl->dev, "pinconf set pin %s\n",
	326	info->pins[pin_id].name);
	327
bf5a5309 JL	328	if (info->flags & SHARE_MUX_CONF_REG) {
	329	u32 reg;
	330	reg = readl(ipctl->base + pin_reg->conf_reg);
	331	reg &= ~0xffff;
	332	reg \|= config;
	333	writel(reg, ipctl->base + pin_reg->conf_reg);
	334	} else {
	335	writel(config, ipctl->base + pin_reg->conf_reg);
	336	}
ae75ff81 DA	337	dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
	338	pin_reg->conf_reg, config);
	339
	340	return 0;
	341	}
	342
	343	static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
	344	struct seq_file *s, unsigned pin_id)
	345	{
	346	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	347	const struct imx_pinctrl_soc_info *info = ipctl->info;
e1641531	348	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
ae75ff81 DA	349	unsigned long config;
ae75ff81 DA	350
ae75ff81 DA	351	if (!pin_reg \|\| !pin_reg->conf_reg) {
	352	seq_printf(s, "N/A");
	353	return;
	354	}
	355
	356	config = readl(ipctl->base + pin_reg->conf_reg);
	357	seq_printf(s, "0x%lx", config);
	358	}
	359
	360	static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
	361	struct seq_file *s, unsigned group)
	362	{
	363	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	364	const struct imx_pinctrl_soc_info *info = ipctl->info;
	365	struct imx_pin_group *grp;
	366	unsigned long config;
	367	const char *name;
	368	int i, ret;
	369
	370	if (group > info->ngroups)
	371	return;
	372
	373	seq_printf(s, "\n");
	374	grp = &info->groups[group];
	375	for (i = 0; i < grp->npins; i++) {
	376	name = pin_get_name(pctldev, grp->pins[i]);
	377	ret = imx_pinconf_get(pctldev, grp->pins[i], &config);
	378	if (ret)
	379	return;
	380	seq_printf(s, "%s: 0x%lx", name, config);
	381	}
	382	}
	383
022ab148	384	static const struct pinconf_ops imx_pinconf_ops = {
ae75ff81 DA	385	.pin_config_get = imx_pinconf_get,
	386	.pin_config_set = imx_pinconf_set,
	387	.pin_config_dbg_show = imx_pinconf_dbg_show,
	388	.pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
	389	};
	390
	391	static struct pinctrl_desc imx_pinctrl_desc = {
	392	.pctlops = &imx_pctrl_ops,
	393	.pmxops = &imx_pmx_ops,
	394	.confops = &imx_pinconf_ops,
	395	.owner = THIS_MODULE,
	396	};
	397
e1641531 SG	398	/*
	399	* Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
	400	* 1 u32 CONFIG, so 24 types in total for each pin.
	401	*/
	402	#define FSL_PIN_SIZE 24
bf5a5309	403	#define SHARE_FSL_PIN_SIZE 20
ae75ff81	404
150632b0 GKH	405	static int imx_pinctrl_parse_groups(struct device_node *np,
	406	struct imx_pin_group *grp,
	407	struct imx_pinctrl_soc_info *info,
	408	u32 index)
ae75ff81	409	{
bf5a5309	410	int size, pin_size;
a695145b	411	const __be32 *list;
e1641531	412	int i;
ae75ff81 DA	413	u32 config;
	414
	415	dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
	416
bf5a5309 JL	417	if (info->flags & SHARE_MUX_CONF_REG)
	418	pin_size = SHARE_FSL_PIN_SIZE;
	419	else
	420	pin_size = FSL_PIN_SIZE;
ae75ff81 DA	421	/* Initialise group */
	422	grp->name = np->name;
	423
	424	/*
	425	* the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
	426	* do sanity check and calculate pins number
	427	*/
	428	list = of_get_property(np, "fsl,pins", &size);
	429	/* we do not check return since it's safe node passed down */
bf5a5309	430	if (!size \|\| size % pin_size) {
e1641531	431	dev_err(info->dev, "Invalid fsl,pins property\n");
ae75ff81 DA	432	return -EINVAL;
	433	}
	434
bf5a5309	435	grp->npins = size / pin_size;
ae75ff81 DA	436	grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
	437	GFP_KERNEL);
	438	grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
	439	GFP_KERNEL);
e1641531 SG	440	grp->input_reg = devm_kzalloc(info->dev, grp->npins * sizeof(u16),
	441	GFP_KERNEL);
	442	grp->input_val = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
	443	GFP_KERNEL);
ae75ff81 DA	444	grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long),
ae75ff81 DA	445	GFP_KERNEL);
e1641531 SG	446	for (i = 0; i < grp->npins; i++) {
e1641531 SG	447	u32 mux_reg = be32_to_cpu(*list++);
bf5a5309 JL	448	u32 conf_reg;
	449	unsigned int pin_id;
	450	struct imx_pin_reg *pin_reg;
e1641531	451
bf5a5309 JL	452	if (info->flags & SHARE_MUX_CONF_REG)
	453	conf_reg = mux_reg;
	454	else
	455	conf_reg = be32_to_cpu(*list++);
	456
	457	pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
	458	pin_reg = &info->pin_regs[pin_id];
e1641531 SG	459	grp->pins[i] = pin_id;
	460	pin_reg->mux_reg = mux_reg;
	461	pin_reg->conf_reg = conf_reg;
	462	grp->input_reg[i] = be32_to_cpu(*list++);
	463	grp->mux_mode[i] = be32_to_cpu(*list++);
	464	grp->input_val[i] = be32_to_cpu(*list++);
	465
ae75ff81 DA	466	/* SION bit is in mux register */
	467	config = be32_to_cpu(*list++);
	468	if (config & IMX_PAD_SION)
e1641531 SG	469	grp->mux_mode[i] \|= IOMUXC_CONFIG_SION;
e1641531 SG	470	grp->configs[i] = config & ~IMX_PAD_SION;
ae75ff81 DA	471	}
ae75ff81 DA	472
a6e7360b	473	#ifdef DEBUG
ae75ff81	474	IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins);
a6e7360b	475	#endif
3a86a5f8	476
ae75ff81 DA	477	return 0;
	478	}
	479
150632b0 GKH	480	static int imx_pinctrl_parse_functions(struct device_node *np,
	481	struct imx_pinctrl_soc_info *info,
	482	u32 index)
ae75ff81 DA	483	{
	484	struct device_node *child;
	485	struct imx_pmx_func *func;
	486	struct imx_pin_group *grp;
	487	int ret;
	488	static u32 grp_index;
	489	u32 i = 0;
	490
	491	dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
	492
	493	func = &info->functions[index];
	494
	495	/* Initialise function */
	496	func->name = np->name;
	497	func->num_groups = of_get_child_count(np);
	498	if (func->num_groups <= 0) {
	499	dev_err(info->dev, "no groups defined\n");
	500	return -EINVAL;
	501	}
	502	func->groups = devm_kzalloc(info->dev,
	503	func->num_groups * sizeof(char *), GFP_KERNEL);
	504
	505	for_each_child_of_node(np, child) {
	506	func->groups[i] = child->name;
	507	grp = &info->groups[grp_index++];
	508	ret = imx_pinctrl_parse_groups(child, grp, info, i++);
	509	if (ret)
	510	return ret;
	511	}
	512
	513	return 0;
	514	}
	515
150632b0	516	static int imx_pinctrl_probe_dt(struct platform_device *pdev,
ae75ff81 DA	517	struct imx_pinctrl_soc_info *info)
	518	{
	519	struct device_node *np = pdev->dev.of_node;
	520	struct device_node *child;
	521	int ret;
	522	u32 nfuncs = 0;
	523	u32 i = 0;
	524
	525	if (!np)
	526	return -ENODEV;
	527
	528	nfuncs = of_get_child_count(np);
	529	if (nfuncs <= 0) {
	530	dev_err(&pdev->dev, "no functions defined\n");
	531	return -EINVAL;
	532	}
	533
	534	info->nfunctions = nfuncs;
	535	info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
	536	GFP_KERNEL);
	537	if (!info->functions)
	538	return -ENOMEM;
	539
	540	info->ngroups = 0;
	541	for_each_child_of_node(np, child)
	542	info->ngroups += of_get_child_count(child);
	543	info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
	544	GFP_KERNEL);
	545	if (!info->groups)
	546	return -ENOMEM;
	547
	548	for_each_child_of_node(np, child) {
	549	ret = imx_pinctrl_parse_functions(child, info, i++);
	550	if (ret) {
	551	dev_err(&pdev->dev, "failed to parse function\n");
	552	return ret;
	553	}
	554	}
	555
	556	return 0;
	557	}
	558
150632b0 GKH	559	int imx_pinctrl_probe(struct platform_device *pdev,
150632b0 GKH	560	struct imx_pinctrl_soc_info *info)
ae75ff81 DA	561	{
	562	struct imx_pinctrl *ipctl;
	563	struct resource *res;
	564	int ret;
	565
e1641531	566	if (!info \|\| !info->pins \|\| !info->npins) {
ae75ff81 DA	567	dev_err(&pdev->dev, "wrong pinctrl info\n");
	568	return -EINVAL;
	569	}
	570	info->dev = &pdev->dev;
	571
	572	/* Create state holders etc for this driver */
	573	ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
	574	if (!ipctl)
	575	return -ENOMEM;
	576
e1641531 SG	577	info->pin_regs = devm_kzalloc(&pdev->dev, sizeof(info->pin_regs)
	578	info->npins, GFP_KERNEL);
	579	if (!info->pin_regs)
	580	return -ENOMEM;
	581
ae75ff81 DA	582	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	583	if (!res)
	584	return -ENOENT;
	585
9e0c1fb2 TR	586	ipctl->base = devm_ioremap_resource(&pdev->dev, res);
	587	if (IS_ERR(ipctl->base))
	588	return PTR_ERR(ipctl->base);
ae75ff81 DA	589
	590	imx_pinctrl_desc.name = dev_name(&pdev->dev);
	591	imx_pinctrl_desc.pins = info->pins;
	592	imx_pinctrl_desc.npins = info->npins;
	593
	594	ret = imx_pinctrl_probe_dt(pdev, info);
	595	if (ret) {
	596	dev_err(&pdev->dev, "fail to probe dt properties\n");
	597	return ret;
	598	}
	599
	600	ipctl->info = info;
	601	ipctl->dev = info->dev;
	602	platform_set_drvdata(pdev, ipctl);
	603	ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
	604	if (!ipctl->pctl) {
	605	dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
	606	return -EINVAL;
	607	}
	608
	609	dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
	610
	611	return 0;
	612	}
	613
f90f54b3	614	int imx_pinctrl_remove(struct platform_device *pdev)
ae75ff81 DA	615	{
	616	struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);
	617
	618	pinctrl_unregister(ipctl->pctl);
	619
	620	return 0;
	621	}