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2df723d4 LD |
1 | /* |
2 | * MAX77620 pin control driver. | |
3 | * | |
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | |
5 | * | |
6 | * Author: | |
7 | * Chaitanya Bandi <bandik@nvidia.com> | |
8 | * Laxman Dewangan <ldewangan@nvidia.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms and conditions of the GNU General Public License, | |
12 | * version 2, as published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/mfd/max77620.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/of.h> | |
18 | #include <linux/pinctrl/pinctrl.h> | |
19 | #include <linux/pinctrl/pinconf-generic.h> | |
20 | #include <linux/pinctrl/pinconf.h> | |
21 | #include <linux/pinctrl/pinmux.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/regmap.h> | |
24 | ||
25 | #include "core.h" | |
26 | #include "pinconf.h" | |
27 | #include "pinctrl-utils.h" | |
28 | ||
29 | #define MAX77620_PIN_NUM 8 | |
30 | ||
31 | enum max77620_pin_ppdrv { | |
32 | MAX77620_PIN_UNCONFIG_DRV, | |
33 | MAX77620_PIN_OD_DRV, | |
34 | MAX77620_PIN_PP_DRV, | |
35 | }; | |
36 | ||
37 | enum max77620_pinconf_param { | |
38 | MAX77620_ACTIVE_FPS_SOURCE = PIN_CONFIG_END + 1, | |
39 | MAX77620_ACTIVE_FPS_POWER_ON_SLOTS, | |
40 | MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS, | |
41 | MAX77620_SUSPEND_FPS_SOURCE, | |
42 | MAX77620_SUSPEND_FPS_POWER_ON_SLOTS, | |
43 | MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS, | |
44 | }; | |
45 | ||
46 | struct max77620_pin_function { | |
47 | const char *name; | |
48 | const char * const *groups; | |
49 | unsigned int ngroups; | |
50 | int mux_option; | |
51 | }; | |
52 | ||
2df723d4 LD |
53 | static const struct pinconf_generic_params max77620_cfg_params[] = { |
54 | { | |
55 | .property = "maxim,active-fps-source", | |
56 | .param = MAX77620_ACTIVE_FPS_SOURCE, | |
57 | }, { | |
58 | .property = "maxim,active-fps-power-up-slot", | |
59 | .param = MAX77620_ACTIVE_FPS_POWER_ON_SLOTS, | |
60 | }, { | |
61 | .property = "maxim,active-fps-power-down-slot", | |
62 | .param = MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS, | |
63 | }, { | |
64 | .property = "maxim,suspend-fps-source", | |
65 | .param = MAX77620_SUSPEND_FPS_SOURCE, | |
66 | }, { | |
67 | .property = "maxim,suspend-fps-power-up-slot", | |
68 | .param = MAX77620_SUSPEND_FPS_POWER_ON_SLOTS, | |
69 | }, { | |
70 | .property = "maxim,suspend-fps-power-down-slot", | |
71 | .param = MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS, | |
72 | }, | |
73 | }; | |
74 | ||
75 | enum max77620_alternate_pinmux_option { | |
76 | MAX77620_PINMUX_GPIO = 0, | |
77 | MAX77620_PINMUX_LOW_POWER_MODE_CONTROL_IN = 1, | |
78 | MAX77620_PINMUX_FLEXIBLE_POWER_SEQUENCER_OUT = 2, | |
79 | MAX77620_PINMUX_32K_OUT1 = 3, | |
80 | MAX77620_PINMUX_SD0_DYNAMIC_VOLTAGE_SCALING_IN = 4, | |
81 | MAX77620_PINMUX_SD1_DYNAMIC_VOLTAGE_SCALING_IN = 5, | |
82 | MAX77620_PINMUX_REFERENCE_OUT = 6, | |
83 | }; | |
84 | ||
85 | struct max77620_pingroup { | |
86 | const char *name; | |
87 | const unsigned int pins[1]; | |
88 | unsigned int npins; | |
89 | enum max77620_alternate_pinmux_option alt_option; | |
90 | }; | |
91 | ||
92 | struct max77620_pin_info { | |
93 | enum max77620_pin_ppdrv drv_type; | |
94 | int pull_config; | |
95 | }; | |
96 | ||
97 | struct max77620_fps_config { | |
98 | int active_fps_src; | |
99 | int active_power_up_slots; | |
100 | int active_power_down_slots; | |
101 | int suspend_fps_src; | |
102 | int suspend_power_up_slots; | |
103 | int suspend_power_down_slots; | |
104 | }; | |
105 | ||
106 | struct max77620_pctrl_info { | |
107 | struct device *dev; | |
108 | struct pinctrl_dev *pctl; | |
109 | struct regmap *rmap; | |
110 | int pins_current_opt[MAX77620_GPIO_NR]; | |
111 | const struct max77620_pin_function *functions; | |
112 | unsigned int num_functions; | |
113 | const struct max77620_pingroup *pin_groups; | |
114 | int num_pin_groups; | |
115 | const struct pinctrl_pin_desc *pins; | |
116 | unsigned int num_pins; | |
117 | struct max77620_pin_info pin_info[MAX77620_PIN_NUM]; | |
118 | struct max77620_fps_config fps_config[MAX77620_PIN_NUM]; | |
119 | }; | |
120 | ||
121 | static const struct pinctrl_pin_desc max77620_pins_desc[] = { | |
122 | PINCTRL_PIN(MAX77620_GPIO0, "gpio0"), | |
123 | PINCTRL_PIN(MAX77620_GPIO1, "gpio1"), | |
124 | PINCTRL_PIN(MAX77620_GPIO2, "gpio2"), | |
125 | PINCTRL_PIN(MAX77620_GPIO3, "gpio3"), | |
126 | PINCTRL_PIN(MAX77620_GPIO4, "gpio4"), | |
127 | PINCTRL_PIN(MAX77620_GPIO5, "gpio5"), | |
128 | PINCTRL_PIN(MAX77620_GPIO6, "gpio6"), | |
129 | PINCTRL_PIN(MAX77620_GPIO7, "gpio7"), | |
130 | }; | |
131 | ||
132 | static const char * const gpio_groups[] = { | |
133 | "gpio0", | |
134 | "gpio1", | |
135 | "gpio2", | |
136 | "gpio3", | |
137 | "gpio4", | |
138 | "gpio5", | |
139 | "gpio6", | |
140 | "gpio7", | |
141 | }; | |
142 | ||
143 | #define FUNCTION_GROUP(fname, mux) \ | |
144 | { \ | |
145 | .name = fname, \ | |
146 | .groups = gpio_groups, \ | |
147 | .ngroups = ARRAY_SIZE(gpio_groups), \ | |
148 | .mux_option = MAX77620_PINMUX_##mux, \ | |
149 | } | |
150 | ||
151 | static const struct max77620_pin_function max77620_pin_function[] = { | |
152 | FUNCTION_GROUP("gpio", GPIO), | |
153 | FUNCTION_GROUP("lpm-control-in", LOW_POWER_MODE_CONTROL_IN), | |
154 | FUNCTION_GROUP("fps-out", FLEXIBLE_POWER_SEQUENCER_OUT), | |
155 | FUNCTION_GROUP("32k-out1", 32K_OUT1), | |
156 | FUNCTION_GROUP("sd0-dvs-in", SD0_DYNAMIC_VOLTAGE_SCALING_IN), | |
157 | FUNCTION_GROUP("sd1-dvs-in", SD1_DYNAMIC_VOLTAGE_SCALING_IN), | |
158 | FUNCTION_GROUP("reference-out", REFERENCE_OUT), | |
159 | }; | |
160 | ||
161 | #define MAX77620_PINGROUP(pg_name, pin_id, option) \ | |
162 | { \ | |
163 | .name = #pg_name, \ | |
164 | .pins = {MAX77620_##pin_id}, \ | |
165 | .npins = 1, \ | |
166 | .alt_option = MAX77620_PINMUX_##option, \ | |
167 | } | |
168 | ||
169 | static const struct max77620_pingroup max77620_pingroups[] = { | |
170 | MAX77620_PINGROUP(gpio0, GPIO0, LOW_POWER_MODE_CONTROL_IN), | |
171 | MAX77620_PINGROUP(gpio1, GPIO1, FLEXIBLE_POWER_SEQUENCER_OUT), | |
172 | MAX77620_PINGROUP(gpio2, GPIO2, FLEXIBLE_POWER_SEQUENCER_OUT), | |
173 | MAX77620_PINGROUP(gpio3, GPIO3, FLEXIBLE_POWER_SEQUENCER_OUT), | |
174 | MAX77620_PINGROUP(gpio4, GPIO4, 32K_OUT1), | |
175 | MAX77620_PINGROUP(gpio5, GPIO5, SD0_DYNAMIC_VOLTAGE_SCALING_IN), | |
176 | MAX77620_PINGROUP(gpio6, GPIO6, SD1_DYNAMIC_VOLTAGE_SCALING_IN), | |
177 | MAX77620_PINGROUP(gpio7, GPIO7, REFERENCE_OUT), | |
178 | }; | |
179 | ||
180 | static int max77620_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) | |
181 | { | |
182 | struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); | |
183 | ||
184 | return mpci->num_pin_groups; | |
185 | } | |
186 | ||
187 | static const char *max77620_pinctrl_get_group_name( | |
188 | struct pinctrl_dev *pctldev, unsigned int group) | |
189 | { | |
190 | struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); | |
191 | ||
192 | return mpci->pin_groups[group].name; | |
193 | } | |
194 | ||
195 | static int max77620_pinctrl_get_group_pins( | |
196 | struct pinctrl_dev *pctldev, unsigned int group, | |
197 | const unsigned int **pins, unsigned int *num_pins) | |
198 | { | |
199 | struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); | |
200 | ||
201 | *pins = mpci->pin_groups[group].pins; | |
202 | *num_pins = mpci->pin_groups[group].npins; | |
203 | ||
204 | return 0; | |
205 | } | |
206 | ||
207 | static const struct pinctrl_ops max77620_pinctrl_ops = { | |
208 | .get_groups_count = max77620_pinctrl_get_groups_count, | |
209 | .get_group_name = max77620_pinctrl_get_group_name, | |
210 | .get_group_pins = max77620_pinctrl_get_group_pins, | |
211 | .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, | |
212 | .dt_free_map = pinctrl_utils_free_map, | |
213 | }; | |
214 | ||
215 | static int max77620_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) | |
216 | { | |
217 | struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); | |
218 | ||
219 | return mpci->num_functions; | |
220 | } | |
221 | ||
222 | static const char *max77620_pinctrl_get_func_name(struct pinctrl_dev *pctldev, | |
223 | unsigned int function) | |
224 | { | |
225 | struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); | |
226 | ||
227 | return mpci->functions[function].name; | |
228 | } | |
229 | ||
230 | static int max77620_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, | |
231 | unsigned int function, | |
232 | const char * const **groups, | |
233 | unsigned int * const num_groups) | |
234 | { | |
235 | struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); | |
236 | ||
237 | *groups = mpci->functions[function].groups; | |
238 | *num_groups = mpci->functions[function].ngroups; | |
239 | ||
240 | return 0; | |
241 | } | |
242 | ||
243 | static int max77620_pinctrl_enable(struct pinctrl_dev *pctldev, | |
244 | unsigned int function, unsigned int group) | |
245 | { | |
246 | struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); | |
247 | u8 val; | |
248 | int ret; | |
249 | ||
250 | if (function == MAX77620_PINMUX_GPIO) { | |
251 | val = 0; | |
252 | } else if (function == mpci->pin_groups[group].alt_option) { | |
253 | val = 1 << group; | |
254 | } else { | |
255 | dev_err(mpci->dev, "GPIO %u doesn't have function %u\n", | |
256 | group, function); | |
257 | return -EINVAL; | |
258 | } | |
259 | ret = regmap_update_bits(mpci->rmap, MAX77620_REG_AME_GPIO, | |
260 | BIT(group), val); | |
261 | if (ret < 0) | |
262 | dev_err(mpci->dev, "REG AME GPIO update failed: %d\n", ret); | |
263 | ||
264 | return ret; | |
265 | } | |
266 | ||
267 | static const struct pinmux_ops max77620_pinmux_ops = { | |
268 | .get_functions_count = max77620_pinctrl_get_funcs_count, | |
269 | .get_function_name = max77620_pinctrl_get_func_name, | |
270 | .get_function_groups = max77620_pinctrl_get_func_groups, | |
271 | .set_mux = max77620_pinctrl_enable, | |
272 | }; | |
273 | ||
274 | static int max77620_pinconf_get(struct pinctrl_dev *pctldev, | |
275 | unsigned int pin, unsigned long *config) | |
276 | { | |
277 | struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); | |
278 | struct device *dev = mpci->dev; | |
279 | enum pin_config_param param = pinconf_to_config_param(*config); | |
280 | unsigned int val; | |
281 | int arg = 0; | |
282 | int ret; | |
283 | ||
284 | switch (param) { | |
285 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
286 | if (mpci->pin_info[pin].drv_type == MAX77620_PIN_OD_DRV) | |
287 | arg = 1; | |
288 | break; | |
289 | ||
290 | case PIN_CONFIG_DRIVE_PUSH_PULL: | |
291 | if (mpci->pin_info[pin].drv_type == MAX77620_PIN_PP_DRV) | |
292 | arg = 1; | |
293 | break; | |
294 | ||
295 | case PIN_CONFIG_BIAS_PULL_UP: | |
296 | ret = regmap_read(mpci->rmap, MAX77620_REG_PUE_GPIO, &val); | |
297 | if (ret < 0) { | |
298 | dev_err(dev, "Reg PUE_GPIO read failed: %d\n", ret); | |
299 | return ret; | |
300 | } | |
301 | if (val & BIT(pin)) | |
302 | arg = 1; | |
303 | break; | |
304 | ||
305 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
306 | ret = regmap_read(mpci->rmap, MAX77620_REG_PDE_GPIO, &val); | |
307 | if (ret < 0) { | |
308 | dev_err(dev, "Reg PDE_GPIO read failed: %d\n", ret); | |
309 | return ret; | |
310 | } | |
311 | if (val & BIT(pin)) | |
312 | arg = 1; | |
313 | break; | |
314 | ||
315 | default: | |
316 | dev_err(dev, "Properties not supported\n"); | |
317 | return -ENOTSUPP; | |
318 | } | |
319 | ||
320 | *config = pinconf_to_config_packed(param, (u16)arg); | |
321 | ||
322 | return 0; | |
323 | } | |
324 | ||
325 | static int max77620_get_default_fps(struct max77620_pctrl_info *mpci, | |
326 | int addr, int *fps) | |
327 | { | |
328 | unsigned int val; | |
329 | int ret; | |
330 | ||
331 | ret = regmap_read(mpci->rmap, addr, &val); | |
332 | if (ret < 0) { | |
333 | dev_err(mpci->dev, "Reg PUE_GPIO read failed: %d\n", ret); | |
334 | return ret; | |
335 | } | |
336 | *fps = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT; | |
337 | ||
338 | return 0; | |
339 | } | |
340 | ||
341 | static int max77620_set_fps_param(struct max77620_pctrl_info *mpci, | |
342 | int pin, int param) | |
343 | { | |
344 | struct max77620_fps_config *fps_config = &mpci->fps_config[pin]; | |
345 | int addr, ret; | |
346 | int param_val; | |
347 | int mask, shift; | |
348 | ||
349 | if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) | |
350 | return 0; | |
351 | ||
352 | addr = MAX77620_REG_FPS_GPIO1 + pin - 1; | |
353 | switch (param) { | |
354 | case MAX77620_ACTIVE_FPS_SOURCE: | |
355 | case MAX77620_SUSPEND_FPS_SOURCE: | |
356 | mask = MAX77620_FPS_SRC_MASK; | |
357 | shift = MAX77620_FPS_SRC_SHIFT; | |
358 | param_val = fps_config->active_fps_src; | |
359 | if (param == MAX77620_SUSPEND_FPS_SOURCE) | |
360 | param_val = fps_config->suspend_fps_src; | |
361 | break; | |
362 | ||
363 | case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS: | |
364 | case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS: | |
365 | mask = MAX77620_FPS_PU_PERIOD_MASK; | |
366 | shift = MAX77620_FPS_PU_PERIOD_SHIFT; | |
367 | param_val = fps_config->active_power_up_slots; | |
368 | if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS) | |
369 | param_val = fps_config->suspend_power_up_slots; | |
370 | break; | |
371 | ||
372 | case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS: | |
373 | case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS: | |
374 | mask = MAX77620_FPS_PD_PERIOD_MASK; | |
375 | shift = MAX77620_FPS_PD_PERIOD_SHIFT; | |
376 | param_val = fps_config->active_power_down_slots; | |
377 | if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS) | |
378 | param_val = fps_config->suspend_power_down_slots; | |
379 | break; | |
380 | ||
381 | default: | |
382 | dev_err(mpci->dev, "Invalid parameter %d for pin %d\n", | |
383 | param, pin); | |
384 | return -EINVAL; | |
385 | } | |
386 | ||
387 | if (param_val < 0) | |
388 | return 0; | |
389 | ||
390 | ret = regmap_update_bits(mpci->rmap, addr, mask, param_val << shift); | |
391 | if (ret < 0) | |
392 | dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret); | |
393 | ||
394 | return ret; | |
395 | } | |
396 | ||
397 | static int max77620_pinconf_set(struct pinctrl_dev *pctldev, | |
398 | unsigned int pin, unsigned long *configs, | |
399 | unsigned int num_configs) | |
400 | { | |
401 | struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); | |
402 | struct device *dev = mpci->dev; | |
403 | struct max77620_fps_config *fps_config; | |
404 | int param; | |
405 | u16 param_val; | |
406 | unsigned int val; | |
407 | unsigned int pu_val; | |
408 | unsigned int pd_val; | |
409 | int addr, ret; | |
410 | int i; | |
411 | ||
412 | for (i = 0; i < num_configs; i++) { | |
413 | param = pinconf_to_config_param(configs[i]); | |
414 | param_val = pinconf_to_config_argument(configs[i]); | |
415 | ||
416 | switch (param) { | |
417 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
418 | val = param_val ? 0 : 1; | |
419 | ret = regmap_update_bits(mpci->rmap, | |
420 | MAX77620_REG_GPIO0 + pin, | |
421 | MAX77620_CNFG_GPIO_DRV_MASK, | |
422 | val); | |
423 | if (ret < 0) { | |
424 | dev_err(dev, "Reg 0x%02x update failed %d\n", | |
425 | MAX77620_REG_GPIO0 + pin, ret); | |
426 | return ret; | |
427 | } | |
428 | mpci->pin_info[pin].drv_type = val ? | |
429 | MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV; | |
430 | break; | |
431 | ||
432 | case PIN_CONFIG_DRIVE_PUSH_PULL: | |
433 | val = param_val ? 1 : 0; | |
434 | ret = regmap_update_bits(mpci->rmap, | |
435 | MAX77620_REG_GPIO0 + pin, | |
436 | MAX77620_CNFG_GPIO_DRV_MASK, | |
437 | val); | |
438 | if (ret < 0) { | |
439 | dev_err(dev, "Reg 0x%02x update failed %d\n", | |
440 | MAX77620_REG_GPIO0 + pin, ret); | |
441 | return ret; | |
442 | } | |
443 | mpci->pin_info[pin].drv_type = val ? | |
444 | MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV; | |
445 | break; | |
446 | ||
447 | case MAX77620_ACTIVE_FPS_SOURCE: | |
448 | case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS: | |
449 | case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS: | |
450 | if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) | |
451 | return -EINVAL; | |
452 | ||
453 | fps_config = &mpci->fps_config[pin]; | |
454 | ||
455 | if ((param == MAX77620_ACTIVE_FPS_SOURCE) && | |
456 | (param_val == MAX77620_FPS_SRC_DEF)) { | |
457 | addr = MAX77620_REG_FPS_GPIO1 + pin - 1; | |
458 | ret = max77620_get_default_fps( | |
459 | mpci, addr, | |
460 | &fps_config->active_fps_src); | |
461 | if (ret < 0) | |
462 | return ret; | |
463 | break; | |
464 | } | |
465 | ||
466 | if (param == MAX77620_ACTIVE_FPS_SOURCE) | |
467 | fps_config->active_fps_src = param_val; | |
468 | else if (param == MAX77620_ACTIVE_FPS_POWER_ON_SLOTS) | |
469 | fps_config->active_power_up_slots = param_val; | |
470 | else | |
471 | fps_config->active_power_down_slots = param_val; | |
472 | ||
473 | ret = max77620_set_fps_param(mpci, pin, param); | |
474 | if (ret < 0) | |
475 | return ret; | |
476 | break; | |
477 | ||
478 | case MAX77620_SUSPEND_FPS_SOURCE: | |
479 | case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS: | |
480 | case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS: | |
481 | if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) | |
482 | return -EINVAL; | |
483 | ||
484 | fps_config = &mpci->fps_config[pin]; | |
485 | ||
486 | if ((param == MAX77620_SUSPEND_FPS_SOURCE) && | |
487 | (param_val == MAX77620_FPS_SRC_DEF)) { | |
488 | addr = MAX77620_REG_FPS_GPIO1 + pin - 1; | |
489 | ret = max77620_get_default_fps( | |
490 | mpci, addr, | |
491 | &fps_config->suspend_fps_src); | |
492 | if (ret < 0) | |
493 | return ret; | |
494 | break; | |
495 | } | |
496 | ||
497 | if (param == MAX77620_SUSPEND_FPS_SOURCE) | |
498 | fps_config->suspend_fps_src = param_val; | |
499 | else if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS) | |
500 | fps_config->suspend_power_up_slots = param_val; | |
501 | else | |
502 | fps_config->suspend_power_down_slots = | |
503 | param_val; | |
504 | break; | |
505 | ||
506 | case PIN_CONFIG_BIAS_PULL_UP: | |
507 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
508 | pu_val = (param == PIN_CONFIG_BIAS_PULL_UP) ? | |
509 | BIT(pin) : 0; | |
510 | pd_val = (param == PIN_CONFIG_BIAS_PULL_DOWN) ? | |
511 | BIT(pin) : 0; | |
512 | ||
513 | ret = regmap_update_bits(mpci->rmap, | |
514 | MAX77620_REG_PUE_GPIO, | |
515 | BIT(pin), pu_val); | |
516 | if (ret < 0) { | |
517 | dev_err(dev, "PUE_GPIO update failed: %d\n", | |
518 | ret); | |
519 | return ret; | |
520 | } | |
521 | ||
522 | ret = regmap_update_bits(mpci->rmap, | |
523 | MAX77620_REG_PDE_GPIO, | |
524 | BIT(pin), pd_val); | |
525 | if (ret < 0) { | |
526 | dev_err(dev, "PDE_GPIO update failed: %d\n", | |
527 | ret); | |
528 | return ret; | |
529 | } | |
530 | break; | |
531 | ||
532 | default: | |
533 | dev_err(dev, "Properties not supported\n"); | |
534 | return -ENOTSUPP; | |
535 | } | |
536 | } | |
537 | ||
538 | return 0; | |
539 | } | |
540 | ||
541 | static const struct pinconf_ops max77620_pinconf_ops = { | |
542 | .pin_config_get = max77620_pinconf_get, | |
543 | .pin_config_set = max77620_pinconf_set, | |
544 | }; | |
545 | ||
546 | static struct pinctrl_desc max77620_pinctrl_desc = { | |
547 | .pctlops = &max77620_pinctrl_ops, | |
548 | .pmxops = &max77620_pinmux_ops, | |
549 | .confops = &max77620_pinconf_ops, | |
550 | }; | |
551 | ||
552 | static int max77620_pinctrl_probe(struct platform_device *pdev) | |
553 | { | |
554 | struct max77620_chip *max77620 = dev_get_drvdata(pdev->dev.parent); | |
555 | struct max77620_pctrl_info *mpci; | |
556 | int i; | |
557 | ||
558 | mpci = devm_kzalloc(&pdev->dev, sizeof(*mpci), GFP_KERNEL); | |
559 | if (!mpci) | |
560 | return -ENOMEM; | |
561 | ||
562 | mpci->dev = &pdev->dev; | |
563 | mpci->dev->of_node = pdev->dev.parent->of_node; | |
564 | mpci->rmap = max77620->rmap; | |
565 | ||
566 | mpci->pins = max77620_pins_desc; | |
567 | mpci->num_pins = ARRAY_SIZE(max77620_pins_desc); | |
568 | mpci->functions = max77620_pin_function; | |
569 | mpci->num_functions = ARRAY_SIZE(max77620_pin_function); | |
570 | mpci->pin_groups = max77620_pingroups; | |
571 | mpci->num_pin_groups = ARRAY_SIZE(max77620_pingroups); | |
572 | platform_set_drvdata(pdev, mpci); | |
573 | ||
574 | max77620_pinctrl_desc.name = dev_name(&pdev->dev); | |
575 | max77620_pinctrl_desc.pins = max77620_pins_desc; | |
576 | max77620_pinctrl_desc.npins = ARRAY_SIZE(max77620_pins_desc); | |
577 | max77620_pinctrl_desc.num_custom_params = | |
578 | ARRAY_SIZE(max77620_cfg_params); | |
579 | max77620_pinctrl_desc.custom_params = max77620_cfg_params; | |
580 | ||
581 | for (i = 0; i < MAX77620_PIN_NUM; ++i) { | |
582 | mpci->fps_config[i].active_fps_src = -1; | |
583 | mpci->fps_config[i].active_power_up_slots = -1; | |
584 | mpci->fps_config[i].active_power_down_slots = -1; | |
585 | mpci->fps_config[i].suspend_fps_src = -1; | |
586 | mpci->fps_config[i].suspend_power_up_slots = -1; | |
587 | mpci->fps_config[i].suspend_power_down_slots = -1; | |
588 | } | |
589 | ||
590 | mpci->pctl = devm_pinctrl_register(&pdev->dev, &max77620_pinctrl_desc, | |
591 | mpci); | |
592 | if (IS_ERR(mpci->pctl)) { | |
593 | dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); | |
594 | return PTR_ERR(mpci->pctl); | |
595 | } | |
596 | ||
597 | return 0; | |
598 | } | |
599 | ||
600 | #ifdef CONFIG_PM_SLEEP | |
601 | static int max77620_suspend_fps_param[] = { | |
602 | MAX77620_SUSPEND_FPS_SOURCE, | |
603 | MAX77620_SUSPEND_FPS_POWER_ON_SLOTS, | |
604 | MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS, | |
605 | }; | |
606 | ||
607 | static int max77620_active_fps_param[] = { | |
608 | MAX77620_ACTIVE_FPS_SOURCE, | |
609 | MAX77620_ACTIVE_FPS_POWER_ON_SLOTS, | |
610 | MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS, | |
611 | }; | |
612 | ||
613 | static int max77620_pinctrl_suspend(struct device *dev) | |
614 | { | |
615 | struct max77620_pctrl_info *mpci = dev_get_drvdata(dev); | |
616 | int pin, p; | |
617 | ||
618 | for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) { | |
619 | if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) | |
620 | continue; | |
621 | for (p = 0; p < 3; ++p) | |
622 | max77620_set_fps_param( | |
623 | mpci, pin, max77620_suspend_fps_param[p]); | |
624 | } | |
625 | ||
626 | return 0; | |
627 | }; | |
628 | ||
629 | static int max77620_pinctrl_resume(struct device *dev) | |
630 | { | |
631 | struct max77620_pctrl_info *mpci = dev_get_drvdata(dev); | |
632 | int pin, p; | |
633 | ||
634 | for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) { | |
635 | if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) | |
636 | continue; | |
637 | for (p = 0; p < 3; ++p) | |
638 | max77620_set_fps_param( | |
639 | mpci, pin, max77620_active_fps_param[p]); | |
640 | } | |
641 | ||
642 | return 0; | |
643 | } | |
644 | #endif | |
645 | ||
646 | static const struct dev_pm_ops max77620_pinctrl_pm_ops = { | |
647 | SET_SYSTEM_SLEEP_PM_OPS( | |
648 | max77620_pinctrl_suspend, max77620_pinctrl_resume) | |
649 | }; | |
650 | ||
651 | static const struct platform_device_id max77620_pinctrl_devtype[] = { | |
652 | { .name = "max77620-pinctrl", }, | |
653 | { .name = "max20024-pinctrl", }, | |
654 | {}, | |
655 | }; | |
656 | MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype); | |
657 | ||
658 | static struct platform_driver max77620_pinctrl_driver = { | |
659 | .driver = { | |
660 | .name = "max77620-pinctrl", | |
661 | .pm = &max77620_pinctrl_pm_ops, | |
662 | }, | |
663 | .probe = max77620_pinctrl_probe, | |
664 | .id_table = max77620_pinctrl_devtype, | |
665 | }; | |
666 | ||
667 | module_platform_driver(max77620_pinctrl_driver); | |
668 | ||
669 | MODULE_DESCRIPTION("MAX77620/MAX20024 pin control driver"); | |
670 | MODULE_AUTHOR("Chaitanya Bandi<bandik@nvidia.com>"); | |
671 | MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>"); | |
672 | MODULE_ALIAS("platform:max77620-pinctrl"); | |
673 | MODULE_LICENSE("GPL v2"); |