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Merge branch 'pm-tools'
[deliverable/linux.git] / drivers / pinctrl / pinctrl-msm.c
CommitLineData
f365be09
BA		 1/*
2 * Copyright (c) 2013, Sony Mobile Communications AB.
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/err.h>
f365be09
BA		 16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/pinctrl/machine.h>
21#include <linux/pinctrl/pinctrl.h>
22#include <linux/pinctrl/pinmux.h>
23#include <linux/pinctrl/pinconf.h>
24#include <linux/pinctrl/pinconf-generic.h>
25#include <linux/slab.h>
26#include <linux/gpio.h>
27#include <linux/interrupt.h>
f365be09
BA		 28#include <linux/spinlock.h>
29
30#include "core.h"
31#include "pinconf.h"
32#include "pinctrl-msm.h"
33#include "pinctrl-utils.h"
34
408e3c66
BA		 35#define MAX_NR_GPIO 300
36
f365be09
BA		 37/**
38 * struct msm_pinctrl - state for a pinctrl-msm device
39 * @dev: device handle.
40 * @pctrl: pinctrl handle.
f365be09
BA		 41 * @chip: gpiochip handle.
42 * @irq: parent irq for the TLMM irq_chip.
43 * @lock: Spinlock to protect register resources as well
44 * as msm_pinctrl data structures.
45 * @enabled_irqs: Bitmap of currently enabled irqs.
46 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
47 * detection.
f365be09
BA		 48 * @soc; Reference to soc_data of platform specific data.
49 * @regs: Base address for the TLMM register map.
50 */
51struct msm_pinctrl {
52 struct device *dev;
53 struct pinctrl_dev *pctrl;
f365be09 54 struct gpio_chip chip;
f393e489 55 int irq;
f365be09
BA		 56
57 spinlock_t lock;
58
408e3c66
BA		 59 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
60 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
f365be09
BA		 61
62 const struct msm_pinctrl_soc_data *soc;
63 void __iomem *regs;
64};
65
cdcb0ab6
LW		 66static inline struct msm_pinctrl *to_msm_pinctrl(struct gpio_chip *gc)
67{
68 return container_of(gc, struct msm_pinctrl, chip);
69}
70
f365be09
BA		 71static int msm_get_groups_count(struct pinctrl_dev *pctldev)
72{
73 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
74
75 return pctrl->soc->ngroups;
76}
77
78static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
79 unsigned group)
80{
81 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
82
83 return pctrl->soc->groups[group].name;
84}
85
86static int msm_get_group_pins(struct pinctrl_dev *pctldev,
87 unsigned group,
88 const unsigned **pins,
89 unsigned *num_pins)
90{
91 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
92
93 *pins = pctrl->soc->groups[group].pins;
94 *num_pins = pctrl->soc->groups[group].npins;
95 return 0;
96}
97
1f2b2398 98static const struct pinctrl_ops msm_pinctrl_ops = {
f365be09
BA		 99 .get_groups_count = msm_get_groups_count,
100 .get_group_name = msm_get_group_name,
101 .get_group_pins = msm_get_group_pins,
102 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
103 .dt_free_map = pinctrl_utils_dt_free_map,
104};
105
106static int msm_get_functions_count(struct pinctrl_dev *pctldev)
107{
108 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
109
110 return pctrl->soc->nfunctions;
111}
112
113static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
114 unsigned function)
115{
116 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
117
118 return pctrl->soc->functions[function].name;
119}
120
121static int msm_get_function_groups(struct pinctrl_dev *pctldev,
122 unsigned function,
123 const char * const **groups,
124 unsigned * const num_groups)
125{
126 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
127
128 *groups = pctrl->soc->functions[function].groups;
129 *num_groups = pctrl->soc->functions[function].ngroups;
130 return 0;
131}
132
133static int msm_pinmux_enable(struct pinctrl_dev *pctldev,
134 unsigned function,
135 unsigned group)
136{
137 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
138 const struct msm_pingroup *g;
139 unsigned long flags;
140 u32 val;
141 int i;
142
143 g = &pctrl->soc->groups[group];
144
145 if (WARN_ON(g->mux_bit < 0))
146 return -EINVAL;
147
3c25381f 148 for (i = 0; i < g->nfuncs; i++) {
f365be09
BA		 149 if (g->funcs[i] == function)
150 break;
151 }
152
3c25381f 153 if (WARN_ON(i == g->nfuncs))
f365be09
BA		 154 return -EINVAL;
155
156 spin_lock_irqsave(&pctrl->lock, flags);
157
158 val = readl(pctrl->regs + g->ctl_reg);
159 val &= ~(0x7 << g->mux_bit);
160 val |= i << g->mux_bit;
161 writel(val, pctrl->regs + g->ctl_reg);
162
163 spin_unlock_irqrestore(&pctrl->lock, flags);
164
165 return 0;
166}
167
168static void msm_pinmux_disable(struct pinctrl_dev *pctldev,
169 unsigned function,
170 unsigned group)
171{
172 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
173 const struct msm_pingroup *g;
174 unsigned long flags;
175 u32 val;
176
177 g = &pctrl->soc->groups[group];
178
179 if (WARN_ON(g->mux_bit < 0))
180 return;
181
182 spin_lock_irqsave(&pctrl->lock, flags);
183
184 /* Clear the mux bits to select gpio mode */
185 val = readl(pctrl->regs + g->ctl_reg);
186 val &= ~(0x7 << g->mux_bit);
187 writel(val, pctrl->regs + g->ctl_reg);
188
189 spin_unlock_irqrestore(&pctrl->lock, flags);
190}
191
1f2b2398 192static const struct pinmux_ops msm_pinmux_ops = {
f365be09
BA		 193 .get_functions_count = msm_get_functions_count,
194 .get_function_name = msm_get_function_name,
195 .get_function_groups = msm_get_function_groups,
196 .enable = msm_pinmux_enable,
197 .disable = msm_pinmux_disable,
198};
199
200static int msm_config_reg(struct msm_pinctrl *pctrl,
201 const struct msm_pingroup *g,
202 unsigned param,
f365be09
BA		 203 unsigned *mask,
204 unsigned *bit)
205{
206 switch (param) {
207 case PIN_CONFIG_BIAS_DISABLE:
f365be09 208 case PIN_CONFIG_BIAS_PULL_DOWN:
f365be09 209 case PIN_CONFIG_BIAS_PULL_UP:
f365be09
BA		 210 *bit = g->pull_bit;
211 *mask = 3;
212 break;
213 case PIN_CONFIG_DRIVE_STRENGTH:
f365be09
BA		 214 *bit = g->drv_bit;
215 *mask = 7;
216 break;
ed118a5f 217 case PIN_CONFIG_OUTPUT:
ed118a5f
BA		 218 *bit = g->oe_bit;
219 *mask = 1;
220 break;
f365be09
BA		 221 default:
222 dev_err(pctrl->dev, "Invalid config param %04x\n", param);
223 return -ENOTSUPP;
224 }
225
f365be09
BA		 226 return 0;
227}
228
229static int msm_config_get(struct pinctrl_dev *pctldev,
230 unsigned int pin,
231 unsigned long *config)
232{
233 dev_err(pctldev->dev, "pin_config_set op not supported\n");
234 return -ENOTSUPP;
235}
236
237static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
238 unsigned long *configs, unsigned num_configs)
239{
240 dev_err(pctldev->dev, "pin_config_set op not supported\n");
241 return -ENOTSUPP;
242}
243
244#define MSM_NO_PULL 0
245#define MSM_PULL_DOWN 1
246#define MSM_PULL_UP 3
247
7cc34e2e
SB		 248static unsigned msm_regval_to_drive(u32 val)
249{
250 return (val + 1) * 2;
251}
f365be09
BA		 252
253static int msm_config_group_get(struct pinctrl_dev *pctldev,
254 unsigned int group,
255 unsigned long *config)
256{
257 const struct msm_pingroup *g;
258 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
259 unsigned param = pinconf_to_config_param(*config);
260 unsigned mask;
261 unsigned arg;
262 unsigned bit;
f365be09
BA		 263 int ret;
264 u32 val;
265
266 g = &pctrl->soc->groups[group];
267
051a58b4 268 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
f365be09
BA		 269 if (ret < 0)
270 return ret;
271
051a58b4 272 val = readl(pctrl->regs + g->ctl_reg);
f365be09
BA		 273 arg = (val >> bit) & mask;
274
275 /* Convert register value to pinconf value */
276 switch (param) {
277 case PIN_CONFIG_BIAS_DISABLE:
278 arg = arg == MSM_NO_PULL;
279 break;
280 case PIN_CONFIG_BIAS_PULL_DOWN:
281 arg = arg == MSM_PULL_DOWN;
282 break;
283 case PIN_CONFIG_BIAS_PULL_UP:
284 arg = arg == MSM_PULL_UP;
285 break;
286 case PIN_CONFIG_DRIVE_STRENGTH:
7cc34e2e 287 arg = msm_regval_to_drive(arg);
f365be09 288 break;
ed118a5f
BA		 289 case PIN_CONFIG_OUTPUT:
290 /* Pin is not output */
291 if (!arg)
292 return -EINVAL;
293
294 val = readl(pctrl->regs + g->io_reg);
295 arg = !!(val & BIT(g->in_bit));
296 break;
f365be09
BA		 297 default:
298 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
299 param);
300 return -EINVAL;
301 }
302
303 *config = pinconf_to_config_packed(param, arg);
304
305 return 0;
306}
307
308static int msm_config_group_set(struct pinctrl_dev *pctldev,
309 unsigned group,
310 unsigned long *configs,
311 unsigned num_configs)
312{
313 const struct msm_pingroup *g;
314 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
315 unsigned long flags;
316 unsigned param;
317 unsigned mask;
318 unsigned arg;
319 unsigned bit;
f365be09
BA		 320 int ret;
321 u32 val;
322 int i;
323
324 g = &pctrl->soc->groups[group];
325
326 for (i = 0; i < num_configs; i++) {
327 param = pinconf_to_config_param(configs[i]);
328 arg = pinconf_to_config_argument(configs[i]);
329
051a58b4 330 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
f365be09
BA		 331 if (ret < 0)
332 return ret;
333
334 /* Convert pinconf values to register values */
335 switch (param) {
336 case PIN_CONFIG_BIAS_DISABLE:
337 arg = MSM_NO_PULL;
338 break;
339 case PIN_CONFIG_BIAS_PULL_DOWN:
340 arg = MSM_PULL_DOWN;
341 break;
342 case PIN_CONFIG_BIAS_PULL_UP:
343 arg = MSM_PULL_UP;
344 break;
345 case PIN_CONFIG_DRIVE_STRENGTH:
346 /* Check for invalid values */
7cc34e2e 347 if (arg > 16 || arg < 2 || (arg % 2) != 0)
f365be09
BA		 348 arg = -1;
349 else
7cc34e2e 350 arg = (arg / 2) - 1;
f365be09 351 break;
ed118a5f
BA		 352 case PIN_CONFIG_OUTPUT:
353 /* set output value */
354 spin_lock_irqsave(&pctrl->lock, flags);
355 val = readl(pctrl->regs + g->io_reg);
356 if (arg)
357 val |= BIT(g->out_bit);
358 else
359 val &= ~BIT(g->out_bit);
360 writel(val, pctrl->regs + g->io_reg);
361 spin_unlock_irqrestore(&pctrl->lock, flags);
362
363 /* enable output */
364 arg = 1;
365 break;
f365be09
BA		 366 default:
367 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
368 param);
369 return -EINVAL;
370 }
371
372 /* Range-check user-supplied value */
373 if (arg & ~mask) {
374 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
375 return -EINVAL;
376 }
377
378 spin_lock_irqsave(&pctrl->lock, flags);
051a58b4 379 val = readl(pctrl->regs + g->ctl_reg);
f365be09
BA		 380 val &= ~(mask << bit);
381 val |= arg << bit;
051a58b4 382 writel(val, pctrl->regs + g->ctl_reg);
f365be09
BA		 383 spin_unlock_irqrestore(&pctrl->lock, flags);
384 }
385
386 return 0;
387}
388
1f2b2398 389static const struct pinconf_ops msm_pinconf_ops = {
f365be09
BA		 390 .pin_config_get = msm_config_get,
391 .pin_config_set = msm_config_set,
392 .pin_config_group_get = msm_config_group_get,
393 .pin_config_group_set = msm_config_group_set,
394};
395
396static struct pinctrl_desc msm_pinctrl_desc = {
397 .pctlops = &msm_pinctrl_ops,
398 .pmxops = &msm_pinmux_ops,
399 .confops = &msm_pinconf_ops,
400 .owner = THIS_MODULE,
401};
402
403static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
404{
405 const struct msm_pingroup *g;
406 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
407 unsigned long flags;
408 u32 val;
409
f365be09 410 g = &pctrl->soc->groups[offset];
f365be09
BA		 411
412 spin_lock_irqsave(&pctrl->lock, flags);
413
414 val = readl(pctrl->regs + g->ctl_reg);
415 val &= ~BIT(g->oe_bit);
416 writel(val, pctrl->regs + g->ctl_reg);
417
418 spin_unlock_irqrestore(&pctrl->lock, flags);
419
420 return 0;
421}
422
423static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
424{
425 const struct msm_pingroup *g;
426 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
427 unsigned long flags;
428 u32 val;
429
f365be09 430 g = &pctrl->soc->groups[offset];
f365be09
BA		 431
432 spin_lock_irqsave(&pctrl->lock, flags);
433
e476e77f
AL		 434 val = readl(pctrl->regs + g->io_reg);
435 if (value)
436 val |= BIT(g->out_bit);
437 else
438 val &= ~BIT(g->out_bit);
439 writel(val, pctrl->regs + g->io_reg);
f365be09
BA		 440
441 val = readl(pctrl->regs + g->ctl_reg);
442 val |= BIT(g->oe_bit);
443 writel(val, pctrl->regs + g->ctl_reg);
444
445 spin_unlock_irqrestore(&pctrl->lock, flags);
446
447 return 0;
448}
449
450static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
451{
452 const struct msm_pingroup *g;
453 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
454 u32 val;
455
f365be09
BA		 456 g = &pctrl->soc->groups[offset];
457
458 val = readl(pctrl->regs + g->io_reg);
459 return !!(val & BIT(g->in_bit));
460}
461
462static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
463{
464 const struct msm_pingroup *g;
465 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
466 unsigned long flags;
467 u32 val;
468
f365be09
BA		 469 g = &pctrl->soc->groups[offset];
470
471 spin_lock_irqsave(&pctrl->lock, flags);
472
473 val = readl(pctrl->regs + g->io_reg);
e476e77f
AL		 474 if (value)
475 val |= BIT(g->out_bit);
476 else
477 val &= ~BIT(g->out_bit);
f365be09
BA		 478 writel(val, pctrl->regs + g->io_reg);
479
480 spin_unlock_irqrestore(&pctrl->lock, flags);
481}
482
f365be09
BA		 483static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
484{
485 int gpio = chip->base + offset;
486 return pinctrl_request_gpio(gpio);
487}
488
489static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
490{
491 int gpio = chip->base + offset;
492 return pinctrl_free_gpio(gpio);
493}
494
495#ifdef CONFIG_DEBUG_FS
496#include <linux/seq_file.h>
497
498static void msm_gpio_dbg_show_one(struct seq_file *s,
499 struct pinctrl_dev *pctldev,
500 struct gpio_chip *chip,
501 unsigned offset,
502 unsigned gpio)
503{
504 const struct msm_pingroup *g;
505 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
506 unsigned func;
507 int is_out;
508 int drive;
509 int pull;
510 u32 ctl_reg;
511
1f2b2398 512 static const char * const pulls[] = {
f365be09
BA		 513 "no pull",
514 "pull down",
515 "keeper",
516 "pull up"
517 };
518
519 g = &pctrl->soc->groups[offset];
520 ctl_reg = readl(pctrl->regs + g->ctl_reg);
521
522 is_out = !!(ctl_reg & BIT(g->oe_bit));
523 func = (ctl_reg >> g->mux_bit) & 7;
524 drive = (ctl_reg >> g->drv_bit) & 7;
525 pull = (ctl_reg >> g->pull_bit) & 3;
526
527 seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
7cc34e2e 528 seq_printf(s, " %dmA", msm_regval_to_drive(drive));
f365be09
BA		 529 seq_printf(s, " %s", pulls[pull]);
530}
531
532static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
533{
534 unsigned gpio = chip->base;
535 unsigned i;
536
537 for (i = 0; i < chip->ngpio; i++, gpio++) {
538 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
1f2b2398 539 seq_puts(s, "\n");
f365be09
BA		 540 }
541}
542
543#else
544#define msm_gpio_dbg_show NULL
545#endif
546
547static struct gpio_chip msm_gpio_template = {
548 .direction_input = msm_gpio_direction_input,
549 .direction_output = msm_gpio_direction_output,
550 .get = msm_gpio_get,
551 .set = msm_gpio_set,
f365be09
BA		 552 .request = msm_gpio_request,
553 .free = msm_gpio_free,
554 .dbg_show = msm_gpio_dbg_show,
555};
556
557/* For dual-edge interrupts in software, since some hardware has no
558 * such support:
559 *
560 * At appropriate moments, this function may be called to flip the polarity
561 * settings of both-edge irq lines to try and catch the next edge.
562 *
563 * The attempt is considered successful if:
564 * - the status bit goes high, indicating that an edge was caught, or
565 * - the input value of the gpio doesn't change during the attempt.
566 * If the value changes twice during the process, that would cause the first
567 * test to fail but would force the second, as two opposite
568 * transitions would cause a detection no matter the polarity setting.
569 *
570 * The do-loop tries to sledge-hammer closed the timing hole between
571 * the initial value-read and the polarity-write - if the line value changes
572 * during that window, an interrupt is lost, the new polarity setting is
573 * incorrect, and the first success test will fail, causing a retry.
574 *
575 * Algorithm comes from Google's msmgpio driver.
576 */
577static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
578 const struct msm_pingroup *g,
579 struct irq_data *d)
580{
581 int loop_limit = 100;
582 unsigned val, val2, intstat;
583 unsigned pol;
584
585 do {
586 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
587
588 pol = readl(pctrl->regs + g->intr_cfg_reg);
589 pol ^= BIT(g->intr_polarity_bit);
590 writel(pol, pctrl->regs + g->intr_cfg_reg);
591
592 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
593 intstat = readl(pctrl->regs + g->intr_status_reg);
594 if (intstat || (val == val2))
595 return;
596 } while (loop_limit-- > 0);
597 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
598 val, val2);
599}
600
601static void msm_gpio_irq_mask(struct irq_data *d)
602{
cdcb0ab6
LW		 603 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
604 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
f365be09 605 const struct msm_pingroup *g;
f365be09
BA		 606 unsigned long flags;
607 u32 val;
608
f365be09
BA		 609 g = &pctrl->soc->groups[d->hwirq];
610
611 spin_lock_irqsave(&pctrl->lock, flags);
612
613 val = readl(pctrl->regs + g->intr_cfg_reg);
614 val &= ~BIT(g->intr_enable_bit);
615 writel(val, pctrl->regs + g->intr_cfg_reg);
616
617 clear_bit(d->hwirq, pctrl->enabled_irqs);
618
619 spin_unlock_irqrestore(&pctrl->lock, flags);
620}
621
622static void msm_gpio_irq_unmask(struct irq_data *d)
623{
cdcb0ab6
LW		 624 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
625 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
f365be09 626 const struct msm_pingroup *g;
f365be09
BA		 627 unsigned long flags;
628 u32 val;
629
f365be09
BA		 630 g = &pctrl->soc->groups[d->hwirq];
631
632 spin_lock_irqsave(&pctrl->lock, flags);
633
634 val = readl(pctrl->regs + g->intr_status_reg);
635 val &= ~BIT(g->intr_status_bit);
636 writel(val, pctrl->regs + g->intr_status_reg);
637
638 val = readl(pctrl->regs + g->intr_cfg_reg);
639 val |= BIT(g->intr_enable_bit);
640 writel(val, pctrl->regs + g->intr_cfg_reg);
641
642 set_bit(d->hwirq, pctrl->enabled_irqs);
643
644 spin_unlock_irqrestore(&pctrl->lock, flags);
645}
646
647static void msm_gpio_irq_ack(struct irq_data *d)
648{
cdcb0ab6
LW		 649 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
650 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
f365be09 651 const struct msm_pingroup *g;
f365be09
BA		 652 unsigned long flags;
653 u32 val;
654
f365be09
BA		 655 g = &pctrl->soc->groups[d->hwirq];
656
657 spin_lock_irqsave(&pctrl->lock, flags);
658
659 val = readl(pctrl->regs + g->intr_status_reg);
48f15e94
BA		 660 if (g->intr_ack_high)
661 val |= BIT(g->intr_status_bit);
662 else
663 val &= ~BIT(g->intr_status_bit);
f365be09
BA		 664 writel(val, pctrl->regs + g->intr_status_reg);
665
666 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
667 msm_gpio_update_dual_edge_pos(pctrl, g, d);
668
669 spin_unlock_irqrestore(&pctrl->lock, flags);
670}
671
672#define INTR_TARGET_PROC_APPS 4
673
674static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
675{
cdcb0ab6
LW		 676 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
677 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
f365be09 678 const struct msm_pingroup *g;
f365be09
BA		 679 unsigned long flags;
680 u32 val;
681
f365be09
BA		 682 g = &pctrl->soc->groups[d->hwirq];
683
684 spin_lock_irqsave(&pctrl->lock, flags);
685
686 /*
687 * For hw without possibility of detecting both edges
688 */
689 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
690 set_bit(d->hwirq, pctrl->dual_edge_irqs);
691 else
692 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
693
694 /* Route interrupts to application cpu */
695 val = readl(pctrl->regs + g->intr_target_reg);
696 val &= ~(7 << g->intr_target_bit);
697 val |= INTR_TARGET_PROC_APPS << g->intr_target_bit;
698 writel(val, pctrl->regs + g->intr_target_reg);
699
700 /* Update configuration for gpio.
701 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
702 * internal circuitry of TLMM, toggling the RAW_STATUS
703 * could cause the INTR_STATUS to be set for EDGE interrupts.
704 */
705 val = readl(pctrl->regs + g->intr_cfg_reg);
706 val |= BIT(g->intr_raw_status_bit);
707 if (g->intr_detection_width == 2) {
708 val &= ~(3 << g->intr_detection_bit);
709 val &= ~(1 << g->intr_polarity_bit);
710 switch (type) {
711 case IRQ_TYPE_EDGE_RISING:
712 val |= 1 << g->intr_detection_bit;
713 val |= BIT(g->intr_polarity_bit);
714 break;
715 case IRQ_TYPE_EDGE_FALLING:
716 val |= 2 << g->intr_detection_bit;
717 val |= BIT(g->intr_polarity_bit);
718 break;
719 case IRQ_TYPE_EDGE_BOTH:
720 val |= 3 << g->intr_detection_bit;
721 val |= BIT(g->intr_polarity_bit);
722 break;
723 case IRQ_TYPE_LEVEL_LOW:
724 break;
725 case IRQ_TYPE_LEVEL_HIGH:
726 val |= BIT(g->intr_polarity_bit);
727 break;
728 }
729 } else if (g->intr_detection_width == 1) {
730 val &= ~(1 << g->intr_detection_bit);
731 val &= ~(1 << g->intr_polarity_bit);
732 switch (type) {
733 case IRQ_TYPE_EDGE_RISING:
734 val |= BIT(g->intr_detection_bit);
735 val |= BIT(g->intr_polarity_bit);
736 break;
737 case IRQ_TYPE_EDGE_FALLING:
738 val |= BIT(g->intr_detection_bit);
739 break;
740 case IRQ_TYPE_EDGE_BOTH:
741 val |= BIT(g->intr_detection_bit);
48f15e94 742 val |= BIT(g->intr_polarity_bit);
f365be09
BA		 743 break;
744 case IRQ_TYPE_LEVEL_LOW:
745 break;
746 case IRQ_TYPE_LEVEL_HIGH:
747 val |= BIT(g->intr_polarity_bit);
748 break;
749 }
750 } else {
751 BUG();
752 }
753 writel(val, pctrl->regs + g->intr_cfg_reg);
754
755 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
756 msm_gpio_update_dual_edge_pos(pctrl, g, d);
757
758 spin_unlock_irqrestore(&pctrl->lock, flags);
759
760 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
761 __irq_set_handler_locked(d->irq, handle_level_irq);
762 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
763 __irq_set_handler_locked(d->irq, handle_edge_irq);
764
765 return 0;
766}
767
768static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
769{
cdcb0ab6
LW		 770 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
771 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
f365be09 772 unsigned long flags;
f365be09 773
f365be09
BA		 774 spin_lock_irqsave(&pctrl->lock, flags);
775
6aced33f 776 irq_set_irq_wake(pctrl->irq, on);
f365be09
BA		 777
778 spin_unlock_irqrestore(&pctrl->lock, flags);
779
780 return 0;
781}
782
f365be09
BA		 783static struct irq_chip msm_gpio_irq_chip = {
784 .name = "msmgpio",
785 .irq_mask = msm_gpio_irq_mask,
786 .irq_unmask = msm_gpio_irq_unmask,
787 .irq_ack = msm_gpio_irq_ack,
788 .irq_set_type = msm_gpio_irq_set_type,
789 .irq_set_wake = msm_gpio_irq_set_wake,
f365be09
BA		 790};
791
792static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
793{
cdcb0ab6 794 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
f365be09 795 const struct msm_pingroup *g;
cdcb0ab6 796 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
f365be09
BA		 797 struct irq_chip *chip = irq_get_chip(irq);
798 int irq_pin;
799 int handled = 0;
800 u32 val;
801 int i;
802
803 chained_irq_enter(chip, desc);
804
805 /*
1f2b2398 806 * Each pin has it's own IRQ status register, so use
f365be09
BA		 807 * enabled_irq bitmap to limit the number of reads.
808 */
809 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
810 g = &pctrl->soc->groups[i];
811 val = readl(pctrl->regs + g->intr_status_reg);
812 if (val & BIT(g->intr_status_bit)) {
cdcb0ab6 813 irq_pin = irq_find_mapping(gc->irqdomain, i);
f365be09
BA		 814 generic_handle_irq(irq_pin);
815 handled++;
816 }
817 }
818
1f2b2398 819 /* No interrupts were flagged */
f365be09
BA		 820 if (handled == 0)
821 handle_bad_irq(irq, desc);
822
823 chained_irq_exit(chip, desc);
824}
825
826static int msm_gpio_init(struct msm_pinctrl *pctrl)
827{
828 struct gpio_chip *chip;
f365be09 829 int ret;
dcd278b8
SB		 830 unsigned ngpio = pctrl->soc->ngpios;
831
832 if (WARN_ON(ngpio > MAX_NR_GPIO))
833 return -EINVAL;
f365be09
BA		 834
835 chip = &pctrl->chip;
836 chip->base = 0;
dcd278b8 837 chip->ngpio = ngpio;
f365be09
BA		 838 chip->label = dev_name(pctrl->dev);
839 chip->dev = pctrl->dev;
840 chip->owner = THIS_MODULE;
841 chip->of_node = pctrl->dev->of_node;
842
f365be09
BA		 843 ret = gpiochip_add(&pctrl->chip);
844 if (ret) {
845 dev_err(pctrl->dev, "Failed register gpiochip\n");
846 return ret;
847 }
848
849 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
850 if (ret) {
851 dev_err(pctrl->dev, "Failed to add pin range\n");
852 return ret;
853 }
854
cdcb0ab6
LW		 855 ret = gpiochip_irqchip_add(chip,
856 &msm_gpio_irq_chip,
857 0,
858 handle_edge_irq,
859 IRQ_TYPE_NONE);
860 if (ret) {
861 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
f365be09
BA		 862 return -ENOSYS;
863 }
864
cdcb0ab6
LW		 865 gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq,
866 msm_gpio_irq_handler);
f365be09
BA		 867
868 return 0;
869}
870
871int msm_pinctrl_probe(struct platform_device *pdev,
872 const struct msm_pinctrl_soc_data *soc_data)
873{
874 struct msm_pinctrl *pctrl;
875 struct resource *res;
876 int ret;
877
878 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
879 if (!pctrl) {
880 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n");
881 return -ENOMEM;
882 }
883 pctrl->dev = &pdev->dev;
884 pctrl->soc = soc_data;
885 pctrl->chip = msm_gpio_template;
886
887 spin_lock_init(&pctrl->lock);
888
889 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
890 pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
891 if (IS_ERR(pctrl->regs))
892 return PTR_ERR(pctrl->regs);
893
f393e489 894 pctrl->irq = platform_get_irq(pdev, 0);
f365be09
BA		 895 if (pctrl->irq < 0) {
896 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
897 return pctrl->irq;
898 }
899
900 msm_pinctrl_desc.name = dev_name(&pdev->dev);
901 msm_pinctrl_desc.pins = pctrl->soc->pins;
902 msm_pinctrl_desc.npins = pctrl->soc->npins;
903 pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl);
904 if (!pctrl->pctrl) {
905 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
906 return -ENODEV;
907 }
908
909 ret = msm_gpio_init(pctrl);
910 if (ret) {
911 pinctrl_unregister(pctrl->pctrl);
912 return ret;
913 }
914
915 platform_set_drvdata(pdev, pctrl);
916
917 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
918
919 return 0;
920}
921EXPORT_SYMBOL(msm_pinctrl_probe);
922
923int msm_pinctrl_remove(struct platform_device *pdev)
924{
925 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
926 int ret;
927
f393e489
BA		 928 ret = gpiochip_remove(&pctrl->chip);
929 if (ret) {
930 dev_err(&pdev->dev, "Failed to remove gpiochip\n");
931 return ret;
932 }
933
f365be09
BA		 934 pinctrl_unregister(pctrl->pctrl);
935
936 return 0;
937}
938EXPORT_SYMBOL(msm_pinctrl_remove);
939
Linux kernel - Deliverables
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