Commit | Line | Data |
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2ec1d359 AR |
1 | /* |
2 | * Generic GPIO driver for logic cells found in the Nomadik SoC | |
3 | * | |
4 | * Copyright (C) 2008,2009 STMicroelectronics | |
5 | * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> | |
6 | * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> | |
33d78647 | 7 | * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org> |
2ec1d359 AR |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/device.h> | |
3e3c62ca | 17 | #include <linux/platform_device.h> |
2ec1d359 | 18 | #include <linux/io.h> |
af7dc228 RV |
19 | #include <linux/clk.h> |
20 | #include <linux/err.h> | |
2ec1d359 AR |
21 | #include <linux/gpio.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/irq.h> | |
a60b57ed | 25 | #include <linux/irqdomain.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
e98ea774 | 27 | #include <linux/pinctrl/pinctrl.h> |
dbfe8ca2 | 28 | #include <linux/pinctrl/pinmux.h> |
d41af627 | 29 | #include <linux/pinctrl/pinconf.h> |
dbfe8ca2 LW |
30 | /* Since we request GPIOs from ourself */ |
31 | #include <linux/pinctrl/consumer.h> | |
2ec1d359 | 32 | |
adfed159 WD |
33 | #include <asm/mach/irq.h> |
34 | ||
378be066 | 35 | #include <plat/pincfg.h> |
0f332861 | 36 | #include <plat/gpio-nomadik.h> |
2ec1d359 | 37 | |
e98ea774 LW |
38 | #include "pinctrl-nomadik.h" |
39 | ||
2ec1d359 AR |
40 | /* |
41 | * The GPIO module in the Nomadik family of Systems-on-Chip is an | |
42 | * AMBA device, managing 32 pins and alternate functions. The logic block | |
9c66ee6f | 43 | * is currently used in the Nomadik and ux500. |
2ec1d359 AR |
44 | * |
45 | * Symbols in this file are called "nmk_gpio" for "nomadik gpio" | |
46 | */ | |
47 | ||
01727e61 RV |
48 | #define NMK_GPIO_PER_CHIP 32 |
49 | ||
2ec1d359 AR |
50 | struct nmk_gpio_chip { |
51 | struct gpio_chip chip; | |
a60b57ed | 52 | struct irq_domain *domain; |
2ec1d359 | 53 | void __iomem *addr; |
af7dc228 | 54 | struct clk *clk; |
33b744b3 | 55 | unsigned int bank; |
2ec1d359 | 56 | unsigned int parent_irq; |
2c8bb0eb | 57 | int secondary_parent_irq; |
33b744b3 | 58 | u32 (*get_secondary_status)(unsigned int bank); |
01727e61 | 59 | void (*set_ioforce)(bool enable); |
c0fcb8db | 60 | spinlock_t lock; |
33d78647 | 61 | bool sleepmode; |
2ec1d359 AR |
62 | /* Keep track of configured edges */ |
63 | u32 edge_rising; | |
64 | u32 edge_falling; | |
b9df468d RV |
65 | u32 real_wake; |
66 | u32 rwimsc; | |
67 | u32 fwimsc; | |
6c12fe88 RV |
68 | u32 rimsc; |
69 | u32 fimsc; | |
bc6f5cf6 | 70 | u32 pull_up; |
ebc6178d | 71 | u32 lowemi; |
2ec1d359 AR |
72 | }; |
73 | ||
e98ea774 LW |
74 | struct nmk_pinctrl { |
75 | struct device *dev; | |
76 | struct pinctrl_dev *pctl; | |
77 | const struct nmk_pinctrl_soc_data *soc; | |
78 | }; | |
79 | ||
01727e61 RV |
80 | static struct nmk_gpio_chip * |
81 | nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; | |
82 | ||
83 | static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); | |
84 | ||
85 | #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) | |
86 | ||
6f9a974c RV |
87 | static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, |
88 | unsigned offset, int gpio_mode) | |
89 | { | |
90 | u32 bit = 1 << offset; | |
91 | u32 afunc, bfunc; | |
92 | ||
93 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; | |
94 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; | |
95 | if (gpio_mode & NMK_GPIO_ALT_A) | |
96 | afunc |= bit; | |
97 | if (gpio_mode & NMK_GPIO_ALT_B) | |
98 | bfunc |= bit; | |
99 | writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); | |
100 | writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); | |
101 | } | |
102 | ||
81a3c298 RV |
103 | static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, |
104 | unsigned offset, enum nmk_gpio_slpm mode) | |
105 | { | |
106 | u32 bit = 1 << offset; | |
107 | u32 slpm; | |
108 | ||
109 | slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); | |
110 | if (mode == NMK_GPIO_SLPM_NOCHANGE) | |
111 | slpm |= bit; | |
112 | else | |
113 | slpm &= ~bit; | |
114 | writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); | |
115 | } | |
116 | ||
5b327edf RV |
117 | static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, |
118 | unsigned offset, enum nmk_gpio_pull pull) | |
119 | { | |
120 | u32 bit = 1 << offset; | |
121 | u32 pdis; | |
122 | ||
123 | pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); | |
bc6f5cf6 | 124 | if (pull == NMK_GPIO_PULL_NONE) { |
5b327edf | 125 | pdis |= bit; |
bc6f5cf6 RA |
126 | nmk_chip->pull_up &= ~bit; |
127 | } else { | |
5b327edf | 128 | pdis &= ~bit; |
bc6f5cf6 RA |
129 | } |
130 | ||
5b327edf RV |
131 | writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); |
132 | ||
bc6f5cf6 RA |
133 | if (pull == NMK_GPIO_PULL_UP) { |
134 | nmk_chip->pull_up |= bit; | |
5b327edf | 135 | writel(bit, nmk_chip->addr + NMK_GPIO_DATS); |
bc6f5cf6 RA |
136 | } else if (pull == NMK_GPIO_PULL_DOWN) { |
137 | nmk_chip->pull_up &= ~bit; | |
5b327edf | 138 | writel(bit, nmk_chip->addr + NMK_GPIO_DATC); |
bc6f5cf6 | 139 | } |
5b327edf RV |
140 | } |
141 | ||
ebc6178d RV |
142 | static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, |
143 | unsigned offset, bool lowemi) | |
144 | { | |
145 | u32 bit = BIT(offset); | |
146 | bool enabled = nmk_chip->lowemi & bit; | |
147 | ||
148 | if (lowemi == enabled) | |
149 | return; | |
150 | ||
151 | if (lowemi) | |
152 | nmk_chip->lowemi |= bit; | |
153 | else | |
154 | nmk_chip->lowemi &= ~bit; | |
155 | ||
156 | writel_relaxed(nmk_chip->lowemi, | |
157 | nmk_chip->addr + NMK_GPIO_LOWEMI); | |
158 | } | |
159 | ||
378be066 RV |
160 | static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, |
161 | unsigned offset) | |
162 | { | |
163 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); | |
164 | } | |
165 | ||
6720db7c RV |
166 | static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, |
167 | unsigned offset, int val) | |
168 | { | |
169 | if (val) | |
170 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); | |
171 | else | |
172 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); | |
173 | } | |
174 | ||
175 | static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, | |
176 | unsigned offset, int val) | |
177 | { | |
178 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); | |
179 | __nmk_gpio_set_output(nmk_chip, offset, val); | |
180 | } | |
181 | ||
01727e61 RV |
182 | static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, |
183 | unsigned offset, int gpio_mode, | |
184 | bool glitch) | |
185 | { | |
6c12fe88 RV |
186 | u32 rwimsc = nmk_chip->rwimsc; |
187 | u32 fwimsc = nmk_chip->fwimsc; | |
01727e61 RV |
188 | |
189 | if (glitch && nmk_chip->set_ioforce) { | |
190 | u32 bit = BIT(offset); | |
191 | ||
01727e61 RV |
192 | /* Prevent spurious wakeups */ |
193 | writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
194 | writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
195 | ||
196 | nmk_chip->set_ioforce(true); | |
197 | } | |
198 | ||
199 | __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); | |
200 | ||
201 | if (glitch && nmk_chip->set_ioforce) { | |
202 | nmk_chip->set_ioforce(false); | |
203 | ||
204 | writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
205 | writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
206 | } | |
207 | } | |
208 | ||
6c42ad1c RV |
209 | static void |
210 | nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) | |
211 | { | |
212 | u32 falling = nmk_chip->fimsc & BIT(offset); | |
213 | u32 rising = nmk_chip->rimsc & BIT(offset); | |
214 | int gpio = nmk_chip->chip.base + offset; | |
215 | int irq = NOMADIK_GPIO_TO_IRQ(gpio); | |
216 | struct irq_data *d = irq_get_irq_data(irq); | |
217 | ||
218 | if (!rising && !falling) | |
219 | return; | |
220 | ||
221 | if (!d || !irqd_irq_disabled(d)) | |
222 | return; | |
223 | ||
224 | if (rising) { | |
225 | nmk_chip->rimsc &= ~BIT(offset); | |
226 | writel_relaxed(nmk_chip->rimsc, | |
227 | nmk_chip->addr + NMK_GPIO_RIMSC); | |
228 | } | |
229 | ||
230 | if (falling) { | |
231 | nmk_chip->fimsc &= ~BIT(offset); | |
232 | writel_relaxed(nmk_chip->fimsc, | |
233 | nmk_chip->addr + NMK_GPIO_FIMSC); | |
234 | } | |
235 | ||
236 | dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); | |
237 | } | |
238 | ||
378be066 | 239 | static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, |
01727e61 | 240 | pin_cfg_t cfg, bool sleep, unsigned int *slpmregs) |
378be066 RV |
241 | { |
242 | static const char *afnames[] = { | |
243 | [NMK_GPIO_ALT_GPIO] = "GPIO", | |
244 | [NMK_GPIO_ALT_A] = "A", | |
245 | [NMK_GPIO_ALT_B] = "B", | |
246 | [NMK_GPIO_ALT_C] = "C" | |
247 | }; | |
248 | static const char *pullnames[] = { | |
249 | [NMK_GPIO_PULL_NONE] = "none", | |
250 | [NMK_GPIO_PULL_UP] = "up", | |
251 | [NMK_GPIO_PULL_DOWN] = "down", | |
252 | [3] /* illegal */ = "??" | |
253 | }; | |
254 | static const char *slpmnames[] = { | |
7e3f7e59 RV |
255 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", |
256 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
378be066 RV |
257 | }; |
258 | ||
259 | int pin = PIN_NUM(cfg); | |
260 | int pull = PIN_PULL(cfg); | |
261 | int af = PIN_ALT(cfg); | |
262 | int slpm = PIN_SLPM(cfg); | |
6720db7c RV |
263 | int output = PIN_DIR(cfg); |
264 | int val = PIN_VAL(cfg); | |
01727e61 | 265 | bool glitch = af == NMK_GPIO_ALT_C; |
378be066 | 266 | |
dacdc96c RV |
267 | dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n", |
268 | pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm], | |
6720db7c RV |
269 | output ? "output " : "input", |
270 | output ? (val ? "high" : "low") : ""); | |
271 | ||
dacdc96c RV |
272 | if (sleep) { |
273 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
274 | int slpm_output = PIN_SLPM_DIR(cfg); | |
275 | int slpm_val = PIN_SLPM_VAL(cfg); | |
276 | ||
3546d15c RV |
277 | af = NMK_GPIO_ALT_GPIO; |
278 | ||
dacdc96c RV |
279 | /* |
280 | * The SLPM_* values are normal values + 1 to allow zero to | |
281 | * mean "same as normal". | |
282 | */ | |
283 | if (slpm_pull) | |
284 | pull = slpm_pull - 1; | |
285 | if (slpm_output) | |
286 | output = slpm_output - 1; | |
287 | if (slpm_val) | |
288 | val = slpm_val - 1; | |
289 | ||
290 | dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", | |
291 | pin, | |
292 | slpm_pull ? pullnames[pull] : "same", | |
293 | slpm_output ? (output ? "output" : "input") : "same", | |
294 | slpm_val ? (val ? "high" : "low") : "same"); | |
295 | } | |
296 | ||
6720db7c RV |
297 | if (output) |
298 | __nmk_gpio_make_output(nmk_chip, offset, val); | |
299 | else { | |
300 | __nmk_gpio_make_input(nmk_chip, offset); | |
301 | __nmk_gpio_set_pull(nmk_chip, offset, pull); | |
302 | } | |
378be066 | 303 | |
ebc6178d RV |
304 | __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg)); |
305 | ||
6c42ad1c RV |
306 | /* |
307 | * If the pin is switching to altfunc, and there was an interrupt | |
308 | * installed on it which has been lazy disabled, actually mask the | |
309 | * interrupt to prevent spurious interrupts that would occur while the | |
310 | * pin is under control of the peripheral. Only SKE does this. | |
311 | */ | |
312 | if (af != NMK_GPIO_ALT_GPIO) | |
313 | nmk_gpio_disable_lazy_irq(nmk_chip, offset); | |
314 | ||
01727e61 RV |
315 | /* |
316 | * If we've backed up the SLPM registers (glitch workaround), modify | |
317 | * the backups since they will be restored. | |
318 | */ | |
319 | if (slpmregs) { | |
320 | if (slpm == NMK_GPIO_SLPM_NOCHANGE) | |
321 | slpmregs[nmk_chip->bank] |= BIT(offset); | |
322 | else | |
323 | slpmregs[nmk_chip->bank] &= ~BIT(offset); | |
324 | } else | |
325 | __nmk_gpio_set_slpm(nmk_chip, offset, slpm); | |
326 | ||
327 | __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch); | |
328 | } | |
329 | ||
330 | /* | |
331 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
332 | * - Save SLPM registers | |
333 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
334 | * - Configure the GPIO registers for the IOs that are being switched | |
335 | * - Set IOFORCE=1 | |
336 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
337 | * - Set IOFORCE=0 | |
338 | * - Restore SLPM registers | |
339 | * - Any spurious wake up event during switch sequence to be ignored and | |
340 | * cleared | |
341 | */ | |
342 | static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) | |
343 | { | |
344 | int i; | |
345 | ||
346 | for (i = 0; i < NUM_BANKS; i++) { | |
347 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
348 | unsigned int temp = slpm[i]; | |
349 | ||
350 | if (!chip) | |
351 | break; | |
352 | ||
3c0227d2 RV |
353 | clk_enable(chip->clk); |
354 | ||
01727e61 RV |
355 | slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); |
356 | writel(temp, chip->addr + NMK_GPIO_SLPC); | |
357 | } | |
358 | } | |
359 | ||
360 | static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) | |
361 | { | |
362 | int i; | |
363 | ||
364 | for (i = 0; i < NUM_BANKS; i++) { | |
365 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
366 | ||
367 | if (!chip) | |
368 | break; | |
369 | ||
370 | writel(slpm[i], chip->addr + NMK_GPIO_SLPC); | |
3c0227d2 RV |
371 | |
372 | clk_disable(chip->clk); | |
01727e61 RV |
373 | } |
374 | } | |
375 | ||
376 | static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) | |
377 | { | |
378 | static unsigned int slpm[NUM_BANKS]; | |
379 | unsigned long flags; | |
380 | bool glitch = false; | |
381 | int ret = 0; | |
382 | int i; | |
383 | ||
384 | for (i = 0; i < num; i++) { | |
385 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) { | |
386 | glitch = true; | |
387 | break; | |
388 | } | |
389 | } | |
390 | ||
391 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | |
392 | ||
393 | if (glitch) { | |
394 | memset(slpm, 0xff, sizeof(slpm)); | |
395 | ||
396 | for (i = 0; i < num; i++) { | |
397 | int pin = PIN_NUM(cfgs[i]); | |
398 | int offset = pin % NMK_GPIO_PER_CHIP; | |
399 | ||
400 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) | |
401 | slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset); | |
402 | } | |
403 | ||
404 | nmk_gpio_glitch_slpm_init(slpm); | |
405 | } | |
406 | ||
407 | for (i = 0; i < num; i++) { | |
408 | struct nmk_gpio_chip *nmk_chip; | |
409 | int pin = PIN_NUM(cfgs[i]); | |
410 | ||
a60b57ed | 411 | nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP]; |
01727e61 RV |
412 | if (!nmk_chip) { |
413 | ret = -EINVAL; | |
414 | break; | |
415 | } | |
416 | ||
3c0227d2 | 417 | clk_enable(nmk_chip->clk); |
01727e61 | 418 | spin_lock(&nmk_chip->lock); |
a60b57ed | 419 | __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP, |
01727e61 RV |
420 | cfgs[i], sleep, glitch ? slpm : NULL); |
421 | spin_unlock(&nmk_chip->lock); | |
3c0227d2 | 422 | clk_disable(nmk_chip->clk); |
01727e61 RV |
423 | } |
424 | ||
425 | if (glitch) | |
426 | nmk_gpio_glitch_slpm_restore(slpm); | |
427 | ||
428 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
429 | ||
430 | return ret; | |
378be066 RV |
431 | } |
432 | ||
433 | /** | |
434 | * nmk_config_pin - configure a pin's mux attributes | |
435 | * @cfg: pin confguration | |
436 | * | |
437 | * Configures a pin's mode (alternate function or GPIO), its pull up status, | |
438 | * and its sleep mode based on the specified configuration. The @cfg is | |
439 | * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These | |
440 | * are constructed using, and can be further enhanced with, the macros in | |
441 | * plat/pincfg.h. | |
442 | * | |
443 | * If a pin's mode is set to GPIO, it is configured as an input to avoid | |
444 | * side-effects. The gpio can be manipulated later using standard GPIO API | |
445 | * calls. | |
446 | */ | |
dacdc96c | 447 | int nmk_config_pin(pin_cfg_t cfg, bool sleep) |
378be066 | 448 | { |
01727e61 | 449 | return __nmk_config_pins(&cfg, 1, sleep); |
378be066 RV |
450 | } |
451 | EXPORT_SYMBOL(nmk_config_pin); | |
452 | ||
453 | /** | |
454 | * nmk_config_pins - configure several pins at once | |
455 | * @cfgs: array of pin configurations | |
456 | * @num: number of elments in the array | |
457 | * | |
458 | * Configures several pins using nmk_config_pin(). Refer to that function for | |
459 | * further information. | |
460 | */ | |
461 | int nmk_config_pins(pin_cfg_t *cfgs, int num) | |
462 | { | |
01727e61 | 463 | return __nmk_config_pins(cfgs, num, false); |
378be066 RV |
464 | } |
465 | EXPORT_SYMBOL(nmk_config_pins); | |
466 | ||
dacdc96c RV |
467 | int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num) |
468 | { | |
01727e61 | 469 | return __nmk_config_pins(cfgs, num, true); |
dacdc96c RV |
470 | } |
471 | EXPORT_SYMBOL(nmk_config_pins_sleep); | |
472 | ||
81a3c298 RV |
473 | /** |
474 | * nmk_gpio_set_slpm() - configure the sleep mode of a pin | |
475 | * @gpio: pin number | |
476 | * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE, | |
477 | * | |
33d78647 LW |
478 | * This register is actually in the pinmux layer, not the GPIO block itself. |
479 | * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP | |
480 | * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code). | |
481 | * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is | |
482 | * HIGH, overriding the normal setting defined by GPIO_AFSELx registers. | |
483 | * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit), | |
484 | * the GPIOs return to the normal setting defined by GPIO_AFSELx registers. | |
7e3f7e59 | 485 | * |
33d78647 LW |
486 | * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO |
487 | * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is | |
488 | * entered) regardless of the altfunction selected. Also wake-up detection is | |
489 | * ENABLED. | |
490 | * | |
491 | * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains | |
492 | * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS | |
493 | * (for altfunction GPIO) or respective on-chip peripherals (for other | |
494 | * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED. | |
495 | * | |
496 | * Note that enable_irq_wake() will automatically enable wakeup detection. | |
81a3c298 RV |
497 | */ |
498 | int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) | |
499 | { | |
500 | struct nmk_gpio_chip *nmk_chip; | |
501 | unsigned long flags; | |
502 | ||
a60b57ed | 503 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
81a3c298 RV |
504 | if (!nmk_chip) |
505 | return -EINVAL; | |
506 | ||
3c0227d2 | 507 | clk_enable(nmk_chip->clk); |
01727e61 RV |
508 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
509 | spin_lock(&nmk_chip->lock); | |
510 | ||
a60b57ed | 511 | __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode); |
01727e61 RV |
512 | |
513 | spin_unlock(&nmk_chip->lock); | |
514 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 515 | clk_disable(nmk_chip->clk); |
81a3c298 RV |
516 | |
517 | return 0; | |
518 | } | |
519 | ||
5b327edf RV |
520 | /** |
521 | * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio | |
522 | * @gpio: pin number | |
523 | * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE | |
524 | * | |
525 | * Enables/disables pull up/down on a specified pin. This only takes effect if | |
526 | * the pin is configured as an input (either explicitly or by the alternate | |
527 | * function). | |
528 | * | |
529 | * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is | |
530 | * configured as an input. Otherwise, due to the way the controller registers | |
531 | * work, this function will change the value output on the pin. | |
532 | */ | |
533 | int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) | |
534 | { | |
535 | struct nmk_gpio_chip *nmk_chip; | |
536 | unsigned long flags; | |
537 | ||
a60b57ed | 538 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
5b327edf RV |
539 | if (!nmk_chip) |
540 | return -EINVAL; | |
541 | ||
3c0227d2 | 542 | clk_enable(nmk_chip->clk); |
5b327edf | 543 | spin_lock_irqsave(&nmk_chip->lock, flags); |
a60b57ed | 544 | __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull); |
5b327edf | 545 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 546 | clk_disable(nmk_chip->clk); |
5b327edf RV |
547 | |
548 | return 0; | |
549 | } | |
550 | ||
2ec1d359 | 551 | /* Mode functions */ |
9c66ee6f JA |
552 | /** |
553 | * nmk_gpio_set_mode() - set the mux mode of a gpio pin | |
554 | * @gpio: pin number | |
555 | * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A, | |
556 | * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C | |
557 | * | |
558 | * Sets the mode of the specified pin to one of the alternate functions or | |
559 | * plain GPIO. | |
560 | */ | |
2ec1d359 AR |
561 | int nmk_gpio_set_mode(int gpio, int gpio_mode) |
562 | { | |
563 | struct nmk_gpio_chip *nmk_chip; | |
564 | unsigned long flags; | |
2ec1d359 | 565 | |
a60b57ed | 566 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
2ec1d359 AR |
567 | if (!nmk_chip) |
568 | return -EINVAL; | |
569 | ||
3c0227d2 | 570 | clk_enable(nmk_chip->clk); |
2ec1d359 | 571 | spin_lock_irqsave(&nmk_chip->lock, flags); |
a60b57ed | 572 | __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode); |
2ec1d359 | 573 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 574 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
575 | |
576 | return 0; | |
577 | } | |
578 | EXPORT_SYMBOL(nmk_gpio_set_mode); | |
579 | ||
580 | int nmk_gpio_get_mode(int gpio) | |
581 | { | |
582 | struct nmk_gpio_chip *nmk_chip; | |
583 | u32 afunc, bfunc, bit; | |
584 | ||
a60b57ed | 585 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
2ec1d359 AR |
586 | if (!nmk_chip) |
587 | return -EINVAL; | |
588 | ||
a60b57ed | 589 | bit = 1 << (gpio % NMK_GPIO_PER_CHIP); |
2ec1d359 | 590 | |
3c0227d2 RV |
591 | clk_enable(nmk_chip->clk); |
592 | ||
2ec1d359 AR |
593 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; |
594 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; | |
595 | ||
3c0227d2 RV |
596 | clk_disable(nmk_chip->clk); |
597 | ||
2ec1d359 AR |
598 | return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); |
599 | } | |
600 | EXPORT_SYMBOL(nmk_gpio_get_mode); | |
601 | ||
602 | ||
603 | /* IRQ functions */ | |
604 | static inline int nmk_gpio_get_bitmask(int gpio) | |
605 | { | |
a60b57ed | 606 | return 1 << (gpio % NMK_GPIO_PER_CHIP); |
2ec1d359 AR |
607 | } |
608 | ||
f272c00e | 609 | static void nmk_gpio_irq_ack(struct irq_data *d) |
2ec1d359 | 610 | { |
2ec1d359 AR |
611 | struct nmk_gpio_chip *nmk_chip; |
612 | ||
f272c00e | 613 | nmk_chip = irq_data_get_irq_chip_data(d); |
2ec1d359 AR |
614 | if (!nmk_chip) |
615 | return; | |
3c0227d2 RV |
616 | |
617 | clk_enable(nmk_chip->clk); | |
a60b57ed | 618 | writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); |
3c0227d2 | 619 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
620 | } |
621 | ||
4d4e20f7 RV |
622 | enum nmk_gpio_irq_type { |
623 | NORMAL, | |
624 | WAKE, | |
625 | }; | |
626 | ||
040e5ecd | 627 | static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, |
4d4e20f7 RV |
628 | int gpio, enum nmk_gpio_irq_type which, |
629 | bool enable) | |
2ec1d359 | 630 | { |
040e5ecd | 631 | u32 bitmask = nmk_gpio_get_bitmask(gpio); |
6c12fe88 RV |
632 | u32 *rimscval; |
633 | u32 *fimscval; | |
634 | u32 rimscreg; | |
635 | u32 fimscreg; | |
636 | ||
637 | if (which == NORMAL) { | |
638 | rimscreg = NMK_GPIO_RIMSC; | |
639 | fimscreg = NMK_GPIO_FIMSC; | |
640 | rimscval = &nmk_chip->rimsc; | |
641 | fimscval = &nmk_chip->fimsc; | |
642 | } else { | |
643 | rimscreg = NMK_GPIO_RWIMSC; | |
644 | fimscreg = NMK_GPIO_FWIMSC; | |
645 | rimscval = &nmk_chip->rwimsc; | |
646 | fimscval = &nmk_chip->fwimsc; | |
647 | } | |
2ec1d359 | 648 | |
040e5ecd | 649 | /* we must individually set/clear the two edges */ |
2ec1d359 | 650 | if (nmk_chip->edge_rising & bitmask) { |
040e5ecd | 651 | if (enable) |
6c12fe88 | 652 | *rimscval |= bitmask; |
040e5ecd | 653 | else |
6c12fe88 RV |
654 | *rimscval &= ~bitmask; |
655 | writel(*rimscval, nmk_chip->addr + rimscreg); | |
2ec1d359 AR |
656 | } |
657 | if (nmk_chip->edge_falling & bitmask) { | |
040e5ecd | 658 | if (enable) |
6c12fe88 | 659 | *fimscval |= bitmask; |
040e5ecd | 660 | else |
6c12fe88 RV |
661 | *fimscval &= ~bitmask; |
662 | writel(*fimscval, nmk_chip->addr + fimscreg); | |
2ec1d359 | 663 | } |
040e5ecd | 664 | } |
2ec1d359 | 665 | |
b9df468d RV |
666 | static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, |
667 | int gpio, bool on) | |
668 | { | |
b982ff0e RV |
669 | /* |
670 | * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is | |
671 | * disabled, since setting SLPM to 1 increases power consumption, and | |
672 | * wakeup is anyhow controlled by the RIMSC and FIMSC registers. | |
673 | */ | |
674 | if (nmk_chip->sleepmode && on) { | |
a60b57ed | 675 | __nmk_gpio_set_slpm(nmk_chip, gpio % nmk_chip->chip.base, |
b982ff0e | 676 | NMK_GPIO_SLPM_WAKEUP_ENABLE); |
33d78647 LW |
677 | } |
678 | ||
b9df468d RV |
679 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); |
680 | } | |
681 | ||
682 | static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) | |
2ec1d359 | 683 | { |
2ec1d359 AR |
684 | struct nmk_gpio_chip *nmk_chip; |
685 | unsigned long flags; | |
040e5ecd | 686 | u32 bitmask; |
2ec1d359 | 687 | |
f272c00e | 688 | nmk_chip = irq_data_get_irq_chip_data(d); |
a60b57ed | 689 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
2ec1d359 | 690 | if (!nmk_chip) |
4d4e20f7 | 691 | return -EINVAL; |
2ec1d359 | 692 | |
3c0227d2 | 693 | clk_enable(nmk_chip->clk); |
b9df468d RV |
694 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
695 | spin_lock(&nmk_chip->lock); | |
696 | ||
a60b57ed | 697 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); |
b9df468d RV |
698 | |
699 | if (!(nmk_chip->real_wake & bitmask)) | |
a60b57ed | 700 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); |
b9df468d RV |
701 | |
702 | spin_unlock(&nmk_chip->lock); | |
703 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 704 | clk_disable(nmk_chip->clk); |
4d4e20f7 RV |
705 | |
706 | return 0; | |
2ec1d359 AR |
707 | } |
708 | ||
f272c00e | 709 | static void nmk_gpio_irq_mask(struct irq_data *d) |
040e5ecd | 710 | { |
b9df468d | 711 | nmk_gpio_irq_maskunmask(d, false); |
4d4e20f7 | 712 | } |
040e5ecd | 713 | |
f272c00e | 714 | static void nmk_gpio_irq_unmask(struct irq_data *d) |
040e5ecd | 715 | { |
b9df468d | 716 | nmk_gpio_irq_maskunmask(d, true); |
4d4e20f7 RV |
717 | } |
718 | ||
f272c00e | 719 | static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
4d4e20f7 | 720 | { |
7e3f7e59 RV |
721 | struct nmk_gpio_chip *nmk_chip; |
722 | unsigned long flags; | |
b9df468d | 723 | u32 bitmask; |
7e3f7e59 | 724 | |
f272c00e | 725 | nmk_chip = irq_data_get_irq_chip_data(d); |
7e3f7e59 RV |
726 | if (!nmk_chip) |
727 | return -EINVAL; | |
a60b57ed | 728 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
7e3f7e59 | 729 | |
3c0227d2 | 730 | clk_enable(nmk_chip->clk); |
01727e61 RV |
731 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
732 | spin_lock(&nmk_chip->lock); | |
733 | ||
479a0c7e | 734 | if (irqd_irq_disabled(d)) |
a60b57ed | 735 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); |
b9df468d RV |
736 | |
737 | if (on) | |
738 | nmk_chip->real_wake |= bitmask; | |
739 | else | |
740 | nmk_chip->real_wake &= ~bitmask; | |
01727e61 RV |
741 | |
742 | spin_unlock(&nmk_chip->lock); | |
743 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 744 | clk_disable(nmk_chip->clk); |
7e3f7e59 RV |
745 | |
746 | return 0; | |
040e5ecd RV |
747 | } |
748 | ||
f272c00e | 749 | static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
2ec1d359 | 750 | { |
479a0c7e | 751 | bool enabled = !irqd_irq_disabled(d); |
3c0227d2 | 752 | bool wake = irqd_is_wakeup_set(d); |
2ec1d359 AR |
753 | struct nmk_gpio_chip *nmk_chip; |
754 | unsigned long flags; | |
755 | u32 bitmask; | |
756 | ||
f272c00e | 757 | nmk_chip = irq_data_get_irq_chip_data(d); |
a60b57ed | 758 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
2ec1d359 AR |
759 | if (!nmk_chip) |
760 | return -EINVAL; | |
2ec1d359 AR |
761 | if (type & IRQ_TYPE_LEVEL_HIGH) |
762 | return -EINVAL; | |
763 | if (type & IRQ_TYPE_LEVEL_LOW) | |
764 | return -EINVAL; | |
765 | ||
3c0227d2 | 766 | clk_enable(nmk_chip->clk); |
2ec1d359 AR |
767 | spin_lock_irqsave(&nmk_chip->lock, flags); |
768 | ||
7a852d80 | 769 | if (enabled) |
a60b57ed | 770 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); |
4d4e20f7 | 771 | |
b9df468d | 772 | if (enabled || wake) |
a60b57ed | 773 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); |
7a852d80 | 774 | |
2ec1d359 AR |
775 | nmk_chip->edge_rising &= ~bitmask; |
776 | if (type & IRQ_TYPE_EDGE_RISING) | |
777 | nmk_chip->edge_rising |= bitmask; | |
2ec1d359 AR |
778 | |
779 | nmk_chip->edge_falling &= ~bitmask; | |
780 | if (type & IRQ_TYPE_EDGE_FALLING) | |
781 | nmk_chip->edge_falling |= bitmask; | |
2ec1d359 | 782 | |
7a852d80 | 783 | if (enabled) |
a60b57ed | 784 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); |
4d4e20f7 | 785 | |
b9df468d | 786 | if (enabled || wake) |
a60b57ed | 787 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); |
2ec1d359 | 788 | |
7a852d80 | 789 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 790 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
791 | |
792 | return 0; | |
793 | } | |
794 | ||
3c0227d2 RV |
795 | static unsigned int nmk_gpio_irq_startup(struct irq_data *d) |
796 | { | |
797 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 | 798 | |
3c0227d2 RV |
799 | clk_enable(nmk_chip->clk); |
800 | nmk_gpio_irq_unmask(d); | |
2ec1d359 AR |
801 | return 0; |
802 | } | |
803 | ||
3c0227d2 RV |
804 | static void nmk_gpio_irq_shutdown(struct irq_data *d) |
805 | { | |
806 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
807 | ||
808 | nmk_gpio_irq_mask(d); | |
809 | clk_disable(nmk_chip->clk); | |
810 | } | |
811 | ||
2ec1d359 AR |
812 | static struct irq_chip nmk_gpio_irq_chip = { |
813 | .name = "Nomadik-GPIO", | |
f272c00e LB |
814 | .irq_ack = nmk_gpio_irq_ack, |
815 | .irq_mask = nmk_gpio_irq_mask, | |
816 | .irq_unmask = nmk_gpio_irq_unmask, | |
817 | .irq_set_type = nmk_gpio_irq_set_type, | |
818 | .irq_set_wake = nmk_gpio_irq_set_wake, | |
3c0227d2 RV |
819 | .irq_startup = nmk_gpio_irq_startup, |
820 | .irq_shutdown = nmk_gpio_irq_shutdown, | |
2ec1d359 AR |
821 | }; |
822 | ||
33b744b3 RV |
823 | static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, |
824 | u32 status) | |
2ec1d359 AR |
825 | { |
826 | struct nmk_gpio_chip *nmk_chip; | |
6845664a | 827 | struct irq_chip *host_chip = irq_get_chip(irq); |
2ec1d359 AR |
828 | unsigned int first_irq; |
829 | ||
adfed159 | 830 | chained_irq_enter(host_chip, desc); |
aaedaa2b | 831 | |
6845664a | 832 | nmk_chip = irq_get_handler_data(irq); |
a60b57ed | 833 | first_irq = nmk_chip->domain->revmap_data.legacy.first_irq; |
33b744b3 RV |
834 | while (status) { |
835 | int bit = __ffs(status); | |
836 | ||
837 | generic_handle_irq(first_irq + bit); | |
838 | status &= ~BIT(bit); | |
2ec1d359 | 839 | } |
aaedaa2b | 840 | |
adfed159 | 841 | chained_irq_exit(host_chip, desc); |
2ec1d359 AR |
842 | } |
843 | ||
33b744b3 RV |
844 | static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
845 | { | |
6845664a | 846 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
3c0227d2 RV |
847 | u32 status; |
848 | ||
849 | clk_enable(nmk_chip->clk); | |
850 | status = readl(nmk_chip->addr + NMK_GPIO_IS); | |
851 | clk_disable(nmk_chip->clk); | |
33b744b3 RV |
852 | |
853 | __nmk_gpio_irq_handler(irq, desc, status); | |
854 | } | |
855 | ||
856 | static void nmk_gpio_secondary_irq_handler(unsigned int irq, | |
857 | struct irq_desc *desc) | |
858 | { | |
6845664a | 859 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
33b744b3 RV |
860 | u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); |
861 | ||
862 | __nmk_gpio_irq_handler(irq, desc, status); | |
863 | } | |
864 | ||
2ec1d359 AR |
865 | static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) |
866 | { | |
6845664a TG |
867 | irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); |
868 | irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); | |
33b744b3 RV |
869 | |
870 | if (nmk_chip->secondary_parent_irq >= 0) { | |
6845664a | 871 | irq_set_chained_handler(nmk_chip->secondary_parent_irq, |
33b744b3 | 872 | nmk_gpio_secondary_irq_handler); |
6845664a | 873 | irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); |
33b744b3 RV |
874 | } |
875 | ||
2ec1d359 AR |
876 | return 0; |
877 | } | |
878 | ||
879 | /* I/O Functions */ | |
dbfe8ca2 LW |
880 | |
881 | static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset) | |
882 | { | |
883 | /* | |
884 | * Map back to global GPIO space and request muxing, the direction | |
885 | * parameter does not matter for this controller. | |
886 | */ | |
887 | int gpio = chip->base + offset; | |
888 | ||
889 | return pinctrl_request_gpio(gpio); | |
890 | } | |
891 | ||
892 | static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset) | |
893 | { | |
894 | int gpio = chip->base + offset; | |
895 | ||
896 | pinctrl_free_gpio(gpio); | |
897 | } | |
898 | ||
2ec1d359 AR |
899 | static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) |
900 | { | |
901 | struct nmk_gpio_chip *nmk_chip = | |
902 | container_of(chip, struct nmk_gpio_chip, chip); | |
903 | ||
3c0227d2 RV |
904 | clk_enable(nmk_chip->clk); |
905 | ||
2ec1d359 | 906 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); |
3c0227d2 RV |
907 | |
908 | clk_disable(nmk_chip->clk); | |
909 | ||
2ec1d359 AR |
910 | return 0; |
911 | } | |
912 | ||
2ec1d359 AR |
913 | static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) |
914 | { | |
915 | struct nmk_gpio_chip *nmk_chip = | |
916 | container_of(chip, struct nmk_gpio_chip, chip); | |
917 | u32 bit = 1 << offset; | |
3c0227d2 RV |
918 | int value; |
919 | ||
920 | clk_enable(nmk_chip->clk); | |
2ec1d359 | 921 | |
3c0227d2 | 922 | value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; |
2ec1d359 | 923 | |
3c0227d2 RV |
924 | clk_disable(nmk_chip->clk); |
925 | ||
926 | return value; | |
2ec1d359 AR |
927 | } |
928 | ||
929 | static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, | |
930 | int val) | |
931 | { | |
932 | struct nmk_gpio_chip *nmk_chip = | |
933 | container_of(chip, struct nmk_gpio_chip, chip); | |
2ec1d359 | 934 | |
3c0227d2 RV |
935 | clk_enable(nmk_chip->clk); |
936 | ||
6720db7c | 937 | __nmk_gpio_set_output(nmk_chip, offset, val); |
3c0227d2 RV |
938 | |
939 | clk_disable(nmk_chip->clk); | |
2ec1d359 AR |
940 | } |
941 | ||
6647c6c0 RV |
942 | static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, |
943 | int val) | |
944 | { | |
945 | struct nmk_gpio_chip *nmk_chip = | |
946 | container_of(chip, struct nmk_gpio_chip, chip); | |
947 | ||
3c0227d2 RV |
948 | clk_enable(nmk_chip->clk); |
949 | ||
6720db7c | 950 | __nmk_gpio_make_output(nmk_chip, offset, val); |
6647c6c0 | 951 | |
3c0227d2 RV |
952 | clk_disable(nmk_chip->clk); |
953 | ||
6647c6c0 RV |
954 | return 0; |
955 | } | |
956 | ||
0d2aec9c RV |
957 | static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
958 | { | |
959 | struct nmk_gpio_chip *nmk_chip = | |
960 | container_of(chip, struct nmk_gpio_chip, chip); | |
961 | ||
a60b57ed | 962 | return irq_find_mapping(nmk_chip->domain, offset); |
0d2aec9c RV |
963 | } |
964 | ||
d0b543c7 RV |
965 | #ifdef CONFIG_DEBUG_FS |
966 | ||
967 | #include <linux/seq_file.h> | |
968 | ||
6f4350a6 LW |
969 | static void nmk_gpio_dbg_show_one(struct seq_file *s, struct gpio_chip *chip, |
970 | unsigned offset, unsigned gpio) | |
d0b543c7 | 971 | { |
6f4350a6 | 972 | const char *label = gpiochip_is_requested(chip, offset); |
d0b543c7 RV |
973 | struct nmk_gpio_chip *nmk_chip = |
974 | container_of(chip, struct nmk_gpio_chip, chip); | |
6f4350a6 LW |
975 | int mode; |
976 | bool is_out; | |
977 | bool pull; | |
978 | u32 bit = 1 << offset; | |
d0b543c7 RV |
979 | const char *modes[] = { |
980 | [NMK_GPIO_ALT_GPIO] = "gpio", | |
981 | [NMK_GPIO_ALT_A] = "altA", | |
982 | [NMK_GPIO_ALT_B] = "altB", | |
983 | [NMK_GPIO_ALT_C] = "altC", | |
984 | }; | |
985 | ||
3c0227d2 | 986 | clk_enable(nmk_chip->clk); |
6f4350a6 LW |
987 | is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit); |
988 | pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); | |
989 | mode = nmk_gpio_get_mode(gpio); | |
990 | ||
991 | seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", | |
992 | gpio, label ?: "(none)", | |
993 | is_out ? "out" : "in ", | |
994 | chip->get | |
995 | ? (chip->get(chip, offset) ? "hi" : "lo") | |
996 | : "? ", | |
997 | (mode < 0) ? "unknown" : modes[mode], | |
998 | pull ? "pull" : "none"); | |
999 | ||
1000 | if (label && !is_out) { | |
1001 | int irq = gpio_to_irq(gpio); | |
1002 | struct irq_desc *desc = irq_to_desc(irq); | |
1003 | ||
1004 | /* This races with request_irq(), set_irq_type(), | |
1005 | * and set_irq_wake() ... but those are "rare". | |
1006 | */ | |
1007 | if (irq >= 0 && desc->action) { | |
1008 | char *trigger; | |
1009 | u32 bitmask = nmk_gpio_get_bitmask(gpio); | |
1010 | ||
1011 | if (nmk_chip->edge_rising & bitmask) | |
1012 | trigger = "edge-rising"; | |
1013 | else if (nmk_chip->edge_falling & bitmask) | |
1014 | trigger = "edge-falling"; | |
1015 | else | |
1016 | trigger = "edge-undefined"; | |
1017 | ||
1018 | seq_printf(s, " irq-%d %s%s", | |
1019 | irq, trigger, | |
1020 | irqd_is_wakeup_set(&desc->irq_data) | |
1021 | ? " wakeup" : ""); | |
8ea72a30 | 1022 | } |
6f4350a6 LW |
1023 | } |
1024 | clk_disable(nmk_chip->clk); | |
1025 | } | |
1026 | ||
1027 | static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
1028 | { | |
1029 | unsigned i; | |
1030 | unsigned gpio = chip->base; | |
8ea72a30 | 1031 | |
6f4350a6 LW |
1032 | for (i = 0; i < chip->ngpio; i++, gpio++) { |
1033 | nmk_gpio_dbg_show_one(s, chip, i, gpio); | |
d0b543c7 RV |
1034 | seq_printf(s, "\n"); |
1035 | } | |
1036 | } | |
1037 | ||
1038 | #else | |
6f4350a6 LW |
1039 | static inline void nmk_gpio_dbg_show_one(struct seq_file *s, |
1040 | struct gpio_chip *chip, | |
1041 | unsigned offset, unsigned gpio) | |
1042 | { | |
1043 | } | |
d0b543c7 RV |
1044 | #define nmk_gpio_dbg_show NULL |
1045 | #endif | |
1046 | ||
2ec1d359 AR |
1047 | /* This structure is replicated for each GPIO block allocated at probe time */ |
1048 | static struct gpio_chip nmk_gpio_template = { | |
dbfe8ca2 LW |
1049 | .request = nmk_gpio_request, |
1050 | .free = nmk_gpio_free, | |
2ec1d359 AR |
1051 | .direction_input = nmk_gpio_make_input, |
1052 | .get = nmk_gpio_get_input, | |
1053 | .direction_output = nmk_gpio_make_output, | |
1054 | .set = nmk_gpio_set_output, | |
0d2aec9c | 1055 | .to_irq = nmk_gpio_to_irq, |
d0b543c7 | 1056 | .dbg_show = nmk_gpio_dbg_show, |
2ec1d359 AR |
1057 | .can_sleep = 0, |
1058 | }; | |
1059 | ||
3c0227d2 RV |
1060 | void nmk_gpio_clocks_enable(void) |
1061 | { | |
1062 | int i; | |
1063 | ||
1064 | for (i = 0; i < NUM_BANKS; i++) { | |
1065 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1066 | ||
1067 | if (!chip) | |
1068 | continue; | |
1069 | ||
1070 | clk_enable(chip->clk); | |
1071 | } | |
1072 | } | |
1073 | ||
1074 | void nmk_gpio_clocks_disable(void) | |
1075 | { | |
1076 | int i; | |
1077 | ||
1078 | for (i = 0; i < NUM_BANKS; i++) { | |
1079 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1080 | ||
1081 | if (!chip) | |
1082 | continue; | |
1083 | ||
1084 | clk_disable(chip->clk); | |
1085 | } | |
1086 | } | |
1087 | ||
b9df468d RV |
1088 | /* |
1089 | * Called from the suspend/resume path to only keep the real wakeup interrupts | |
1090 | * (those that have had set_irq_wake() called on them) as wakeup interrupts, | |
1091 | * and not the rest of the interrupts which we needed to have as wakeups for | |
1092 | * cpuidle. | |
1093 | * | |
1094 | * PM ops are not used since this needs to be done at the end, after all the | |
1095 | * other drivers are done with their suspend callbacks. | |
1096 | */ | |
1097 | void nmk_gpio_wakeups_suspend(void) | |
1098 | { | |
1099 | int i; | |
1100 | ||
1101 | for (i = 0; i < NUM_BANKS; i++) { | |
1102 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1103 | ||
1104 | if (!chip) | |
1105 | break; | |
1106 | ||
3c0227d2 RV |
1107 | clk_enable(chip->clk); |
1108 | ||
b9df468d RV |
1109 | writel(chip->rwimsc & chip->real_wake, |
1110 | chip->addr + NMK_GPIO_RWIMSC); | |
1111 | writel(chip->fwimsc & chip->real_wake, | |
1112 | chip->addr + NMK_GPIO_FWIMSC); | |
1113 | ||
3c0227d2 | 1114 | clk_disable(chip->clk); |
b9df468d RV |
1115 | } |
1116 | } | |
1117 | ||
1118 | void nmk_gpio_wakeups_resume(void) | |
1119 | { | |
1120 | int i; | |
1121 | ||
1122 | for (i = 0; i < NUM_BANKS; i++) { | |
1123 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1124 | ||
1125 | if (!chip) | |
1126 | break; | |
1127 | ||
3c0227d2 RV |
1128 | clk_enable(chip->clk); |
1129 | ||
b9df468d RV |
1130 | writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); |
1131 | writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); | |
1132 | ||
3c0227d2 | 1133 | clk_disable(chip->clk); |
b9df468d RV |
1134 | } |
1135 | } | |
1136 | ||
bc6f5cf6 RA |
1137 | /* |
1138 | * Read the pull up/pull down status. | |
1139 | * A bit set in 'pull_up' means that pull up | |
1140 | * is selected if pull is enabled in PDIS register. | |
1141 | * Note: only pull up/down set via this driver can | |
1142 | * be detected due to HW limitations. | |
1143 | */ | |
1144 | void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) | |
1145 | { | |
1146 | if (gpio_bank < NUM_BANKS) { | |
1147 | struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; | |
1148 | ||
1149 | if (!chip) | |
1150 | return; | |
1151 | ||
1152 | *pull_up = chip->pull_up; | |
1153 | } | |
1154 | } | |
1155 | ||
a60b57ed LJ |
1156 | int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq, |
1157 | irq_hw_number_t hwirq) | |
1158 | { | |
1159 | struct nmk_gpio_chip *nmk_chip = d->host_data; | |
1160 | ||
1161 | if (!nmk_chip) | |
1162 | return -EINVAL; | |
1163 | ||
1164 | irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq); | |
1165 | set_irq_flags(irq, IRQF_VALID); | |
1166 | irq_set_chip_data(irq, nmk_chip); | |
1167 | irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING); | |
1168 | ||
1169 | return 0; | |
1170 | } | |
1171 | ||
1172 | const struct irq_domain_ops nmk_gpio_irq_simple_ops = { | |
1173 | .map = nmk_gpio_irq_map, | |
1174 | .xlate = irq_domain_xlate_twocell, | |
1175 | }; | |
1176 | ||
fd0d67d6 | 1177 | static int __devinit nmk_gpio_probe(struct platform_device *dev) |
2ec1d359 | 1178 | { |
3e3c62ca | 1179 | struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; |
513c27f8 | 1180 | struct device_node *np = dev->dev.of_node; |
2ec1d359 AR |
1181 | struct nmk_gpio_chip *nmk_chip; |
1182 | struct gpio_chip *chip; | |
3e3c62ca | 1183 | struct resource *res; |
af7dc228 | 1184 | struct clk *clk; |
33b744b3 | 1185 | int secondary_irq; |
8d91771c | 1186 | void __iomem *base; |
3e3c62ca | 1187 | int irq; |
2ec1d359 AR |
1188 | int ret; |
1189 | ||
513c27f8 LJ |
1190 | if (!pdata && !np) { |
1191 | dev_err(&dev->dev, "No platform data or device tree found\n"); | |
3e3c62ca | 1192 | return -ENODEV; |
513c27f8 LJ |
1193 | } |
1194 | ||
1195 | if (np) { | |
1196 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); | |
1197 | if (!pdata) | |
1198 | return -ENOMEM; | |
1199 | ||
1200 | if (of_get_property(np, "supports-sleepmode", NULL)) | |
1201 | pdata->supports_sleepmode = true; | |
1202 | ||
1203 | if (of_property_read_u32(np, "gpio-bank", &dev->id)) { | |
1204 | dev_err(&dev->dev, "gpio-bank property not found\n"); | |
1205 | ret = -EINVAL; | |
a60b57ed | 1206 | goto out; |
513c27f8 LJ |
1207 | } |
1208 | ||
1209 | pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP; | |
1210 | pdata->num_gpio = NMK_GPIO_PER_CHIP; | |
1211 | } | |
3e3c62ca RV |
1212 | |
1213 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
1214 | if (!res) { | |
1215 | ret = -ENOENT; | |
1216 | goto out; | |
1217 | } | |
1218 | ||
1219 | irq = platform_get_irq(dev, 0); | |
1220 | if (irq < 0) { | |
1221 | ret = irq; | |
1222 | goto out; | |
1223 | } | |
1224 | ||
33b744b3 RV |
1225 | secondary_irq = platform_get_irq(dev, 1); |
1226 | if (secondary_irq >= 0 && !pdata->get_secondary_status) { | |
1227 | ret = -EINVAL; | |
1228 | goto out; | |
1229 | } | |
1230 | ||
3e3c62ca RV |
1231 | if (request_mem_region(res->start, resource_size(res), |
1232 | dev_name(&dev->dev)) == NULL) { | |
1233 | ret = -EBUSY; | |
1234 | goto out; | |
1235 | } | |
2ec1d359 | 1236 | |
8d91771c LW |
1237 | base = ioremap(res->start, resource_size(res)); |
1238 | if (!base) { | |
1239 | ret = -ENOMEM; | |
1240 | goto out_release; | |
1241 | } | |
1242 | ||
af7dc228 RV |
1243 | clk = clk_get(&dev->dev, NULL); |
1244 | if (IS_ERR(clk)) { | |
1245 | ret = PTR_ERR(clk); | |
8d91771c | 1246 | goto out_unmap; |
af7dc228 RV |
1247 | } |
1248 | ||
2ec1d359 AR |
1249 | nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL); |
1250 | if (!nmk_chip) { | |
1251 | ret = -ENOMEM; | |
af7dc228 | 1252 | goto out_clk; |
2ec1d359 | 1253 | } |
513c27f8 | 1254 | |
2ec1d359 AR |
1255 | /* |
1256 | * The virt address in nmk_chip->addr is in the nomadik register space, | |
1257 | * so we can simply convert the resource address, without remapping | |
1258 | */ | |
33b744b3 | 1259 | nmk_chip->bank = dev->id; |
af7dc228 | 1260 | nmk_chip->clk = clk; |
8d91771c | 1261 | nmk_chip->addr = base; |
2ec1d359 | 1262 | nmk_chip->chip = nmk_gpio_template; |
3e3c62ca | 1263 | nmk_chip->parent_irq = irq; |
33b744b3 RV |
1264 | nmk_chip->secondary_parent_irq = secondary_irq; |
1265 | nmk_chip->get_secondary_status = pdata->get_secondary_status; | |
01727e61 | 1266 | nmk_chip->set_ioforce = pdata->set_ioforce; |
33d78647 | 1267 | nmk_chip->sleepmode = pdata->supports_sleepmode; |
c0fcb8db | 1268 | spin_lock_init(&nmk_chip->lock); |
2ec1d359 AR |
1269 | |
1270 | chip = &nmk_chip->chip; | |
1271 | chip->base = pdata->first_gpio; | |
e493e06f | 1272 | chip->ngpio = pdata->num_gpio; |
8d568ae5 | 1273 | chip->label = pdata->name ?: dev_name(&dev->dev); |
2ec1d359 AR |
1274 | chip->dev = &dev->dev; |
1275 | chip->owner = THIS_MODULE; | |
1276 | ||
ebc6178d RV |
1277 | clk_enable(nmk_chip->clk); |
1278 | nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); | |
1279 | clk_disable(nmk_chip->clk); | |
1280 | ||
072e82a1 | 1281 | #ifdef CONFIG_OF_GPIO |
513c27f8 | 1282 | chip->of_node = np; |
072e82a1 | 1283 | #endif |
513c27f8 | 1284 | |
2ec1d359 AR |
1285 | ret = gpiochip_add(&nmk_chip->chip); |
1286 | if (ret) | |
1287 | goto out_free; | |
1288 | ||
01727e61 RV |
1289 | BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); |
1290 | ||
1291 | nmk_gpio_chips[nmk_chip->bank] = nmk_chip; | |
513c27f8 | 1292 | |
3e3c62ca | 1293 | platform_set_drvdata(dev, nmk_chip); |
2ec1d359 | 1294 | |
a60b57ed LJ |
1295 | nmk_chip->domain = irq_domain_add_legacy(np, NMK_GPIO_PER_CHIP, |
1296 | NOMADIK_GPIO_TO_IRQ(pdata->first_gpio), | |
1297 | 0, &nmk_gpio_irq_simple_ops, nmk_chip); | |
1298 | if (!nmk_chip->domain) { | |
1299 | pr_err("%s: Failed to create irqdomain\n", np->full_name); | |
1300 | ret = -ENOSYS; | |
1301 | goto out_free; | |
1302 | } | |
1303 | ||
2ec1d359 AR |
1304 | nmk_gpio_init_irq(nmk_chip); |
1305 | ||
513c27f8 LJ |
1306 | dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); |
1307 | ||
2ec1d359 AR |
1308 | return 0; |
1309 | ||
3e3c62ca | 1310 | out_free: |
2ec1d359 | 1311 | kfree(nmk_chip); |
af7dc228 RV |
1312 | out_clk: |
1313 | clk_disable(clk); | |
1314 | clk_put(clk); | |
8d91771c LW |
1315 | out_unmap: |
1316 | iounmap(base); | |
3e3c62ca RV |
1317 | out_release: |
1318 | release_mem_region(res->start, resource_size(res)); | |
1319 | out: | |
2ec1d359 AR |
1320 | dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, |
1321 | pdata->first_gpio, pdata->first_gpio+31); | |
513c27f8 LJ |
1322 | if (np) |
1323 | kfree(pdata); | |
1324 | ||
2ec1d359 AR |
1325 | return ret; |
1326 | } | |
1327 | ||
e98ea774 LW |
1328 | static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) |
1329 | { | |
1330 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1331 | ||
1332 | return npct->soc->ngroups; | |
1333 | } | |
1334 | ||
1335 | static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, | |
1336 | unsigned selector) | |
1337 | { | |
1338 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1339 | ||
1340 | return npct->soc->groups[selector].name; | |
1341 | } | |
1342 | ||
1343 | static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
1344 | const unsigned **pins, | |
1345 | unsigned *num_pins) | |
1346 | { | |
1347 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1348 | ||
1349 | *pins = npct->soc->groups[selector].pins; | |
1350 | *num_pins = npct->soc->groups[selector].npins; | |
1351 | return 0; | |
1352 | } | |
1353 | ||
24cbdd75 LW |
1354 | static struct pinctrl_gpio_range * |
1355 | nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset) | |
1356 | { | |
1357 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1358 | int i; | |
1359 | ||
1360 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) { | |
1361 | struct pinctrl_gpio_range *range; | |
1362 | ||
1363 | range = &npct->soc->gpio_ranges[i]; | |
1364 | if (offset >= range->pin_base && | |
1365 | offset <= (range->pin_base + range->npins - 1)) | |
1366 | return range; | |
1367 | } | |
1368 | return NULL; | |
1369 | } | |
1370 | ||
e98ea774 LW |
1371 | static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
1372 | unsigned offset) | |
1373 | { | |
24cbdd75 LW |
1374 | struct pinctrl_gpio_range *range; |
1375 | struct gpio_chip *chip; | |
1376 | ||
1377 | range = nmk_match_gpio_range(pctldev, offset); | |
1378 | if (!range || !range->gc) { | |
1379 | seq_printf(s, "invalid pin offset"); | |
1380 | return; | |
1381 | } | |
1382 | chip = range->gc; | |
1383 | nmk_gpio_dbg_show_one(s, chip, offset - chip->base, offset); | |
e98ea774 LW |
1384 | } |
1385 | ||
1386 | static struct pinctrl_ops nmk_pinctrl_ops = { | |
1387 | .get_groups_count = nmk_get_groups_cnt, | |
1388 | .get_group_name = nmk_get_group_name, | |
1389 | .get_group_pins = nmk_get_group_pins, | |
1390 | .pin_dbg_show = nmk_pin_dbg_show, | |
1391 | }; | |
1392 | ||
dbfe8ca2 LW |
1393 | static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) |
1394 | { | |
1395 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1396 | ||
1397 | return npct->soc->nfunctions; | |
1398 | } | |
1399 | ||
1400 | static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
1401 | unsigned function) | |
1402 | { | |
1403 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1404 | ||
1405 | return npct->soc->functions[function].name; | |
1406 | } | |
1407 | ||
1408 | static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
1409 | unsigned function, | |
1410 | const char * const **groups, | |
1411 | unsigned * const num_groups) | |
1412 | { | |
1413 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1414 | ||
1415 | *groups = npct->soc->functions[function].groups; | |
1416 | *num_groups = npct->soc->functions[function].ngroups; | |
1417 | ||
1418 | return 0; | |
1419 | } | |
1420 | ||
1421 | static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, | |
1422 | unsigned group) | |
1423 | { | |
1424 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1425 | const struct nmk_pingroup *g; | |
1426 | static unsigned int slpm[NUM_BANKS]; | |
1427 | unsigned long flags; | |
1428 | bool glitch; | |
1429 | int ret = -EINVAL; | |
1430 | int i; | |
1431 | ||
1432 | g = &npct->soc->groups[group]; | |
1433 | ||
1434 | if (g->altsetting < 0) | |
1435 | return -EINVAL; | |
1436 | ||
1437 | dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); | |
1438 | ||
1439 | /* Handle this special glitch on altfunction C */ | |
1440 | glitch = (g->altsetting == NMK_GPIO_ALT_C); | |
1441 | ||
1442 | if (glitch) { | |
1443 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | |
1444 | ||
1445 | /* Initially don't put any pins to sleep when switching */ | |
1446 | memset(slpm, 0xff, sizeof(slpm)); | |
1447 | ||
1448 | /* | |
1449 | * Then mask the pins that need to be sleeping now when we're | |
1450 | * switching to the ALT C function. | |
1451 | */ | |
1452 | for (i = 0; i < g->npins; i++) | |
1453 | slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); | |
1454 | nmk_gpio_glitch_slpm_init(slpm); | |
1455 | } | |
1456 | ||
1457 | for (i = 0; i < g->npins; i++) { | |
1458 | struct pinctrl_gpio_range *range; | |
1459 | struct nmk_gpio_chip *nmk_chip; | |
1460 | struct gpio_chip *chip; | |
1461 | unsigned bit; | |
1462 | ||
1463 | range = nmk_match_gpio_range(pctldev, g->pins[i]); | |
1464 | if (!range) { | |
1465 | dev_err(npct->dev, | |
1466 | "invalid pin offset %d in group %s at index %d\n", | |
1467 | g->pins[i], g->name, i); | |
1468 | goto out_glitch; | |
1469 | } | |
1470 | if (!range->gc) { | |
1471 | dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n", | |
1472 | g->pins[i], g->name, i); | |
1473 | goto out_glitch; | |
1474 | } | |
1475 | chip = range->gc; | |
1476 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
1477 | dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); | |
1478 | ||
1479 | clk_enable(nmk_chip->clk); | |
1480 | bit = g->pins[i] % NMK_GPIO_PER_CHIP; | |
1481 | /* | |
1482 | * If the pin is switching to altfunc, and there was an | |
1483 | * interrupt installed on it which has been lazy disabled, | |
1484 | * actually mask the interrupt to prevent spurious interrupts | |
1485 | * that would occur while the pin is under control of the | |
1486 | * peripheral. Only SKE does this. | |
1487 | */ | |
1488 | nmk_gpio_disable_lazy_irq(nmk_chip, bit); | |
1489 | ||
1490 | __nmk_gpio_set_mode_safe(nmk_chip, bit, g->altsetting, glitch); | |
1491 | clk_disable(nmk_chip->clk); | |
1492 | } | |
1493 | ||
1494 | /* When all pins are successfully reconfigured we get here */ | |
1495 | ret = 0; | |
1496 | ||
1497 | out_glitch: | |
1498 | if (glitch) { | |
1499 | nmk_gpio_glitch_slpm_restore(slpm); | |
1500 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
1501 | } | |
1502 | ||
1503 | return ret; | |
1504 | } | |
1505 | ||
1506 | static void nmk_pmx_disable(struct pinctrl_dev *pctldev, | |
1507 | unsigned function, unsigned group) | |
1508 | { | |
1509 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1510 | const struct nmk_pingroup *g; | |
1511 | ||
1512 | g = &npct->soc->groups[group]; | |
1513 | ||
1514 | if (g->altsetting < 0) | |
1515 | return; | |
1516 | ||
1517 | /* Poke out the mux, set the pin to some default state? */ | |
1518 | dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins); | |
1519 | } | |
1520 | ||
1521 | int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, | |
1522 | struct pinctrl_gpio_range *range, | |
1523 | unsigned offset) | |
1524 | { | |
1525 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1526 | struct nmk_gpio_chip *nmk_chip; | |
1527 | struct gpio_chip *chip; | |
1528 | unsigned bit; | |
1529 | ||
1530 | if (!range) { | |
1531 | dev_err(npct->dev, "invalid range\n"); | |
1532 | return -EINVAL; | |
1533 | } | |
1534 | if (!range->gc) { | |
1535 | dev_err(npct->dev, "missing GPIO chip in range\n"); | |
1536 | return -EINVAL; | |
1537 | } | |
1538 | chip = range->gc; | |
1539 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
1540 | ||
1541 | dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); | |
1542 | ||
1543 | clk_enable(nmk_chip->clk); | |
1544 | bit = offset % NMK_GPIO_PER_CHIP; | |
1545 | /* There is no glitch when converting any pin to GPIO */ | |
1546 | __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); | |
1547 | clk_disable(nmk_chip->clk); | |
1548 | ||
1549 | return 0; | |
1550 | } | |
1551 | ||
1552 | void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, | |
1553 | struct pinctrl_gpio_range *range, | |
1554 | unsigned offset) | |
1555 | { | |
1556 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1557 | ||
1558 | dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); | |
1559 | /* Set the pin to some default state, GPIO is usually default */ | |
1560 | } | |
1561 | ||
1562 | static struct pinmux_ops nmk_pinmux_ops = { | |
1563 | .get_functions_count = nmk_pmx_get_funcs_cnt, | |
1564 | .get_function_name = nmk_pmx_get_func_name, | |
1565 | .get_function_groups = nmk_pmx_get_func_groups, | |
1566 | .enable = nmk_pmx_enable, | |
1567 | .disable = nmk_pmx_disable, | |
1568 | .gpio_request_enable = nmk_gpio_request_enable, | |
1569 | .gpio_disable_free = nmk_gpio_disable_free, | |
1570 | }; | |
1571 | ||
d41af627 LW |
1572 | int nmk_pin_config_get(struct pinctrl_dev *pctldev, |
1573 | unsigned pin, | |
1574 | unsigned long *config) | |
1575 | { | |
1576 | /* Not implemented */ | |
1577 | return -EINVAL; | |
1578 | } | |
1579 | ||
1580 | int nmk_pin_config_set(struct pinctrl_dev *pctldev, | |
1581 | unsigned pin, | |
1582 | unsigned long config) | |
1583 | { | |
1584 | static const char *pullnames[] = { | |
1585 | [NMK_GPIO_PULL_NONE] = "none", | |
1586 | [NMK_GPIO_PULL_UP] = "up", | |
1587 | [NMK_GPIO_PULL_DOWN] = "down", | |
1588 | [3] /* illegal */ = "??" | |
1589 | }; | |
1590 | static const char *slpmnames[] = { | |
1591 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", | |
1592 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
1593 | }; | |
1594 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1595 | struct nmk_gpio_chip *nmk_chip; | |
1596 | struct pinctrl_gpio_range *range; | |
1597 | struct gpio_chip *chip; | |
1598 | unsigned bit; | |
1599 | ||
1600 | /* | |
1601 | * The pin config contains pin number and altfunction fields, here | |
1602 | * we just ignore that part. It's being handled by the framework and | |
1603 | * pinmux callback respectively. | |
1604 | */ | |
1605 | pin_cfg_t cfg = (pin_cfg_t) config; | |
1606 | int pull = PIN_PULL(cfg); | |
1607 | int slpm = PIN_SLPM(cfg); | |
1608 | int output = PIN_DIR(cfg); | |
1609 | int val = PIN_VAL(cfg); | |
1610 | bool lowemi = PIN_LOWEMI(cfg); | |
1611 | bool gpiomode = PIN_GPIOMODE(cfg); | |
1612 | bool sleep = PIN_SLEEPMODE(cfg); | |
1613 | ||
1614 | range = nmk_match_gpio_range(pctldev, pin); | |
1615 | if (!range) { | |
1616 | dev_err(npct->dev, "invalid pin offset %d\n", pin); | |
1617 | return -EINVAL; | |
1618 | } | |
1619 | if (!range->gc) { | |
1620 | dev_err(npct->dev, "GPIO chip missing in range for pin %d\n", | |
1621 | pin); | |
1622 | return -EINVAL; | |
1623 | } | |
1624 | chip = range->gc; | |
1625 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
1626 | ||
1627 | if (sleep) { | |
1628 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
1629 | int slpm_output = PIN_SLPM_DIR(cfg); | |
1630 | int slpm_val = PIN_SLPM_VAL(cfg); | |
1631 | ||
1632 | /* All pins go into GPIO mode at sleep */ | |
1633 | gpiomode = true; | |
1634 | ||
1635 | /* | |
1636 | * The SLPM_* values are normal values + 1 to allow zero to | |
1637 | * mean "same as normal". | |
1638 | */ | |
1639 | if (slpm_pull) | |
1640 | pull = slpm_pull - 1; | |
1641 | if (slpm_output) | |
1642 | output = slpm_output - 1; | |
1643 | if (slpm_val) | |
1644 | val = slpm_val - 1; | |
1645 | ||
1646 | dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", | |
1647 | pin, | |
1648 | slpm_pull ? pullnames[pull] : "same", | |
1649 | slpm_output ? (output ? "output" : "input") : "same", | |
1650 | slpm_val ? (val ? "high" : "low") : "same"); | |
1651 | } | |
1652 | ||
1653 | dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", | |
1654 | pin, cfg, pullnames[pull], slpmnames[slpm], | |
1655 | output ? "output " : "input", | |
1656 | output ? (val ? "high" : "low") : "", | |
1657 | lowemi ? "on" : "off" ); | |
1658 | ||
1659 | clk_enable(nmk_chip->clk); | |
1660 | bit = pin % NMK_GPIO_PER_CHIP; | |
1661 | if (gpiomode) | |
1662 | /* No glitch when going to GPIO mode */ | |
1663 | __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); | |
1664 | if (output) | |
1665 | __nmk_gpio_make_output(nmk_chip, bit, val); | |
1666 | else { | |
1667 | __nmk_gpio_make_input(nmk_chip, bit); | |
1668 | __nmk_gpio_set_pull(nmk_chip, bit, pull); | |
1669 | } | |
1670 | /* TODO: isn't this only applicable on output pins? */ | |
1671 | __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); | |
1672 | ||
1673 | __nmk_gpio_set_slpm(nmk_chip, bit, slpm); | |
1674 | clk_disable(nmk_chip->clk); | |
1675 | return 0; | |
1676 | } | |
1677 | ||
1678 | static struct pinconf_ops nmk_pinconf_ops = { | |
1679 | .pin_config_get = nmk_pin_config_get, | |
1680 | .pin_config_set = nmk_pin_config_set, | |
1681 | }; | |
1682 | ||
e98ea774 LW |
1683 | static struct pinctrl_desc nmk_pinctrl_desc = { |
1684 | .name = "pinctrl-nomadik", | |
1685 | .pctlops = &nmk_pinctrl_ops, | |
dbfe8ca2 | 1686 | .pmxops = &nmk_pinmux_ops, |
d41af627 | 1687 | .confops = &nmk_pinconf_ops, |
e98ea774 LW |
1688 | .owner = THIS_MODULE, |
1689 | }; | |
1690 | ||
1691 | static int __devinit nmk_pinctrl_probe(struct platform_device *pdev) | |
1692 | { | |
1693 | const struct platform_device_id *platid = platform_get_device_id(pdev); | |
1694 | struct nmk_pinctrl *npct; | |
1695 | int i; | |
1696 | ||
1697 | npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); | |
1698 | if (!npct) | |
1699 | return -ENOMEM; | |
1700 | ||
1701 | /* Poke in other ASIC variants here */ | |
1702 | if (platid->driver_data == PINCTRL_NMK_DB8500) | |
1703 | nmk_pinctrl_db8500_init(&npct->soc); | |
1704 | ||
1705 | /* | |
1706 | * We need all the GPIO drivers to probe FIRST, or we will not be able | |
1707 | * to obtain references to the struct gpio_chip * for them, and we | |
1708 | * need this to proceed. | |
1709 | */ | |
1710 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) { | |
1711 | if (!nmk_gpio_chips[i]) { | |
1712 | dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); | |
1713 | devm_kfree(&pdev->dev, npct); | |
1714 | return -EPROBE_DEFER; | |
1715 | } | |
1716 | npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[i]->chip; | |
1717 | } | |
1718 | ||
1719 | nmk_pinctrl_desc.pins = npct->soc->pins; | |
1720 | nmk_pinctrl_desc.npins = npct->soc->npins; | |
1721 | npct->dev = &pdev->dev; | |
1722 | npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct); | |
1723 | if (!npct->pctl) { | |
1724 | dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); | |
1725 | return -EINVAL; | |
1726 | } | |
1727 | ||
1728 | /* We will handle a range of GPIO pins */ | |
1729 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) | |
1730 | pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]); | |
1731 | ||
1732 | platform_set_drvdata(pdev, npct); | |
1733 | dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); | |
1734 | ||
1735 | return 0; | |
1736 | } | |
1737 | ||
513c27f8 LJ |
1738 | static const struct of_device_id nmk_gpio_match[] = { |
1739 | { .compatible = "st,nomadik-gpio", }, | |
1740 | {} | |
1741 | }; | |
1742 | ||
3e3c62ca RV |
1743 | static struct platform_driver nmk_gpio_driver = { |
1744 | .driver = { | |
2ec1d359 AR |
1745 | .owner = THIS_MODULE, |
1746 | .name = "gpio", | |
513c27f8 | 1747 | .of_match_table = nmk_gpio_match, |
5317e4d1 | 1748 | }, |
2ec1d359 | 1749 | .probe = nmk_gpio_probe, |
2ec1d359 AR |
1750 | }; |
1751 | ||
e98ea774 LW |
1752 | static const struct platform_device_id nmk_pinctrl_id[] = { |
1753 | { "pinctrl-stn8815", PINCTRL_NMK_STN8815 }, | |
1754 | { "pinctrl-db8500", PINCTRL_NMK_DB8500 }, | |
1755 | }; | |
1756 | ||
1757 | static struct platform_driver nmk_pinctrl_driver = { | |
1758 | .driver = { | |
1759 | .owner = THIS_MODULE, | |
1760 | .name = "pinctrl-nomadik", | |
1761 | }, | |
1762 | .probe = nmk_pinctrl_probe, | |
1763 | .id_table = nmk_pinctrl_id, | |
1764 | }; | |
1765 | ||
2ec1d359 AR |
1766 | static int __init nmk_gpio_init(void) |
1767 | { | |
e98ea774 LW |
1768 | int ret; |
1769 | ||
1770 | ret = platform_driver_register(&nmk_gpio_driver); | |
1771 | if (ret) | |
1772 | return ret; | |
1773 | return platform_driver_register(&nmk_pinctrl_driver); | |
2ec1d359 AR |
1774 | } |
1775 | ||
33f45ea9 | 1776 | core_initcall(nmk_gpio_init); |
2ec1d359 AR |
1777 | |
1778 | MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); | |
1779 | MODULE_DESCRIPTION("Nomadik GPIO Driver"); | |
1780 | MODULE_LICENSE("GPL"); |