Commit | Line | Data |
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2ec1d359 AR |
1 | /* |
2 | * Generic GPIO driver for logic cells found in the Nomadik SoC | |
3 | * | |
4 | * Copyright (C) 2008,2009 STMicroelectronics | |
5 | * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> | |
6 | * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> | |
33d78647 | 7 | * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org> |
2ec1d359 AR |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/device.h> | |
3e3c62ca | 17 | #include <linux/platform_device.h> |
2ec1d359 | 18 | #include <linux/io.h> |
af7dc228 RV |
19 | #include <linux/clk.h> |
20 | #include <linux/err.h> | |
2ec1d359 AR |
21 | #include <linux/gpio.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/irq.h> | |
a60b57ed | 25 | #include <linux/irqdomain.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
855f80cd | 27 | #include <linux/of_device.h> |
32e67eee | 28 | #include <linux/of_address.h> |
e32af889 | 29 | #include <linux/pinctrl/machine.h> |
e98ea774 | 30 | #include <linux/pinctrl/pinctrl.h> |
dbfe8ca2 | 31 | #include <linux/pinctrl/pinmux.h> |
d41af627 | 32 | #include <linux/pinctrl/pinconf.h> |
dbfe8ca2 LW |
33 | /* Since we request GPIOs from ourself */ |
34 | #include <linux/pinctrl/consumer.h> | |
bb16bd9b | 35 | #include <linux/platform_data/pinctrl-nomadik.h> |
adfed159 | 36 | #include <asm/mach/irq.h> |
e98ea774 | 37 | #include "pinctrl-nomadik.h" |
8d99b32d | 38 | #include "core.h" |
e98ea774 | 39 | |
2ec1d359 AR |
40 | /* |
41 | * The GPIO module in the Nomadik family of Systems-on-Chip is an | |
42 | * AMBA device, managing 32 pins and alternate functions. The logic block | |
9c66ee6f | 43 | * is currently used in the Nomadik and ux500. |
2ec1d359 AR |
44 | * |
45 | * Symbols in this file are called "nmk_gpio" for "nomadik gpio" | |
46 | */ | |
47 | ||
2ec1d359 AR |
48 | struct nmk_gpio_chip { |
49 | struct gpio_chip chip; | |
a60b57ed | 50 | struct irq_domain *domain; |
2ec1d359 | 51 | void __iomem *addr; |
af7dc228 | 52 | struct clk *clk; |
33b744b3 | 53 | unsigned int bank; |
2ec1d359 | 54 | unsigned int parent_irq; |
2c8bb0eb | 55 | int secondary_parent_irq; |
33b744b3 | 56 | u32 (*get_secondary_status)(unsigned int bank); |
01727e61 | 57 | void (*set_ioforce)(bool enable); |
c0fcb8db | 58 | spinlock_t lock; |
33d78647 | 59 | bool sleepmode; |
2ec1d359 AR |
60 | /* Keep track of configured edges */ |
61 | u32 edge_rising; | |
62 | u32 edge_falling; | |
b9df468d RV |
63 | u32 real_wake; |
64 | u32 rwimsc; | |
65 | u32 fwimsc; | |
6c12fe88 RV |
66 | u32 rimsc; |
67 | u32 fimsc; | |
bc6f5cf6 | 68 | u32 pull_up; |
ebc6178d | 69 | u32 lowemi; |
2ec1d359 AR |
70 | }; |
71 | ||
f1671bf5 JA |
72 | /** |
73 | * struct nmk_pinctrl - state container for the Nomadik pin controller | |
74 | * @dev: containing device pointer | |
75 | * @pctl: corresponding pin controller device | |
76 | * @soc: SoC data for this specific chip | |
77 | * @prcm_base: PRCM register range virtual base | |
78 | */ | |
e98ea774 LW |
79 | struct nmk_pinctrl { |
80 | struct device *dev; | |
81 | struct pinctrl_dev *pctl; | |
82 | const struct nmk_pinctrl_soc_data *soc; | |
f1671bf5 | 83 | void __iomem *prcm_base; |
e98ea774 LW |
84 | }; |
85 | ||
01727e61 RV |
86 | static struct nmk_gpio_chip * |
87 | nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; | |
88 | ||
89 | static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); | |
90 | ||
91 | #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) | |
92 | ||
6f9a974c RV |
93 | static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, |
94 | unsigned offset, int gpio_mode) | |
95 | { | |
96 | u32 bit = 1 << offset; | |
97 | u32 afunc, bfunc; | |
98 | ||
99 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; | |
100 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; | |
101 | if (gpio_mode & NMK_GPIO_ALT_A) | |
102 | afunc |= bit; | |
103 | if (gpio_mode & NMK_GPIO_ALT_B) | |
104 | bfunc |= bit; | |
105 | writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); | |
106 | writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); | |
107 | } | |
108 | ||
81a3c298 RV |
109 | static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, |
110 | unsigned offset, enum nmk_gpio_slpm mode) | |
111 | { | |
112 | u32 bit = 1 << offset; | |
113 | u32 slpm; | |
114 | ||
115 | slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); | |
116 | if (mode == NMK_GPIO_SLPM_NOCHANGE) | |
117 | slpm |= bit; | |
118 | else | |
119 | slpm &= ~bit; | |
120 | writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); | |
121 | } | |
122 | ||
5b327edf RV |
123 | static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, |
124 | unsigned offset, enum nmk_gpio_pull pull) | |
125 | { | |
126 | u32 bit = 1 << offset; | |
127 | u32 pdis; | |
128 | ||
129 | pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); | |
bc6f5cf6 | 130 | if (pull == NMK_GPIO_PULL_NONE) { |
5b327edf | 131 | pdis |= bit; |
bc6f5cf6 RA |
132 | nmk_chip->pull_up &= ~bit; |
133 | } else { | |
5b327edf | 134 | pdis &= ~bit; |
bc6f5cf6 RA |
135 | } |
136 | ||
5b327edf RV |
137 | writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); |
138 | ||
bc6f5cf6 RA |
139 | if (pull == NMK_GPIO_PULL_UP) { |
140 | nmk_chip->pull_up |= bit; | |
5b327edf | 141 | writel(bit, nmk_chip->addr + NMK_GPIO_DATS); |
bc6f5cf6 RA |
142 | } else if (pull == NMK_GPIO_PULL_DOWN) { |
143 | nmk_chip->pull_up &= ~bit; | |
5b327edf | 144 | writel(bit, nmk_chip->addr + NMK_GPIO_DATC); |
bc6f5cf6 | 145 | } |
5b327edf RV |
146 | } |
147 | ||
ebc6178d RV |
148 | static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, |
149 | unsigned offset, bool lowemi) | |
150 | { | |
151 | u32 bit = BIT(offset); | |
152 | bool enabled = nmk_chip->lowemi & bit; | |
153 | ||
154 | if (lowemi == enabled) | |
155 | return; | |
156 | ||
157 | if (lowemi) | |
158 | nmk_chip->lowemi |= bit; | |
159 | else | |
160 | nmk_chip->lowemi &= ~bit; | |
161 | ||
162 | writel_relaxed(nmk_chip->lowemi, | |
163 | nmk_chip->addr + NMK_GPIO_LOWEMI); | |
164 | } | |
165 | ||
378be066 RV |
166 | static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, |
167 | unsigned offset) | |
168 | { | |
169 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); | |
170 | } | |
171 | ||
6720db7c RV |
172 | static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, |
173 | unsigned offset, int val) | |
174 | { | |
175 | if (val) | |
176 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); | |
177 | else | |
178 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); | |
179 | } | |
180 | ||
181 | static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, | |
182 | unsigned offset, int val) | |
183 | { | |
184 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); | |
185 | __nmk_gpio_set_output(nmk_chip, offset, val); | |
186 | } | |
187 | ||
01727e61 RV |
188 | static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, |
189 | unsigned offset, int gpio_mode, | |
190 | bool glitch) | |
191 | { | |
6c12fe88 RV |
192 | u32 rwimsc = nmk_chip->rwimsc; |
193 | u32 fwimsc = nmk_chip->fwimsc; | |
01727e61 RV |
194 | |
195 | if (glitch && nmk_chip->set_ioforce) { | |
196 | u32 bit = BIT(offset); | |
197 | ||
01727e61 RV |
198 | /* Prevent spurious wakeups */ |
199 | writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
200 | writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
201 | ||
202 | nmk_chip->set_ioforce(true); | |
203 | } | |
204 | ||
205 | __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); | |
206 | ||
207 | if (glitch && nmk_chip->set_ioforce) { | |
208 | nmk_chip->set_ioforce(false); | |
209 | ||
210 | writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
211 | writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
212 | } | |
213 | } | |
214 | ||
6c42ad1c RV |
215 | static void |
216 | nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) | |
217 | { | |
218 | u32 falling = nmk_chip->fimsc & BIT(offset); | |
219 | u32 rising = nmk_chip->rimsc & BIT(offset); | |
220 | int gpio = nmk_chip->chip.base + offset; | |
aa6e379a | 221 | int irq = irq_find_mapping(nmk_chip->domain, offset); |
6c42ad1c RV |
222 | struct irq_data *d = irq_get_irq_data(irq); |
223 | ||
224 | if (!rising && !falling) | |
225 | return; | |
226 | ||
227 | if (!d || !irqd_irq_disabled(d)) | |
228 | return; | |
229 | ||
230 | if (rising) { | |
231 | nmk_chip->rimsc &= ~BIT(offset); | |
232 | writel_relaxed(nmk_chip->rimsc, | |
233 | nmk_chip->addr + NMK_GPIO_RIMSC); | |
234 | } | |
235 | ||
236 | if (falling) { | |
237 | nmk_chip->fimsc &= ~BIT(offset); | |
238 | writel_relaxed(nmk_chip->fimsc, | |
239 | nmk_chip->addr + NMK_GPIO_FIMSC); | |
240 | } | |
241 | ||
242 | dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); | |
243 | } | |
244 | ||
f1671bf5 JA |
245 | static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value) |
246 | { | |
247 | u32 val; | |
248 | ||
249 | val = readl(reg); | |
250 | val = ((val & ~mask) | (value & mask)); | |
251 | writel(val, reg); | |
252 | } | |
253 | ||
c22df08c JNG |
254 | static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct, |
255 | unsigned offset, unsigned alt_num) | |
256 | { | |
257 | int i; | |
258 | u16 reg; | |
259 | u8 bit; | |
260 | u8 alt_index; | |
261 | const struct prcm_gpiocr_altcx_pin_desc *pin_desc; | |
262 | const u16 *gpiocr_regs; | |
263 | ||
4ca075de FB |
264 | if (!npct->prcm_base) |
265 | return; | |
266 | ||
c22df08c JNG |
267 | if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) { |
268 | dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n", | |
269 | alt_num); | |
270 | return; | |
271 | } | |
272 | ||
273 | for (i = 0 ; i < npct->soc->npins_altcx ; i++) { | |
274 | if (npct->soc->altcx_pins[i].pin == offset) | |
275 | break; | |
276 | } | |
277 | if (i == npct->soc->npins_altcx) { | |
278 | dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n", | |
279 | offset); | |
280 | return; | |
281 | } | |
282 | ||
283 | pin_desc = npct->soc->altcx_pins + i; | |
284 | gpiocr_regs = npct->soc->prcm_gpiocr_registers; | |
285 | ||
286 | /* | |
287 | * If alt_num is NULL, just clear current ALTCx selection | |
288 | * to make sure we come back to a pure ALTC selection | |
289 | */ | |
290 | if (!alt_num) { | |
291 | for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { | |
292 | if (pin_desc->altcx[i].used == true) { | |
293 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
294 | bit = pin_desc->altcx[i].control_bit; | |
f1671bf5 JA |
295 | if (readl(npct->prcm_base + reg) & BIT(bit)) { |
296 | nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); | |
c22df08c JNG |
297 | dev_dbg(npct->dev, |
298 | "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", | |
299 | offset, i+1); | |
300 | } | |
301 | } | |
302 | } | |
303 | return; | |
304 | } | |
305 | ||
306 | alt_index = alt_num - 1; | |
307 | if (pin_desc->altcx[alt_index].used == false) { | |
308 | dev_warn(npct->dev, | |
309 | "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n", | |
310 | offset, alt_num); | |
311 | return; | |
312 | } | |
313 | ||
314 | /* | |
315 | * Check if any other ALTCx functions are activated on this pin | |
316 | * and disable it first. | |
317 | */ | |
318 | for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { | |
319 | if (i == alt_index) | |
320 | continue; | |
321 | if (pin_desc->altcx[i].used == true) { | |
322 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
323 | bit = pin_desc->altcx[i].control_bit; | |
f1671bf5 JA |
324 | if (readl(npct->prcm_base + reg) & BIT(bit)) { |
325 | nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); | |
c22df08c JNG |
326 | dev_dbg(npct->dev, |
327 | "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", | |
328 | offset, i+1); | |
329 | } | |
330 | } | |
331 | } | |
332 | ||
333 | reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; | |
334 | bit = pin_desc->altcx[alt_index].control_bit; | |
335 | dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n", | |
336 | offset, alt_index+1); | |
f1671bf5 | 337 | nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); |
c22df08c JNG |
338 | } |
339 | ||
378be066 | 340 | static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, |
01727e61 | 341 | pin_cfg_t cfg, bool sleep, unsigned int *slpmregs) |
378be066 RV |
342 | { |
343 | static const char *afnames[] = { | |
344 | [NMK_GPIO_ALT_GPIO] = "GPIO", | |
345 | [NMK_GPIO_ALT_A] = "A", | |
346 | [NMK_GPIO_ALT_B] = "B", | |
347 | [NMK_GPIO_ALT_C] = "C" | |
348 | }; | |
349 | static const char *pullnames[] = { | |
350 | [NMK_GPIO_PULL_NONE] = "none", | |
351 | [NMK_GPIO_PULL_UP] = "up", | |
352 | [NMK_GPIO_PULL_DOWN] = "down", | |
353 | [3] /* illegal */ = "??" | |
354 | }; | |
355 | static const char *slpmnames[] = { | |
7e3f7e59 RV |
356 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", |
357 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
378be066 RV |
358 | }; |
359 | ||
360 | int pin = PIN_NUM(cfg); | |
361 | int pull = PIN_PULL(cfg); | |
362 | int af = PIN_ALT(cfg); | |
363 | int slpm = PIN_SLPM(cfg); | |
6720db7c RV |
364 | int output = PIN_DIR(cfg); |
365 | int val = PIN_VAL(cfg); | |
01727e61 | 366 | bool glitch = af == NMK_GPIO_ALT_C; |
378be066 | 367 | |
dacdc96c RV |
368 | dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n", |
369 | pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm], | |
6720db7c RV |
370 | output ? "output " : "input", |
371 | output ? (val ? "high" : "low") : ""); | |
372 | ||
dacdc96c RV |
373 | if (sleep) { |
374 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
375 | int slpm_output = PIN_SLPM_DIR(cfg); | |
376 | int slpm_val = PIN_SLPM_VAL(cfg); | |
377 | ||
3546d15c RV |
378 | af = NMK_GPIO_ALT_GPIO; |
379 | ||
dacdc96c RV |
380 | /* |
381 | * The SLPM_* values are normal values + 1 to allow zero to | |
382 | * mean "same as normal". | |
383 | */ | |
384 | if (slpm_pull) | |
385 | pull = slpm_pull - 1; | |
386 | if (slpm_output) | |
387 | output = slpm_output - 1; | |
388 | if (slpm_val) | |
389 | val = slpm_val - 1; | |
390 | ||
391 | dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", | |
392 | pin, | |
393 | slpm_pull ? pullnames[pull] : "same", | |
394 | slpm_output ? (output ? "output" : "input") : "same", | |
395 | slpm_val ? (val ? "high" : "low") : "same"); | |
396 | } | |
397 | ||
6720db7c RV |
398 | if (output) |
399 | __nmk_gpio_make_output(nmk_chip, offset, val); | |
400 | else { | |
401 | __nmk_gpio_make_input(nmk_chip, offset); | |
402 | __nmk_gpio_set_pull(nmk_chip, offset, pull); | |
403 | } | |
378be066 | 404 | |
ebc6178d RV |
405 | __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg)); |
406 | ||
6c42ad1c RV |
407 | /* |
408 | * If the pin is switching to altfunc, and there was an interrupt | |
409 | * installed on it which has been lazy disabled, actually mask the | |
410 | * interrupt to prevent spurious interrupts that would occur while the | |
411 | * pin is under control of the peripheral. Only SKE does this. | |
412 | */ | |
413 | if (af != NMK_GPIO_ALT_GPIO) | |
414 | nmk_gpio_disable_lazy_irq(nmk_chip, offset); | |
415 | ||
01727e61 RV |
416 | /* |
417 | * If we've backed up the SLPM registers (glitch workaround), modify | |
418 | * the backups since they will be restored. | |
419 | */ | |
420 | if (slpmregs) { | |
421 | if (slpm == NMK_GPIO_SLPM_NOCHANGE) | |
422 | slpmregs[nmk_chip->bank] |= BIT(offset); | |
423 | else | |
424 | slpmregs[nmk_chip->bank] &= ~BIT(offset); | |
425 | } else | |
426 | __nmk_gpio_set_slpm(nmk_chip, offset, slpm); | |
427 | ||
428 | __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch); | |
429 | } | |
430 | ||
431 | /* | |
432 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
433 | * - Save SLPM registers | |
434 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
435 | * - Configure the GPIO registers for the IOs that are being switched | |
436 | * - Set IOFORCE=1 | |
437 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
438 | * - Set IOFORCE=0 | |
439 | * - Restore SLPM registers | |
440 | * - Any spurious wake up event during switch sequence to be ignored and | |
441 | * cleared | |
442 | */ | |
443 | static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) | |
444 | { | |
445 | int i; | |
446 | ||
447 | for (i = 0; i < NUM_BANKS; i++) { | |
448 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
449 | unsigned int temp = slpm[i]; | |
450 | ||
451 | if (!chip) | |
452 | break; | |
453 | ||
3c0227d2 RV |
454 | clk_enable(chip->clk); |
455 | ||
01727e61 RV |
456 | slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); |
457 | writel(temp, chip->addr + NMK_GPIO_SLPC); | |
458 | } | |
459 | } | |
460 | ||
461 | static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) | |
462 | { | |
463 | int i; | |
464 | ||
465 | for (i = 0; i < NUM_BANKS; i++) { | |
466 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
467 | ||
468 | if (!chip) | |
469 | break; | |
470 | ||
471 | writel(slpm[i], chip->addr + NMK_GPIO_SLPC); | |
3c0227d2 RV |
472 | |
473 | clk_disable(chip->clk); | |
01727e61 RV |
474 | } |
475 | } | |
476 | ||
477 | static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) | |
478 | { | |
479 | static unsigned int slpm[NUM_BANKS]; | |
480 | unsigned long flags; | |
481 | bool glitch = false; | |
482 | int ret = 0; | |
483 | int i; | |
484 | ||
485 | for (i = 0; i < num; i++) { | |
486 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) { | |
487 | glitch = true; | |
488 | break; | |
489 | } | |
490 | } | |
491 | ||
492 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | |
493 | ||
494 | if (glitch) { | |
495 | memset(slpm, 0xff, sizeof(slpm)); | |
496 | ||
497 | for (i = 0; i < num; i++) { | |
498 | int pin = PIN_NUM(cfgs[i]); | |
499 | int offset = pin % NMK_GPIO_PER_CHIP; | |
500 | ||
501 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) | |
502 | slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset); | |
503 | } | |
504 | ||
505 | nmk_gpio_glitch_slpm_init(slpm); | |
506 | } | |
507 | ||
508 | for (i = 0; i < num; i++) { | |
509 | struct nmk_gpio_chip *nmk_chip; | |
510 | int pin = PIN_NUM(cfgs[i]); | |
511 | ||
a60b57ed | 512 | nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP]; |
01727e61 RV |
513 | if (!nmk_chip) { |
514 | ret = -EINVAL; | |
515 | break; | |
516 | } | |
517 | ||
3c0227d2 | 518 | clk_enable(nmk_chip->clk); |
01727e61 | 519 | spin_lock(&nmk_chip->lock); |
a60b57ed | 520 | __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP, |
01727e61 RV |
521 | cfgs[i], sleep, glitch ? slpm : NULL); |
522 | spin_unlock(&nmk_chip->lock); | |
3c0227d2 | 523 | clk_disable(nmk_chip->clk); |
01727e61 RV |
524 | } |
525 | ||
526 | if (glitch) | |
527 | nmk_gpio_glitch_slpm_restore(slpm); | |
528 | ||
529 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
530 | ||
531 | return ret; | |
378be066 RV |
532 | } |
533 | ||
534 | /** | |
535 | * nmk_config_pin - configure a pin's mux attributes | |
536 | * @cfg: pin confguration | |
50bcd47c | 537 | * @sleep: Non-zero to apply the sleep mode configuration |
378be066 RV |
538 | * Configures a pin's mode (alternate function or GPIO), its pull up status, |
539 | * and its sleep mode based on the specified configuration. The @cfg is | |
540 | * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These | |
541 | * are constructed using, and can be further enhanced with, the macros in | |
287f121c | 542 | * <linux/platform_data/pinctrl-nomadik.h> |
378be066 RV |
543 | * |
544 | * If a pin's mode is set to GPIO, it is configured as an input to avoid | |
545 | * side-effects. The gpio can be manipulated later using standard GPIO API | |
546 | * calls. | |
547 | */ | |
dacdc96c | 548 | int nmk_config_pin(pin_cfg_t cfg, bool sleep) |
378be066 | 549 | { |
01727e61 | 550 | return __nmk_config_pins(&cfg, 1, sleep); |
378be066 RV |
551 | } |
552 | EXPORT_SYMBOL(nmk_config_pin); | |
553 | ||
554 | /** | |
555 | * nmk_config_pins - configure several pins at once | |
556 | * @cfgs: array of pin configurations | |
557 | * @num: number of elments in the array | |
558 | * | |
559 | * Configures several pins using nmk_config_pin(). Refer to that function for | |
560 | * further information. | |
561 | */ | |
562 | int nmk_config_pins(pin_cfg_t *cfgs, int num) | |
563 | { | |
01727e61 | 564 | return __nmk_config_pins(cfgs, num, false); |
378be066 RV |
565 | } |
566 | EXPORT_SYMBOL(nmk_config_pins); | |
567 | ||
dacdc96c RV |
568 | int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num) |
569 | { | |
01727e61 | 570 | return __nmk_config_pins(cfgs, num, true); |
dacdc96c RV |
571 | } |
572 | EXPORT_SYMBOL(nmk_config_pins_sleep); | |
573 | ||
81a3c298 RV |
574 | /** |
575 | * nmk_gpio_set_slpm() - configure the sleep mode of a pin | |
576 | * @gpio: pin number | |
577 | * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE, | |
578 | * | |
33d78647 LW |
579 | * This register is actually in the pinmux layer, not the GPIO block itself. |
580 | * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP | |
581 | * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code). | |
582 | * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is | |
583 | * HIGH, overriding the normal setting defined by GPIO_AFSELx registers. | |
584 | * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit), | |
585 | * the GPIOs return to the normal setting defined by GPIO_AFSELx registers. | |
7e3f7e59 | 586 | * |
33d78647 LW |
587 | * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO |
588 | * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is | |
589 | * entered) regardless of the altfunction selected. Also wake-up detection is | |
590 | * ENABLED. | |
591 | * | |
592 | * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains | |
593 | * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS | |
594 | * (for altfunction GPIO) or respective on-chip peripherals (for other | |
595 | * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED. | |
596 | * | |
597 | * Note that enable_irq_wake() will automatically enable wakeup detection. | |
81a3c298 RV |
598 | */ |
599 | int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) | |
600 | { | |
601 | struct nmk_gpio_chip *nmk_chip; | |
602 | unsigned long flags; | |
603 | ||
a60b57ed | 604 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
81a3c298 RV |
605 | if (!nmk_chip) |
606 | return -EINVAL; | |
607 | ||
3c0227d2 | 608 | clk_enable(nmk_chip->clk); |
01727e61 RV |
609 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
610 | spin_lock(&nmk_chip->lock); | |
611 | ||
a60b57ed | 612 | __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode); |
01727e61 RV |
613 | |
614 | spin_unlock(&nmk_chip->lock); | |
615 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 616 | clk_disable(nmk_chip->clk); |
81a3c298 RV |
617 | |
618 | return 0; | |
619 | } | |
620 | ||
5b327edf RV |
621 | /** |
622 | * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio | |
623 | * @gpio: pin number | |
624 | * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE | |
625 | * | |
626 | * Enables/disables pull up/down on a specified pin. This only takes effect if | |
627 | * the pin is configured as an input (either explicitly or by the alternate | |
628 | * function). | |
629 | * | |
630 | * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is | |
631 | * configured as an input. Otherwise, due to the way the controller registers | |
632 | * work, this function will change the value output on the pin. | |
633 | */ | |
634 | int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) | |
635 | { | |
636 | struct nmk_gpio_chip *nmk_chip; | |
637 | unsigned long flags; | |
638 | ||
a60b57ed | 639 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
5b327edf RV |
640 | if (!nmk_chip) |
641 | return -EINVAL; | |
642 | ||
3c0227d2 | 643 | clk_enable(nmk_chip->clk); |
5b327edf | 644 | spin_lock_irqsave(&nmk_chip->lock, flags); |
a60b57ed | 645 | __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull); |
5b327edf | 646 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 647 | clk_disable(nmk_chip->clk); |
5b327edf RV |
648 | |
649 | return 0; | |
650 | } | |
651 | ||
2ec1d359 | 652 | /* Mode functions */ |
9c66ee6f JA |
653 | /** |
654 | * nmk_gpio_set_mode() - set the mux mode of a gpio pin | |
655 | * @gpio: pin number | |
656 | * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A, | |
657 | * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C | |
658 | * | |
659 | * Sets the mode of the specified pin to one of the alternate functions or | |
660 | * plain GPIO. | |
661 | */ | |
2ec1d359 AR |
662 | int nmk_gpio_set_mode(int gpio, int gpio_mode) |
663 | { | |
664 | struct nmk_gpio_chip *nmk_chip; | |
665 | unsigned long flags; | |
2ec1d359 | 666 | |
a60b57ed | 667 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
2ec1d359 AR |
668 | if (!nmk_chip) |
669 | return -EINVAL; | |
670 | ||
3c0227d2 | 671 | clk_enable(nmk_chip->clk); |
2ec1d359 | 672 | spin_lock_irqsave(&nmk_chip->lock, flags); |
a60b57ed | 673 | __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode); |
2ec1d359 | 674 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 675 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
676 | |
677 | return 0; | |
678 | } | |
679 | EXPORT_SYMBOL(nmk_gpio_set_mode); | |
680 | ||
0fafd50e | 681 | static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio) |
2249b19f JNG |
682 | { |
683 | int i; | |
684 | u16 reg; | |
685 | u8 bit; | |
686 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
687 | const struct prcm_gpiocr_altcx_pin_desc *pin_desc; | |
688 | const u16 *gpiocr_regs; | |
689 | ||
4ca075de FB |
690 | if (!npct->prcm_base) |
691 | return NMK_GPIO_ALT_C; | |
692 | ||
2249b19f JNG |
693 | for (i = 0; i < npct->soc->npins_altcx; i++) { |
694 | if (npct->soc->altcx_pins[i].pin == gpio) | |
695 | break; | |
696 | } | |
697 | if (i == npct->soc->npins_altcx) | |
698 | return NMK_GPIO_ALT_C; | |
699 | ||
700 | pin_desc = npct->soc->altcx_pins + i; | |
701 | gpiocr_regs = npct->soc->prcm_gpiocr_registers; | |
702 | for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) { | |
703 | if (pin_desc->altcx[i].used == true) { | |
704 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
705 | bit = pin_desc->altcx[i].control_bit; | |
f1671bf5 | 706 | if (readl(npct->prcm_base + reg) & BIT(bit)) |
2249b19f JNG |
707 | return NMK_GPIO_ALT_C+i+1; |
708 | } | |
709 | } | |
710 | return NMK_GPIO_ALT_C; | |
711 | } | |
712 | ||
2ec1d359 AR |
713 | int nmk_gpio_get_mode(int gpio) |
714 | { | |
715 | struct nmk_gpio_chip *nmk_chip; | |
716 | u32 afunc, bfunc, bit; | |
717 | ||
a60b57ed | 718 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
2ec1d359 AR |
719 | if (!nmk_chip) |
720 | return -EINVAL; | |
721 | ||
a60b57ed | 722 | bit = 1 << (gpio % NMK_GPIO_PER_CHIP); |
2ec1d359 | 723 | |
3c0227d2 RV |
724 | clk_enable(nmk_chip->clk); |
725 | ||
2ec1d359 AR |
726 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; |
727 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; | |
728 | ||
3c0227d2 RV |
729 | clk_disable(nmk_chip->clk); |
730 | ||
2ec1d359 AR |
731 | return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); |
732 | } | |
733 | EXPORT_SYMBOL(nmk_gpio_get_mode); | |
734 | ||
735 | ||
736 | /* IRQ functions */ | |
737 | static inline int nmk_gpio_get_bitmask(int gpio) | |
738 | { | |
a60b57ed | 739 | return 1 << (gpio % NMK_GPIO_PER_CHIP); |
2ec1d359 AR |
740 | } |
741 | ||
f272c00e | 742 | static void nmk_gpio_irq_ack(struct irq_data *d) |
2ec1d359 | 743 | { |
2ec1d359 AR |
744 | struct nmk_gpio_chip *nmk_chip; |
745 | ||
f272c00e | 746 | nmk_chip = irq_data_get_irq_chip_data(d); |
2ec1d359 AR |
747 | if (!nmk_chip) |
748 | return; | |
3c0227d2 RV |
749 | |
750 | clk_enable(nmk_chip->clk); | |
a60b57ed | 751 | writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); |
3c0227d2 | 752 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
753 | } |
754 | ||
4d4e20f7 RV |
755 | enum nmk_gpio_irq_type { |
756 | NORMAL, | |
757 | WAKE, | |
758 | }; | |
759 | ||
040e5ecd | 760 | static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, |
4d4e20f7 RV |
761 | int gpio, enum nmk_gpio_irq_type which, |
762 | bool enable) | |
2ec1d359 | 763 | { |
040e5ecd | 764 | u32 bitmask = nmk_gpio_get_bitmask(gpio); |
6c12fe88 RV |
765 | u32 *rimscval; |
766 | u32 *fimscval; | |
767 | u32 rimscreg; | |
768 | u32 fimscreg; | |
769 | ||
770 | if (which == NORMAL) { | |
771 | rimscreg = NMK_GPIO_RIMSC; | |
772 | fimscreg = NMK_GPIO_FIMSC; | |
773 | rimscval = &nmk_chip->rimsc; | |
774 | fimscval = &nmk_chip->fimsc; | |
775 | } else { | |
776 | rimscreg = NMK_GPIO_RWIMSC; | |
777 | fimscreg = NMK_GPIO_FWIMSC; | |
778 | rimscval = &nmk_chip->rwimsc; | |
779 | fimscval = &nmk_chip->fwimsc; | |
780 | } | |
2ec1d359 | 781 | |
040e5ecd | 782 | /* we must individually set/clear the two edges */ |
2ec1d359 | 783 | if (nmk_chip->edge_rising & bitmask) { |
040e5ecd | 784 | if (enable) |
6c12fe88 | 785 | *rimscval |= bitmask; |
040e5ecd | 786 | else |
6c12fe88 RV |
787 | *rimscval &= ~bitmask; |
788 | writel(*rimscval, nmk_chip->addr + rimscreg); | |
2ec1d359 AR |
789 | } |
790 | if (nmk_chip->edge_falling & bitmask) { | |
040e5ecd | 791 | if (enable) |
6c12fe88 | 792 | *fimscval |= bitmask; |
040e5ecd | 793 | else |
6c12fe88 RV |
794 | *fimscval &= ~bitmask; |
795 | writel(*fimscval, nmk_chip->addr + fimscreg); | |
2ec1d359 | 796 | } |
040e5ecd | 797 | } |
2ec1d359 | 798 | |
b9df468d RV |
799 | static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, |
800 | int gpio, bool on) | |
801 | { | |
b982ff0e RV |
802 | /* |
803 | * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is | |
804 | * disabled, since setting SLPM to 1 increases power consumption, and | |
805 | * wakeup is anyhow controlled by the RIMSC and FIMSC registers. | |
806 | */ | |
807 | if (nmk_chip->sleepmode && on) { | |
e85bbc19 | 808 | __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, |
b982ff0e | 809 | NMK_GPIO_SLPM_WAKEUP_ENABLE); |
33d78647 LW |
810 | } |
811 | ||
b9df468d RV |
812 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); |
813 | } | |
814 | ||
815 | static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) | |
2ec1d359 | 816 | { |
2ec1d359 AR |
817 | struct nmk_gpio_chip *nmk_chip; |
818 | unsigned long flags; | |
040e5ecd | 819 | u32 bitmask; |
2ec1d359 | 820 | |
f272c00e | 821 | nmk_chip = irq_data_get_irq_chip_data(d); |
a60b57ed | 822 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
2ec1d359 | 823 | if (!nmk_chip) |
4d4e20f7 | 824 | return -EINVAL; |
2ec1d359 | 825 | |
3c0227d2 | 826 | clk_enable(nmk_chip->clk); |
b9df468d RV |
827 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
828 | spin_lock(&nmk_chip->lock); | |
829 | ||
a60b57ed | 830 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); |
b9df468d RV |
831 | |
832 | if (!(nmk_chip->real_wake & bitmask)) | |
a60b57ed | 833 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); |
b9df468d RV |
834 | |
835 | spin_unlock(&nmk_chip->lock); | |
836 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 837 | clk_disable(nmk_chip->clk); |
4d4e20f7 RV |
838 | |
839 | return 0; | |
2ec1d359 AR |
840 | } |
841 | ||
f272c00e | 842 | static void nmk_gpio_irq_mask(struct irq_data *d) |
040e5ecd | 843 | { |
b9df468d | 844 | nmk_gpio_irq_maskunmask(d, false); |
4d4e20f7 | 845 | } |
040e5ecd | 846 | |
f272c00e | 847 | static void nmk_gpio_irq_unmask(struct irq_data *d) |
040e5ecd | 848 | { |
b9df468d | 849 | nmk_gpio_irq_maskunmask(d, true); |
4d4e20f7 RV |
850 | } |
851 | ||
f272c00e | 852 | static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
4d4e20f7 | 853 | { |
7e3f7e59 RV |
854 | struct nmk_gpio_chip *nmk_chip; |
855 | unsigned long flags; | |
b9df468d | 856 | u32 bitmask; |
7e3f7e59 | 857 | |
f272c00e | 858 | nmk_chip = irq_data_get_irq_chip_data(d); |
7e3f7e59 RV |
859 | if (!nmk_chip) |
860 | return -EINVAL; | |
a60b57ed | 861 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
7e3f7e59 | 862 | |
3c0227d2 | 863 | clk_enable(nmk_chip->clk); |
01727e61 RV |
864 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
865 | spin_lock(&nmk_chip->lock); | |
866 | ||
479a0c7e | 867 | if (irqd_irq_disabled(d)) |
a60b57ed | 868 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); |
b9df468d RV |
869 | |
870 | if (on) | |
871 | nmk_chip->real_wake |= bitmask; | |
872 | else | |
873 | nmk_chip->real_wake &= ~bitmask; | |
01727e61 RV |
874 | |
875 | spin_unlock(&nmk_chip->lock); | |
876 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 877 | clk_disable(nmk_chip->clk); |
7e3f7e59 RV |
878 | |
879 | return 0; | |
040e5ecd RV |
880 | } |
881 | ||
f272c00e | 882 | static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
2ec1d359 | 883 | { |
479a0c7e | 884 | bool enabled = !irqd_irq_disabled(d); |
3c0227d2 | 885 | bool wake = irqd_is_wakeup_set(d); |
2ec1d359 AR |
886 | struct nmk_gpio_chip *nmk_chip; |
887 | unsigned long flags; | |
888 | u32 bitmask; | |
889 | ||
f272c00e | 890 | nmk_chip = irq_data_get_irq_chip_data(d); |
a60b57ed | 891 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
2ec1d359 AR |
892 | if (!nmk_chip) |
893 | return -EINVAL; | |
2ec1d359 AR |
894 | if (type & IRQ_TYPE_LEVEL_HIGH) |
895 | return -EINVAL; | |
896 | if (type & IRQ_TYPE_LEVEL_LOW) | |
897 | return -EINVAL; | |
898 | ||
3c0227d2 | 899 | clk_enable(nmk_chip->clk); |
2ec1d359 AR |
900 | spin_lock_irqsave(&nmk_chip->lock, flags); |
901 | ||
7a852d80 | 902 | if (enabled) |
a60b57ed | 903 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); |
4d4e20f7 | 904 | |
b9df468d | 905 | if (enabled || wake) |
a60b57ed | 906 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); |
7a852d80 | 907 | |
2ec1d359 AR |
908 | nmk_chip->edge_rising &= ~bitmask; |
909 | if (type & IRQ_TYPE_EDGE_RISING) | |
910 | nmk_chip->edge_rising |= bitmask; | |
2ec1d359 AR |
911 | |
912 | nmk_chip->edge_falling &= ~bitmask; | |
913 | if (type & IRQ_TYPE_EDGE_FALLING) | |
914 | nmk_chip->edge_falling |= bitmask; | |
2ec1d359 | 915 | |
7a852d80 | 916 | if (enabled) |
a60b57ed | 917 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); |
4d4e20f7 | 918 | |
b9df468d | 919 | if (enabled || wake) |
a60b57ed | 920 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); |
2ec1d359 | 921 | |
7a852d80 | 922 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 923 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
924 | |
925 | return 0; | |
926 | } | |
927 | ||
3c0227d2 RV |
928 | static unsigned int nmk_gpio_irq_startup(struct irq_data *d) |
929 | { | |
930 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 | 931 | |
3c0227d2 RV |
932 | clk_enable(nmk_chip->clk); |
933 | nmk_gpio_irq_unmask(d); | |
2ec1d359 AR |
934 | return 0; |
935 | } | |
936 | ||
3c0227d2 RV |
937 | static void nmk_gpio_irq_shutdown(struct irq_data *d) |
938 | { | |
939 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
940 | ||
941 | nmk_gpio_irq_mask(d); | |
942 | clk_disable(nmk_chip->clk); | |
943 | } | |
944 | ||
2ec1d359 AR |
945 | static struct irq_chip nmk_gpio_irq_chip = { |
946 | .name = "Nomadik-GPIO", | |
f272c00e LB |
947 | .irq_ack = nmk_gpio_irq_ack, |
948 | .irq_mask = nmk_gpio_irq_mask, | |
949 | .irq_unmask = nmk_gpio_irq_unmask, | |
950 | .irq_set_type = nmk_gpio_irq_set_type, | |
951 | .irq_set_wake = nmk_gpio_irq_set_wake, | |
3c0227d2 RV |
952 | .irq_startup = nmk_gpio_irq_startup, |
953 | .irq_shutdown = nmk_gpio_irq_shutdown, | |
4921e745 | 954 | .flags = IRQCHIP_MASK_ON_SUSPEND, |
2ec1d359 AR |
955 | }; |
956 | ||
33b744b3 RV |
957 | static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, |
958 | u32 status) | |
2ec1d359 AR |
959 | { |
960 | struct nmk_gpio_chip *nmk_chip; | |
6845664a | 961 | struct irq_chip *host_chip = irq_get_chip(irq); |
2ec1d359 | 962 | |
adfed159 | 963 | chained_irq_enter(host_chip, desc); |
aaedaa2b | 964 | |
6845664a | 965 | nmk_chip = irq_get_handler_data(irq); |
33b744b3 RV |
966 | while (status) { |
967 | int bit = __ffs(status); | |
968 | ||
95f0bc9b | 969 | generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit)); |
33b744b3 | 970 | status &= ~BIT(bit); |
2ec1d359 | 971 | } |
aaedaa2b | 972 | |
adfed159 | 973 | chained_irq_exit(host_chip, desc); |
2ec1d359 AR |
974 | } |
975 | ||
33b744b3 RV |
976 | static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
977 | { | |
6845664a | 978 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
3c0227d2 RV |
979 | u32 status; |
980 | ||
981 | clk_enable(nmk_chip->clk); | |
982 | status = readl(nmk_chip->addr + NMK_GPIO_IS); | |
983 | clk_disable(nmk_chip->clk); | |
33b744b3 RV |
984 | |
985 | __nmk_gpio_irq_handler(irq, desc, status); | |
986 | } | |
987 | ||
988 | static void nmk_gpio_secondary_irq_handler(unsigned int irq, | |
989 | struct irq_desc *desc) | |
990 | { | |
6845664a | 991 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
33b744b3 RV |
992 | u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); |
993 | ||
994 | __nmk_gpio_irq_handler(irq, desc, status); | |
995 | } | |
996 | ||
2ec1d359 AR |
997 | static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) |
998 | { | |
6845664a TG |
999 | irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); |
1000 | irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); | |
33b744b3 RV |
1001 | |
1002 | if (nmk_chip->secondary_parent_irq >= 0) { | |
6845664a | 1003 | irq_set_chained_handler(nmk_chip->secondary_parent_irq, |
33b744b3 | 1004 | nmk_gpio_secondary_irq_handler); |
6845664a | 1005 | irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); |
33b744b3 RV |
1006 | } |
1007 | ||
2ec1d359 AR |
1008 | return 0; |
1009 | } | |
1010 | ||
1011 | /* I/O Functions */ | |
dbfe8ca2 LW |
1012 | |
1013 | static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset) | |
1014 | { | |
1015 | /* | |
1016 | * Map back to global GPIO space and request muxing, the direction | |
1017 | * parameter does not matter for this controller. | |
1018 | */ | |
1019 | int gpio = chip->base + offset; | |
1020 | ||
1021 | return pinctrl_request_gpio(gpio); | |
1022 | } | |
1023 | ||
1024 | static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset) | |
1025 | { | |
1026 | int gpio = chip->base + offset; | |
1027 | ||
1028 | pinctrl_free_gpio(gpio); | |
1029 | } | |
1030 | ||
2ec1d359 AR |
1031 | static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) |
1032 | { | |
1033 | struct nmk_gpio_chip *nmk_chip = | |
1034 | container_of(chip, struct nmk_gpio_chip, chip); | |
1035 | ||
3c0227d2 RV |
1036 | clk_enable(nmk_chip->clk); |
1037 | ||
2ec1d359 | 1038 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); |
3c0227d2 RV |
1039 | |
1040 | clk_disable(nmk_chip->clk); | |
1041 | ||
2ec1d359 AR |
1042 | return 0; |
1043 | } | |
1044 | ||
2ec1d359 AR |
1045 | static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) |
1046 | { | |
1047 | struct nmk_gpio_chip *nmk_chip = | |
1048 | container_of(chip, struct nmk_gpio_chip, chip); | |
1049 | u32 bit = 1 << offset; | |
3c0227d2 RV |
1050 | int value; |
1051 | ||
1052 | clk_enable(nmk_chip->clk); | |
2ec1d359 | 1053 | |
3c0227d2 | 1054 | value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; |
2ec1d359 | 1055 | |
3c0227d2 RV |
1056 | clk_disable(nmk_chip->clk); |
1057 | ||
1058 | return value; | |
2ec1d359 AR |
1059 | } |
1060 | ||
1061 | static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, | |
1062 | int val) | |
1063 | { | |
1064 | struct nmk_gpio_chip *nmk_chip = | |
1065 | container_of(chip, struct nmk_gpio_chip, chip); | |
2ec1d359 | 1066 | |
3c0227d2 RV |
1067 | clk_enable(nmk_chip->clk); |
1068 | ||
6720db7c | 1069 | __nmk_gpio_set_output(nmk_chip, offset, val); |
3c0227d2 RV |
1070 | |
1071 | clk_disable(nmk_chip->clk); | |
2ec1d359 AR |
1072 | } |
1073 | ||
6647c6c0 RV |
1074 | static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, |
1075 | int val) | |
1076 | { | |
1077 | struct nmk_gpio_chip *nmk_chip = | |
1078 | container_of(chip, struct nmk_gpio_chip, chip); | |
1079 | ||
3c0227d2 RV |
1080 | clk_enable(nmk_chip->clk); |
1081 | ||
6720db7c | 1082 | __nmk_gpio_make_output(nmk_chip, offset, val); |
6647c6c0 | 1083 | |
3c0227d2 RV |
1084 | clk_disable(nmk_chip->clk); |
1085 | ||
6647c6c0 RV |
1086 | return 0; |
1087 | } | |
1088 | ||
0d2aec9c RV |
1089 | static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
1090 | { | |
1091 | struct nmk_gpio_chip *nmk_chip = | |
1092 | container_of(chip, struct nmk_gpio_chip, chip); | |
1093 | ||
268300be | 1094 | return irq_create_mapping(nmk_chip->domain, offset); |
0d2aec9c RV |
1095 | } |
1096 | ||
d0b543c7 RV |
1097 | #ifdef CONFIG_DEBUG_FS |
1098 | ||
1099 | #include <linux/seq_file.h> | |
1100 | ||
2249b19f JNG |
1101 | static void nmk_gpio_dbg_show_one(struct seq_file *s, |
1102 | struct pinctrl_dev *pctldev, struct gpio_chip *chip, | |
1103 | unsigned offset, unsigned gpio) | |
d0b543c7 | 1104 | { |
6f4350a6 | 1105 | const char *label = gpiochip_is_requested(chip, offset); |
d0b543c7 RV |
1106 | struct nmk_gpio_chip *nmk_chip = |
1107 | container_of(chip, struct nmk_gpio_chip, chip); | |
6f4350a6 LW |
1108 | int mode; |
1109 | bool is_out; | |
1110 | bool pull; | |
1111 | u32 bit = 1 << offset; | |
d0b543c7 RV |
1112 | const char *modes[] = { |
1113 | [NMK_GPIO_ALT_GPIO] = "gpio", | |
1114 | [NMK_GPIO_ALT_A] = "altA", | |
1115 | [NMK_GPIO_ALT_B] = "altB", | |
1116 | [NMK_GPIO_ALT_C] = "altC", | |
2249b19f JNG |
1117 | [NMK_GPIO_ALT_C+1] = "altC1", |
1118 | [NMK_GPIO_ALT_C+2] = "altC2", | |
1119 | [NMK_GPIO_ALT_C+3] = "altC3", | |
1120 | [NMK_GPIO_ALT_C+4] = "altC4", | |
d0b543c7 RV |
1121 | }; |
1122 | ||
3c0227d2 | 1123 | clk_enable(nmk_chip->clk); |
6f4350a6 LW |
1124 | is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit); |
1125 | pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); | |
1126 | mode = nmk_gpio_get_mode(gpio); | |
2249b19f JNG |
1127 | if ((mode == NMK_GPIO_ALT_C) && pctldev) |
1128 | mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); | |
6f4350a6 LW |
1129 | |
1130 | seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", | |
1131 | gpio, label ?: "(none)", | |
1132 | is_out ? "out" : "in ", | |
1133 | chip->get | |
1134 | ? (chip->get(chip, offset) ? "hi" : "lo") | |
1135 | : "? ", | |
1136 | (mode < 0) ? "unknown" : modes[mode], | |
1137 | pull ? "pull" : "none"); | |
1138 | ||
1139 | if (label && !is_out) { | |
1140 | int irq = gpio_to_irq(gpio); | |
1141 | struct irq_desc *desc = irq_to_desc(irq); | |
1142 | ||
1143 | /* This races with request_irq(), set_irq_type(), | |
1144 | * and set_irq_wake() ... but those are "rare". | |
1145 | */ | |
1146 | if (irq >= 0 && desc->action) { | |
1147 | char *trigger; | |
1148 | u32 bitmask = nmk_gpio_get_bitmask(gpio); | |
1149 | ||
1150 | if (nmk_chip->edge_rising & bitmask) | |
1151 | trigger = "edge-rising"; | |
1152 | else if (nmk_chip->edge_falling & bitmask) | |
1153 | trigger = "edge-falling"; | |
1154 | else | |
1155 | trigger = "edge-undefined"; | |
1156 | ||
1157 | seq_printf(s, " irq-%d %s%s", | |
1158 | irq, trigger, | |
1159 | irqd_is_wakeup_set(&desc->irq_data) | |
1160 | ? " wakeup" : ""); | |
8ea72a30 | 1161 | } |
6f4350a6 LW |
1162 | } |
1163 | clk_disable(nmk_chip->clk); | |
1164 | } | |
1165 | ||
1166 | static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
1167 | { | |
1168 | unsigned i; | |
1169 | unsigned gpio = chip->base; | |
8ea72a30 | 1170 | |
6f4350a6 | 1171 | for (i = 0; i < chip->ngpio; i++, gpio++) { |
2249b19f | 1172 | nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio); |
d0b543c7 RV |
1173 | seq_printf(s, "\n"); |
1174 | } | |
1175 | } | |
1176 | ||
1177 | #else | |
6f4350a6 | 1178 | static inline void nmk_gpio_dbg_show_one(struct seq_file *s, |
2249b19f | 1179 | struct pinctrl_dev *pctldev, |
6f4350a6 LW |
1180 | struct gpio_chip *chip, |
1181 | unsigned offset, unsigned gpio) | |
1182 | { | |
1183 | } | |
d0b543c7 RV |
1184 | #define nmk_gpio_dbg_show NULL |
1185 | #endif | |
1186 | ||
2ec1d359 AR |
1187 | /* This structure is replicated for each GPIO block allocated at probe time */ |
1188 | static struct gpio_chip nmk_gpio_template = { | |
dbfe8ca2 LW |
1189 | .request = nmk_gpio_request, |
1190 | .free = nmk_gpio_free, | |
2ec1d359 AR |
1191 | .direction_input = nmk_gpio_make_input, |
1192 | .get = nmk_gpio_get_input, | |
1193 | .direction_output = nmk_gpio_make_output, | |
1194 | .set = nmk_gpio_set_output, | |
0d2aec9c | 1195 | .to_irq = nmk_gpio_to_irq, |
d0b543c7 | 1196 | .dbg_show = nmk_gpio_dbg_show, |
2ec1d359 AR |
1197 | .can_sleep = 0, |
1198 | }; | |
1199 | ||
3c0227d2 RV |
1200 | void nmk_gpio_clocks_enable(void) |
1201 | { | |
1202 | int i; | |
1203 | ||
1204 | for (i = 0; i < NUM_BANKS; i++) { | |
1205 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1206 | ||
1207 | if (!chip) | |
1208 | continue; | |
1209 | ||
1210 | clk_enable(chip->clk); | |
1211 | } | |
1212 | } | |
1213 | ||
1214 | void nmk_gpio_clocks_disable(void) | |
1215 | { | |
1216 | int i; | |
1217 | ||
1218 | for (i = 0; i < NUM_BANKS; i++) { | |
1219 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1220 | ||
1221 | if (!chip) | |
1222 | continue; | |
1223 | ||
1224 | clk_disable(chip->clk); | |
1225 | } | |
1226 | } | |
1227 | ||
b9df468d RV |
1228 | /* |
1229 | * Called from the suspend/resume path to only keep the real wakeup interrupts | |
1230 | * (those that have had set_irq_wake() called on them) as wakeup interrupts, | |
1231 | * and not the rest of the interrupts which we needed to have as wakeups for | |
1232 | * cpuidle. | |
1233 | * | |
1234 | * PM ops are not used since this needs to be done at the end, after all the | |
1235 | * other drivers are done with their suspend callbacks. | |
1236 | */ | |
1237 | void nmk_gpio_wakeups_suspend(void) | |
1238 | { | |
1239 | int i; | |
1240 | ||
1241 | for (i = 0; i < NUM_BANKS; i++) { | |
1242 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1243 | ||
1244 | if (!chip) | |
1245 | break; | |
1246 | ||
3c0227d2 RV |
1247 | clk_enable(chip->clk); |
1248 | ||
b9df468d RV |
1249 | writel(chip->rwimsc & chip->real_wake, |
1250 | chip->addr + NMK_GPIO_RWIMSC); | |
1251 | writel(chip->fwimsc & chip->real_wake, | |
1252 | chip->addr + NMK_GPIO_FWIMSC); | |
1253 | ||
3c0227d2 | 1254 | clk_disable(chip->clk); |
b9df468d RV |
1255 | } |
1256 | } | |
1257 | ||
1258 | void nmk_gpio_wakeups_resume(void) | |
1259 | { | |
1260 | int i; | |
1261 | ||
1262 | for (i = 0; i < NUM_BANKS; i++) { | |
1263 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1264 | ||
1265 | if (!chip) | |
1266 | break; | |
1267 | ||
3c0227d2 RV |
1268 | clk_enable(chip->clk); |
1269 | ||
b9df468d RV |
1270 | writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); |
1271 | writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); | |
1272 | ||
3c0227d2 | 1273 | clk_disable(chip->clk); |
b9df468d RV |
1274 | } |
1275 | } | |
1276 | ||
bc6f5cf6 RA |
1277 | /* |
1278 | * Read the pull up/pull down status. | |
1279 | * A bit set in 'pull_up' means that pull up | |
1280 | * is selected if pull is enabled in PDIS register. | |
1281 | * Note: only pull up/down set via this driver can | |
1282 | * be detected due to HW limitations. | |
1283 | */ | |
1284 | void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) | |
1285 | { | |
1286 | if (gpio_bank < NUM_BANKS) { | |
1287 | struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; | |
1288 | ||
1289 | if (!chip) | |
1290 | return; | |
1291 | ||
1292 | *pull_up = chip->pull_up; | |
1293 | } | |
1294 | } | |
1295 | ||
5212d096 AL |
1296 | static int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq, |
1297 | irq_hw_number_t hwirq) | |
a60b57ed LJ |
1298 | { |
1299 | struct nmk_gpio_chip *nmk_chip = d->host_data; | |
1300 | ||
1301 | if (!nmk_chip) | |
1302 | return -EINVAL; | |
1303 | ||
1304 | irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq); | |
1305 | set_irq_flags(irq, IRQF_VALID); | |
1306 | irq_set_chip_data(irq, nmk_chip); | |
1307 | irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING); | |
1308 | ||
1309 | return 0; | |
1310 | } | |
1311 | ||
1312 | const struct irq_domain_ops nmk_gpio_irq_simple_ops = { | |
1313 | .map = nmk_gpio_irq_map, | |
1314 | .xlate = irq_domain_xlate_twocell, | |
1315 | }; | |
1316 | ||
150632b0 | 1317 | static int nmk_gpio_probe(struct platform_device *dev) |
2ec1d359 | 1318 | { |
3e3c62ca | 1319 | struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; |
513c27f8 | 1320 | struct device_node *np = dev->dev.of_node; |
2ec1d359 AR |
1321 | struct nmk_gpio_chip *nmk_chip; |
1322 | struct gpio_chip *chip; | |
3e3c62ca | 1323 | struct resource *res; |
af7dc228 | 1324 | struct clk *clk; |
33b744b3 | 1325 | int secondary_irq; |
8d91771c | 1326 | void __iomem *base; |
832b6cdf | 1327 | int irq_start = 0; |
3e3c62ca | 1328 | int irq; |
2ec1d359 AR |
1329 | int ret; |
1330 | ||
513c27f8 LJ |
1331 | if (!pdata && !np) { |
1332 | dev_err(&dev->dev, "No platform data or device tree found\n"); | |
3e3c62ca | 1333 | return -ENODEV; |
513c27f8 LJ |
1334 | } |
1335 | ||
1336 | if (np) { | |
5e754f33 | 1337 | pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL); |
513c27f8 LJ |
1338 | if (!pdata) |
1339 | return -ENOMEM; | |
1340 | ||
612e1d5f | 1341 | if (of_get_property(np, "st,supports-sleepmode", NULL)) |
513c27f8 LJ |
1342 | pdata->supports_sleepmode = true; |
1343 | ||
1344 | if (of_property_read_u32(np, "gpio-bank", &dev->id)) { | |
1345 | dev_err(&dev->dev, "gpio-bank property not found\n"); | |
50f690d8 | 1346 | return -EINVAL; |
513c27f8 LJ |
1347 | } |
1348 | ||
1349 | pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP; | |
1350 | pdata->num_gpio = NMK_GPIO_PER_CHIP; | |
1351 | } | |
3e3c62ca RV |
1352 | |
1353 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
50f690d8 LW |
1354 | if (!res) |
1355 | return -ENOENT; | |
3e3c62ca RV |
1356 | |
1357 | irq = platform_get_irq(dev, 0); | |
50f690d8 LW |
1358 | if (irq < 0) |
1359 | return irq; | |
3e3c62ca | 1360 | |
33b744b3 | 1361 | secondary_irq = platform_get_irq(dev, 1); |
50f690d8 LW |
1362 | if (secondary_irq >= 0 && !pdata->get_secondary_status) |
1363 | return -EINVAL; | |
33b744b3 | 1364 | |
9e0c1fb2 | 1365 | base = devm_ioremap_resource(&dev->dev, res); |
06991c28 LT |
1366 | if (IS_ERR(base)) |
1367 | return PTR_ERR(base); | |
8d91771c | 1368 | |
5e754f33 | 1369 | clk = devm_clk_get(&dev->dev, NULL); |
50f690d8 LW |
1370 | if (IS_ERR(clk)) |
1371 | return PTR_ERR(clk); | |
efec381c | 1372 | clk_prepare(clk); |
af7dc228 | 1373 | |
5e754f33 | 1374 | nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL); |
50f690d8 LW |
1375 | if (!nmk_chip) |
1376 | return -ENOMEM; | |
513c27f8 | 1377 | |
2ec1d359 AR |
1378 | /* |
1379 | * The virt address in nmk_chip->addr is in the nomadik register space, | |
1380 | * so we can simply convert the resource address, without remapping | |
1381 | */ | |
33b744b3 | 1382 | nmk_chip->bank = dev->id; |
af7dc228 | 1383 | nmk_chip->clk = clk; |
8d91771c | 1384 | nmk_chip->addr = base; |
2ec1d359 | 1385 | nmk_chip->chip = nmk_gpio_template; |
3e3c62ca | 1386 | nmk_chip->parent_irq = irq; |
33b744b3 RV |
1387 | nmk_chip->secondary_parent_irq = secondary_irq; |
1388 | nmk_chip->get_secondary_status = pdata->get_secondary_status; | |
01727e61 | 1389 | nmk_chip->set_ioforce = pdata->set_ioforce; |
33d78647 | 1390 | nmk_chip->sleepmode = pdata->supports_sleepmode; |
c0fcb8db | 1391 | spin_lock_init(&nmk_chip->lock); |
2ec1d359 AR |
1392 | |
1393 | chip = &nmk_chip->chip; | |
1394 | chip->base = pdata->first_gpio; | |
e493e06f | 1395 | chip->ngpio = pdata->num_gpio; |
8d568ae5 | 1396 | chip->label = pdata->name ?: dev_name(&dev->dev); |
2ec1d359 AR |
1397 | chip->dev = &dev->dev; |
1398 | chip->owner = THIS_MODULE; | |
1399 | ||
ebc6178d RV |
1400 | clk_enable(nmk_chip->clk); |
1401 | nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); | |
1402 | clk_disable(nmk_chip->clk); | |
1403 | ||
072e82a1 | 1404 | #ifdef CONFIG_OF_GPIO |
513c27f8 | 1405 | chip->of_node = np; |
072e82a1 | 1406 | #endif |
513c27f8 | 1407 | |
2ec1d359 AR |
1408 | ret = gpiochip_add(&nmk_chip->chip); |
1409 | if (ret) | |
50f690d8 | 1410 | return ret; |
2ec1d359 | 1411 | |
01727e61 RV |
1412 | BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); |
1413 | ||
1414 | nmk_gpio_chips[nmk_chip->bank] = nmk_chip; | |
513c27f8 | 1415 | |
3e3c62ca | 1416 | platform_set_drvdata(dev, nmk_chip); |
2ec1d359 | 1417 | |
51f58c68 | 1418 | if (!np) |
aa6e379a | 1419 | irq_start = pdata->first_irq; |
38843e29 | 1420 | nmk_chip->domain = irq_domain_add_simple(np, |
6054b9ca LW |
1421 | NMK_GPIO_PER_CHIP, irq_start, |
1422 | &nmk_gpio_irq_simple_ops, nmk_chip); | |
a60b57ed | 1423 | if (!nmk_chip->domain) { |
2ee38d4d | 1424 | dev_err(&dev->dev, "failed to create irqdomain\n"); |
50f690d8 LW |
1425 | /* Just do this, no matter if it fails */ |
1426 | ret = gpiochip_remove(&nmk_chip->chip); | |
1427 | return -ENOSYS; | |
a60b57ed LJ |
1428 | } |
1429 | ||
2ec1d359 AR |
1430 | nmk_gpio_init_irq(nmk_chip); |
1431 | ||
513c27f8 LJ |
1432 | dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); |
1433 | ||
2ec1d359 | 1434 | return 0; |
2ec1d359 AR |
1435 | } |
1436 | ||
e98ea774 LW |
1437 | static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) |
1438 | { | |
1439 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1440 | ||
1441 | return npct->soc->ngroups; | |
1442 | } | |
1443 | ||
1444 | static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, | |
1445 | unsigned selector) | |
1446 | { | |
1447 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1448 | ||
1449 | return npct->soc->groups[selector].name; | |
1450 | } | |
1451 | ||
1452 | static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
1453 | const unsigned **pins, | |
1454 | unsigned *num_pins) | |
1455 | { | |
1456 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1457 | ||
1458 | *pins = npct->soc->groups[selector].pins; | |
1459 | *num_pins = npct->soc->groups[selector].npins; | |
1460 | return 0; | |
1461 | } | |
1462 | ||
24cbdd75 LW |
1463 | static struct pinctrl_gpio_range * |
1464 | nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset) | |
1465 | { | |
1466 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1467 | int i; | |
1468 | ||
1469 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) { | |
1470 | struct pinctrl_gpio_range *range; | |
1471 | ||
1472 | range = &npct->soc->gpio_ranges[i]; | |
1473 | if (offset >= range->pin_base && | |
1474 | offset <= (range->pin_base + range->npins - 1)) | |
1475 | return range; | |
1476 | } | |
1477 | return NULL; | |
1478 | } | |
1479 | ||
e98ea774 LW |
1480 | static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
1481 | unsigned offset) | |
1482 | { | |
24cbdd75 LW |
1483 | struct pinctrl_gpio_range *range; |
1484 | struct gpio_chip *chip; | |
1485 | ||
1486 | range = nmk_match_gpio_range(pctldev, offset); | |
1487 | if (!range || !range->gc) { | |
1488 | seq_printf(s, "invalid pin offset"); | |
1489 | return; | |
1490 | } | |
1491 | chip = range->gc; | |
2249b19f | 1492 | nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); |
e98ea774 LW |
1493 | } |
1494 | ||
e32af889 GF |
1495 | static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, |
1496 | struct pinctrl_map *map, unsigned num_maps) | |
1497 | { | |
1498 | int i; | |
1499 | ||
1500 | for (i = 0; i < num_maps; i++) | |
1501 | if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) | |
1502 | kfree(map[i].data.configs.configs); | |
1503 | kfree(map); | |
1504 | } | |
1505 | ||
1506 | static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps, | |
1507 | unsigned *num_maps, unsigned reserve) | |
1508 | { | |
1509 | unsigned old_num = *reserved_maps; | |
1510 | unsigned new_num = *num_maps + reserve; | |
1511 | struct pinctrl_map *new_map; | |
1512 | ||
1513 | if (old_num >= new_num) | |
1514 | return 0; | |
1515 | ||
1516 | new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); | |
1517 | if (!new_map) | |
1518 | return -ENOMEM; | |
1519 | ||
1520 | memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); | |
1521 | ||
1522 | *map = new_map; | |
1523 | *reserved_maps = new_num; | |
1524 | ||
1525 | return 0; | |
1526 | } | |
1527 | ||
1528 | static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, | |
1529 | unsigned *num_maps, const char *group, | |
1530 | const char *function) | |
1531 | { | |
1532 | if (*num_maps == *reserved_maps) | |
1533 | return -ENOSPC; | |
1534 | ||
1535 | (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; | |
1536 | (*map)[*num_maps].data.mux.group = group; | |
1537 | (*map)[*num_maps].data.mux.function = function; | |
1538 | (*num_maps)++; | |
1539 | ||
1540 | return 0; | |
1541 | } | |
1542 | ||
1543 | static int nmk_dt_add_map_configs(struct pinctrl_map **map, | |
1544 | unsigned *reserved_maps, | |
1545 | unsigned *num_maps, const char *group, | |
1546 | unsigned long *configs, unsigned num_configs) | |
1547 | { | |
1548 | unsigned long *dup_configs; | |
1549 | ||
1550 | if (*num_maps == *reserved_maps) | |
1551 | return -ENOSPC; | |
1552 | ||
1553 | dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), | |
1554 | GFP_KERNEL); | |
1555 | if (!dup_configs) | |
1556 | return -ENOMEM; | |
1557 | ||
1558 | (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; | |
1559 | ||
1560 | (*map)[*num_maps].data.configs.group_or_pin = group; | |
1561 | (*map)[*num_maps].data.configs.configs = dup_configs; | |
1562 | (*map)[*num_maps].data.configs.num_configs = num_configs; | |
1563 | (*num_maps)++; | |
1564 | ||
1565 | return 0; | |
1566 | } | |
1567 | ||
87ff934a SK |
1568 | #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, } |
1569 | #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \ | |
e32af889 GF |
1570 | .size = ARRAY_SIZE(y), } |
1571 | ||
1572 | static const unsigned long nmk_pin_input_modes[] = { | |
1573 | PIN_INPUT_NOPULL, | |
1574 | PIN_INPUT_PULLUP, | |
1575 | PIN_INPUT_PULLDOWN, | |
1576 | }; | |
1577 | ||
1578 | static const unsigned long nmk_pin_output_modes[] = { | |
1579 | PIN_OUTPUT_LOW, | |
1580 | PIN_OUTPUT_HIGH, | |
1581 | PIN_DIR_OUTPUT, | |
1582 | }; | |
1583 | ||
1584 | static const unsigned long nmk_pin_sleep_modes[] = { | |
1585 | PIN_SLEEPMODE_DISABLED, | |
1586 | PIN_SLEEPMODE_ENABLED, | |
1587 | }; | |
1588 | ||
1589 | static const unsigned long nmk_pin_sleep_input_modes[] = { | |
1590 | PIN_SLPM_INPUT_NOPULL, | |
1591 | PIN_SLPM_INPUT_PULLUP, | |
1592 | PIN_SLPM_INPUT_PULLDOWN, | |
1593 | PIN_SLPM_DIR_INPUT, | |
1594 | }; | |
1595 | ||
1596 | static const unsigned long nmk_pin_sleep_output_modes[] = { | |
1597 | PIN_SLPM_OUTPUT_LOW, | |
1598 | PIN_SLPM_OUTPUT_HIGH, | |
1599 | PIN_SLPM_DIR_OUTPUT, | |
1600 | }; | |
1601 | ||
1602 | static const unsigned long nmk_pin_sleep_wakeup_modes[] = { | |
1603 | PIN_SLPM_WAKEUP_DISABLE, | |
1604 | PIN_SLPM_WAKEUP_ENABLE, | |
1605 | }; | |
1606 | ||
1607 | static const unsigned long nmk_pin_gpio_modes[] = { | |
1608 | PIN_GPIOMODE_DISABLED, | |
1609 | PIN_GPIOMODE_ENABLED, | |
1610 | }; | |
1611 | ||
1612 | static const unsigned long nmk_pin_sleep_pdis_modes[] = { | |
1613 | PIN_SLPM_PDIS_DISABLED, | |
1614 | PIN_SLPM_PDIS_ENABLED, | |
1615 | }; | |
1616 | ||
1617 | struct nmk_cfg_param { | |
1618 | const char *property; | |
1619 | unsigned long config; | |
1620 | const unsigned long *choice; | |
1621 | int size; | |
1622 | }; | |
1623 | ||
1624 | static const struct nmk_cfg_param nmk_cfg_params[] = { | |
1625 | NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes), | |
1626 | NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes), | |
1627 | NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes), | |
1628 | NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes), | |
1629 | NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes), | |
1630 | NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes), | |
1631 | NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes), | |
1632 | NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes), | |
1633 | }; | |
1634 | ||
1635 | static int nmk_dt_pin_config(int index, int val, unsigned long *config) | |
1636 | { | |
1637 | int ret = 0; | |
1638 | ||
1639 | if (nmk_cfg_params[index].choice == NULL) | |
1640 | *config = nmk_cfg_params[index].config; | |
1641 | else { | |
1642 | /* test if out of range */ | |
1643 | if (val < nmk_cfg_params[index].size) { | |
1644 | *config = nmk_cfg_params[index].config | | |
1645 | nmk_cfg_params[index].choice[val]; | |
1646 | } | |
1647 | } | |
1648 | return ret; | |
1649 | } | |
1650 | ||
1651 | static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name) | |
1652 | { | |
1653 | int i, pin_number; | |
1654 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1655 | ||
1656 | if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) | |
1657 | for (i = 0; i < npct->soc->npins; i++) | |
1658 | if (npct->soc->pins[i].number == pin_number) | |
1659 | return npct->soc->pins[i].name; | |
1660 | return NULL; | |
1661 | } | |
1662 | ||
1663 | static bool nmk_pinctrl_dt_get_config(struct device_node *np, | |
1664 | unsigned long *configs) | |
1665 | { | |
1666 | bool has_config = 0; | |
1667 | unsigned long cfg = 0; | |
1668 | int i, val, ret; | |
1669 | ||
1670 | for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) { | |
1671 | ret = of_property_read_u32(np, | |
1672 | nmk_cfg_params[i].property, &val); | |
1673 | if (ret != -EINVAL) { | |
1674 | if (nmk_dt_pin_config(i, val, &cfg) == 0) { | |
1675 | *configs |= cfg; | |
1676 | has_config = 1; | |
1677 | } | |
1678 | } | |
1679 | } | |
1680 | ||
1681 | return has_config; | |
1682 | } | |
1683 | ||
1684 | int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, | |
1685 | struct device_node *np, | |
1686 | struct pinctrl_map **map, | |
1687 | unsigned *reserved_maps, | |
1688 | unsigned *num_maps) | |
1689 | { | |
1690 | int ret; | |
1691 | const char *function = NULL; | |
1692 | unsigned long configs = 0; | |
1693 | bool has_config = 0; | |
1694 | unsigned reserve = 0; | |
1695 | struct property *prop; | |
1696 | const char *group, *gpio_name; | |
1697 | struct device_node *np_config; | |
1698 | ||
1699 | ret = of_property_read_string(np, "ste,function", &function); | |
1700 | if (ret >= 0) | |
1701 | reserve = 1; | |
1702 | ||
1703 | has_config = nmk_pinctrl_dt_get_config(np, &configs); | |
1704 | ||
1705 | np_config = of_parse_phandle(np, "ste,config", 0); | |
1706 | if (np_config) | |
1707 | has_config |= nmk_pinctrl_dt_get_config(np_config, &configs); | |
1708 | ||
1709 | ret = of_property_count_strings(np, "ste,pins"); | |
1710 | if (ret < 0) | |
1711 | goto exit; | |
1712 | ||
1713 | if (has_config) | |
1714 | reserve++; | |
1715 | ||
1716 | reserve *= ret; | |
1717 | ||
1718 | ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve); | |
1719 | if (ret < 0) | |
1720 | goto exit; | |
1721 | ||
1722 | of_property_for_each_string(np, "ste,pins", prop, group) { | |
1723 | if (function) { | |
1724 | ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps, | |
1725 | group, function); | |
1726 | if (ret < 0) | |
1727 | goto exit; | |
1728 | } | |
1729 | if (has_config) { | |
1730 | gpio_name = nmk_find_pin_name(pctldev, group); | |
1731 | ||
1732 | ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps, | |
1733 | gpio_name, &configs, 1); | |
1734 | if (ret < 0) | |
1735 | goto exit; | |
1736 | } | |
1737 | ||
1738 | } | |
1739 | exit: | |
1740 | return ret; | |
1741 | } | |
1742 | ||
1743 | int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, | |
1744 | struct device_node *np_config, | |
1745 | struct pinctrl_map **map, unsigned *num_maps) | |
1746 | { | |
1747 | unsigned reserved_maps; | |
1748 | struct device_node *np; | |
1749 | int ret; | |
1750 | ||
1751 | reserved_maps = 0; | |
1752 | *map = NULL; | |
1753 | *num_maps = 0; | |
1754 | ||
1755 | for_each_child_of_node(np_config, np) { | |
1756 | ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map, | |
1757 | &reserved_maps, num_maps); | |
1758 | if (ret < 0) { | |
1759 | nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps); | |
1760 | return ret; | |
1761 | } | |
1762 | } | |
1763 | ||
1764 | return 0; | |
1765 | } | |
1766 | ||
022ab148 | 1767 | static const struct pinctrl_ops nmk_pinctrl_ops = { |
e98ea774 LW |
1768 | .get_groups_count = nmk_get_groups_cnt, |
1769 | .get_group_name = nmk_get_group_name, | |
1770 | .get_group_pins = nmk_get_group_pins, | |
1771 | .pin_dbg_show = nmk_pin_dbg_show, | |
e32af889 GF |
1772 | .dt_node_to_map = nmk_pinctrl_dt_node_to_map, |
1773 | .dt_free_map = nmk_pinctrl_dt_free_map, | |
e98ea774 LW |
1774 | }; |
1775 | ||
dbfe8ca2 LW |
1776 | static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) |
1777 | { | |
1778 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1779 | ||
1780 | return npct->soc->nfunctions; | |
1781 | } | |
1782 | ||
1783 | static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
1784 | unsigned function) | |
1785 | { | |
1786 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1787 | ||
1788 | return npct->soc->functions[function].name; | |
1789 | } | |
1790 | ||
1791 | static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
1792 | unsigned function, | |
1793 | const char * const **groups, | |
1794 | unsigned * const num_groups) | |
1795 | { | |
1796 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1797 | ||
1798 | *groups = npct->soc->functions[function].groups; | |
1799 | *num_groups = npct->soc->functions[function].ngroups; | |
1800 | ||
1801 | return 0; | |
1802 | } | |
1803 | ||
1804 | static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, | |
1805 | unsigned group) | |
1806 | { | |
1807 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1808 | const struct nmk_pingroup *g; | |
1809 | static unsigned int slpm[NUM_BANKS]; | |
1810 | unsigned long flags; | |
1811 | bool glitch; | |
1812 | int ret = -EINVAL; | |
1813 | int i; | |
1814 | ||
1815 | g = &npct->soc->groups[group]; | |
1816 | ||
1817 | if (g->altsetting < 0) | |
1818 | return -EINVAL; | |
1819 | ||
1820 | dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); | |
1821 | ||
daf73174 LW |
1822 | /* |
1823 | * If we're setting altfunc C by setting both AFSLA and AFSLB to 1, | |
1824 | * we may pass through an undesired state. In this case we take | |
1825 | * some extra care. | |
1826 | * | |
1827 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
1828 | * - Save SLPM registers (since we have a shadow register in the | |
1829 | * nmk_chip we're using that as backup) | |
1830 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
1831 | * - Configure the GPIO registers for the IOs that are being switched | |
1832 | * - Set IOFORCE=1 | |
1833 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
1834 | * - Set IOFORCE=0 | |
1835 | * - Restore SLPM registers | |
1836 | * - Any spurious wake up event during switch sequence to be ignored | |
1837 | * and cleared | |
1838 | * | |
1839 | * We REALLY need to save ALL slpm registers, because the external | |
1840 | * IOFORCE will switch *all* ports to their sleepmode setting to as | |
1841 | * to avoid glitches. (Not just one port!) | |
1842 | */ | |
c22df08c | 1843 | glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); |
dbfe8ca2 LW |
1844 | |
1845 | if (glitch) { | |
1846 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | |
1847 | ||
1848 | /* Initially don't put any pins to sleep when switching */ | |
1849 | memset(slpm, 0xff, sizeof(slpm)); | |
1850 | ||
1851 | /* | |
1852 | * Then mask the pins that need to be sleeping now when we're | |
1853 | * switching to the ALT C function. | |
1854 | */ | |
1855 | for (i = 0; i < g->npins; i++) | |
1856 | slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); | |
1857 | nmk_gpio_glitch_slpm_init(slpm); | |
1858 | } | |
1859 | ||
1860 | for (i = 0; i < g->npins; i++) { | |
1861 | struct pinctrl_gpio_range *range; | |
1862 | struct nmk_gpio_chip *nmk_chip; | |
1863 | struct gpio_chip *chip; | |
1864 | unsigned bit; | |
1865 | ||
1866 | range = nmk_match_gpio_range(pctldev, g->pins[i]); | |
1867 | if (!range) { | |
1868 | dev_err(npct->dev, | |
1869 | "invalid pin offset %d in group %s at index %d\n", | |
1870 | g->pins[i], g->name, i); | |
1871 | goto out_glitch; | |
1872 | } | |
1873 | if (!range->gc) { | |
1874 | dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n", | |
1875 | g->pins[i], g->name, i); | |
1876 | goto out_glitch; | |
1877 | } | |
1878 | chip = range->gc; | |
1879 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
1880 | dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); | |
1881 | ||
1882 | clk_enable(nmk_chip->clk); | |
1883 | bit = g->pins[i] % NMK_GPIO_PER_CHIP; | |
1884 | /* | |
1885 | * If the pin is switching to altfunc, and there was an | |
1886 | * interrupt installed on it which has been lazy disabled, | |
1887 | * actually mask the interrupt to prevent spurious interrupts | |
1888 | * that would occur while the pin is under control of the | |
1889 | * peripheral. Only SKE does this. | |
1890 | */ | |
1891 | nmk_gpio_disable_lazy_irq(nmk_chip, bit); | |
1892 | ||
c22df08c JNG |
1893 | __nmk_gpio_set_mode_safe(nmk_chip, bit, |
1894 | (g->altsetting & NMK_GPIO_ALT_C), glitch); | |
dbfe8ca2 | 1895 | clk_disable(nmk_chip->clk); |
c22df08c JNG |
1896 | |
1897 | /* | |
1898 | * Call PRCM GPIOCR config function in case ALTC | |
1899 | * has been selected: | |
1900 | * - If selection is a ALTCx, some bits in PRCM GPIOCR registers | |
1901 | * must be set. | |
1902 | * - If selection is pure ALTC and previous selection was ALTCx, | |
1903 | * then some bits in PRCM GPIOCR registers must be cleared. | |
1904 | */ | |
1905 | if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C) | |
1906 | nmk_prcm_altcx_set_mode(npct, g->pins[i], | |
1907 | g->altsetting >> NMK_GPIO_ALT_CX_SHIFT); | |
dbfe8ca2 LW |
1908 | } |
1909 | ||
1910 | /* When all pins are successfully reconfigured we get here */ | |
1911 | ret = 0; | |
1912 | ||
1913 | out_glitch: | |
1914 | if (glitch) { | |
1915 | nmk_gpio_glitch_slpm_restore(slpm); | |
1916 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
1917 | } | |
1918 | ||
1919 | return ret; | |
1920 | } | |
1921 | ||
1922 | static void nmk_pmx_disable(struct pinctrl_dev *pctldev, | |
1923 | unsigned function, unsigned group) | |
1924 | { | |
1925 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1926 | const struct nmk_pingroup *g; | |
1927 | ||
1928 | g = &npct->soc->groups[group]; | |
1929 | ||
1930 | if (g->altsetting < 0) | |
1931 | return; | |
1932 | ||
1933 | /* Poke out the mux, set the pin to some default state? */ | |
1934 | dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins); | |
1935 | } | |
1936 | ||
5212d096 AL |
1937 | static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, |
1938 | struct pinctrl_gpio_range *range, | |
1939 | unsigned offset) | |
dbfe8ca2 LW |
1940 | { |
1941 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1942 | struct nmk_gpio_chip *nmk_chip; | |
1943 | struct gpio_chip *chip; | |
1944 | unsigned bit; | |
1945 | ||
1946 | if (!range) { | |
1947 | dev_err(npct->dev, "invalid range\n"); | |
1948 | return -EINVAL; | |
1949 | } | |
1950 | if (!range->gc) { | |
1951 | dev_err(npct->dev, "missing GPIO chip in range\n"); | |
1952 | return -EINVAL; | |
1953 | } | |
1954 | chip = range->gc; | |
1955 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
1956 | ||
1957 | dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); | |
1958 | ||
1959 | clk_enable(nmk_chip->clk); | |
1960 | bit = offset % NMK_GPIO_PER_CHIP; | |
1961 | /* There is no glitch when converting any pin to GPIO */ | |
1962 | __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); | |
1963 | clk_disable(nmk_chip->clk); | |
1964 | ||
1965 | return 0; | |
1966 | } | |
1967 | ||
5212d096 AL |
1968 | static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, |
1969 | struct pinctrl_gpio_range *range, | |
1970 | unsigned offset) | |
dbfe8ca2 LW |
1971 | { |
1972 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1973 | ||
1974 | dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); | |
1975 | /* Set the pin to some default state, GPIO is usually default */ | |
1976 | } | |
1977 | ||
022ab148 | 1978 | static const struct pinmux_ops nmk_pinmux_ops = { |
dbfe8ca2 LW |
1979 | .get_functions_count = nmk_pmx_get_funcs_cnt, |
1980 | .get_function_name = nmk_pmx_get_func_name, | |
1981 | .get_function_groups = nmk_pmx_get_func_groups, | |
1982 | .enable = nmk_pmx_enable, | |
1983 | .disable = nmk_pmx_disable, | |
1984 | .gpio_request_enable = nmk_gpio_request_enable, | |
1985 | .gpio_disable_free = nmk_gpio_disable_free, | |
1986 | }; | |
1987 | ||
5212d096 AL |
1988 | static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, |
1989 | unsigned long *config) | |
d41af627 LW |
1990 | { |
1991 | /* Not implemented */ | |
1992 | return -EINVAL; | |
1993 | } | |
1994 | ||
5212d096 AL |
1995 | static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, |
1996 | unsigned long config) | |
d41af627 LW |
1997 | { |
1998 | static const char *pullnames[] = { | |
1999 | [NMK_GPIO_PULL_NONE] = "none", | |
2000 | [NMK_GPIO_PULL_UP] = "up", | |
2001 | [NMK_GPIO_PULL_DOWN] = "down", | |
2002 | [3] /* illegal */ = "??" | |
2003 | }; | |
2004 | static const char *slpmnames[] = { | |
2005 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", | |
2006 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
2007 | }; | |
2008 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
2009 | struct nmk_gpio_chip *nmk_chip; | |
2010 | struct pinctrl_gpio_range *range; | |
2011 | struct gpio_chip *chip; | |
2012 | unsigned bit; | |
2013 | ||
2014 | /* | |
2015 | * The pin config contains pin number and altfunction fields, here | |
2016 | * we just ignore that part. It's being handled by the framework and | |
2017 | * pinmux callback respectively. | |
2018 | */ | |
2019 | pin_cfg_t cfg = (pin_cfg_t) config; | |
2020 | int pull = PIN_PULL(cfg); | |
2021 | int slpm = PIN_SLPM(cfg); | |
2022 | int output = PIN_DIR(cfg); | |
2023 | int val = PIN_VAL(cfg); | |
2024 | bool lowemi = PIN_LOWEMI(cfg); | |
2025 | bool gpiomode = PIN_GPIOMODE(cfg); | |
2026 | bool sleep = PIN_SLEEPMODE(cfg); | |
2027 | ||
2028 | range = nmk_match_gpio_range(pctldev, pin); | |
2029 | if (!range) { | |
2030 | dev_err(npct->dev, "invalid pin offset %d\n", pin); | |
2031 | return -EINVAL; | |
2032 | } | |
2033 | if (!range->gc) { | |
2034 | dev_err(npct->dev, "GPIO chip missing in range for pin %d\n", | |
2035 | pin); | |
2036 | return -EINVAL; | |
2037 | } | |
2038 | chip = range->gc; | |
2039 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
2040 | ||
2041 | if (sleep) { | |
2042 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
2043 | int slpm_output = PIN_SLPM_DIR(cfg); | |
2044 | int slpm_val = PIN_SLPM_VAL(cfg); | |
2045 | ||
2046 | /* All pins go into GPIO mode at sleep */ | |
2047 | gpiomode = true; | |
2048 | ||
2049 | /* | |
2050 | * The SLPM_* values are normal values + 1 to allow zero to | |
2051 | * mean "same as normal". | |
2052 | */ | |
2053 | if (slpm_pull) | |
2054 | pull = slpm_pull - 1; | |
2055 | if (slpm_output) | |
2056 | output = slpm_output - 1; | |
2057 | if (slpm_val) | |
2058 | val = slpm_val - 1; | |
2059 | ||
2060 | dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", | |
2061 | pin, | |
2062 | slpm_pull ? pullnames[pull] : "same", | |
2063 | slpm_output ? (output ? "output" : "input") : "same", | |
2064 | slpm_val ? (val ? "high" : "low") : "same"); | |
2065 | } | |
2066 | ||
2067 | dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", | |
2068 | pin, cfg, pullnames[pull], slpmnames[slpm], | |
2069 | output ? "output " : "input", | |
2070 | output ? (val ? "high" : "low") : "", | |
87ff934a | 2071 | lowemi ? "on" : "off"); |
d41af627 LW |
2072 | |
2073 | clk_enable(nmk_chip->clk); | |
2074 | bit = pin % NMK_GPIO_PER_CHIP; | |
2075 | if (gpiomode) | |
2076 | /* No glitch when going to GPIO mode */ | |
2077 | __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); | |
2078 | if (output) | |
2079 | __nmk_gpio_make_output(nmk_chip, bit, val); | |
2080 | else { | |
2081 | __nmk_gpio_make_input(nmk_chip, bit); | |
2082 | __nmk_gpio_set_pull(nmk_chip, bit, pull); | |
2083 | } | |
2084 | /* TODO: isn't this only applicable on output pins? */ | |
2085 | __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); | |
2086 | ||
2087 | __nmk_gpio_set_slpm(nmk_chip, bit, slpm); | |
2088 | clk_disable(nmk_chip->clk); | |
2089 | return 0; | |
2090 | } | |
2091 | ||
022ab148 | 2092 | static const struct pinconf_ops nmk_pinconf_ops = { |
d41af627 LW |
2093 | .pin_config_get = nmk_pin_config_get, |
2094 | .pin_config_set = nmk_pin_config_set, | |
2095 | }; | |
2096 | ||
e98ea774 LW |
2097 | static struct pinctrl_desc nmk_pinctrl_desc = { |
2098 | .name = "pinctrl-nomadik", | |
2099 | .pctlops = &nmk_pinctrl_ops, | |
dbfe8ca2 | 2100 | .pmxops = &nmk_pinmux_ops, |
d41af627 | 2101 | .confops = &nmk_pinconf_ops, |
e98ea774 LW |
2102 | .owner = THIS_MODULE, |
2103 | }; | |
2104 | ||
855f80cd | 2105 | static const struct of_device_id nmk_pinctrl_match[] = { |
6010d403 LW |
2106 | { |
2107 | .compatible = "stericsson,nmk-pinctrl-stn8815", | |
2108 | .data = (void *)PINCTRL_NMK_STN8815, | |
2109 | }, | |
855f80cd | 2110 | { |
e32af889 | 2111 | .compatible = "stericsson,nmk-pinctrl", |
855f80cd LJ |
2112 | .data = (void *)PINCTRL_NMK_DB8500, |
2113 | }, | |
2114 | {}, | |
2115 | }; | |
2116 | ||
8d99b32d JD |
2117 | static int nmk_pinctrl_suspend(struct platform_device *pdev, pm_message_t state) |
2118 | { | |
2119 | struct nmk_pinctrl *npct; | |
2120 | ||
2121 | npct = platform_get_drvdata(pdev); | |
2122 | if (!npct) | |
2123 | return -EINVAL; | |
2124 | ||
2125 | return pinctrl_force_sleep(npct->pctl); | |
2126 | } | |
2127 | ||
2128 | static int nmk_pinctrl_resume(struct platform_device *pdev) | |
2129 | { | |
2130 | struct nmk_pinctrl *npct; | |
2131 | ||
2132 | npct = platform_get_drvdata(pdev); | |
2133 | if (!npct) | |
2134 | return -EINVAL; | |
2135 | ||
2136 | return pinctrl_force_default(npct->pctl); | |
2137 | } | |
2138 | ||
150632b0 | 2139 | static int nmk_pinctrl_probe(struct platform_device *pdev) |
e98ea774 LW |
2140 | { |
2141 | const struct platform_device_id *platid = platform_get_device_id(pdev); | |
855f80cd | 2142 | struct device_node *np = pdev->dev.of_node; |
32e67eee | 2143 | struct device_node *prcm_np; |
e98ea774 | 2144 | struct nmk_pinctrl *npct; |
f1671bf5 | 2145 | struct resource *res; |
855f80cd | 2146 | unsigned int version = 0; |
e98ea774 LW |
2147 | int i; |
2148 | ||
2149 | npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); | |
2150 | if (!npct) | |
2151 | return -ENOMEM; | |
2152 | ||
855f80cd LJ |
2153 | if (platid) |
2154 | version = platid->driver_data; | |
953e9e93 AL |
2155 | else if (np) { |
2156 | const struct of_device_id *match; | |
2157 | ||
2158 | match = of_match_device(nmk_pinctrl_match, &pdev->dev); | |
2159 | if (!match) | |
2160 | return -ENODEV; | |
2161 | version = (unsigned int) match->data; | |
2162 | } | |
855f80cd | 2163 | |
e98ea774 | 2164 | /* Poke in other ASIC variants here */ |
f79c5ed9 LW |
2165 | if (version == PINCTRL_NMK_STN8815) |
2166 | nmk_pinctrl_stn8815_init(&npct->soc); | |
855f80cd | 2167 | if (version == PINCTRL_NMK_DB8500) |
e98ea774 | 2168 | nmk_pinctrl_db8500_init(&npct->soc); |
45a1b531 PC |
2169 | if (version == PINCTRL_NMK_DB8540) |
2170 | nmk_pinctrl_db8540_init(&npct->soc); | |
e98ea774 | 2171 | |
32e67eee LJ |
2172 | if (np) { |
2173 | prcm_np = of_parse_phandle(np, "prcm", 0); | |
2174 | if (prcm_np) | |
2175 | npct->prcm_base = of_iomap(prcm_np, 0); | |
2176 | } | |
2177 | ||
2178 | /* Allow platform passed information to over-write DT. */ | |
f1671bf5 | 2179 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
32e67eee | 2180 | if (res) |
f1671bf5 JA |
2181 | npct->prcm_base = devm_ioremap(&pdev->dev, res->start, |
2182 | resource_size(res)); | |
32e67eee LJ |
2183 | if (!npct->prcm_base) { |
2184 | if (version == PINCTRL_NMK_STN8815) { | |
2185 | dev_info(&pdev->dev, | |
2186 | "No PRCM base, " | |
2187 | "assuming no ALT-Cx control is available\n"); | |
2188 | } else { | |
2189 | dev_err(&pdev->dev, "missing PRCM base address\n"); | |
2190 | return -EINVAL; | |
f1671bf5 | 2191 | } |
f1671bf5 JA |
2192 | } |
2193 | ||
e98ea774 LW |
2194 | /* |
2195 | * We need all the GPIO drivers to probe FIRST, or we will not be able | |
2196 | * to obtain references to the struct gpio_chip * for them, and we | |
2197 | * need this to proceed. | |
2198 | */ | |
2199 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) { | |
1d853ca5 | 2200 | if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) { |
e98ea774 | 2201 | dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); |
e98ea774 LW |
2202 | return -EPROBE_DEFER; |
2203 | } | |
1d853ca5 | 2204 | npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip; |
e98ea774 LW |
2205 | } |
2206 | ||
2207 | nmk_pinctrl_desc.pins = npct->soc->pins; | |
2208 | nmk_pinctrl_desc.npins = npct->soc->npins; | |
2209 | npct->dev = &pdev->dev; | |
f1671bf5 | 2210 | |
e98ea774 LW |
2211 | npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct); |
2212 | if (!npct->pctl) { | |
2213 | dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); | |
2214 | return -EINVAL; | |
2215 | } | |
2216 | ||
2217 | /* We will handle a range of GPIO pins */ | |
2218 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) | |
2219 | pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]); | |
2220 | ||
2221 | platform_set_drvdata(pdev, npct); | |
2222 | dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); | |
2223 | ||
2224 | return 0; | |
2225 | } | |
2226 | ||
513c27f8 LJ |
2227 | static const struct of_device_id nmk_gpio_match[] = { |
2228 | { .compatible = "st,nomadik-gpio", }, | |
2229 | {} | |
2230 | }; | |
2231 | ||
3e3c62ca RV |
2232 | static struct platform_driver nmk_gpio_driver = { |
2233 | .driver = { | |
2ec1d359 AR |
2234 | .owner = THIS_MODULE, |
2235 | .name = "gpio", | |
513c27f8 | 2236 | .of_match_table = nmk_gpio_match, |
5317e4d1 | 2237 | }, |
2ec1d359 | 2238 | .probe = nmk_gpio_probe, |
2ec1d359 AR |
2239 | }; |
2240 | ||
e98ea774 LW |
2241 | static const struct platform_device_id nmk_pinctrl_id[] = { |
2242 | { "pinctrl-stn8815", PINCTRL_NMK_STN8815 }, | |
2243 | { "pinctrl-db8500", PINCTRL_NMK_DB8500 }, | |
45a1b531 | 2244 | { "pinctrl-db8540", PINCTRL_NMK_DB8540 }, |
8c995d6d | 2245 | { } |
e98ea774 LW |
2246 | }; |
2247 | ||
2248 | static struct platform_driver nmk_pinctrl_driver = { | |
2249 | .driver = { | |
2250 | .owner = THIS_MODULE, | |
2251 | .name = "pinctrl-nomadik", | |
855f80cd | 2252 | .of_match_table = nmk_pinctrl_match, |
e98ea774 LW |
2253 | }, |
2254 | .probe = nmk_pinctrl_probe, | |
2255 | .id_table = nmk_pinctrl_id, | |
8d99b32d JD |
2256 | #ifdef CONFIG_PM |
2257 | .suspend = nmk_pinctrl_suspend, | |
2258 | .resume = nmk_pinctrl_resume, | |
2259 | #endif | |
e98ea774 LW |
2260 | }; |
2261 | ||
2ec1d359 AR |
2262 | static int __init nmk_gpio_init(void) |
2263 | { | |
e98ea774 LW |
2264 | int ret; |
2265 | ||
2266 | ret = platform_driver_register(&nmk_gpio_driver); | |
2267 | if (ret) | |
2268 | return ret; | |
2269 | return platform_driver_register(&nmk_pinctrl_driver); | |
2ec1d359 AR |
2270 | } |
2271 | ||
33f45ea9 | 2272 | core_initcall(nmk_gpio_init); |
2ec1d359 AR |
2273 | |
2274 | MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); | |
2275 | MODULE_DESCRIPTION("Nomadik GPIO Driver"); | |
2276 | MODULE_LICENSE("GPL"); |