Commit | Line | Data |
---|---|---|
2ec1d359 AR |
1 | /* |
2 | * Generic GPIO driver for logic cells found in the Nomadik SoC | |
3 | * | |
4 | * Copyright (C) 2008,2009 STMicroelectronics | |
5 | * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> | |
6 | * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> | |
33d78647 | 7 | * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org> |
2ec1d359 AR |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/device.h> | |
3e3c62ca | 17 | #include <linux/platform_device.h> |
2ec1d359 | 18 | #include <linux/io.h> |
af7dc228 RV |
19 | #include <linux/clk.h> |
20 | #include <linux/err.h> | |
2ec1d359 AR |
21 | #include <linux/gpio.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/irq.h> | |
a60b57ed | 25 | #include <linux/irqdomain.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
855f80cd | 27 | #include <linux/of_device.h> |
e98ea774 | 28 | #include <linux/pinctrl/pinctrl.h> |
dbfe8ca2 | 29 | #include <linux/pinctrl/pinmux.h> |
d41af627 | 30 | #include <linux/pinctrl/pinconf.h> |
dbfe8ca2 LW |
31 | /* Since we request GPIOs from ourself */ |
32 | #include <linux/pinctrl/consumer.h> | |
b7213702 LW |
33 | /* |
34 | * For the U8500 archs, use the PRCMU register interface, for the older | |
35 | * Nomadik, provide some stubs. The functions using these will only be | |
36 | * called on the U8500 series. | |
37 | */ | |
38 | #ifdef CONFIG_ARCH_U8500 | |
c22df08c | 39 | #include <linux/mfd/dbx500-prcmu.h> |
b7213702 LW |
40 | #else |
41 | static inline u32 prcmu_read(unsigned int reg) { | |
42 | return 0; | |
43 | } | |
44 | static inline void prcmu_write(unsigned int reg, u32 value) {} | |
45 | static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {} | |
46 | #endif | |
bb16bd9b | 47 | #include <linux/platform_data/pinctrl-nomadik.h> |
2ec1d359 | 48 | |
adfed159 WD |
49 | #include <asm/mach/irq.h> |
50 | ||
e98ea774 LW |
51 | #include "pinctrl-nomadik.h" |
52 | ||
2ec1d359 AR |
53 | /* |
54 | * The GPIO module in the Nomadik family of Systems-on-Chip is an | |
55 | * AMBA device, managing 32 pins and alternate functions. The logic block | |
9c66ee6f | 56 | * is currently used in the Nomadik and ux500. |
2ec1d359 AR |
57 | * |
58 | * Symbols in this file are called "nmk_gpio" for "nomadik gpio" | |
59 | */ | |
60 | ||
2ec1d359 AR |
61 | struct nmk_gpio_chip { |
62 | struct gpio_chip chip; | |
a60b57ed | 63 | struct irq_domain *domain; |
2ec1d359 | 64 | void __iomem *addr; |
af7dc228 | 65 | struct clk *clk; |
33b744b3 | 66 | unsigned int bank; |
2ec1d359 | 67 | unsigned int parent_irq; |
2c8bb0eb | 68 | int secondary_parent_irq; |
33b744b3 | 69 | u32 (*get_secondary_status)(unsigned int bank); |
01727e61 | 70 | void (*set_ioforce)(bool enable); |
c0fcb8db | 71 | spinlock_t lock; |
33d78647 | 72 | bool sleepmode; |
2ec1d359 AR |
73 | /* Keep track of configured edges */ |
74 | u32 edge_rising; | |
75 | u32 edge_falling; | |
b9df468d RV |
76 | u32 real_wake; |
77 | u32 rwimsc; | |
78 | u32 fwimsc; | |
6c12fe88 RV |
79 | u32 rimsc; |
80 | u32 fimsc; | |
bc6f5cf6 | 81 | u32 pull_up; |
ebc6178d | 82 | u32 lowemi; |
2ec1d359 AR |
83 | }; |
84 | ||
e98ea774 LW |
85 | struct nmk_pinctrl { |
86 | struct device *dev; | |
87 | struct pinctrl_dev *pctl; | |
88 | const struct nmk_pinctrl_soc_data *soc; | |
89 | }; | |
90 | ||
01727e61 RV |
91 | static struct nmk_gpio_chip * |
92 | nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; | |
93 | ||
94 | static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); | |
95 | ||
96 | #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) | |
97 | ||
6f9a974c RV |
98 | static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, |
99 | unsigned offset, int gpio_mode) | |
100 | { | |
101 | u32 bit = 1 << offset; | |
102 | u32 afunc, bfunc; | |
103 | ||
104 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; | |
105 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; | |
106 | if (gpio_mode & NMK_GPIO_ALT_A) | |
107 | afunc |= bit; | |
108 | if (gpio_mode & NMK_GPIO_ALT_B) | |
109 | bfunc |= bit; | |
110 | writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); | |
111 | writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); | |
112 | } | |
113 | ||
81a3c298 RV |
114 | static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, |
115 | unsigned offset, enum nmk_gpio_slpm mode) | |
116 | { | |
117 | u32 bit = 1 << offset; | |
118 | u32 slpm; | |
119 | ||
120 | slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); | |
121 | if (mode == NMK_GPIO_SLPM_NOCHANGE) | |
122 | slpm |= bit; | |
123 | else | |
124 | slpm &= ~bit; | |
125 | writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); | |
126 | } | |
127 | ||
5b327edf RV |
128 | static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, |
129 | unsigned offset, enum nmk_gpio_pull pull) | |
130 | { | |
131 | u32 bit = 1 << offset; | |
132 | u32 pdis; | |
133 | ||
134 | pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); | |
bc6f5cf6 | 135 | if (pull == NMK_GPIO_PULL_NONE) { |
5b327edf | 136 | pdis |= bit; |
bc6f5cf6 RA |
137 | nmk_chip->pull_up &= ~bit; |
138 | } else { | |
5b327edf | 139 | pdis &= ~bit; |
bc6f5cf6 RA |
140 | } |
141 | ||
5b327edf RV |
142 | writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); |
143 | ||
bc6f5cf6 RA |
144 | if (pull == NMK_GPIO_PULL_UP) { |
145 | nmk_chip->pull_up |= bit; | |
5b327edf | 146 | writel(bit, nmk_chip->addr + NMK_GPIO_DATS); |
bc6f5cf6 RA |
147 | } else if (pull == NMK_GPIO_PULL_DOWN) { |
148 | nmk_chip->pull_up &= ~bit; | |
5b327edf | 149 | writel(bit, nmk_chip->addr + NMK_GPIO_DATC); |
bc6f5cf6 | 150 | } |
5b327edf RV |
151 | } |
152 | ||
ebc6178d RV |
153 | static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, |
154 | unsigned offset, bool lowemi) | |
155 | { | |
156 | u32 bit = BIT(offset); | |
157 | bool enabled = nmk_chip->lowemi & bit; | |
158 | ||
159 | if (lowemi == enabled) | |
160 | return; | |
161 | ||
162 | if (lowemi) | |
163 | nmk_chip->lowemi |= bit; | |
164 | else | |
165 | nmk_chip->lowemi &= ~bit; | |
166 | ||
167 | writel_relaxed(nmk_chip->lowemi, | |
168 | nmk_chip->addr + NMK_GPIO_LOWEMI); | |
169 | } | |
170 | ||
378be066 RV |
171 | static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, |
172 | unsigned offset) | |
173 | { | |
174 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); | |
175 | } | |
176 | ||
6720db7c RV |
177 | static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, |
178 | unsigned offset, int val) | |
179 | { | |
180 | if (val) | |
181 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); | |
182 | else | |
183 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); | |
184 | } | |
185 | ||
186 | static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, | |
187 | unsigned offset, int val) | |
188 | { | |
189 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); | |
190 | __nmk_gpio_set_output(nmk_chip, offset, val); | |
191 | } | |
192 | ||
01727e61 RV |
193 | static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, |
194 | unsigned offset, int gpio_mode, | |
195 | bool glitch) | |
196 | { | |
6c12fe88 RV |
197 | u32 rwimsc = nmk_chip->rwimsc; |
198 | u32 fwimsc = nmk_chip->fwimsc; | |
01727e61 RV |
199 | |
200 | if (glitch && nmk_chip->set_ioforce) { | |
201 | u32 bit = BIT(offset); | |
202 | ||
01727e61 RV |
203 | /* Prevent spurious wakeups */ |
204 | writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
205 | writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
206 | ||
207 | nmk_chip->set_ioforce(true); | |
208 | } | |
209 | ||
210 | __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); | |
211 | ||
212 | if (glitch && nmk_chip->set_ioforce) { | |
213 | nmk_chip->set_ioforce(false); | |
214 | ||
215 | writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
216 | writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
217 | } | |
218 | } | |
219 | ||
6c42ad1c RV |
220 | static void |
221 | nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) | |
222 | { | |
223 | u32 falling = nmk_chip->fimsc & BIT(offset); | |
224 | u32 rising = nmk_chip->rimsc & BIT(offset); | |
225 | int gpio = nmk_chip->chip.base + offset; | |
226 | int irq = NOMADIK_GPIO_TO_IRQ(gpio); | |
227 | struct irq_data *d = irq_get_irq_data(irq); | |
228 | ||
229 | if (!rising && !falling) | |
230 | return; | |
231 | ||
232 | if (!d || !irqd_irq_disabled(d)) | |
233 | return; | |
234 | ||
235 | if (rising) { | |
236 | nmk_chip->rimsc &= ~BIT(offset); | |
237 | writel_relaxed(nmk_chip->rimsc, | |
238 | nmk_chip->addr + NMK_GPIO_RIMSC); | |
239 | } | |
240 | ||
241 | if (falling) { | |
242 | nmk_chip->fimsc &= ~BIT(offset); | |
243 | writel_relaxed(nmk_chip->fimsc, | |
244 | nmk_chip->addr + NMK_GPIO_FIMSC); | |
245 | } | |
246 | ||
247 | dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); | |
248 | } | |
249 | ||
c22df08c JNG |
250 | static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct, |
251 | unsigned offset, unsigned alt_num) | |
252 | { | |
253 | int i; | |
254 | u16 reg; | |
255 | u8 bit; | |
256 | u8 alt_index; | |
257 | const struct prcm_gpiocr_altcx_pin_desc *pin_desc; | |
258 | const u16 *gpiocr_regs; | |
259 | ||
260 | if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) { | |
261 | dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n", | |
262 | alt_num); | |
263 | return; | |
264 | } | |
265 | ||
266 | for (i = 0 ; i < npct->soc->npins_altcx ; i++) { | |
267 | if (npct->soc->altcx_pins[i].pin == offset) | |
268 | break; | |
269 | } | |
270 | if (i == npct->soc->npins_altcx) { | |
271 | dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n", | |
272 | offset); | |
273 | return; | |
274 | } | |
275 | ||
276 | pin_desc = npct->soc->altcx_pins + i; | |
277 | gpiocr_regs = npct->soc->prcm_gpiocr_registers; | |
278 | ||
279 | /* | |
280 | * If alt_num is NULL, just clear current ALTCx selection | |
281 | * to make sure we come back to a pure ALTC selection | |
282 | */ | |
283 | if (!alt_num) { | |
284 | for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { | |
285 | if (pin_desc->altcx[i].used == true) { | |
286 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
287 | bit = pin_desc->altcx[i].control_bit; | |
288 | if (prcmu_read(reg) & BIT(bit)) { | |
289 | prcmu_write_masked(reg, BIT(bit), 0); | |
290 | dev_dbg(npct->dev, | |
291 | "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", | |
292 | offset, i+1); | |
293 | } | |
294 | } | |
295 | } | |
296 | return; | |
297 | } | |
298 | ||
299 | alt_index = alt_num - 1; | |
300 | if (pin_desc->altcx[alt_index].used == false) { | |
301 | dev_warn(npct->dev, | |
302 | "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n", | |
303 | offset, alt_num); | |
304 | return; | |
305 | } | |
306 | ||
307 | /* | |
308 | * Check if any other ALTCx functions are activated on this pin | |
309 | * and disable it first. | |
310 | */ | |
311 | for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { | |
312 | if (i == alt_index) | |
313 | continue; | |
314 | if (pin_desc->altcx[i].used == true) { | |
315 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
316 | bit = pin_desc->altcx[i].control_bit; | |
317 | if (prcmu_read(reg) & BIT(bit)) { | |
318 | prcmu_write_masked(reg, BIT(bit), 0); | |
319 | dev_dbg(npct->dev, | |
320 | "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", | |
321 | offset, i+1); | |
322 | } | |
323 | } | |
324 | } | |
325 | ||
326 | reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; | |
327 | bit = pin_desc->altcx[alt_index].control_bit; | |
328 | dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n", | |
329 | offset, alt_index+1); | |
330 | prcmu_write_masked(reg, BIT(bit), BIT(bit)); | |
331 | } | |
332 | ||
378be066 | 333 | static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, |
01727e61 | 334 | pin_cfg_t cfg, bool sleep, unsigned int *slpmregs) |
378be066 RV |
335 | { |
336 | static const char *afnames[] = { | |
337 | [NMK_GPIO_ALT_GPIO] = "GPIO", | |
338 | [NMK_GPIO_ALT_A] = "A", | |
339 | [NMK_GPIO_ALT_B] = "B", | |
340 | [NMK_GPIO_ALT_C] = "C" | |
341 | }; | |
342 | static const char *pullnames[] = { | |
343 | [NMK_GPIO_PULL_NONE] = "none", | |
344 | [NMK_GPIO_PULL_UP] = "up", | |
345 | [NMK_GPIO_PULL_DOWN] = "down", | |
346 | [3] /* illegal */ = "??" | |
347 | }; | |
348 | static const char *slpmnames[] = { | |
7e3f7e59 RV |
349 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", |
350 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
378be066 RV |
351 | }; |
352 | ||
353 | int pin = PIN_NUM(cfg); | |
354 | int pull = PIN_PULL(cfg); | |
355 | int af = PIN_ALT(cfg); | |
356 | int slpm = PIN_SLPM(cfg); | |
6720db7c RV |
357 | int output = PIN_DIR(cfg); |
358 | int val = PIN_VAL(cfg); | |
01727e61 | 359 | bool glitch = af == NMK_GPIO_ALT_C; |
378be066 | 360 | |
dacdc96c RV |
361 | dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n", |
362 | pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm], | |
6720db7c RV |
363 | output ? "output " : "input", |
364 | output ? (val ? "high" : "low") : ""); | |
365 | ||
dacdc96c RV |
366 | if (sleep) { |
367 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
368 | int slpm_output = PIN_SLPM_DIR(cfg); | |
369 | int slpm_val = PIN_SLPM_VAL(cfg); | |
370 | ||
3546d15c RV |
371 | af = NMK_GPIO_ALT_GPIO; |
372 | ||
dacdc96c RV |
373 | /* |
374 | * The SLPM_* values are normal values + 1 to allow zero to | |
375 | * mean "same as normal". | |
376 | */ | |
377 | if (slpm_pull) | |
378 | pull = slpm_pull - 1; | |
379 | if (slpm_output) | |
380 | output = slpm_output - 1; | |
381 | if (slpm_val) | |
382 | val = slpm_val - 1; | |
383 | ||
384 | dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", | |
385 | pin, | |
386 | slpm_pull ? pullnames[pull] : "same", | |
387 | slpm_output ? (output ? "output" : "input") : "same", | |
388 | slpm_val ? (val ? "high" : "low") : "same"); | |
389 | } | |
390 | ||
6720db7c RV |
391 | if (output) |
392 | __nmk_gpio_make_output(nmk_chip, offset, val); | |
393 | else { | |
394 | __nmk_gpio_make_input(nmk_chip, offset); | |
395 | __nmk_gpio_set_pull(nmk_chip, offset, pull); | |
396 | } | |
378be066 | 397 | |
ebc6178d RV |
398 | __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg)); |
399 | ||
6c42ad1c RV |
400 | /* |
401 | * If the pin is switching to altfunc, and there was an interrupt | |
402 | * installed on it which has been lazy disabled, actually mask the | |
403 | * interrupt to prevent spurious interrupts that would occur while the | |
404 | * pin is under control of the peripheral. Only SKE does this. | |
405 | */ | |
406 | if (af != NMK_GPIO_ALT_GPIO) | |
407 | nmk_gpio_disable_lazy_irq(nmk_chip, offset); | |
408 | ||
01727e61 RV |
409 | /* |
410 | * If we've backed up the SLPM registers (glitch workaround), modify | |
411 | * the backups since they will be restored. | |
412 | */ | |
413 | if (slpmregs) { | |
414 | if (slpm == NMK_GPIO_SLPM_NOCHANGE) | |
415 | slpmregs[nmk_chip->bank] |= BIT(offset); | |
416 | else | |
417 | slpmregs[nmk_chip->bank] &= ~BIT(offset); | |
418 | } else | |
419 | __nmk_gpio_set_slpm(nmk_chip, offset, slpm); | |
420 | ||
421 | __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch); | |
422 | } | |
423 | ||
424 | /* | |
425 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
426 | * - Save SLPM registers | |
427 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
428 | * - Configure the GPIO registers for the IOs that are being switched | |
429 | * - Set IOFORCE=1 | |
430 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
431 | * - Set IOFORCE=0 | |
432 | * - Restore SLPM registers | |
433 | * - Any spurious wake up event during switch sequence to be ignored and | |
434 | * cleared | |
435 | */ | |
436 | static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) | |
437 | { | |
438 | int i; | |
439 | ||
440 | for (i = 0; i < NUM_BANKS; i++) { | |
441 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
442 | unsigned int temp = slpm[i]; | |
443 | ||
444 | if (!chip) | |
445 | break; | |
446 | ||
3c0227d2 RV |
447 | clk_enable(chip->clk); |
448 | ||
01727e61 RV |
449 | slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); |
450 | writel(temp, chip->addr + NMK_GPIO_SLPC); | |
451 | } | |
452 | } | |
453 | ||
454 | static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) | |
455 | { | |
456 | int i; | |
457 | ||
458 | for (i = 0; i < NUM_BANKS; i++) { | |
459 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
460 | ||
461 | if (!chip) | |
462 | break; | |
463 | ||
464 | writel(slpm[i], chip->addr + NMK_GPIO_SLPC); | |
3c0227d2 RV |
465 | |
466 | clk_disable(chip->clk); | |
01727e61 RV |
467 | } |
468 | } | |
469 | ||
470 | static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) | |
471 | { | |
472 | static unsigned int slpm[NUM_BANKS]; | |
473 | unsigned long flags; | |
474 | bool glitch = false; | |
475 | int ret = 0; | |
476 | int i; | |
477 | ||
478 | for (i = 0; i < num; i++) { | |
479 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) { | |
480 | glitch = true; | |
481 | break; | |
482 | } | |
483 | } | |
484 | ||
485 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | |
486 | ||
487 | if (glitch) { | |
488 | memset(slpm, 0xff, sizeof(slpm)); | |
489 | ||
490 | for (i = 0; i < num; i++) { | |
491 | int pin = PIN_NUM(cfgs[i]); | |
492 | int offset = pin % NMK_GPIO_PER_CHIP; | |
493 | ||
494 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) | |
495 | slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset); | |
496 | } | |
497 | ||
498 | nmk_gpio_glitch_slpm_init(slpm); | |
499 | } | |
500 | ||
501 | for (i = 0; i < num; i++) { | |
502 | struct nmk_gpio_chip *nmk_chip; | |
503 | int pin = PIN_NUM(cfgs[i]); | |
504 | ||
a60b57ed | 505 | nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP]; |
01727e61 RV |
506 | if (!nmk_chip) { |
507 | ret = -EINVAL; | |
508 | break; | |
509 | } | |
510 | ||
3c0227d2 | 511 | clk_enable(nmk_chip->clk); |
01727e61 | 512 | spin_lock(&nmk_chip->lock); |
a60b57ed | 513 | __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP, |
01727e61 RV |
514 | cfgs[i], sleep, glitch ? slpm : NULL); |
515 | spin_unlock(&nmk_chip->lock); | |
3c0227d2 | 516 | clk_disable(nmk_chip->clk); |
01727e61 RV |
517 | } |
518 | ||
519 | if (glitch) | |
520 | nmk_gpio_glitch_slpm_restore(slpm); | |
521 | ||
522 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
523 | ||
524 | return ret; | |
378be066 RV |
525 | } |
526 | ||
527 | /** | |
528 | * nmk_config_pin - configure a pin's mux attributes | |
529 | * @cfg: pin confguration | |
50bcd47c | 530 | * @sleep: Non-zero to apply the sleep mode configuration |
378be066 RV |
531 | * Configures a pin's mode (alternate function or GPIO), its pull up status, |
532 | * and its sleep mode based on the specified configuration. The @cfg is | |
533 | * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These | |
534 | * are constructed using, and can be further enhanced with, the macros in | |
287f121c | 535 | * <linux/platform_data/pinctrl-nomadik.h> |
378be066 RV |
536 | * |
537 | * If a pin's mode is set to GPIO, it is configured as an input to avoid | |
538 | * side-effects. The gpio can be manipulated later using standard GPIO API | |
539 | * calls. | |
540 | */ | |
dacdc96c | 541 | int nmk_config_pin(pin_cfg_t cfg, bool sleep) |
378be066 | 542 | { |
01727e61 | 543 | return __nmk_config_pins(&cfg, 1, sleep); |
378be066 RV |
544 | } |
545 | EXPORT_SYMBOL(nmk_config_pin); | |
546 | ||
547 | /** | |
548 | * nmk_config_pins - configure several pins at once | |
549 | * @cfgs: array of pin configurations | |
550 | * @num: number of elments in the array | |
551 | * | |
552 | * Configures several pins using nmk_config_pin(). Refer to that function for | |
553 | * further information. | |
554 | */ | |
555 | int nmk_config_pins(pin_cfg_t *cfgs, int num) | |
556 | { | |
01727e61 | 557 | return __nmk_config_pins(cfgs, num, false); |
378be066 RV |
558 | } |
559 | EXPORT_SYMBOL(nmk_config_pins); | |
560 | ||
dacdc96c RV |
561 | int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num) |
562 | { | |
01727e61 | 563 | return __nmk_config_pins(cfgs, num, true); |
dacdc96c RV |
564 | } |
565 | EXPORT_SYMBOL(nmk_config_pins_sleep); | |
566 | ||
81a3c298 RV |
567 | /** |
568 | * nmk_gpio_set_slpm() - configure the sleep mode of a pin | |
569 | * @gpio: pin number | |
570 | * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE, | |
571 | * | |
33d78647 LW |
572 | * This register is actually in the pinmux layer, not the GPIO block itself. |
573 | * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP | |
574 | * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code). | |
575 | * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is | |
576 | * HIGH, overriding the normal setting defined by GPIO_AFSELx registers. | |
577 | * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit), | |
578 | * the GPIOs return to the normal setting defined by GPIO_AFSELx registers. | |
7e3f7e59 | 579 | * |
33d78647 LW |
580 | * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO |
581 | * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is | |
582 | * entered) regardless of the altfunction selected. Also wake-up detection is | |
583 | * ENABLED. | |
584 | * | |
585 | * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains | |
586 | * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS | |
587 | * (for altfunction GPIO) or respective on-chip peripherals (for other | |
588 | * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED. | |
589 | * | |
590 | * Note that enable_irq_wake() will automatically enable wakeup detection. | |
81a3c298 RV |
591 | */ |
592 | int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) | |
593 | { | |
594 | struct nmk_gpio_chip *nmk_chip; | |
595 | unsigned long flags; | |
596 | ||
a60b57ed | 597 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
81a3c298 RV |
598 | if (!nmk_chip) |
599 | return -EINVAL; | |
600 | ||
3c0227d2 | 601 | clk_enable(nmk_chip->clk); |
01727e61 RV |
602 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
603 | spin_lock(&nmk_chip->lock); | |
604 | ||
a60b57ed | 605 | __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode); |
01727e61 RV |
606 | |
607 | spin_unlock(&nmk_chip->lock); | |
608 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 609 | clk_disable(nmk_chip->clk); |
81a3c298 RV |
610 | |
611 | return 0; | |
612 | } | |
613 | ||
5b327edf RV |
614 | /** |
615 | * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio | |
616 | * @gpio: pin number | |
617 | * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE | |
618 | * | |
619 | * Enables/disables pull up/down on a specified pin. This only takes effect if | |
620 | * the pin is configured as an input (either explicitly or by the alternate | |
621 | * function). | |
622 | * | |
623 | * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is | |
624 | * configured as an input. Otherwise, due to the way the controller registers | |
625 | * work, this function will change the value output on the pin. | |
626 | */ | |
627 | int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) | |
628 | { | |
629 | struct nmk_gpio_chip *nmk_chip; | |
630 | unsigned long flags; | |
631 | ||
a60b57ed | 632 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
5b327edf RV |
633 | if (!nmk_chip) |
634 | return -EINVAL; | |
635 | ||
3c0227d2 | 636 | clk_enable(nmk_chip->clk); |
5b327edf | 637 | spin_lock_irqsave(&nmk_chip->lock, flags); |
a60b57ed | 638 | __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull); |
5b327edf | 639 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 640 | clk_disable(nmk_chip->clk); |
5b327edf RV |
641 | |
642 | return 0; | |
643 | } | |
644 | ||
2ec1d359 | 645 | /* Mode functions */ |
9c66ee6f JA |
646 | /** |
647 | * nmk_gpio_set_mode() - set the mux mode of a gpio pin | |
648 | * @gpio: pin number | |
649 | * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A, | |
650 | * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C | |
651 | * | |
652 | * Sets the mode of the specified pin to one of the alternate functions or | |
653 | * plain GPIO. | |
654 | */ | |
2ec1d359 AR |
655 | int nmk_gpio_set_mode(int gpio, int gpio_mode) |
656 | { | |
657 | struct nmk_gpio_chip *nmk_chip; | |
658 | unsigned long flags; | |
2ec1d359 | 659 | |
a60b57ed | 660 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
2ec1d359 AR |
661 | if (!nmk_chip) |
662 | return -EINVAL; | |
663 | ||
3c0227d2 | 664 | clk_enable(nmk_chip->clk); |
2ec1d359 | 665 | spin_lock_irqsave(&nmk_chip->lock, flags); |
a60b57ed | 666 | __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode); |
2ec1d359 | 667 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 668 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
669 | |
670 | return 0; | |
671 | } | |
672 | EXPORT_SYMBOL(nmk_gpio_set_mode); | |
673 | ||
674 | int nmk_gpio_get_mode(int gpio) | |
675 | { | |
676 | struct nmk_gpio_chip *nmk_chip; | |
677 | u32 afunc, bfunc, bit; | |
678 | ||
a60b57ed | 679 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
2ec1d359 AR |
680 | if (!nmk_chip) |
681 | return -EINVAL; | |
682 | ||
a60b57ed | 683 | bit = 1 << (gpio % NMK_GPIO_PER_CHIP); |
2ec1d359 | 684 | |
3c0227d2 RV |
685 | clk_enable(nmk_chip->clk); |
686 | ||
2ec1d359 AR |
687 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; |
688 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; | |
689 | ||
3c0227d2 RV |
690 | clk_disable(nmk_chip->clk); |
691 | ||
2ec1d359 AR |
692 | return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); |
693 | } | |
694 | EXPORT_SYMBOL(nmk_gpio_get_mode); | |
695 | ||
696 | ||
697 | /* IRQ functions */ | |
698 | static inline int nmk_gpio_get_bitmask(int gpio) | |
699 | { | |
a60b57ed | 700 | return 1 << (gpio % NMK_GPIO_PER_CHIP); |
2ec1d359 AR |
701 | } |
702 | ||
f272c00e | 703 | static void nmk_gpio_irq_ack(struct irq_data *d) |
2ec1d359 | 704 | { |
2ec1d359 AR |
705 | struct nmk_gpio_chip *nmk_chip; |
706 | ||
f272c00e | 707 | nmk_chip = irq_data_get_irq_chip_data(d); |
2ec1d359 AR |
708 | if (!nmk_chip) |
709 | return; | |
3c0227d2 RV |
710 | |
711 | clk_enable(nmk_chip->clk); | |
a60b57ed | 712 | writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); |
3c0227d2 | 713 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
714 | } |
715 | ||
4d4e20f7 RV |
716 | enum nmk_gpio_irq_type { |
717 | NORMAL, | |
718 | WAKE, | |
719 | }; | |
720 | ||
040e5ecd | 721 | static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, |
4d4e20f7 RV |
722 | int gpio, enum nmk_gpio_irq_type which, |
723 | bool enable) | |
2ec1d359 | 724 | { |
040e5ecd | 725 | u32 bitmask = nmk_gpio_get_bitmask(gpio); |
6c12fe88 RV |
726 | u32 *rimscval; |
727 | u32 *fimscval; | |
728 | u32 rimscreg; | |
729 | u32 fimscreg; | |
730 | ||
731 | if (which == NORMAL) { | |
732 | rimscreg = NMK_GPIO_RIMSC; | |
733 | fimscreg = NMK_GPIO_FIMSC; | |
734 | rimscval = &nmk_chip->rimsc; | |
735 | fimscval = &nmk_chip->fimsc; | |
736 | } else { | |
737 | rimscreg = NMK_GPIO_RWIMSC; | |
738 | fimscreg = NMK_GPIO_FWIMSC; | |
739 | rimscval = &nmk_chip->rwimsc; | |
740 | fimscval = &nmk_chip->fwimsc; | |
741 | } | |
2ec1d359 | 742 | |
040e5ecd | 743 | /* we must individually set/clear the two edges */ |
2ec1d359 | 744 | if (nmk_chip->edge_rising & bitmask) { |
040e5ecd | 745 | if (enable) |
6c12fe88 | 746 | *rimscval |= bitmask; |
040e5ecd | 747 | else |
6c12fe88 RV |
748 | *rimscval &= ~bitmask; |
749 | writel(*rimscval, nmk_chip->addr + rimscreg); | |
2ec1d359 AR |
750 | } |
751 | if (nmk_chip->edge_falling & bitmask) { | |
040e5ecd | 752 | if (enable) |
6c12fe88 | 753 | *fimscval |= bitmask; |
040e5ecd | 754 | else |
6c12fe88 RV |
755 | *fimscval &= ~bitmask; |
756 | writel(*fimscval, nmk_chip->addr + fimscreg); | |
2ec1d359 | 757 | } |
040e5ecd | 758 | } |
2ec1d359 | 759 | |
b9df468d RV |
760 | static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, |
761 | int gpio, bool on) | |
762 | { | |
b982ff0e RV |
763 | /* |
764 | * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is | |
765 | * disabled, since setting SLPM to 1 increases power consumption, and | |
766 | * wakeup is anyhow controlled by the RIMSC and FIMSC registers. | |
767 | */ | |
768 | if (nmk_chip->sleepmode && on) { | |
e85bbc19 | 769 | __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, |
b982ff0e | 770 | NMK_GPIO_SLPM_WAKEUP_ENABLE); |
33d78647 LW |
771 | } |
772 | ||
b9df468d RV |
773 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); |
774 | } | |
775 | ||
776 | static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) | |
2ec1d359 | 777 | { |
2ec1d359 AR |
778 | struct nmk_gpio_chip *nmk_chip; |
779 | unsigned long flags; | |
040e5ecd | 780 | u32 bitmask; |
2ec1d359 | 781 | |
f272c00e | 782 | nmk_chip = irq_data_get_irq_chip_data(d); |
a60b57ed | 783 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
2ec1d359 | 784 | if (!nmk_chip) |
4d4e20f7 | 785 | return -EINVAL; |
2ec1d359 | 786 | |
3c0227d2 | 787 | clk_enable(nmk_chip->clk); |
b9df468d RV |
788 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
789 | spin_lock(&nmk_chip->lock); | |
790 | ||
a60b57ed | 791 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); |
b9df468d RV |
792 | |
793 | if (!(nmk_chip->real_wake & bitmask)) | |
a60b57ed | 794 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); |
b9df468d RV |
795 | |
796 | spin_unlock(&nmk_chip->lock); | |
797 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 798 | clk_disable(nmk_chip->clk); |
4d4e20f7 RV |
799 | |
800 | return 0; | |
2ec1d359 AR |
801 | } |
802 | ||
f272c00e | 803 | static void nmk_gpio_irq_mask(struct irq_data *d) |
040e5ecd | 804 | { |
b9df468d | 805 | nmk_gpio_irq_maskunmask(d, false); |
4d4e20f7 | 806 | } |
040e5ecd | 807 | |
f272c00e | 808 | static void nmk_gpio_irq_unmask(struct irq_data *d) |
040e5ecd | 809 | { |
b9df468d | 810 | nmk_gpio_irq_maskunmask(d, true); |
4d4e20f7 RV |
811 | } |
812 | ||
f272c00e | 813 | static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
4d4e20f7 | 814 | { |
7e3f7e59 RV |
815 | struct nmk_gpio_chip *nmk_chip; |
816 | unsigned long flags; | |
b9df468d | 817 | u32 bitmask; |
7e3f7e59 | 818 | |
f272c00e | 819 | nmk_chip = irq_data_get_irq_chip_data(d); |
7e3f7e59 RV |
820 | if (!nmk_chip) |
821 | return -EINVAL; | |
a60b57ed | 822 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
7e3f7e59 | 823 | |
3c0227d2 | 824 | clk_enable(nmk_chip->clk); |
01727e61 RV |
825 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
826 | spin_lock(&nmk_chip->lock); | |
827 | ||
479a0c7e | 828 | if (irqd_irq_disabled(d)) |
a60b57ed | 829 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); |
b9df468d RV |
830 | |
831 | if (on) | |
832 | nmk_chip->real_wake |= bitmask; | |
833 | else | |
834 | nmk_chip->real_wake &= ~bitmask; | |
01727e61 RV |
835 | |
836 | spin_unlock(&nmk_chip->lock); | |
837 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 838 | clk_disable(nmk_chip->clk); |
7e3f7e59 RV |
839 | |
840 | return 0; | |
040e5ecd RV |
841 | } |
842 | ||
f272c00e | 843 | static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
2ec1d359 | 844 | { |
479a0c7e | 845 | bool enabled = !irqd_irq_disabled(d); |
3c0227d2 | 846 | bool wake = irqd_is_wakeup_set(d); |
2ec1d359 AR |
847 | struct nmk_gpio_chip *nmk_chip; |
848 | unsigned long flags; | |
849 | u32 bitmask; | |
850 | ||
f272c00e | 851 | nmk_chip = irq_data_get_irq_chip_data(d); |
a60b57ed | 852 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
2ec1d359 AR |
853 | if (!nmk_chip) |
854 | return -EINVAL; | |
2ec1d359 AR |
855 | if (type & IRQ_TYPE_LEVEL_HIGH) |
856 | return -EINVAL; | |
857 | if (type & IRQ_TYPE_LEVEL_LOW) | |
858 | return -EINVAL; | |
859 | ||
3c0227d2 | 860 | clk_enable(nmk_chip->clk); |
2ec1d359 AR |
861 | spin_lock_irqsave(&nmk_chip->lock, flags); |
862 | ||
7a852d80 | 863 | if (enabled) |
a60b57ed | 864 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); |
4d4e20f7 | 865 | |
b9df468d | 866 | if (enabled || wake) |
a60b57ed | 867 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); |
7a852d80 | 868 | |
2ec1d359 AR |
869 | nmk_chip->edge_rising &= ~bitmask; |
870 | if (type & IRQ_TYPE_EDGE_RISING) | |
871 | nmk_chip->edge_rising |= bitmask; | |
2ec1d359 AR |
872 | |
873 | nmk_chip->edge_falling &= ~bitmask; | |
874 | if (type & IRQ_TYPE_EDGE_FALLING) | |
875 | nmk_chip->edge_falling |= bitmask; | |
2ec1d359 | 876 | |
7a852d80 | 877 | if (enabled) |
a60b57ed | 878 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); |
4d4e20f7 | 879 | |
b9df468d | 880 | if (enabled || wake) |
a60b57ed | 881 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); |
2ec1d359 | 882 | |
7a852d80 | 883 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 884 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
885 | |
886 | return 0; | |
887 | } | |
888 | ||
3c0227d2 RV |
889 | static unsigned int nmk_gpio_irq_startup(struct irq_data *d) |
890 | { | |
891 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 | 892 | |
3c0227d2 RV |
893 | clk_enable(nmk_chip->clk); |
894 | nmk_gpio_irq_unmask(d); | |
2ec1d359 AR |
895 | return 0; |
896 | } | |
897 | ||
3c0227d2 RV |
898 | static void nmk_gpio_irq_shutdown(struct irq_data *d) |
899 | { | |
900 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
901 | ||
902 | nmk_gpio_irq_mask(d); | |
903 | clk_disable(nmk_chip->clk); | |
904 | } | |
905 | ||
2ec1d359 AR |
906 | static struct irq_chip nmk_gpio_irq_chip = { |
907 | .name = "Nomadik-GPIO", | |
f272c00e LB |
908 | .irq_ack = nmk_gpio_irq_ack, |
909 | .irq_mask = nmk_gpio_irq_mask, | |
910 | .irq_unmask = nmk_gpio_irq_unmask, | |
911 | .irq_set_type = nmk_gpio_irq_set_type, | |
912 | .irq_set_wake = nmk_gpio_irq_set_wake, | |
3c0227d2 RV |
913 | .irq_startup = nmk_gpio_irq_startup, |
914 | .irq_shutdown = nmk_gpio_irq_shutdown, | |
4921e745 | 915 | .flags = IRQCHIP_MASK_ON_SUSPEND, |
2ec1d359 AR |
916 | }; |
917 | ||
33b744b3 RV |
918 | static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, |
919 | u32 status) | |
2ec1d359 AR |
920 | { |
921 | struct nmk_gpio_chip *nmk_chip; | |
6845664a | 922 | struct irq_chip *host_chip = irq_get_chip(irq); |
2ec1d359 | 923 | |
adfed159 | 924 | chained_irq_enter(host_chip, desc); |
aaedaa2b | 925 | |
6845664a | 926 | nmk_chip = irq_get_handler_data(irq); |
33b744b3 RV |
927 | while (status) { |
928 | int bit = __ffs(status); | |
929 | ||
95f0bc9b | 930 | generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit)); |
33b744b3 | 931 | status &= ~BIT(bit); |
2ec1d359 | 932 | } |
aaedaa2b | 933 | |
adfed159 | 934 | chained_irq_exit(host_chip, desc); |
2ec1d359 AR |
935 | } |
936 | ||
33b744b3 RV |
937 | static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
938 | { | |
6845664a | 939 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
3c0227d2 RV |
940 | u32 status; |
941 | ||
942 | clk_enable(nmk_chip->clk); | |
943 | status = readl(nmk_chip->addr + NMK_GPIO_IS); | |
944 | clk_disable(nmk_chip->clk); | |
33b744b3 RV |
945 | |
946 | __nmk_gpio_irq_handler(irq, desc, status); | |
947 | } | |
948 | ||
949 | static void nmk_gpio_secondary_irq_handler(unsigned int irq, | |
950 | struct irq_desc *desc) | |
951 | { | |
6845664a | 952 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
33b744b3 RV |
953 | u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); |
954 | ||
955 | __nmk_gpio_irq_handler(irq, desc, status); | |
956 | } | |
957 | ||
2ec1d359 AR |
958 | static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) |
959 | { | |
6845664a TG |
960 | irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); |
961 | irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); | |
33b744b3 RV |
962 | |
963 | if (nmk_chip->secondary_parent_irq >= 0) { | |
6845664a | 964 | irq_set_chained_handler(nmk_chip->secondary_parent_irq, |
33b744b3 | 965 | nmk_gpio_secondary_irq_handler); |
6845664a | 966 | irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); |
33b744b3 RV |
967 | } |
968 | ||
2ec1d359 AR |
969 | return 0; |
970 | } | |
971 | ||
972 | /* I/O Functions */ | |
dbfe8ca2 LW |
973 | |
974 | static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset) | |
975 | { | |
976 | /* | |
977 | * Map back to global GPIO space and request muxing, the direction | |
978 | * parameter does not matter for this controller. | |
979 | */ | |
980 | int gpio = chip->base + offset; | |
981 | ||
982 | return pinctrl_request_gpio(gpio); | |
983 | } | |
984 | ||
985 | static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset) | |
986 | { | |
987 | int gpio = chip->base + offset; | |
988 | ||
989 | pinctrl_free_gpio(gpio); | |
990 | } | |
991 | ||
2ec1d359 AR |
992 | static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) |
993 | { | |
994 | struct nmk_gpio_chip *nmk_chip = | |
995 | container_of(chip, struct nmk_gpio_chip, chip); | |
996 | ||
3c0227d2 RV |
997 | clk_enable(nmk_chip->clk); |
998 | ||
2ec1d359 | 999 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); |
3c0227d2 RV |
1000 | |
1001 | clk_disable(nmk_chip->clk); | |
1002 | ||
2ec1d359 AR |
1003 | return 0; |
1004 | } | |
1005 | ||
2ec1d359 AR |
1006 | static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) |
1007 | { | |
1008 | struct nmk_gpio_chip *nmk_chip = | |
1009 | container_of(chip, struct nmk_gpio_chip, chip); | |
1010 | u32 bit = 1 << offset; | |
3c0227d2 RV |
1011 | int value; |
1012 | ||
1013 | clk_enable(nmk_chip->clk); | |
2ec1d359 | 1014 | |
3c0227d2 | 1015 | value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; |
2ec1d359 | 1016 | |
3c0227d2 RV |
1017 | clk_disable(nmk_chip->clk); |
1018 | ||
1019 | return value; | |
2ec1d359 AR |
1020 | } |
1021 | ||
1022 | static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, | |
1023 | int val) | |
1024 | { | |
1025 | struct nmk_gpio_chip *nmk_chip = | |
1026 | container_of(chip, struct nmk_gpio_chip, chip); | |
2ec1d359 | 1027 | |
3c0227d2 RV |
1028 | clk_enable(nmk_chip->clk); |
1029 | ||
6720db7c | 1030 | __nmk_gpio_set_output(nmk_chip, offset, val); |
3c0227d2 RV |
1031 | |
1032 | clk_disable(nmk_chip->clk); | |
2ec1d359 AR |
1033 | } |
1034 | ||
6647c6c0 RV |
1035 | static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, |
1036 | int val) | |
1037 | { | |
1038 | struct nmk_gpio_chip *nmk_chip = | |
1039 | container_of(chip, struct nmk_gpio_chip, chip); | |
1040 | ||
3c0227d2 RV |
1041 | clk_enable(nmk_chip->clk); |
1042 | ||
6720db7c | 1043 | __nmk_gpio_make_output(nmk_chip, offset, val); |
6647c6c0 | 1044 | |
3c0227d2 RV |
1045 | clk_disable(nmk_chip->clk); |
1046 | ||
6647c6c0 RV |
1047 | return 0; |
1048 | } | |
1049 | ||
0d2aec9c RV |
1050 | static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
1051 | { | |
1052 | struct nmk_gpio_chip *nmk_chip = | |
1053 | container_of(chip, struct nmk_gpio_chip, chip); | |
1054 | ||
268300be | 1055 | return irq_create_mapping(nmk_chip->domain, offset); |
0d2aec9c RV |
1056 | } |
1057 | ||
d0b543c7 RV |
1058 | #ifdef CONFIG_DEBUG_FS |
1059 | ||
1060 | #include <linux/seq_file.h> | |
1061 | ||
6f4350a6 LW |
1062 | static void nmk_gpio_dbg_show_one(struct seq_file *s, struct gpio_chip *chip, |
1063 | unsigned offset, unsigned gpio) | |
d0b543c7 | 1064 | { |
6f4350a6 | 1065 | const char *label = gpiochip_is_requested(chip, offset); |
d0b543c7 RV |
1066 | struct nmk_gpio_chip *nmk_chip = |
1067 | container_of(chip, struct nmk_gpio_chip, chip); | |
6f4350a6 LW |
1068 | int mode; |
1069 | bool is_out; | |
1070 | bool pull; | |
1071 | u32 bit = 1 << offset; | |
d0b543c7 RV |
1072 | const char *modes[] = { |
1073 | [NMK_GPIO_ALT_GPIO] = "gpio", | |
1074 | [NMK_GPIO_ALT_A] = "altA", | |
1075 | [NMK_GPIO_ALT_B] = "altB", | |
1076 | [NMK_GPIO_ALT_C] = "altC", | |
1077 | }; | |
1078 | ||
3c0227d2 | 1079 | clk_enable(nmk_chip->clk); |
6f4350a6 LW |
1080 | is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit); |
1081 | pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); | |
1082 | mode = nmk_gpio_get_mode(gpio); | |
1083 | ||
1084 | seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", | |
1085 | gpio, label ?: "(none)", | |
1086 | is_out ? "out" : "in ", | |
1087 | chip->get | |
1088 | ? (chip->get(chip, offset) ? "hi" : "lo") | |
1089 | : "? ", | |
1090 | (mode < 0) ? "unknown" : modes[mode], | |
1091 | pull ? "pull" : "none"); | |
1092 | ||
1093 | if (label && !is_out) { | |
1094 | int irq = gpio_to_irq(gpio); | |
1095 | struct irq_desc *desc = irq_to_desc(irq); | |
1096 | ||
1097 | /* This races with request_irq(), set_irq_type(), | |
1098 | * and set_irq_wake() ... but those are "rare". | |
1099 | */ | |
1100 | if (irq >= 0 && desc->action) { | |
1101 | char *trigger; | |
1102 | u32 bitmask = nmk_gpio_get_bitmask(gpio); | |
1103 | ||
1104 | if (nmk_chip->edge_rising & bitmask) | |
1105 | trigger = "edge-rising"; | |
1106 | else if (nmk_chip->edge_falling & bitmask) | |
1107 | trigger = "edge-falling"; | |
1108 | else | |
1109 | trigger = "edge-undefined"; | |
1110 | ||
1111 | seq_printf(s, " irq-%d %s%s", | |
1112 | irq, trigger, | |
1113 | irqd_is_wakeup_set(&desc->irq_data) | |
1114 | ? " wakeup" : ""); | |
8ea72a30 | 1115 | } |
6f4350a6 LW |
1116 | } |
1117 | clk_disable(nmk_chip->clk); | |
1118 | } | |
1119 | ||
1120 | static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
1121 | { | |
1122 | unsigned i; | |
1123 | unsigned gpio = chip->base; | |
8ea72a30 | 1124 | |
6f4350a6 LW |
1125 | for (i = 0; i < chip->ngpio; i++, gpio++) { |
1126 | nmk_gpio_dbg_show_one(s, chip, i, gpio); | |
d0b543c7 RV |
1127 | seq_printf(s, "\n"); |
1128 | } | |
1129 | } | |
1130 | ||
1131 | #else | |
6f4350a6 LW |
1132 | static inline void nmk_gpio_dbg_show_one(struct seq_file *s, |
1133 | struct gpio_chip *chip, | |
1134 | unsigned offset, unsigned gpio) | |
1135 | { | |
1136 | } | |
d0b543c7 RV |
1137 | #define nmk_gpio_dbg_show NULL |
1138 | #endif | |
1139 | ||
2ec1d359 AR |
1140 | /* This structure is replicated for each GPIO block allocated at probe time */ |
1141 | static struct gpio_chip nmk_gpio_template = { | |
dbfe8ca2 LW |
1142 | .request = nmk_gpio_request, |
1143 | .free = nmk_gpio_free, | |
2ec1d359 AR |
1144 | .direction_input = nmk_gpio_make_input, |
1145 | .get = nmk_gpio_get_input, | |
1146 | .direction_output = nmk_gpio_make_output, | |
1147 | .set = nmk_gpio_set_output, | |
0d2aec9c | 1148 | .to_irq = nmk_gpio_to_irq, |
d0b543c7 | 1149 | .dbg_show = nmk_gpio_dbg_show, |
2ec1d359 AR |
1150 | .can_sleep = 0, |
1151 | }; | |
1152 | ||
3c0227d2 RV |
1153 | void nmk_gpio_clocks_enable(void) |
1154 | { | |
1155 | int i; | |
1156 | ||
1157 | for (i = 0; i < NUM_BANKS; i++) { | |
1158 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1159 | ||
1160 | if (!chip) | |
1161 | continue; | |
1162 | ||
1163 | clk_enable(chip->clk); | |
1164 | } | |
1165 | } | |
1166 | ||
1167 | void nmk_gpio_clocks_disable(void) | |
1168 | { | |
1169 | int i; | |
1170 | ||
1171 | for (i = 0; i < NUM_BANKS; i++) { | |
1172 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1173 | ||
1174 | if (!chip) | |
1175 | continue; | |
1176 | ||
1177 | clk_disable(chip->clk); | |
1178 | } | |
1179 | } | |
1180 | ||
b9df468d RV |
1181 | /* |
1182 | * Called from the suspend/resume path to only keep the real wakeup interrupts | |
1183 | * (those that have had set_irq_wake() called on them) as wakeup interrupts, | |
1184 | * and not the rest of the interrupts which we needed to have as wakeups for | |
1185 | * cpuidle. | |
1186 | * | |
1187 | * PM ops are not used since this needs to be done at the end, after all the | |
1188 | * other drivers are done with their suspend callbacks. | |
1189 | */ | |
1190 | void nmk_gpio_wakeups_suspend(void) | |
1191 | { | |
1192 | int i; | |
1193 | ||
1194 | for (i = 0; i < NUM_BANKS; i++) { | |
1195 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1196 | ||
1197 | if (!chip) | |
1198 | break; | |
1199 | ||
3c0227d2 RV |
1200 | clk_enable(chip->clk); |
1201 | ||
b9df468d RV |
1202 | writel(chip->rwimsc & chip->real_wake, |
1203 | chip->addr + NMK_GPIO_RWIMSC); | |
1204 | writel(chip->fwimsc & chip->real_wake, | |
1205 | chip->addr + NMK_GPIO_FWIMSC); | |
1206 | ||
3c0227d2 | 1207 | clk_disable(chip->clk); |
b9df468d RV |
1208 | } |
1209 | } | |
1210 | ||
1211 | void nmk_gpio_wakeups_resume(void) | |
1212 | { | |
1213 | int i; | |
1214 | ||
1215 | for (i = 0; i < NUM_BANKS; i++) { | |
1216 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1217 | ||
1218 | if (!chip) | |
1219 | break; | |
1220 | ||
3c0227d2 RV |
1221 | clk_enable(chip->clk); |
1222 | ||
b9df468d RV |
1223 | writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); |
1224 | writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); | |
1225 | ||
3c0227d2 | 1226 | clk_disable(chip->clk); |
b9df468d RV |
1227 | } |
1228 | } | |
1229 | ||
bc6f5cf6 RA |
1230 | /* |
1231 | * Read the pull up/pull down status. | |
1232 | * A bit set in 'pull_up' means that pull up | |
1233 | * is selected if pull is enabled in PDIS register. | |
1234 | * Note: only pull up/down set via this driver can | |
1235 | * be detected due to HW limitations. | |
1236 | */ | |
1237 | void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) | |
1238 | { | |
1239 | if (gpio_bank < NUM_BANKS) { | |
1240 | struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; | |
1241 | ||
1242 | if (!chip) | |
1243 | return; | |
1244 | ||
1245 | *pull_up = chip->pull_up; | |
1246 | } | |
1247 | } | |
1248 | ||
a60b57ed LJ |
1249 | int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq, |
1250 | irq_hw_number_t hwirq) | |
1251 | { | |
1252 | struct nmk_gpio_chip *nmk_chip = d->host_data; | |
1253 | ||
1254 | if (!nmk_chip) | |
1255 | return -EINVAL; | |
1256 | ||
1257 | irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq); | |
1258 | set_irq_flags(irq, IRQF_VALID); | |
1259 | irq_set_chip_data(irq, nmk_chip); | |
1260 | irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING); | |
1261 | ||
1262 | return 0; | |
1263 | } | |
1264 | ||
1265 | const struct irq_domain_ops nmk_gpio_irq_simple_ops = { | |
1266 | .map = nmk_gpio_irq_map, | |
1267 | .xlate = irq_domain_xlate_twocell, | |
1268 | }; | |
1269 | ||
fd0d67d6 | 1270 | static int __devinit nmk_gpio_probe(struct platform_device *dev) |
2ec1d359 | 1271 | { |
3e3c62ca | 1272 | struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; |
513c27f8 | 1273 | struct device_node *np = dev->dev.of_node; |
2ec1d359 AR |
1274 | struct nmk_gpio_chip *nmk_chip; |
1275 | struct gpio_chip *chip; | |
3e3c62ca | 1276 | struct resource *res; |
af7dc228 | 1277 | struct clk *clk; |
33b744b3 | 1278 | int secondary_irq; |
8d91771c | 1279 | void __iomem *base; |
832b6cdf | 1280 | int irq_start = 0; |
3e3c62ca | 1281 | int irq; |
2ec1d359 AR |
1282 | int ret; |
1283 | ||
513c27f8 LJ |
1284 | if (!pdata && !np) { |
1285 | dev_err(&dev->dev, "No platform data or device tree found\n"); | |
3e3c62ca | 1286 | return -ENODEV; |
513c27f8 LJ |
1287 | } |
1288 | ||
1289 | if (np) { | |
5e754f33 | 1290 | pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL); |
513c27f8 LJ |
1291 | if (!pdata) |
1292 | return -ENOMEM; | |
1293 | ||
612e1d5f | 1294 | if (of_get_property(np, "st,supports-sleepmode", NULL)) |
513c27f8 LJ |
1295 | pdata->supports_sleepmode = true; |
1296 | ||
1297 | if (of_property_read_u32(np, "gpio-bank", &dev->id)) { | |
1298 | dev_err(&dev->dev, "gpio-bank property not found\n"); | |
1299 | ret = -EINVAL; | |
a60b57ed | 1300 | goto out; |
513c27f8 LJ |
1301 | } |
1302 | ||
1303 | pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP; | |
1304 | pdata->num_gpio = NMK_GPIO_PER_CHIP; | |
1305 | } | |
3e3c62ca RV |
1306 | |
1307 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
1308 | if (!res) { | |
1309 | ret = -ENOENT; | |
1310 | goto out; | |
1311 | } | |
1312 | ||
1313 | irq = platform_get_irq(dev, 0); | |
1314 | if (irq < 0) { | |
1315 | ret = irq; | |
1316 | goto out; | |
1317 | } | |
1318 | ||
33b744b3 RV |
1319 | secondary_irq = platform_get_irq(dev, 1); |
1320 | if (secondary_irq >= 0 && !pdata->get_secondary_status) { | |
1321 | ret = -EINVAL; | |
1322 | goto out; | |
1323 | } | |
1324 | ||
5e754f33 | 1325 | base = devm_request_and_ioremap(&dev->dev, res); |
8d91771c LW |
1326 | if (!base) { |
1327 | ret = -ENOMEM; | |
5e754f33 | 1328 | goto out; |
8d91771c LW |
1329 | } |
1330 | ||
5e754f33 | 1331 | clk = devm_clk_get(&dev->dev, NULL); |
af7dc228 RV |
1332 | if (IS_ERR(clk)) { |
1333 | ret = PTR_ERR(clk); | |
5e754f33 | 1334 | goto out; |
af7dc228 | 1335 | } |
efec381c | 1336 | clk_prepare(clk); |
af7dc228 | 1337 | |
5e754f33 | 1338 | nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL); |
2ec1d359 AR |
1339 | if (!nmk_chip) { |
1340 | ret = -ENOMEM; | |
5e754f33 | 1341 | goto out; |
2ec1d359 | 1342 | } |
513c27f8 | 1343 | |
2ec1d359 AR |
1344 | /* |
1345 | * The virt address in nmk_chip->addr is in the nomadik register space, | |
1346 | * so we can simply convert the resource address, without remapping | |
1347 | */ | |
33b744b3 | 1348 | nmk_chip->bank = dev->id; |
af7dc228 | 1349 | nmk_chip->clk = clk; |
8d91771c | 1350 | nmk_chip->addr = base; |
2ec1d359 | 1351 | nmk_chip->chip = nmk_gpio_template; |
3e3c62ca | 1352 | nmk_chip->parent_irq = irq; |
33b744b3 RV |
1353 | nmk_chip->secondary_parent_irq = secondary_irq; |
1354 | nmk_chip->get_secondary_status = pdata->get_secondary_status; | |
01727e61 | 1355 | nmk_chip->set_ioforce = pdata->set_ioforce; |
33d78647 | 1356 | nmk_chip->sleepmode = pdata->supports_sleepmode; |
c0fcb8db | 1357 | spin_lock_init(&nmk_chip->lock); |
2ec1d359 AR |
1358 | |
1359 | chip = &nmk_chip->chip; | |
1360 | chip->base = pdata->first_gpio; | |
e493e06f | 1361 | chip->ngpio = pdata->num_gpio; |
8d568ae5 | 1362 | chip->label = pdata->name ?: dev_name(&dev->dev); |
2ec1d359 AR |
1363 | chip->dev = &dev->dev; |
1364 | chip->owner = THIS_MODULE; | |
1365 | ||
ebc6178d RV |
1366 | clk_enable(nmk_chip->clk); |
1367 | nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); | |
1368 | clk_disable(nmk_chip->clk); | |
1369 | ||
072e82a1 | 1370 | #ifdef CONFIG_OF_GPIO |
513c27f8 | 1371 | chip->of_node = np; |
072e82a1 | 1372 | #endif |
513c27f8 | 1373 | |
2ec1d359 AR |
1374 | ret = gpiochip_add(&nmk_chip->chip); |
1375 | if (ret) | |
5e754f33 | 1376 | goto out; |
2ec1d359 | 1377 | |
01727e61 RV |
1378 | BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); |
1379 | ||
1380 | nmk_gpio_chips[nmk_chip->bank] = nmk_chip; | |
513c27f8 | 1381 | |
3e3c62ca | 1382 | platform_set_drvdata(dev, nmk_chip); |
2ec1d359 | 1383 | |
51f58c68 | 1384 | if (!np) |
6054b9ca | 1385 | irq_start = NOMADIK_GPIO_TO_IRQ(pdata->first_gpio); |
38843e29 | 1386 | nmk_chip->domain = irq_domain_add_simple(np, |
6054b9ca LW |
1387 | NMK_GPIO_PER_CHIP, irq_start, |
1388 | &nmk_gpio_irq_simple_ops, nmk_chip); | |
a60b57ed | 1389 | if (!nmk_chip->domain) { |
2ee38d4d | 1390 | dev_err(&dev->dev, "failed to create irqdomain\n"); |
a60b57ed | 1391 | ret = -ENOSYS; |
5e754f33 | 1392 | goto out; |
a60b57ed LJ |
1393 | } |
1394 | ||
2ec1d359 AR |
1395 | nmk_gpio_init_irq(nmk_chip); |
1396 | ||
513c27f8 LJ |
1397 | dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); |
1398 | ||
2ec1d359 AR |
1399 | return 0; |
1400 | ||
3e3c62ca | 1401 | out: |
2ec1d359 AR |
1402 | dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, |
1403 | pdata->first_gpio, pdata->first_gpio+31); | |
513c27f8 | 1404 | |
2ec1d359 AR |
1405 | return ret; |
1406 | } | |
1407 | ||
e98ea774 LW |
1408 | static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) |
1409 | { | |
1410 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1411 | ||
1412 | return npct->soc->ngroups; | |
1413 | } | |
1414 | ||
1415 | static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, | |
1416 | unsigned selector) | |
1417 | { | |
1418 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1419 | ||
1420 | return npct->soc->groups[selector].name; | |
1421 | } | |
1422 | ||
1423 | static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
1424 | const unsigned **pins, | |
1425 | unsigned *num_pins) | |
1426 | { | |
1427 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1428 | ||
1429 | *pins = npct->soc->groups[selector].pins; | |
1430 | *num_pins = npct->soc->groups[selector].npins; | |
1431 | return 0; | |
1432 | } | |
1433 | ||
24cbdd75 LW |
1434 | static struct pinctrl_gpio_range * |
1435 | nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset) | |
1436 | { | |
1437 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1438 | int i; | |
1439 | ||
1440 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) { | |
1441 | struct pinctrl_gpio_range *range; | |
1442 | ||
1443 | range = &npct->soc->gpio_ranges[i]; | |
1444 | if (offset >= range->pin_base && | |
1445 | offset <= (range->pin_base + range->npins - 1)) | |
1446 | return range; | |
1447 | } | |
1448 | return NULL; | |
1449 | } | |
1450 | ||
e98ea774 LW |
1451 | static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
1452 | unsigned offset) | |
1453 | { | |
24cbdd75 LW |
1454 | struct pinctrl_gpio_range *range; |
1455 | struct gpio_chip *chip; | |
1456 | ||
1457 | range = nmk_match_gpio_range(pctldev, offset); | |
1458 | if (!range || !range->gc) { | |
1459 | seq_printf(s, "invalid pin offset"); | |
1460 | return; | |
1461 | } | |
1462 | chip = range->gc; | |
1463 | nmk_gpio_dbg_show_one(s, chip, offset - chip->base, offset); | |
e98ea774 LW |
1464 | } |
1465 | ||
1466 | static struct pinctrl_ops nmk_pinctrl_ops = { | |
1467 | .get_groups_count = nmk_get_groups_cnt, | |
1468 | .get_group_name = nmk_get_group_name, | |
1469 | .get_group_pins = nmk_get_group_pins, | |
1470 | .pin_dbg_show = nmk_pin_dbg_show, | |
1471 | }; | |
1472 | ||
dbfe8ca2 LW |
1473 | static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) |
1474 | { | |
1475 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1476 | ||
1477 | return npct->soc->nfunctions; | |
1478 | } | |
1479 | ||
1480 | static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
1481 | unsigned function) | |
1482 | { | |
1483 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1484 | ||
1485 | return npct->soc->functions[function].name; | |
1486 | } | |
1487 | ||
1488 | static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
1489 | unsigned function, | |
1490 | const char * const **groups, | |
1491 | unsigned * const num_groups) | |
1492 | { | |
1493 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1494 | ||
1495 | *groups = npct->soc->functions[function].groups; | |
1496 | *num_groups = npct->soc->functions[function].ngroups; | |
1497 | ||
1498 | return 0; | |
1499 | } | |
1500 | ||
1501 | static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, | |
1502 | unsigned group) | |
1503 | { | |
1504 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1505 | const struct nmk_pingroup *g; | |
1506 | static unsigned int slpm[NUM_BANKS]; | |
1507 | unsigned long flags; | |
1508 | bool glitch; | |
1509 | int ret = -EINVAL; | |
1510 | int i; | |
1511 | ||
1512 | g = &npct->soc->groups[group]; | |
1513 | ||
1514 | if (g->altsetting < 0) | |
1515 | return -EINVAL; | |
1516 | ||
1517 | dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); | |
1518 | ||
daf73174 LW |
1519 | /* |
1520 | * If we're setting altfunc C by setting both AFSLA and AFSLB to 1, | |
1521 | * we may pass through an undesired state. In this case we take | |
1522 | * some extra care. | |
1523 | * | |
1524 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
1525 | * - Save SLPM registers (since we have a shadow register in the | |
1526 | * nmk_chip we're using that as backup) | |
1527 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
1528 | * - Configure the GPIO registers for the IOs that are being switched | |
1529 | * - Set IOFORCE=1 | |
1530 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
1531 | * - Set IOFORCE=0 | |
1532 | * - Restore SLPM registers | |
1533 | * - Any spurious wake up event during switch sequence to be ignored | |
1534 | * and cleared | |
1535 | * | |
1536 | * We REALLY need to save ALL slpm registers, because the external | |
1537 | * IOFORCE will switch *all* ports to their sleepmode setting to as | |
1538 | * to avoid glitches. (Not just one port!) | |
1539 | */ | |
c22df08c | 1540 | glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); |
dbfe8ca2 LW |
1541 | |
1542 | if (glitch) { | |
1543 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | |
1544 | ||
1545 | /* Initially don't put any pins to sleep when switching */ | |
1546 | memset(slpm, 0xff, sizeof(slpm)); | |
1547 | ||
1548 | /* | |
1549 | * Then mask the pins that need to be sleeping now when we're | |
1550 | * switching to the ALT C function. | |
1551 | */ | |
1552 | for (i = 0; i < g->npins; i++) | |
1553 | slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); | |
1554 | nmk_gpio_glitch_slpm_init(slpm); | |
1555 | } | |
1556 | ||
1557 | for (i = 0; i < g->npins; i++) { | |
1558 | struct pinctrl_gpio_range *range; | |
1559 | struct nmk_gpio_chip *nmk_chip; | |
1560 | struct gpio_chip *chip; | |
1561 | unsigned bit; | |
1562 | ||
1563 | range = nmk_match_gpio_range(pctldev, g->pins[i]); | |
1564 | if (!range) { | |
1565 | dev_err(npct->dev, | |
1566 | "invalid pin offset %d in group %s at index %d\n", | |
1567 | g->pins[i], g->name, i); | |
1568 | goto out_glitch; | |
1569 | } | |
1570 | if (!range->gc) { | |
1571 | dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n", | |
1572 | g->pins[i], g->name, i); | |
1573 | goto out_glitch; | |
1574 | } | |
1575 | chip = range->gc; | |
1576 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
1577 | dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); | |
1578 | ||
1579 | clk_enable(nmk_chip->clk); | |
1580 | bit = g->pins[i] % NMK_GPIO_PER_CHIP; | |
1581 | /* | |
1582 | * If the pin is switching to altfunc, and there was an | |
1583 | * interrupt installed on it which has been lazy disabled, | |
1584 | * actually mask the interrupt to prevent spurious interrupts | |
1585 | * that would occur while the pin is under control of the | |
1586 | * peripheral. Only SKE does this. | |
1587 | */ | |
1588 | nmk_gpio_disable_lazy_irq(nmk_chip, bit); | |
1589 | ||
c22df08c JNG |
1590 | __nmk_gpio_set_mode_safe(nmk_chip, bit, |
1591 | (g->altsetting & NMK_GPIO_ALT_C), glitch); | |
dbfe8ca2 | 1592 | clk_disable(nmk_chip->clk); |
c22df08c JNG |
1593 | |
1594 | /* | |
1595 | * Call PRCM GPIOCR config function in case ALTC | |
1596 | * has been selected: | |
1597 | * - If selection is a ALTCx, some bits in PRCM GPIOCR registers | |
1598 | * must be set. | |
1599 | * - If selection is pure ALTC and previous selection was ALTCx, | |
1600 | * then some bits in PRCM GPIOCR registers must be cleared. | |
1601 | */ | |
1602 | if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C) | |
1603 | nmk_prcm_altcx_set_mode(npct, g->pins[i], | |
1604 | g->altsetting >> NMK_GPIO_ALT_CX_SHIFT); | |
dbfe8ca2 LW |
1605 | } |
1606 | ||
1607 | /* When all pins are successfully reconfigured we get here */ | |
1608 | ret = 0; | |
1609 | ||
1610 | out_glitch: | |
1611 | if (glitch) { | |
1612 | nmk_gpio_glitch_slpm_restore(slpm); | |
1613 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
1614 | } | |
1615 | ||
1616 | return ret; | |
1617 | } | |
1618 | ||
1619 | static void nmk_pmx_disable(struct pinctrl_dev *pctldev, | |
1620 | unsigned function, unsigned group) | |
1621 | { | |
1622 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1623 | const struct nmk_pingroup *g; | |
1624 | ||
1625 | g = &npct->soc->groups[group]; | |
1626 | ||
1627 | if (g->altsetting < 0) | |
1628 | return; | |
1629 | ||
1630 | /* Poke out the mux, set the pin to some default state? */ | |
1631 | dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins); | |
1632 | } | |
1633 | ||
1634 | int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, | |
1635 | struct pinctrl_gpio_range *range, | |
1636 | unsigned offset) | |
1637 | { | |
1638 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1639 | struct nmk_gpio_chip *nmk_chip; | |
1640 | struct gpio_chip *chip; | |
1641 | unsigned bit; | |
1642 | ||
1643 | if (!range) { | |
1644 | dev_err(npct->dev, "invalid range\n"); | |
1645 | return -EINVAL; | |
1646 | } | |
1647 | if (!range->gc) { | |
1648 | dev_err(npct->dev, "missing GPIO chip in range\n"); | |
1649 | return -EINVAL; | |
1650 | } | |
1651 | chip = range->gc; | |
1652 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
1653 | ||
1654 | dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); | |
1655 | ||
1656 | clk_enable(nmk_chip->clk); | |
1657 | bit = offset % NMK_GPIO_PER_CHIP; | |
1658 | /* There is no glitch when converting any pin to GPIO */ | |
1659 | __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); | |
1660 | clk_disable(nmk_chip->clk); | |
1661 | ||
1662 | return 0; | |
1663 | } | |
1664 | ||
1665 | void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, | |
1666 | struct pinctrl_gpio_range *range, | |
1667 | unsigned offset) | |
1668 | { | |
1669 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1670 | ||
1671 | dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); | |
1672 | /* Set the pin to some default state, GPIO is usually default */ | |
1673 | } | |
1674 | ||
1675 | static struct pinmux_ops nmk_pinmux_ops = { | |
1676 | .get_functions_count = nmk_pmx_get_funcs_cnt, | |
1677 | .get_function_name = nmk_pmx_get_func_name, | |
1678 | .get_function_groups = nmk_pmx_get_func_groups, | |
1679 | .enable = nmk_pmx_enable, | |
1680 | .disable = nmk_pmx_disable, | |
1681 | .gpio_request_enable = nmk_gpio_request_enable, | |
1682 | .gpio_disable_free = nmk_gpio_disable_free, | |
1683 | }; | |
1684 | ||
d41af627 LW |
1685 | int nmk_pin_config_get(struct pinctrl_dev *pctldev, |
1686 | unsigned pin, | |
1687 | unsigned long *config) | |
1688 | { | |
1689 | /* Not implemented */ | |
1690 | return -EINVAL; | |
1691 | } | |
1692 | ||
1693 | int nmk_pin_config_set(struct pinctrl_dev *pctldev, | |
1694 | unsigned pin, | |
1695 | unsigned long config) | |
1696 | { | |
1697 | static const char *pullnames[] = { | |
1698 | [NMK_GPIO_PULL_NONE] = "none", | |
1699 | [NMK_GPIO_PULL_UP] = "up", | |
1700 | [NMK_GPIO_PULL_DOWN] = "down", | |
1701 | [3] /* illegal */ = "??" | |
1702 | }; | |
1703 | static const char *slpmnames[] = { | |
1704 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", | |
1705 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
1706 | }; | |
1707 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1708 | struct nmk_gpio_chip *nmk_chip; | |
1709 | struct pinctrl_gpio_range *range; | |
1710 | struct gpio_chip *chip; | |
1711 | unsigned bit; | |
1712 | ||
1713 | /* | |
1714 | * The pin config contains pin number and altfunction fields, here | |
1715 | * we just ignore that part. It's being handled by the framework and | |
1716 | * pinmux callback respectively. | |
1717 | */ | |
1718 | pin_cfg_t cfg = (pin_cfg_t) config; | |
1719 | int pull = PIN_PULL(cfg); | |
1720 | int slpm = PIN_SLPM(cfg); | |
1721 | int output = PIN_DIR(cfg); | |
1722 | int val = PIN_VAL(cfg); | |
1723 | bool lowemi = PIN_LOWEMI(cfg); | |
1724 | bool gpiomode = PIN_GPIOMODE(cfg); | |
1725 | bool sleep = PIN_SLEEPMODE(cfg); | |
1726 | ||
1727 | range = nmk_match_gpio_range(pctldev, pin); | |
1728 | if (!range) { | |
1729 | dev_err(npct->dev, "invalid pin offset %d\n", pin); | |
1730 | return -EINVAL; | |
1731 | } | |
1732 | if (!range->gc) { | |
1733 | dev_err(npct->dev, "GPIO chip missing in range for pin %d\n", | |
1734 | pin); | |
1735 | return -EINVAL; | |
1736 | } | |
1737 | chip = range->gc; | |
1738 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
1739 | ||
1740 | if (sleep) { | |
1741 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
1742 | int slpm_output = PIN_SLPM_DIR(cfg); | |
1743 | int slpm_val = PIN_SLPM_VAL(cfg); | |
1744 | ||
1745 | /* All pins go into GPIO mode at sleep */ | |
1746 | gpiomode = true; | |
1747 | ||
1748 | /* | |
1749 | * The SLPM_* values are normal values + 1 to allow zero to | |
1750 | * mean "same as normal". | |
1751 | */ | |
1752 | if (slpm_pull) | |
1753 | pull = slpm_pull - 1; | |
1754 | if (slpm_output) | |
1755 | output = slpm_output - 1; | |
1756 | if (slpm_val) | |
1757 | val = slpm_val - 1; | |
1758 | ||
1759 | dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", | |
1760 | pin, | |
1761 | slpm_pull ? pullnames[pull] : "same", | |
1762 | slpm_output ? (output ? "output" : "input") : "same", | |
1763 | slpm_val ? (val ? "high" : "low") : "same"); | |
1764 | } | |
1765 | ||
1766 | dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", | |
1767 | pin, cfg, pullnames[pull], slpmnames[slpm], | |
1768 | output ? "output " : "input", | |
1769 | output ? (val ? "high" : "low") : "", | |
1770 | lowemi ? "on" : "off" ); | |
1771 | ||
1772 | clk_enable(nmk_chip->clk); | |
1773 | bit = pin % NMK_GPIO_PER_CHIP; | |
1774 | if (gpiomode) | |
1775 | /* No glitch when going to GPIO mode */ | |
1776 | __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); | |
1777 | if (output) | |
1778 | __nmk_gpio_make_output(nmk_chip, bit, val); | |
1779 | else { | |
1780 | __nmk_gpio_make_input(nmk_chip, bit); | |
1781 | __nmk_gpio_set_pull(nmk_chip, bit, pull); | |
1782 | } | |
1783 | /* TODO: isn't this only applicable on output pins? */ | |
1784 | __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); | |
1785 | ||
1786 | __nmk_gpio_set_slpm(nmk_chip, bit, slpm); | |
1787 | clk_disable(nmk_chip->clk); | |
1788 | return 0; | |
1789 | } | |
1790 | ||
1791 | static struct pinconf_ops nmk_pinconf_ops = { | |
1792 | .pin_config_get = nmk_pin_config_get, | |
1793 | .pin_config_set = nmk_pin_config_set, | |
1794 | }; | |
1795 | ||
e98ea774 LW |
1796 | static struct pinctrl_desc nmk_pinctrl_desc = { |
1797 | .name = "pinctrl-nomadik", | |
1798 | .pctlops = &nmk_pinctrl_ops, | |
dbfe8ca2 | 1799 | .pmxops = &nmk_pinmux_ops, |
d41af627 | 1800 | .confops = &nmk_pinconf_ops, |
e98ea774 LW |
1801 | .owner = THIS_MODULE, |
1802 | }; | |
1803 | ||
855f80cd LJ |
1804 | static const struct of_device_id nmk_pinctrl_match[] = { |
1805 | { | |
1806 | .compatible = "stericsson,nmk_pinctrl", | |
1807 | .data = (void *)PINCTRL_NMK_DB8500, | |
1808 | }, | |
1809 | {}, | |
1810 | }; | |
1811 | ||
e98ea774 LW |
1812 | static int __devinit nmk_pinctrl_probe(struct platform_device *pdev) |
1813 | { | |
1814 | const struct platform_device_id *platid = platform_get_device_id(pdev); | |
855f80cd | 1815 | struct device_node *np = pdev->dev.of_node; |
e98ea774 | 1816 | struct nmk_pinctrl *npct; |
855f80cd | 1817 | unsigned int version = 0; |
e98ea774 LW |
1818 | int i; |
1819 | ||
1820 | npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); | |
1821 | if (!npct) | |
1822 | return -ENOMEM; | |
1823 | ||
855f80cd LJ |
1824 | if (platid) |
1825 | version = platid->driver_data; | |
1826 | else if (np) | |
1827 | version = (unsigned int) | |
1828 | of_match_device(nmk_pinctrl_match, &pdev->dev)->data; | |
1829 | ||
e98ea774 | 1830 | /* Poke in other ASIC variants here */ |
f79c5ed9 LW |
1831 | if (version == PINCTRL_NMK_STN8815) |
1832 | nmk_pinctrl_stn8815_init(&npct->soc); | |
855f80cd | 1833 | if (version == PINCTRL_NMK_DB8500) |
e98ea774 | 1834 | nmk_pinctrl_db8500_init(&npct->soc); |
45a1b531 PC |
1835 | if (version == PINCTRL_NMK_DB8540) |
1836 | nmk_pinctrl_db8540_init(&npct->soc); | |
e98ea774 LW |
1837 | |
1838 | /* | |
1839 | * We need all the GPIO drivers to probe FIRST, or we will not be able | |
1840 | * to obtain references to the struct gpio_chip * for them, and we | |
1841 | * need this to proceed. | |
1842 | */ | |
1843 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) { | |
1d853ca5 | 1844 | if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) { |
e98ea774 | 1845 | dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); |
e98ea774 LW |
1846 | return -EPROBE_DEFER; |
1847 | } | |
1d853ca5 | 1848 | npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip; |
e98ea774 LW |
1849 | } |
1850 | ||
1851 | nmk_pinctrl_desc.pins = npct->soc->pins; | |
1852 | nmk_pinctrl_desc.npins = npct->soc->npins; | |
1853 | npct->dev = &pdev->dev; | |
1854 | npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct); | |
1855 | if (!npct->pctl) { | |
1856 | dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); | |
1857 | return -EINVAL; | |
1858 | } | |
1859 | ||
1860 | /* We will handle a range of GPIO pins */ | |
1861 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) | |
1862 | pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]); | |
1863 | ||
1864 | platform_set_drvdata(pdev, npct); | |
1865 | dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); | |
1866 | ||
1867 | return 0; | |
1868 | } | |
1869 | ||
513c27f8 LJ |
1870 | static const struct of_device_id nmk_gpio_match[] = { |
1871 | { .compatible = "st,nomadik-gpio", }, | |
1872 | {} | |
1873 | }; | |
1874 | ||
3e3c62ca RV |
1875 | static struct platform_driver nmk_gpio_driver = { |
1876 | .driver = { | |
2ec1d359 AR |
1877 | .owner = THIS_MODULE, |
1878 | .name = "gpio", | |
513c27f8 | 1879 | .of_match_table = nmk_gpio_match, |
5317e4d1 | 1880 | }, |
2ec1d359 | 1881 | .probe = nmk_gpio_probe, |
2ec1d359 AR |
1882 | }; |
1883 | ||
e98ea774 LW |
1884 | static const struct platform_device_id nmk_pinctrl_id[] = { |
1885 | { "pinctrl-stn8815", PINCTRL_NMK_STN8815 }, | |
1886 | { "pinctrl-db8500", PINCTRL_NMK_DB8500 }, | |
45a1b531 | 1887 | { "pinctrl-db8540", PINCTRL_NMK_DB8540 }, |
e98ea774 LW |
1888 | }; |
1889 | ||
1890 | static struct platform_driver nmk_pinctrl_driver = { | |
1891 | .driver = { | |
1892 | .owner = THIS_MODULE, | |
1893 | .name = "pinctrl-nomadik", | |
855f80cd | 1894 | .of_match_table = nmk_pinctrl_match, |
e98ea774 LW |
1895 | }, |
1896 | .probe = nmk_pinctrl_probe, | |
1897 | .id_table = nmk_pinctrl_id, | |
1898 | }; | |
1899 | ||
2ec1d359 AR |
1900 | static int __init nmk_gpio_init(void) |
1901 | { | |
e98ea774 LW |
1902 | int ret; |
1903 | ||
1904 | ret = platform_driver_register(&nmk_gpio_driver); | |
1905 | if (ret) | |
1906 | return ret; | |
1907 | return platform_driver_register(&nmk_pinctrl_driver); | |
2ec1d359 AR |
1908 | } |
1909 | ||
33f45ea9 | 1910 | core_initcall(nmk_gpio_init); |
2ec1d359 AR |
1911 | |
1912 | MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); | |
1913 | MODULE_DESCRIPTION("Nomadik GPIO Driver"); | |
1914 | MODULE_LICENSE("GPL"); |