Commit | Line | Data |
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2ec1d359 AR |
1 | /* |
2 | * Generic GPIO driver for logic cells found in the Nomadik SoC | |
3 | * | |
4 | * Copyright (C) 2008,2009 STMicroelectronics | |
5 | * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> | |
6 | * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> | |
33d78647 | 7 | * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org> |
2ec1d359 AR |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/device.h> | |
3e3c62ca | 17 | #include <linux/platform_device.h> |
2ec1d359 | 18 | #include <linux/io.h> |
af7dc228 RV |
19 | #include <linux/clk.h> |
20 | #include <linux/err.h> | |
2ec1d359 AR |
21 | #include <linux/gpio.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/irq.h> | |
a60b57ed | 25 | #include <linux/irqdomain.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
855f80cd | 27 | #include <linux/of_device.h> |
e98ea774 | 28 | #include <linux/pinctrl/pinctrl.h> |
dbfe8ca2 | 29 | #include <linux/pinctrl/pinmux.h> |
d41af627 | 30 | #include <linux/pinctrl/pinconf.h> |
dbfe8ca2 LW |
31 | /* Since we request GPIOs from ourself */ |
32 | #include <linux/pinctrl/consumer.h> | |
bb16bd9b | 33 | #include <linux/platform_data/pinctrl-nomadik.h> |
2ec1d359 | 34 | |
adfed159 WD |
35 | #include <asm/mach/irq.h> |
36 | ||
e98ea774 LW |
37 | #include "pinctrl-nomadik.h" |
38 | ||
2ec1d359 AR |
39 | /* |
40 | * The GPIO module in the Nomadik family of Systems-on-Chip is an | |
41 | * AMBA device, managing 32 pins and alternate functions. The logic block | |
9c66ee6f | 42 | * is currently used in the Nomadik and ux500. |
2ec1d359 AR |
43 | * |
44 | * Symbols in this file are called "nmk_gpio" for "nomadik gpio" | |
45 | */ | |
46 | ||
2ec1d359 AR |
47 | struct nmk_gpio_chip { |
48 | struct gpio_chip chip; | |
a60b57ed | 49 | struct irq_domain *domain; |
2ec1d359 | 50 | void __iomem *addr; |
af7dc228 | 51 | struct clk *clk; |
33b744b3 | 52 | unsigned int bank; |
2ec1d359 | 53 | unsigned int parent_irq; |
2c8bb0eb | 54 | int secondary_parent_irq; |
33b744b3 | 55 | u32 (*get_secondary_status)(unsigned int bank); |
01727e61 | 56 | void (*set_ioforce)(bool enable); |
c0fcb8db | 57 | spinlock_t lock; |
33d78647 | 58 | bool sleepmode; |
2ec1d359 AR |
59 | /* Keep track of configured edges */ |
60 | u32 edge_rising; | |
61 | u32 edge_falling; | |
b9df468d RV |
62 | u32 real_wake; |
63 | u32 rwimsc; | |
64 | u32 fwimsc; | |
6c12fe88 RV |
65 | u32 rimsc; |
66 | u32 fimsc; | |
bc6f5cf6 | 67 | u32 pull_up; |
ebc6178d | 68 | u32 lowemi; |
2ec1d359 AR |
69 | }; |
70 | ||
f1671bf5 JA |
71 | /** |
72 | * struct nmk_pinctrl - state container for the Nomadik pin controller | |
73 | * @dev: containing device pointer | |
74 | * @pctl: corresponding pin controller device | |
75 | * @soc: SoC data for this specific chip | |
76 | * @prcm_base: PRCM register range virtual base | |
77 | */ | |
e98ea774 LW |
78 | struct nmk_pinctrl { |
79 | struct device *dev; | |
80 | struct pinctrl_dev *pctl; | |
81 | const struct nmk_pinctrl_soc_data *soc; | |
f1671bf5 | 82 | void __iomem *prcm_base; |
e98ea774 LW |
83 | }; |
84 | ||
01727e61 RV |
85 | static struct nmk_gpio_chip * |
86 | nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; | |
87 | ||
88 | static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); | |
89 | ||
90 | #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) | |
91 | ||
6f9a974c RV |
92 | static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, |
93 | unsigned offset, int gpio_mode) | |
94 | { | |
95 | u32 bit = 1 << offset; | |
96 | u32 afunc, bfunc; | |
97 | ||
98 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; | |
99 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; | |
100 | if (gpio_mode & NMK_GPIO_ALT_A) | |
101 | afunc |= bit; | |
102 | if (gpio_mode & NMK_GPIO_ALT_B) | |
103 | bfunc |= bit; | |
104 | writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); | |
105 | writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); | |
106 | } | |
107 | ||
81a3c298 RV |
108 | static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, |
109 | unsigned offset, enum nmk_gpio_slpm mode) | |
110 | { | |
111 | u32 bit = 1 << offset; | |
112 | u32 slpm; | |
113 | ||
114 | slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); | |
115 | if (mode == NMK_GPIO_SLPM_NOCHANGE) | |
116 | slpm |= bit; | |
117 | else | |
118 | slpm &= ~bit; | |
119 | writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); | |
120 | } | |
121 | ||
5b327edf RV |
122 | static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, |
123 | unsigned offset, enum nmk_gpio_pull pull) | |
124 | { | |
125 | u32 bit = 1 << offset; | |
126 | u32 pdis; | |
127 | ||
128 | pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); | |
bc6f5cf6 | 129 | if (pull == NMK_GPIO_PULL_NONE) { |
5b327edf | 130 | pdis |= bit; |
bc6f5cf6 RA |
131 | nmk_chip->pull_up &= ~bit; |
132 | } else { | |
5b327edf | 133 | pdis &= ~bit; |
bc6f5cf6 RA |
134 | } |
135 | ||
5b327edf RV |
136 | writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); |
137 | ||
bc6f5cf6 RA |
138 | if (pull == NMK_GPIO_PULL_UP) { |
139 | nmk_chip->pull_up |= bit; | |
5b327edf | 140 | writel(bit, nmk_chip->addr + NMK_GPIO_DATS); |
bc6f5cf6 RA |
141 | } else if (pull == NMK_GPIO_PULL_DOWN) { |
142 | nmk_chip->pull_up &= ~bit; | |
5b327edf | 143 | writel(bit, nmk_chip->addr + NMK_GPIO_DATC); |
bc6f5cf6 | 144 | } |
5b327edf RV |
145 | } |
146 | ||
ebc6178d RV |
147 | static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, |
148 | unsigned offset, bool lowemi) | |
149 | { | |
150 | u32 bit = BIT(offset); | |
151 | bool enabled = nmk_chip->lowemi & bit; | |
152 | ||
153 | if (lowemi == enabled) | |
154 | return; | |
155 | ||
156 | if (lowemi) | |
157 | nmk_chip->lowemi |= bit; | |
158 | else | |
159 | nmk_chip->lowemi &= ~bit; | |
160 | ||
161 | writel_relaxed(nmk_chip->lowemi, | |
162 | nmk_chip->addr + NMK_GPIO_LOWEMI); | |
163 | } | |
164 | ||
378be066 RV |
165 | static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, |
166 | unsigned offset) | |
167 | { | |
168 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); | |
169 | } | |
170 | ||
6720db7c RV |
171 | static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, |
172 | unsigned offset, int val) | |
173 | { | |
174 | if (val) | |
175 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); | |
176 | else | |
177 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); | |
178 | } | |
179 | ||
180 | static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, | |
181 | unsigned offset, int val) | |
182 | { | |
183 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); | |
184 | __nmk_gpio_set_output(nmk_chip, offset, val); | |
185 | } | |
186 | ||
01727e61 RV |
187 | static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, |
188 | unsigned offset, int gpio_mode, | |
189 | bool glitch) | |
190 | { | |
6c12fe88 RV |
191 | u32 rwimsc = nmk_chip->rwimsc; |
192 | u32 fwimsc = nmk_chip->fwimsc; | |
01727e61 RV |
193 | |
194 | if (glitch && nmk_chip->set_ioforce) { | |
195 | u32 bit = BIT(offset); | |
196 | ||
01727e61 RV |
197 | /* Prevent spurious wakeups */ |
198 | writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
199 | writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
200 | ||
201 | nmk_chip->set_ioforce(true); | |
202 | } | |
203 | ||
204 | __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); | |
205 | ||
206 | if (glitch && nmk_chip->set_ioforce) { | |
207 | nmk_chip->set_ioforce(false); | |
208 | ||
209 | writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
210 | writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
211 | } | |
212 | } | |
213 | ||
6c42ad1c RV |
214 | static void |
215 | nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) | |
216 | { | |
217 | u32 falling = nmk_chip->fimsc & BIT(offset); | |
218 | u32 rising = nmk_chip->rimsc & BIT(offset); | |
219 | int gpio = nmk_chip->chip.base + offset; | |
220 | int irq = NOMADIK_GPIO_TO_IRQ(gpio); | |
221 | struct irq_data *d = irq_get_irq_data(irq); | |
222 | ||
223 | if (!rising && !falling) | |
224 | return; | |
225 | ||
226 | if (!d || !irqd_irq_disabled(d)) | |
227 | return; | |
228 | ||
229 | if (rising) { | |
230 | nmk_chip->rimsc &= ~BIT(offset); | |
231 | writel_relaxed(nmk_chip->rimsc, | |
232 | nmk_chip->addr + NMK_GPIO_RIMSC); | |
233 | } | |
234 | ||
235 | if (falling) { | |
236 | nmk_chip->fimsc &= ~BIT(offset); | |
237 | writel_relaxed(nmk_chip->fimsc, | |
238 | nmk_chip->addr + NMK_GPIO_FIMSC); | |
239 | } | |
240 | ||
241 | dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); | |
242 | } | |
243 | ||
f1671bf5 JA |
244 | static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value) |
245 | { | |
246 | u32 val; | |
247 | ||
248 | val = readl(reg); | |
249 | val = ((val & ~mask) | (value & mask)); | |
250 | writel(val, reg); | |
251 | } | |
252 | ||
c22df08c JNG |
253 | static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct, |
254 | unsigned offset, unsigned alt_num) | |
255 | { | |
256 | int i; | |
257 | u16 reg; | |
258 | u8 bit; | |
259 | u8 alt_index; | |
260 | const struct prcm_gpiocr_altcx_pin_desc *pin_desc; | |
261 | const u16 *gpiocr_regs; | |
262 | ||
263 | if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) { | |
264 | dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n", | |
265 | alt_num); | |
266 | return; | |
267 | } | |
268 | ||
269 | for (i = 0 ; i < npct->soc->npins_altcx ; i++) { | |
270 | if (npct->soc->altcx_pins[i].pin == offset) | |
271 | break; | |
272 | } | |
273 | if (i == npct->soc->npins_altcx) { | |
274 | dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n", | |
275 | offset); | |
276 | return; | |
277 | } | |
278 | ||
279 | pin_desc = npct->soc->altcx_pins + i; | |
280 | gpiocr_regs = npct->soc->prcm_gpiocr_registers; | |
281 | ||
282 | /* | |
283 | * If alt_num is NULL, just clear current ALTCx selection | |
284 | * to make sure we come back to a pure ALTC selection | |
285 | */ | |
286 | if (!alt_num) { | |
287 | for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { | |
288 | if (pin_desc->altcx[i].used == true) { | |
289 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
290 | bit = pin_desc->altcx[i].control_bit; | |
f1671bf5 JA |
291 | if (readl(npct->prcm_base + reg) & BIT(bit)) { |
292 | nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); | |
c22df08c JNG |
293 | dev_dbg(npct->dev, |
294 | "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", | |
295 | offset, i+1); | |
296 | } | |
297 | } | |
298 | } | |
299 | return; | |
300 | } | |
301 | ||
302 | alt_index = alt_num - 1; | |
303 | if (pin_desc->altcx[alt_index].used == false) { | |
304 | dev_warn(npct->dev, | |
305 | "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n", | |
306 | offset, alt_num); | |
307 | return; | |
308 | } | |
309 | ||
310 | /* | |
311 | * Check if any other ALTCx functions are activated on this pin | |
312 | * and disable it first. | |
313 | */ | |
314 | for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { | |
315 | if (i == alt_index) | |
316 | continue; | |
317 | if (pin_desc->altcx[i].used == true) { | |
318 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
319 | bit = pin_desc->altcx[i].control_bit; | |
f1671bf5 JA |
320 | if (readl(npct->prcm_base + reg) & BIT(bit)) { |
321 | nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); | |
c22df08c JNG |
322 | dev_dbg(npct->dev, |
323 | "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", | |
324 | offset, i+1); | |
325 | } | |
326 | } | |
327 | } | |
328 | ||
329 | reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; | |
330 | bit = pin_desc->altcx[alt_index].control_bit; | |
331 | dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n", | |
332 | offset, alt_index+1); | |
f1671bf5 | 333 | nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); |
c22df08c JNG |
334 | } |
335 | ||
378be066 | 336 | static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, |
01727e61 | 337 | pin_cfg_t cfg, bool sleep, unsigned int *slpmregs) |
378be066 RV |
338 | { |
339 | static const char *afnames[] = { | |
340 | [NMK_GPIO_ALT_GPIO] = "GPIO", | |
341 | [NMK_GPIO_ALT_A] = "A", | |
342 | [NMK_GPIO_ALT_B] = "B", | |
343 | [NMK_GPIO_ALT_C] = "C" | |
344 | }; | |
345 | static const char *pullnames[] = { | |
346 | [NMK_GPIO_PULL_NONE] = "none", | |
347 | [NMK_GPIO_PULL_UP] = "up", | |
348 | [NMK_GPIO_PULL_DOWN] = "down", | |
349 | [3] /* illegal */ = "??" | |
350 | }; | |
351 | static const char *slpmnames[] = { | |
7e3f7e59 RV |
352 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", |
353 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
378be066 RV |
354 | }; |
355 | ||
356 | int pin = PIN_NUM(cfg); | |
357 | int pull = PIN_PULL(cfg); | |
358 | int af = PIN_ALT(cfg); | |
359 | int slpm = PIN_SLPM(cfg); | |
6720db7c RV |
360 | int output = PIN_DIR(cfg); |
361 | int val = PIN_VAL(cfg); | |
01727e61 | 362 | bool glitch = af == NMK_GPIO_ALT_C; |
378be066 | 363 | |
dacdc96c RV |
364 | dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n", |
365 | pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm], | |
6720db7c RV |
366 | output ? "output " : "input", |
367 | output ? (val ? "high" : "low") : ""); | |
368 | ||
dacdc96c RV |
369 | if (sleep) { |
370 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
371 | int slpm_output = PIN_SLPM_DIR(cfg); | |
372 | int slpm_val = PIN_SLPM_VAL(cfg); | |
373 | ||
3546d15c RV |
374 | af = NMK_GPIO_ALT_GPIO; |
375 | ||
dacdc96c RV |
376 | /* |
377 | * The SLPM_* values are normal values + 1 to allow zero to | |
378 | * mean "same as normal". | |
379 | */ | |
380 | if (slpm_pull) | |
381 | pull = slpm_pull - 1; | |
382 | if (slpm_output) | |
383 | output = slpm_output - 1; | |
384 | if (slpm_val) | |
385 | val = slpm_val - 1; | |
386 | ||
387 | dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", | |
388 | pin, | |
389 | slpm_pull ? pullnames[pull] : "same", | |
390 | slpm_output ? (output ? "output" : "input") : "same", | |
391 | slpm_val ? (val ? "high" : "low") : "same"); | |
392 | } | |
393 | ||
6720db7c RV |
394 | if (output) |
395 | __nmk_gpio_make_output(nmk_chip, offset, val); | |
396 | else { | |
397 | __nmk_gpio_make_input(nmk_chip, offset); | |
398 | __nmk_gpio_set_pull(nmk_chip, offset, pull); | |
399 | } | |
378be066 | 400 | |
ebc6178d RV |
401 | __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg)); |
402 | ||
6c42ad1c RV |
403 | /* |
404 | * If the pin is switching to altfunc, and there was an interrupt | |
405 | * installed on it which has been lazy disabled, actually mask the | |
406 | * interrupt to prevent spurious interrupts that would occur while the | |
407 | * pin is under control of the peripheral. Only SKE does this. | |
408 | */ | |
409 | if (af != NMK_GPIO_ALT_GPIO) | |
410 | nmk_gpio_disable_lazy_irq(nmk_chip, offset); | |
411 | ||
01727e61 RV |
412 | /* |
413 | * If we've backed up the SLPM registers (glitch workaround), modify | |
414 | * the backups since they will be restored. | |
415 | */ | |
416 | if (slpmregs) { | |
417 | if (slpm == NMK_GPIO_SLPM_NOCHANGE) | |
418 | slpmregs[nmk_chip->bank] |= BIT(offset); | |
419 | else | |
420 | slpmregs[nmk_chip->bank] &= ~BIT(offset); | |
421 | } else | |
422 | __nmk_gpio_set_slpm(nmk_chip, offset, slpm); | |
423 | ||
424 | __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch); | |
425 | } | |
426 | ||
427 | /* | |
428 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
429 | * - Save SLPM registers | |
430 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
431 | * - Configure the GPIO registers for the IOs that are being switched | |
432 | * - Set IOFORCE=1 | |
433 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
434 | * - Set IOFORCE=0 | |
435 | * - Restore SLPM registers | |
436 | * - Any spurious wake up event during switch sequence to be ignored and | |
437 | * cleared | |
438 | */ | |
439 | static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) | |
440 | { | |
441 | int i; | |
442 | ||
443 | for (i = 0; i < NUM_BANKS; i++) { | |
444 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
445 | unsigned int temp = slpm[i]; | |
446 | ||
447 | if (!chip) | |
448 | break; | |
449 | ||
3c0227d2 RV |
450 | clk_enable(chip->clk); |
451 | ||
01727e61 RV |
452 | slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); |
453 | writel(temp, chip->addr + NMK_GPIO_SLPC); | |
454 | } | |
455 | } | |
456 | ||
457 | static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) | |
458 | { | |
459 | int i; | |
460 | ||
461 | for (i = 0; i < NUM_BANKS; i++) { | |
462 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
463 | ||
464 | if (!chip) | |
465 | break; | |
466 | ||
467 | writel(slpm[i], chip->addr + NMK_GPIO_SLPC); | |
3c0227d2 RV |
468 | |
469 | clk_disable(chip->clk); | |
01727e61 RV |
470 | } |
471 | } | |
472 | ||
473 | static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) | |
474 | { | |
475 | static unsigned int slpm[NUM_BANKS]; | |
476 | unsigned long flags; | |
477 | bool glitch = false; | |
478 | int ret = 0; | |
479 | int i; | |
480 | ||
481 | for (i = 0; i < num; i++) { | |
482 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) { | |
483 | glitch = true; | |
484 | break; | |
485 | } | |
486 | } | |
487 | ||
488 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | |
489 | ||
490 | if (glitch) { | |
491 | memset(slpm, 0xff, sizeof(slpm)); | |
492 | ||
493 | for (i = 0; i < num; i++) { | |
494 | int pin = PIN_NUM(cfgs[i]); | |
495 | int offset = pin % NMK_GPIO_PER_CHIP; | |
496 | ||
497 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) | |
498 | slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset); | |
499 | } | |
500 | ||
501 | nmk_gpio_glitch_slpm_init(slpm); | |
502 | } | |
503 | ||
504 | for (i = 0; i < num; i++) { | |
505 | struct nmk_gpio_chip *nmk_chip; | |
506 | int pin = PIN_NUM(cfgs[i]); | |
507 | ||
a60b57ed | 508 | nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP]; |
01727e61 RV |
509 | if (!nmk_chip) { |
510 | ret = -EINVAL; | |
511 | break; | |
512 | } | |
513 | ||
3c0227d2 | 514 | clk_enable(nmk_chip->clk); |
01727e61 | 515 | spin_lock(&nmk_chip->lock); |
a60b57ed | 516 | __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP, |
01727e61 RV |
517 | cfgs[i], sleep, glitch ? slpm : NULL); |
518 | spin_unlock(&nmk_chip->lock); | |
3c0227d2 | 519 | clk_disable(nmk_chip->clk); |
01727e61 RV |
520 | } |
521 | ||
522 | if (glitch) | |
523 | nmk_gpio_glitch_slpm_restore(slpm); | |
524 | ||
525 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
526 | ||
527 | return ret; | |
378be066 RV |
528 | } |
529 | ||
530 | /** | |
531 | * nmk_config_pin - configure a pin's mux attributes | |
532 | * @cfg: pin confguration | |
50bcd47c | 533 | * @sleep: Non-zero to apply the sleep mode configuration |
378be066 RV |
534 | * Configures a pin's mode (alternate function or GPIO), its pull up status, |
535 | * and its sleep mode based on the specified configuration. The @cfg is | |
536 | * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These | |
537 | * are constructed using, and can be further enhanced with, the macros in | |
287f121c | 538 | * <linux/platform_data/pinctrl-nomadik.h> |
378be066 RV |
539 | * |
540 | * If a pin's mode is set to GPIO, it is configured as an input to avoid | |
541 | * side-effects. The gpio can be manipulated later using standard GPIO API | |
542 | * calls. | |
543 | */ | |
dacdc96c | 544 | int nmk_config_pin(pin_cfg_t cfg, bool sleep) |
378be066 | 545 | { |
01727e61 | 546 | return __nmk_config_pins(&cfg, 1, sleep); |
378be066 RV |
547 | } |
548 | EXPORT_SYMBOL(nmk_config_pin); | |
549 | ||
550 | /** | |
551 | * nmk_config_pins - configure several pins at once | |
552 | * @cfgs: array of pin configurations | |
553 | * @num: number of elments in the array | |
554 | * | |
555 | * Configures several pins using nmk_config_pin(). Refer to that function for | |
556 | * further information. | |
557 | */ | |
558 | int nmk_config_pins(pin_cfg_t *cfgs, int num) | |
559 | { | |
01727e61 | 560 | return __nmk_config_pins(cfgs, num, false); |
378be066 RV |
561 | } |
562 | EXPORT_SYMBOL(nmk_config_pins); | |
563 | ||
dacdc96c RV |
564 | int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num) |
565 | { | |
01727e61 | 566 | return __nmk_config_pins(cfgs, num, true); |
dacdc96c RV |
567 | } |
568 | EXPORT_SYMBOL(nmk_config_pins_sleep); | |
569 | ||
81a3c298 RV |
570 | /** |
571 | * nmk_gpio_set_slpm() - configure the sleep mode of a pin | |
572 | * @gpio: pin number | |
573 | * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE, | |
574 | * | |
33d78647 LW |
575 | * This register is actually in the pinmux layer, not the GPIO block itself. |
576 | * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP | |
577 | * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code). | |
578 | * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is | |
579 | * HIGH, overriding the normal setting defined by GPIO_AFSELx registers. | |
580 | * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit), | |
581 | * the GPIOs return to the normal setting defined by GPIO_AFSELx registers. | |
7e3f7e59 | 582 | * |
33d78647 LW |
583 | * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO |
584 | * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is | |
585 | * entered) regardless of the altfunction selected. Also wake-up detection is | |
586 | * ENABLED. | |
587 | * | |
588 | * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains | |
589 | * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS | |
590 | * (for altfunction GPIO) or respective on-chip peripherals (for other | |
591 | * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED. | |
592 | * | |
593 | * Note that enable_irq_wake() will automatically enable wakeup detection. | |
81a3c298 RV |
594 | */ |
595 | int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) | |
596 | { | |
597 | struct nmk_gpio_chip *nmk_chip; | |
598 | unsigned long flags; | |
599 | ||
a60b57ed | 600 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
81a3c298 RV |
601 | if (!nmk_chip) |
602 | return -EINVAL; | |
603 | ||
3c0227d2 | 604 | clk_enable(nmk_chip->clk); |
01727e61 RV |
605 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
606 | spin_lock(&nmk_chip->lock); | |
607 | ||
a60b57ed | 608 | __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode); |
01727e61 RV |
609 | |
610 | spin_unlock(&nmk_chip->lock); | |
611 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 612 | clk_disable(nmk_chip->clk); |
81a3c298 RV |
613 | |
614 | return 0; | |
615 | } | |
616 | ||
5b327edf RV |
617 | /** |
618 | * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio | |
619 | * @gpio: pin number | |
620 | * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE | |
621 | * | |
622 | * Enables/disables pull up/down on a specified pin. This only takes effect if | |
623 | * the pin is configured as an input (either explicitly or by the alternate | |
624 | * function). | |
625 | * | |
626 | * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is | |
627 | * configured as an input. Otherwise, due to the way the controller registers | |
628 | * work, this function will change the value output on the pin. | |
629 | */ | |
630 | int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) | |
631 | { | |
632 | struct nmk_gpio_chip *nmk_chip; | |
633 | unsigned long flags; | |
634 | ||
a60b57ed | 635 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
5b327edf RV |
636 | if (!nmk_chip) |
637 | return -EINVAL; | |
638 | ||
3c0227d2 | 639 | clk_enable(nmk_chip->clk); |
5b327edf | 640 | spin_lock_irqsave(&nmk_chip->lock, flags); |
a60b57ed | 641 | __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull); |
5b327edf | 642 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 643 | clk_disable(nmk_chip->clk); |
5b327edf RV |
644 | |
645 | return 0; | |
646 | } | |
647 | ||
2ec1d359 | 648 | /* Mode functions */ |
9c66ee6f JA |
649 | /** |
650 | * nmk_gpio_set_mode() - set the mux mode of a gpio pin | |
651 | * @gpio: pin number | |
652 | * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A, | |
653 | * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C | |
654 | * | |
655 | * Sets the mode of the specified pin to one of the alternate functions or | |
656 | * plain GPIO. | |
657 | */ | |
2ec1d359 AR |
658 | int nmk_gpio_set_mode(int gpio, int gpio_mode) |
659 | { | |
660 | struct nmk_gpio_chip *nmk_chip; | |
661 | unsigned long flags; | |
2ec1d359 | 662 | |
a60b57ed | 663 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
2ec1d359 AR |
664 | if (!nmk_chip) |
665 | return -EINVAL; | |
666 | ||
3c0227d2 | 667 | clk_enable(nmk_chip->clk); |
2ec1d359 | 668 | spin_lock_irqsave(&nmk_chip->lock, flags); |
a60b57ed | 669 | __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode); |
2ec1d359 | 670 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 671 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
672 | |
673 | return 0; | |
674 | } | |
675 | EXPORT_SYMBOL(nmk_gpio_set_mode); | |
676 | ||
2249b19f JNG |
677 | static int nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio) |
678 | { | |
679 | int i; | |
680 | u16 reg; | |
681 | u8 bit; | |
682 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
683 | const struct prcm_gpiocr_altcx_pin_desc *pin_desc; | |
684 | const u16 *gpiocr_regs; | |
685 | ||
686 | for (i = 0; i < npct->soc->npins_altcx; i++) { | |
687 | if (npct->soc->altcx_pins[i].pin == gpio) | |
688 | break; | |
689 | } | |
690 | if (i == npct->soc->npins_altcx) | |
691 | return NMK_GPIO_ALT_C; | |
692 | ||
693 | pin_desc = npct->soc->altcx_pins + i; | |
694 | gpiocr_regs = npct->soc->prcm_gpiocr_registers; | |
695 | for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) { | |
696 | if (pin_desc->altcx[i].used == true) { | |
697 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
698 | bit = pin_desc->altcx[i].control_bit; | |
f1671bf5 | 699 | if (readl(npct->prcm_base + reg) & BIT(bit)) |
2249b19f JNG |
700 | return NMK_GPIO_ALT_C+i+1; |
701 | } | |
702 | } | |
703 | return NMK_GPIO_ALT_C; | |
704 | } | |
705 | ||
2ec1d359 AR |
706 | int nmk_gpio_get_mode(int gpio) |
707 | { | |
708 | struct nmk_gpio_chip *nmk_chip; | |
709 | u32 afunc, bfunc, bit; | |
710 | ||
a60b57ed | 711 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
2ec1d359 AR |
712 | if (!nmk_chip) |
713 | return -EINVAL; | |
714 | ||
a60b57ed | 715 | bit = 1 << (gpio % NMK_GPIO_PER_CHIP); |
2ec1d359 | 716 | |
3c0227d2 RV |
717 | clk_enable(nmk_chip->clk); |
718 | ||
2ec1d359 AR |
719 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; |
720 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; | |
721 | ||
3c0227d2 RV |
722 | clk_disable(nmk_chip->clk); |
723 | ||
2ec1d359 AR |
724 | return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); |
725 | } | |
726 | EXPORT_SYMBOL(nmk_gpio_get_mode); | |
727 | ||
728 | ||
729 | /* IRQ functions */ | |
730 | static inline int nmk_gpio_get_bitmask(int gpio) | |
731 | { | |
a60b57ed | 732 | return 1 << (gpio % NMK_GPIO_PER_CHIP); |
2ec1d359 AR |
733 | } |
734 | ||
f272c00e | 735 | static void nmk_gpio_irq_ack(struct irq_data *d) |
2ec1d359 | 736 | { |
2ec1d359 AR |
737 | struct nmk_gpio_chip *nmk_chip; |
738 | ||
f272c00e | 739 | nmk_chip = irq_data_get_irq_chip_data(d); |
2ec1d359 AR |
740 | if (!nmk_chip) |
741 | return; | |
3c0227d2 RV |
742 | |
743 | clk_enable(nmk_chip->clk); | |
a60b57ed | 744 | writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); |
3c0227d2 | 745 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
746 | } |
747 | ||
4d4e20f7 RV |
748 | enum nmk_gpio_irq_type { |
749 | NORMAL, | |
750 | WAKE, | |
751 | }; | |
752 | ||
040e5ecd | 753 | static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, |
4d4e20f7 RV |
754 | int gpio, enum nmk_gpio_irq_type which, |
755 | bool enable) | |
2ec1d359 | 756 | { |
040e5ecd | 757 | u32 bitmask = nmk_gpio_get_bitmask(gpio); |
6c12fe88 RV |
758 | u32 *rimscval; |
759 | u32 *fimscval; | |
760 | u32 rimscreg; | |
761 | u32 fimscreg; | |
762 | ||
763 | if (which == NORMAL) { | |
764 | rimscreg = NMK_GPIO_RIMSC; | |
765 | fimscreg = NMK_GPIO_FIMSC; | |
766 | rimscval = &nmk_chip->rimsc; | |
767 | fimscval = &nmk_chip->fimsc; | |
768 | } else { | |
769 | rimscreg = NMK_GPIO_RWIMSC; | |
770 | fimscreg = NMK_GPIO_FWIMSC; | |
771 | rimscval = &nmk_chip->rwimsc; | |
772 | fimscval = &nmk_chip->fwimsc; | |
773 | } | |
2ec1d359 | 774 | |
040e5ecd | 775 | /* we must individually set/clear the two edges */ |
2ec1d359 | 776 | if (nmk_chip->edge_rising & bitmask) { |
040e5ecd | 777 | if (enable) |
6c12fe88 | 778 | *rimscval |= bitmask; |
040e5ecd | 779 | else |
6c12fe88 RV |
780 | *rimscval &= ~bitmask; |
781 | writel(*rimscval, nmk_chip->addr + rimscreg); | |
2ec1d359 AR |
782 | } |
783 | if (nmk_chip->edge_falling & bitmask) { | |
040e5ecd | 784 | if (enable) |
6c12fe88 | 785 | *fimscval |= bitmask; |
040e5ecd | 786 | else |
6c12fe88 RV |
787 | *fimscval &= ~bitmask; |
788 | writel(*fimscval, nmk_chip->addr + fimscreg); | |
2ec1d359 | 789 | } |
040e5ecd | 790 | } |
2ec1d359 | 791 | |
b9df468d RV |
792 | static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, |
793 | int gpio, bool on) | |
794 | { | |
b982ff0e RV |
795 | /* |
796 | * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is | |
797 | * disabled, since setting SLPM to 1 increases power consumption, and | |
798 | * wakeup is anyhow controlled by the RIMSC and FIMSC registers. | |
799 | */ | |
800 | if (nmk_chip->sleepmode && on) { | |
e85bbc19 | 801 | __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, |
b982ff0e | 802 | NMK_GPIO_SLPM_WAKEUP_ENABLE); |
33d78647 LW |
803 | } |
804 | ||
b9df468d RV |
805 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); |
806 | } | |
807 | ||
808 | static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) | |
2ec1d359 | 809 | { |
2ec1d359 AR |
810 | struct nmk_gpio_chip *nmk_chip; |
811 | unsigned long flags; | |
040e5ecd | 812 | u32 bitmask; |
2ec1d359 | 813 | |
f272c00e | 814 | nmk_chip = irq_data_get_irq_chip_data(d); |
a60b57ed | 815 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
2ec1d359 | 816 | if (!nmk_chip) |
4d4e20f7 | 817 | return -EINVAL; |
2ec1d359 | 818 | |
3c0227d2 | 819 | clk_enable(nmk_chip->clk); |
b9df468d RV |
820 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
821 | spin_lock(&nmk_chip->lock); | |
822 | ||
a60b57ed | 823 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); |
b9df468d RV |
824 | |
825 | if (!(nmk_chip->real_wake & bitmask)) | |
a60b57ed | 826 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); |
b9df468d RV |
827 | |
828 | spin_unlock(&nmk_chip->lock); | |
829 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 830 | clk_disable(nmk_chip->clk); |
4d4e20f7 RV |
831 | |
832 | return 0; | |
2ec1d359 AR |
833 | } |
834 | ||
f272c00e | 835 | static void nmk_gpio_irq_mask(struct irq_data *d) |
040e5ecd | 836 | { |
b9df468d | 837 | nmk_gpio_irq_maskunmask(d, false); |
4d4e20f7 | 838 | } |
040e5ecd | 839 | |
f272c00e | 840 | static void nmk_gpio_irq_unmask(struct irq_data *d) |
040e5ecd | 841 | { |
b9df468d | 842 | nmk_gpio_irq_maskunmask(d, true); |
4d4e20f7 RV |
843 | } |
844 | ||
f272c00e | 845 | static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
4d4e20f7 | 846 | { |
7e3f7e59 RV |
847 | struct nmk_gpio_chip *nmk_chip; |
848 | unsigned long flags; | |
b9df468d | 849 | u32 bitmask; |
7e3f7e59 | 850 | |
f272c00e | 851 | nmk_chip = irq_data_get_irq_chip_data(d); |
7e3f7e59 RV |
852 | if (!nmk_chip) |
853 | return -EINVAL; | |
a60b57ed | 854 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
7e3f7e59 | 855 | |
3c0227d2 | 856 | clk_enable(nmk_chip->clk); |
01727e61 RV |
857 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
858 | spin_lock(&nmk_chip->lock); | |
859 | ||
479a0c7e | 860 | if (irqd_irq_disabled(d)) |
a60b57ed | 861 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); |
b9df468d RV |
862 | |
863 | if (on) | |
864 | nmk_chip->real_wake |= bitmask; | |
865 | else | |
866 | nmk_chip->real_wake &= ~bitmask; | |
01727e61 RV |
867 | |
868 | spin_unlock(&nmk_chip->lock); | |
869 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 870 | clk_disable(nmk_chip->clk); |
7e3f7e59 RV |
871 | |
872 | return 0; | |
040e5ecd RV |
873 | } |
874 | ||
f272c00e | 875 | static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
2ec1d359 | 876 | { |
479a0c7e | 877 | bool enabled = !irqd_irq_disabled(d); |
3c0227d2 | 878 | bool wake = irqd_is_wakeup_set(d); |
2ec1d359 AR |
879 | struct nmk_gpio_chip *nmk_chip; |
880 | unsigned long flags; | |
881 | u32 bitmask; | |
882 | ||
f272c00e | 883 | nmk_chip = irq_data_get_irq_chip_data(d); |
a60b57ed | 884 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
2ec1d359 AR |
885 | if (!nmk_chip) |
886 | return -EINVAL; | |
2ec1d359 AR |
887 | if (type & IRQ_TYPE_LEVEL_HIGH) |
888 | return -EINVAL; | |
889 | if (type & IRQ_TYPE_LEVEL_LOW) | |
890 | return -EINVAL; | |
891 | ||
3c0227d2 | 892 | clk_enable(nmk_chip->clk); |
2ec1d359 AR |
893 | spin_lock_irqsave(&nmk_chip->lock, flags); |
894 | ||
7a852d80 | 895 | if (enabled) |
a60b57ed | 896 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); |
4d4e20f7 | 897 | |
b9df468d | 898 | if (enabled || wake) |
a60b57ed | 899 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); |
7a852d80 | 900 | |
2ec1d359 AR |
901 | nmk_chip->edge_rising &= ~bitmask; |
902 | if (type & IRQ_TYPE_EDGE_RISING) | |
903 | nmk_chip->edge_rising |= bitmask; | |
2ec1d359 AR |
904 | |
905 | nmk_chip->edge_falling &= ~bitmask; | |
906 | if (type & IRQ_TYPE_EDGE_FALLING) | |
907 | nmk_chip->edge_falling |= bitmask; | |
2ec1d359 | 908 | |
7a852d80 | 909 | if (enabled) |
a60b57ed | 910 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); |
4d4e20f7 | 911 | |
b9df468d | 912 | if (enabled || wake) |
a60b57ed | 913 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); |
2ec1d359 | 914 | |
7a852d80 | 915 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 916 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
917 | |
918 | return 0; | |
919 | } | |
920 | ||
3c0227d2 RV |
921 | static unsigned int nmk_gpio_irq_startup(struct irq_data *d) |
922 | { | |
923 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 | 924 | |
3c0227d2 RV |
925 | clk_enable(nmk_chip->clk); |
926 | nmk_gpio_irq_unmask(d); | |
2ec1d359 AR |
927 | return 0; |
928 | } | |
929 | ||
3c0227d2 RV |
930 | static void nmk_gpio_irq_shutdown(struct irq_data *d) |
931 | { | |
932 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
933 | ||
934 | nmk_gpio_irq_mask(d); | |
935 | clk_disable(nmk_chip->clk); | |
936 | } | |
937 | ||
2ec1d359 AR |
938 | static struct irq_chip nmk_gpio_irq_chip = { |
939 | .name = "Nomadik-GPIO", | |
f272c00e LB |
940 | .irq_ack = nmk_gpio_irq_ack, |
941 | .irq_mask = nmk_gpio_irq_mask, | |
942 | .irq_unmask = nmk_gpio_irq_unmask, | |
943 | .irq_set_type = nmk_gpio_irq_set_type, | |
944 | .irq_set_wake = nmk_gpio_irq_set_wake, | |
3c0227d2 RV |
945 | .irq_startup = nmk_gpio_irq_startup, |
946 | .irq_shutdown = nmk_gpio_irq_shutdown, | |
4921e745 | 947 | .flags = IRQCHIP_MASK_ON_SUSPEND, |
2ec1d359 AR |
948 | }; |
949 | ||
33b744b3 RV |
950 | static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, |
951 | u32 status) | |
2ec1d359 AR |
952 | { |
953 | struct nmk_gpio_chip *nmk_chip; | |
6845664a | 954 | struct irq_chip *host_chip = irq_get_chip(irq); |
2ec1d359 | 955 | |
adfed159 | 956 | chained_irq_enter(host_chip, desc); |
aaedaa2b | 957 | |
6845664a | 958 | nmk_chip = irq_get_handler_data(irq); |
33b744b3 RV |
959 | while (status) { |
960 | int bit = __ffs(status); | |
961 | ||
95f0bc9b | 962 | generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit)); |
33b744b3 | 963 | status &= ~BIT(bit); |
2ec1d359 | 964 | } |
aaedaa2b | 965 | |
adfed159 | 966 | chained_irq_exit(host_chip, desc); |
2ec1d359 AR |
967 | } |
968 | ||
33b744b3 RV |
969 | static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
970 | { | |
6845664a | 971 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
3c0227d2 RV |
972 | u32 status; |
973 | ||
974 | clk_enable(nmk_chip->clk); | |
975 | status = readl(nmk_chip->addr + NMK_GPIO_IS); | |
976 | clk_disable(nmk_chip->clk); | |
33b744b3 RV |
977 | |
978 | __nmk_gpio_irq_handler(irq, desc, status); | |
979 | } | |
980 | ||
981 | static void nmk_gpio_secondary_irq_handler(unsigned int irq, | |
982 | struct irq_desc *desc) | |
983 | { | |
6845664a | 984 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
33b744b3 RV |
985 | u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); |
986 | ||
987 | __nmk_gpio_irq_handler(irq, desc, status); | |
988 | } | |
989 | ||
2ec1d359 AR |
990 | static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) |
991 | { | |
6845664a TG |
992 | irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); |
993 | irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); | |
33b744b3 RV |
994 | |
995 | if (nmk_chip->secondary_parent_irq >= 0) { | |
6845664a | 996 | irq_set_chained_handler(nmk_chip->secondary_parent_irq, |
33b744b3 | 997 | nmk_gpio_secondary_irq_handler); |
6845664a | 998 | irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); |
33b744b3 RV |
999 | } |
1000 | ||
2ec1d359 AR |
1001 | return 0; |
1002 | } | |
1003 | ||
1004 | /* I/O Functions */ | |
dbfe8ca2 LW |
1005 | |
1006 | static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset) | |
1007 | { | |
1008 | /* | |
1009 | * Map back to global GPIO space and request muxing, the direction | |
1010 | * parameter does not matter for this controller. | |
1011 | */ | |
1012 | int gpio = chip->base + offset; | |
1013 | ||
1014 | return pinctrl_request_gpio(gpio); | |
1015 | } | |
1016 | ||
1017 | static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset) | |
1018 | { | |
1019 | int gpio = chip->base + offset; | |
1020 | ||
1021 | pinctrl_free_gpio(gpio); | |
1022 | } | |
1023 | ||
2ec1d359 AR |
1024 | static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) |
1025 | { | |
1026 | struct nmk_gpio_chip *nmk_chip = | |
1027 | container_of(chip, struct nmk_gpio_chip, chip); | |
1028 | ||
3c0227d2 RV |
1029 | clk_enable(nmk_chip->clk); |
1030 | ||
2ec1d359 | 1031 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); |
3c0227d2 RV |
1032 | |
1033 | clk_disable(nmk_chip->clk); | |
1034 | ||
2ec1d359 AR |
1035 | return 0; |
1036 | } | |
1037 | ||
2ec1d359 AR |
1038 | static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) |
1039 | { | |
1040 | struct nmk_gpio_chip *nmk_chip = | |
1041 | container_of(chip, struct nmk_gpio_chip, chip); | |
1042 | u32 bit = 1 << offset; | |
3c0227d2 RV |
1043 | int value; |
1044 | ||
1045 | clk_enable(nmk_chip->clk); | |
2ec1d359 | 1046 | |
3c0227d2 | 1047 | value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; |
2ec1d359 | 1048 | |
3c0227d2 RV |
1049 | clk_disable(nmk_chip->clk); |
1050 | ||
1051 | return value; | |
2ec1d359 AR |
1052 | } |
1053 | ||
1054 | static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, | |
1055 | int val) | |
1056 | { | |
1057 | struct nmk_gpio_chip *nmk_chip = | |
1058 | container_of(chip, struct nmk_gpio_chip, chip); | |
2ec1d359 | 1059 | |
3c0227d2 RV |
1060 | clk_enable(nmk_chip->clk); |
1061 | ||
6720db7c | 1062 | __nmk_gpio_set_output(nmk_chip, offset, val); |
3c0227d2 RV |
1063 | |
1064 | clk_disable(nmk_chip->clk); | |
2ec1d359 AR |
1065 | } |
1066 | ||
6647c6c0 RV |
1067 | static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, |
1068 | int val) | |
1069 | { | |
1070 | struct nmk_gpio_chip *nmk_chip = | |
1071 | container_of(chip, struct nmk_gpio_chip, chip); | |
1072 | ||
3c0227d2 RV |
1073 | clk_enable(nmk_chip->clk); |
1074 | ||
6720db7c | 1075 | __nmk_gpio_make_output(nmk_chip, offset, val); |
6647c6c0 | 1076 | |
3c0227d2 RV |
1077 | clk_disable(nmk_chip->clk); |
1078 | ||
6647c6c0 RV |
1079 | return 0; |
1080 | } | |
1081 | ||
0d2aec9c RV |
1082 | static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
1083 | { | |
1084 | struct nmk_gpio_chip *nmk_chip = | |
1085 | container_of(chip, struct nmk_gpio_chip, chip); | |
1086 | ||
268300be | 1087 | return irq_create_mapping(nmk_chip->domain, offset); |
0d2aec9c RV |
1088 | } |
1089 | ||
d0b543c7 RV |
1090 | #ifdef CONFIG_DEBUG_FS |
1091 | ||
1092 | #include <linux/seq_file.h> | |
1093 | ||
2249b19f JNG |
1094 | static void nmk_gpio_dbg_show_one(struct seq_file *s, |
1095 | struct pinctrl_dev *pctldev, struct gpio_chip *chip, | |
1096 | unsigned offset, unsigned gpio) | |
d0b543c7 | 1097 | { |
6f4350a6 | 1098 | const char *label = gpiochip_is_requested(chip, offset); |
d0b543c7 RV |
1099 | struct nmk_gpio_chip *nmk_chip = |
1100 | container_of(chip, struct nmk_gpio_chip, chip); | |
6f4350a6 LW |
1101 | int mode; |
1102 | bool is_out; | |
1103 | bool pull; | |
1104 | u32 bit = 1 << offset; | |
d0b543c7 RV |
1105 | const char *modes[] = { |
1106 | [NMK_GPIO_ALT_GPIO] = "gpio", | |
1107 | [NMK_GPIO_ALT_A] = "altA", | |
1108 | [NMK_GPIO_ALT_B] = "altB", | |
1109 | [NMK_GPIO_ALT_C] = "altC", | |
2249b19f JNG |
1110 | [NMK_GPIO_ALT_C+1] = "altC1", |
1111 | [NMK_GPIO_ALT_C+2] = "altC2", | |
1112 | [NMK_GPIO_ALT_C+3] = "altC3", | |
1113 | [NMK_GPIO_ALT_C+4] = "altC4", | |
d0b543c7 RV |
1114 | }; |
1115 | ||
3c0227d2 | 1116 | clk_enable(nmk_chip->clk); |
6f4350a6 LW |
1117 | is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit); |
1118 | pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); | |
1119 | mode = nmk_gpio_get_mode(gpio); | |
2249b19f JNG |
1120 | if ((mode == NMK_GPIO_ALT_C) && pctldev) |
1121 | mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); | |
6f4350a6 LW |
1122 | |
1123 | seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", | |
1124 | gpio, label ?: "(none)", | |
1125 | is_out ? "out" : "in ", | |
1126 | chip->get | |
1127 | ? (chip->get(chip, offset) ? "hi" : "lo") | |
1128 | : "? ", | |
1129 | (mode < 0) ? "unknown" : modes[mode], | |
1130 | pull ? "pull" : "none"); | |
1131 | ||
1132 | if (label && !is_out) { | |
1133 | int irq = gpio_to_irq(gpio); | |
1134 | struct irq_desc *desc = irq_to_desc(irq); | |
1135 | ||
1136 | /* This races with request_irq(), set_irq_type(), | |
1137 | * and set_irq_wake() ... but those are "rare". | |
1138 | */ | |
1139 | if (irq >= 0 && desc->action) { | |
1140 | char *trigger; | |
1141 | u32 bitmask = nmk_gpio_get_bitmask(gpio); | |
1142 | ||
1143 | if (nmk_chip->edge_rising & bitmask) | |
1144 | trigger = "edge-rising"; | |
1145 | else if (nmk_chip->edge_falling & bitmask) | |
1146 | trigger = "edge-falling"; | |
1147 | else | |
1148 | trigger = "edge-undefined"; | |
1149 | ||
1150 | seq_printf(s, " irq-%d %s%s", | |
1151 | irq, trigger, | |
1152 | irqd_is_wakeup_set(&desc->irq_data) | |
1153 | ? " wakeup" : ""); | |
8ea72a30 | 1154 | } |
6f4350a6 LW |
1155 | } |
1156 | clk_disable(nmk_chip->clk); | |
1157 | } | |
1158 | ||
1159 | static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
1160 | { | |
1161 | unsigned i; | |
1162 | unsigned gpio = chip->base; | |
8ea72a30 | 1163 | |
6f4350a6 | 1164 | for (i = 0; i < chip->ngpio; i++, gpio++) { |
2249b19f | 1165 | nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio); |
d0b543c7 RV |
1166 | seq_printf(s, "\n"); |
1167 | } | |
1168 | } | |
1169 | ||
1170 | #else | |
6f4350a6 | 1171 | static inline void nmk_gpio_dbg_show_one(struct seq_file *s, |
2249b19f | 1172 | struct pinctrl_dev *pctldev, |
6f4350a6 LW |
1173 | struct gpio_chip *chip, |
1174 | unsigned offset, unsigned gpio) | |
1175 | { | |
1176 | } | |
d0b543c7 RV |
1177 | #define nmk_gpio_dbg_show NULL |
1178 | #endif | |
1179 | ||
2ec1d359 AR |
1180 | /* This structure is replicated for each GPIO block allocated at probe time */ |
1181 | static struct gpio_chip nmk_gpio_template = { | |
dbfe8ca2 LW |
1182 | .request = nmk_gpio_request, |
1183 | .free = nmk_gpio_free, | |
2ec1d359 AR |
1184 | .direction_input = nmk_gpio_make_input, |
1185 | .get = nmk_gpio_get_input, | |
1186 | .direction_output = nmk_gpio_make_output, | |
1187 | .set = nmk_gpio_set_output, | |
0d2aec9c | 1188 | .to_irq = nmk_gpio_to_irq, |
d0b543c7 | 1189 | .dbg_show = nmk_gpio_dbg_show, |
2ec1d359 AR |
1190 | .can_sleep = 0, |
1191 | }; | |
1192 | ||
3c0227d2 RV |
1193 | void nmk_gpio_clocks_enable(void) |
1194 | { | |
1195 | int i; | |
1196 | ||
1197 | for (i = 0; i < NUM_BANKS; i++) { | |
1198 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1199 | ||
1200 | if (!chip) | |
1201 | continue; | |
1202 | ||
1203 | clk_enable(chip->clk); | |
1204 | } | |
1205 | } | |
1206 | ||
1207 | void nmk_gpio_clocks_disable(void) | |
1208 | { | |
1209 | int i; | |
1210 | ||
1211 | for (i = 0; i < NUM_BANKS; i++) { | |
1212 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1213 | ||
1214 | if (!chip) | |
1215 | continue; | |
1216 | ||
1217 | clk_disable(chip->clk); | |
1218 | } | |
1219 | } | |
1220 | ||
b9df468d RV |
1221 | /* |
1222 | * Called from the suspend/resume path to only keep the real wakeup interrupts | |
1223 | * (those that have had set_irq_wake() called on them) as wakeup interrupts, | |
1224 | * and not the rest of the interrupts which we needed to have as wakeups for | |
1225 | * cpuidle. | |
1226 | * | |
1227 | * PM ops are not used since this needs to be done at the end, after all the | |
1228 | * other drivers are done with their suspend callbacks. | |
1229 | */ | |
1230 | void nmk_gpio_wakeups_suspend(void) | |
1231 | { | |
1232 | int i; | |
1233 | ||
1234 | for (i = 0; i < NUM_BANKS; i++) { | |
1235 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1236 | ||
1237 | if (!chip) | |
1238 | break; | |
1239 | ||
3c0227d2 RV |
1240 | clk_enable(chip->clk); |
1241 | ||
b9df468d RV |
1242 | writel(chip->rwimsc & chip->real_wake, |
1243 | chip->addr + NMK_GPIO_RWIMSC); | |
1244 | writel(chip->fwimsc & chip->real_wake, | |
1245 | chip->addr + NMK_GPIO_FWIMSC); | |
1246 | ||
3c0227d2 | 1247 | clk_disable(chip->clk); |
b9df468d RV |
1248 | } |
1249 | } | |
1250 | ||
1251 | void nmk_gpio_wakeups_resume(void) | |
1252 | { | |
1253 | int i; | |
1254 | ||
1255 | for (i = 0; i < NUM_BANKS; i++) { | |
1256 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1257 | ||
1258 | if (!chip) | |
1259 | break; | |
1260 | ||
3c0227d2 RV |
1261 | clk_enable(chip->clk); |
1262 | ||
b9df468d RV |
1263 | writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); |
1264 | writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); | |
1265 | ||
3c0227d2 | 1266 | clk_disable(chip->clk); |
b9df468d RV |
1267 | } |
1268 | } | |
1269 | ||
bc6f5cf6 RA |
1270 | /* |
1271 | * Read the pull up/pull down status. | |
1272 | * A bit set in 'pull_up' means that pull up | |
1273 | * is selected if pull is enabled in PDIS register. | |
1274 | * Note: only pull up/down set via this driver can | |
1275 | * be detected due to HW limitations. | |
1276 | */ | |
1277 | void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) | |
1278 | { | |
1279 | if (gpio_bank < NUM_BANKS) { | |
1280 | struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; | |
1281 | ||
1282 | if (!chip) | |
1283 | return; | |
1284 | ||
1285 | *pull_up = chip->pull_up; | |
1286 | } | |
1287 | } | |
1288 | ||
a60b57ed LJ |
1289 | int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq, |
1290 | irq_hw_number_t hwirq) | |
1291 | { | |
1292 | struct nmk_gpio_chip *nmk_chip = d->host_data; | |
1293 | ||
1294 | if (!nmk_chip) | |
1295 | return -EINVAL; | |
1296 | ||
1297 | irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq); | |
1298 | set_irq_flags(irq, IRQF_VALID); | |
1299 | irq_set_chip_data(irq, nmk_chip); | |
1300 | irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING); | |
1301 | ||
1302 | return 0; | |
1303 | } | |
1304 | ||
1305 | const struct irq_domain_ops nmk_gpio_irq_simple_ops = { | |
1306 | .map = nmk_gpio_irq_map, | |
1307 | .xlate = irq_domain_xlate_twocell, | |
1308 | }; | |
1309 | ||
fd0d67d6 | 1310 | static int __devinit nmk_gpio_probe(struct platform_device *dev) |
2ec1d359 | 1311 | { |
3e3c62ca | 1312 | struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; |
513c27f8 | 1313 | struct device_node *np = dev->dev.of_node; |
2ec1d359 AR |
1314 | struct nmk_gpio_chip *nmk_chip; |
1315 | struct gpio_chip *chip; | |
3e3c62ca | 1316 | struct resource *res; |
af7dc228 | 1317 | struct clk *clk; |
33b744b3 | 1318 | int secondary_irq; |
8d91771c | 1319 | void __iomem *base; |
832b6cdf | 1320 | int irq_start = 0; |
3e3c62ca | 1321 | int irq; |
2ec1d359 AR |
1322 | int ret; |
1323 | ||
513c27f8 LJ |
1324 | if (!pdata && !np) { |
1325 | dev_err(&dev->dev, "No platform data or device tree found\n"); | |
3e3c62ca | 1326 | return -ENODEV; |
513c27f8 LJ |
1327 | } |
1328 | ||
1329 | if (np) { | |
5e754f33 | 1330 | pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL); |
513c27f8 LJ |
1331 | if (!pdata) |
1332 | return -ENOMEM; | |
1333 | ||
612e1d5f | 1334 | if (of_get_property(np, "st,supports-sleepmode", NULL)) |
513c27f8 LJ |
1335 | pdata->supports_sleepmode = true; |
1336 | ||
1337 | if (of_property_read_u32(np, "gpio-bank", &dev->id)) { | |
1338 | dev_err(&dev->dev, "gpio-bank property not found\n"); | |
1339 | ret = -EINVAL; | |
a60b57ed | 1340 | goto out; |
513c27f8 LJ |
1341 | } |
1342 | ||
1343 | pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP; | |
1344 | pdata->num_gpio = NMK_GPIO_PER_CHIP; | |
1345 | } | |
3e3c62ca RV |
1346 | |
1347 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
1348 | if (!res) { | |
1349 | ret = -ENOENT; | |
1350 | goto out; | |
1351 | } | |
1352 | ||
1353 | irq = platform_get_irq(dev, 0); | |
1354 | if (irq < 0) { | |
1355 | ret = irq; | |
1356 | goto out; | |
1357 | } | |
1358 | ||
33b744b3 RV |
1359 | secondary_irq = platform_get_irq(dev, 1); |
1360 | if (secondary_irq >= 0 && !pdata->get_secondary_status) { | |
1361 | ret = -EINVAL; | |
1362 | goto out; | |
1363 | } | |
1364 | ||
5e754f33 | 1365 | base = devm_request_and_ioremap(&dev->dev, res); |
8d91771c LW |
1366 | if (!base) { |
1367 | ret = -ENOMEM; | |
5e754f33 | 1368 | goto out; |
8d91771c LW |
1369 | } |
1370 | ||
5e754f33 | 1371 | clk = devm_clk_get(&dev->dev, NULL); |
af7dc228 RV |
1372 | if (IS_ERR(clk)) { |
1373 | ret = PTR_ERR(clk); | |
5e754f33 | 1374 | goto out; |
af7dc228 | 1375 | } |
efec381c | 1376 | clk_prepare(clk); |
af7dc228 | 1377 | |
5e754f33 | 1378 | nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL); |
2ec1d359 AR |
1379 | if (!nmk_chip) { |
1380 | ret = -ENOMEM; | |
5e754f33 | 1381 | goto out; |
2ec1d359 | 1382 | } |
513c27f8 | 1383 | |
2ec1d359 AR |
1384 | /* |
1385 | * The virt address in nmk_chip->addr is in the nomadik register space, | |
1386 | * so we can simply convert the resource address, without remapping | |
1387 | */ | |
33b744b3 | 1388 | nmk_chip->bank = dev->id; |
af7dc228 | 1389 | nmk_chip->clk = clk; |
8d91771c | 1390 | nmk_chip->addr = base; |
2ec1d359 | 1391 | nmk_chip->chip = nmk_gpio_template; |
3e3c62ca | 1392 | nmk_chip->parent_irq = irq; |
33b744b3 RV |
1393 | nmk_chip->secondary_parent_irq = secondary_irq; |
1394 | nmk_chip->get_secondary_status = pdata->get_secondary_status; | |
01727e61 | 1395 | nmk_chip->set_ioforce = pdata->set_ioforce; |
33d78647 | 1396 | nmk_chip->sleepmode = pdata->supports_sleepmode; |
c0fcb8db | 1397 | spin_lock_init(&nmk_chip->lock); |
2ec1d359 AR |
1398 | |
1399 | chip = &nmk_chip->chip; | |
1400 | chip->base = pdata->first_gpio; | |
e493e06f | 1401 | chip->ngpio = pdata->num_gpio; |
8d568ae5 | 1402 | chip->label = pdata->name ?: dev_name(&dev->dev); |
2ec1d359 AR |
1403 | chip->dev = &dev->dev; |
1404 | chip->owner = THIS_MODULE; | |
1405 | ||
ebc6178d RV |
1406 | clk_enable(nmk_chip->clk); |
1407 | nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); | |
1408 | clk_disable(nmk_chip->clk); | |
1409 | ||
072e82a1 | 1410 | #ifdef CONFIG_OF_GPIO |
513c27f8 | 1411 | chip->of_node = np; |
072e82a1 | 1412 | #endif |
513c27f8 | 1413 | |
2ec1d359 AR |
1414 | ret = gpiochip_add(&nmk_chip->chip); |
1415 | if (ret) | |
5e754f33 | 1416 | goto out; |
2ec1d359 | 1417 | |
01727e61 RV |
1418 | BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); |
1419 | ||
1420 | nmk_gpio_chips[nmk_chip->bank] = nmk_chip; | |
513c27f8 | 1421 | |
3e3c62ca | 1422 | platform_set_drvdata(dev, nmk_chip); |
2ec1d359 | 1423 | |
51f58c68 | 1424 | if (!np) |
6054b9ca | 1425 | irq_start = NOMADIK_GPIO_TO_IRQ(pdata->first_gpio); |
38843e29 | 1426 | nmk_chip->domain = irq_domain_add_simple(np, |
6054b9ca LW |
1427 | NMK_GPIO_PER_CHIP, irq_start, |
1428 | &nmk_gpio_irq_simple_ops, nmk_chip); | |
a60b57ed | 1429 | if (!nmk_chip->domain) { |
2ee38d4d | 1430 | dev_err(&dev->dev, "failed to create irqdomain\n"); |
a60b57ed | 1431 | ret = -ENOSYS; |
5e754f33 | 1432 | goto out; |
a60b57ed LJ |
1433 | } |
1434 | ||
2ec1d359 AR |
1435 | nmk_gpio_init_irq(nmk_chip); |
1436 | ||
513c27f8 LJ |
1437 | dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); |
1438 | ||
2ec1d359 AR |
1439 | return 0; |
1440 | ||
3e3c62ca | 1441 | out: |
2ec1d359 AR |
1442 | dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, |
1443 | pdata->first_gpio, pdata->first_gpio+31); | |
513c27f8 | 1444 | |
2ec1d359 AR |
1445 | return ret; |
1446 | } | |
1447 | ||
e98ea774 LW |
1448 | static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) |
1449 | { | |
1450 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1451 | ||
1452 | return npct->soc->ngroups; | |
1453 | } | |
1454 | ||
1455 | static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, | |
1456 | unsigned selector) | |
1457 | { | |
1458 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1459 | ||
1460 | return npct->soc->groups[selector].name; | |
1461 | } | |
1462 | ||
1463 | static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
1464 | const unsigned **pins, | |
1465 | unsigned *num_pins) | |
1466 | { | |
1467 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1468 | ||
1469 | *pins = npct->soc->groups[selector].pins; | |
1470 | *num_pins = npct->soc->groups[selector].npins; | |
1471 | return 0; | |
1472 | } | |
1473 | ||
24cbdd75 LW |
1474 | static struct pinctrl_gpio_range * |
1475 | nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset) | |
1476 | { | |
1477 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1478 | int i; | |
1479 | ||
1480 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) { | |
1481 | struct pinctrl_gpio_range *range; | |
1482 | ||
1483 | range = &npct->soc->gpio_ranges[i]; | |
1484 | if (offset >= range->pin_base && | |
1485 | offset <= (range->pin_base + range->npins - 1)) | |
1486 | return range; | |
1487 | } | |
1488 | return NULL; | |
1489 | } | |
1490 | ||
e98ea774 LW |
1491 | static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
1492 | unsigned offset) | |
1493 | { | |
24cbdd75 LW |
1494 | struct pinctrl_gpio_range *range; |
1495 | struct gpio_chip *chip; | |
1496 | ||
1497 | range = nmk_match_gpio_range(pctldev, offset); | |
1498 | if (!range || !range->gc) { | |
1499 | seq_printf(s, "invalid pin offset"); | |
1500 | return; | |
1501 | } | |
1502 | chip = range->gc; | |
2249b19f | 1503 | nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); |
e98ea774 LW |
1504 | } |
1505 | ||
1506 | static struct pinctrl_ops nmk_pinctrl_ops = { | |
1507 | .get_groups_count = nmk_get_groups_cnt, | |
1508 | .get_group_name = nmk_get_group_name, | |
1509 | .get_group_pins = nmk_get_group_pins, | |
1510 | .pin_dbg_show = nmk_pin_dbg_show, | |
1511 | }; | |
1512 | ||
dbfe8ca2 LW |
1513 | static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) |
1514 | { | |
1515 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1516 | ||
1517 | return npct->soc->nfunctions; | |
1518 | } | |
1519 | ||
1520 | static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
1521 | unsigned function) | |
1522 | { | |
1523 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1524 | ||
1525 | return npct->soc->functions[function].name; | |
1526 | } | |
1527 | ||
1528 | static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
1529 | unsigned function, | |
1530 | const char * const **groups, | |
1531 | unsigned * const num_groups) | |
1532 | { | |
1533 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1534 | ||
1535 | *groups = npct->soc->functions[function].groups; | |
1536 | *num_groups = npct->soc->functions[function].ngroups; | |
1537 | ||
1538 | return 0; | |
1539 | } | |
1540 | ||
1541 | static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, | |
1542 | unsigned group) | |
1543 | { | |
1544 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1545 | const struct nmk_pingroup *g; | |
1546 | static unsigned int slpm[NUM_BANKS]; | |
1547 | unsigned long flags; | |
1548 | bool glitch; | |
1549 | int ret = -EINVAL; | |
1550 | int i; | |
1551 | ||
1552 | g = &npct->soc->groups[group]; | |
1553 | ||
1554 | if (g->altsetting < 0) | |
1555 | return -EINVAL; | |
1556 | ||
1557 | dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); | |
1558 | ||
daf73174 LW |
1559 | /* |
1560 | * If we're setting altfunc C by setting both AFSLA and AFSLB to 1, | |
1561 | * we may pass through an undesired state. In this case we take | |
1562 | * some extra care. | |
1563 | * | |
1564 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
1565 | * - Save SLPM registers (since we have a shadow register in the | |
1566 | * nmk_chip we're using that as backup) | |
1567 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
1568 | * - Configure the GPIO registers for the IOs that are being switched | |
1569 | * - Set IOFORCE=1 | |
1570 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
1571 | * - Set IOFORCE=0 | |
1572 | * - Restore SLPM registers | |
1573 | * - Any spurious wake up event during switch sequence to be ignored | |
1574 | * and cleared | |
1575 | * | |
1576 | * We REALLY need to save ALL slpm registers, because the external | |
1577 | * IOFORCE will switch *all* ports to their sleepmode setting to as | |
1578 | * to avoid glitches. (Not just one port!) | |
1579 | */ | |
c22df08c | 1580 | glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); |
dbfe8ca2 LW |
1581 | |
1582 | if (glitch) { | |
1583 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | |
1584 | ||
1585 | /* Initially don't put any pins to sleep when switching */ | |
1586 | memset(slpm, 0xff, sizeof(slpm)); | |
1587 | ||
1588 | /* | |
1589 | * Then mask the pins that need to be sleeping now when we're | |
1590 | * switching to the ALT C function. | |
1591 | */ | |
1592 | for (i = 0; i < g->npins; i++) | |
1593 | slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); | |
1594 | nmk_gpio_glitch_slpm_init(slpm); | |
1595 | } | |
1596 | ||
1597 | for (i = 0; i < g->npins; i++) { | |
1598 | struct pinctrl_gpio_range *range; | |
1599 | struct nmk_gpio_chip *nmk_chip; | |
1600 | struct gpio_chip *chip; | |
1601 | unsigned bit; | |
1602 | ||
1603 | range = nmk_match_gpio_range(pctldev, g->pins[i]); | |
1604 | if (!range) { | |
1605 | dev_err(npct->dev, | |
1606 | "invalid pin offset %d in group %s at index %d\n", | |
1607 | g->pins[i], g->name, i); | |
1608 | goto out_glitch; | |
1609 | } | |
1610 | if (!range->gc) { | |
1611 | dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n", | |
1612 | g->pins[i], g->name, i); | |
1613 | goto out_glitch; | |
1614 | } | |
1615 | chip = range->gc; | |
1616 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
1617 | dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); | |
1618 | ||
1619 | clk_enable(nmk_chip->clk); | |
1620 | bit = g->pins[i] % NMK_GPIO_PER_CHIP; | |
1621 | /* | |
1622 | * If the pin is switching to altfunc, and there was an | |
1623 | * interrupt installed on it which has been lazy disabled, | |
1624 | * actually mask the interrupt to prevent spurious interrupts | |
1625 | * that would occur while the pin is under control of the | |
1626 | * peripheral. Only SKE does this. | |
1627 | */ | |
1628 | nmk_gpio_disable_lazy_irq(nmk_chip, bit); | |
1629 | ||
c22df08c JNG |
1630 | __nmk_gpio_set_mode_safe(nmk_chip, bit, |
1631 | (g->altsetting & NMK_GPIO_ALT_C), glitch); | |
dbfe8ca2 | 1632 | clk_disable(nmk_chip->clk); |
c22df08c JNG |
1633 | |
1634 | /* | |
1635 | * Call PRCM GPIOCR config function in case ALTC | |
1636 | * has been selected: | |
1637 | * - If selection is a ALTCx, some bits in PRCM GPIOCR registers | |
1638 | * must be set. | |
1639 | * - If selection is pure ALTC and previous selection was ALTCx, | |
1640 | * then some bits in PRCM GPIOCR registers must be cleared. | |
1641 | */ | |
1642 | if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C) | |
1643 | nmk_prcm_altcx_set_mode(npct, g->pins[i], | |
1644 | g->altsetting >> NMK_GPIO_ALT_CX_SHIFT); | |
dbfe8ca2 LW |
1645 | } |
1646 | ||
1647 | /* When all pins are successfully reconfigured we get here */ | |
1648 | ret = 0; | |
1649 | ||
1650 | out_glitch: | |
1651 | if (glitch) { | |
1652 | nmk_gpio_glitch_slpm_restore(slpm); | |
1653 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
1654 | } | |
1655 | ||
1656 | return ret; | |
1657 | } | |
1658 | ||
1659 | static void nmk_pmx_disable(struct pinctrl_dev *pctldev, | |
1660 | unsigned function, unsigned group) | |
1661 | { | |
1662 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1663 | const struct nmk_pingroup *g; | |
1664 | ||
1665 | g = &npct->soc->groups[group]; | |
1666 | ||
1667 | if (g->altsetting < 0) | |
1668 | return; | |
1669 | ||
1670 | /* Poke out the mux, set the pin to some default state? */ | |
1671 | dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins); | |
1672 | } | |
1673 | ||
1674 | int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, | |
1675 | struct pinctrl_gpio_range *range, | |
1676 | unsigned offset) | |
1677 | { | |
1678 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1679 | struct nmk_gpio_chip *nmk_chip; | |
1680 | struct gpio_chip *chip; | |
1681 | unsigned bit; | |
1682 | ||
1683 | if (!range) { | |
1684 | dev_err(npct->dev, "invalid range\n"); | |
1685 | return -EINVAL; | |
1686 | } | |
1687 | if (!range->gc) { | |
1688 | dev_err(npct->dev, "missing GPIO chip in range\n"); | |
1689 | return -EINVAL; | |
1690 | } | |
1691 | chip = range->gc; | |
1692 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
1693 | ||
1694 | dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); | |
1695 | ||
1696 | clk_enable(nmk_chip->clk); | |
1697 | bit = offset % NMK_GPIO_PER_CHIP; | |
1698 | /* There is no glitch when converting any pin to GPIO */ | |
1699 | __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); | |
1700 | clk_disable(nmk_chip->clk); | |
1701 | ||
1702 | return 0; | |
1703 | } | |
1704 | ||
1705 | void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, | |
1706 | struct pinctrl_gpio_range *range, | |
1707 | unsigned offset) | |
1708 | { | |
1709 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1710 | ||
1711 | dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); | |
1712 | /* Set the pin to some default state, GPIO is usually default */ | |
1713 | } | |
1714 | ||
1715 | static struct pinmux_ops nmk_pinmux_ops = { | |
1716 | .get_functions_count = nmk_pmx_get_funcs_cnt, | |
1717 | .get_function_name = nmk_pmx_get_func_name, | |
1718 | .get_function_groups = nmk_pmx_get_func_groups, | |
1719 | .enable = nmk_pmx_enable, | |
1720 | .disable = nmk_pmx_disable, | |
1721 | .gpio_request_enable = nmk_gpio_request_enable, | |
1722 | .gpio_disable_free = nmk_gpio_disable_free, | |
1723 | }; | |
1724 | ||
d41af627 LW |
1725 | int nmk_pin_config_get(struct pinctrl_dev *pctldev, |
1726 | unsigned pin, | |
1727 | unsigned long *config) | |
1728 | { | |
1729 | /* Not implemented */ | |
1730 | return -EINVAL; | |
1731 | } | |
1732 | ||
1733 | int nmk_pin_config_set(struct pinctrl_dev *pctldev, | |
1734 | unsigned pin, | |
1735 | unsigned long config) | |
1736 | { | |
1737 | static const char *pullnames[] = { | |
1738 | [NMK_GPIO_PULL_NONE] = "none", | |
1739 | [NMK_GPIO_PULL_UP] = "up", | |
1740 | [NMK_GPIO_PULL_DOWN] = "down", | |
1741 | [3] /* illegal */ = "??" | |
1742 | }; | |
1743 | static const char *slpmnames[] = { | |
1744 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", | |
1745 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
1746 | }; | |
1747 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1748 | struct nmk_gpio_chip *nmk_chip; | |
1749 | struct pinctrl_gpio_range *range; | |
1750 | struct gpio_chip *chip; | |
1751 | unsigned bit; | |
1752 | ||
1753 | /* | |
1754 | * The pin config contains pin number and altfunction fields, here | |
1755 | * we just ignore that part. It's being handled by the framework and | |
1756 | * pinmux callback respectively. | |
1757 | */ | |
1758 | pin_cfg_t cfg = (pin_cfg_t) config; | |
1759 | int pull = PIN_PULL(cfg); | |
1760 | int slpm = PIN_SLPM(cfg); | |
1761 | int output = PIN_DIR(cfg); | |
1762 | int val = PIN_VAL(cfg); | |
1763 | bool lowemi = PIN_LOWEMI(cfg); | |
1764 | bool gpiomode = PIN_GPIOMODE(cfg); | |
1765 | bool sleep = PIN_SLEEPMODE(cfg); | |
1766 | ||
1767 | range = nmk_match_gpio_range(pctldev, pin); | |
1768 | if (!range) { | |
1769 | dev_err(npct->dev, "invalid pin offset %d\n", pin); | |
1770 | return -EINVAL; | |
1771 | } | |
1772 | if (!range->gc) { | |
1773 | dev_err(npct->dev, "GPIO chip missing in range for pin %d\n", | |
1774 | pin); | |
1775 | return -EINVAL; | |
1776 | } | |
1777 | chip = range->gc; | |
1778 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
1779 | ||
1780 | if (sleep) { | |
1781 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
1782 | int slpm_output = PIN_SLPM_DIR(cfg); | |
1783 | int slpm_val = PIN_SLPM_VAL(cfg); | |
1784 | ||
1785 | /* All pins go into GPIO mode at sleep */ | |
1786 | gpiomode = true; | |
1787 | ||
1788 | /* | |
1789 | * The SLPM_* values are normal values + 1 to allow zero to | |
1790 | * mean "same as normal". | |
1791 | */ | |
1792 | if (slpm_pull) | |
1793 | pull = slpm_pull - 1; | |
1794 | if (slpm_output) | |
1795 | output = slpm_output - 1; | |
1796 | if (slpm_val) | |
1797 | val = slpm_val - 1; | |
1798 | ||
1799 | dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", | |
1800 | pin, | |
1801 | slpm_pull ? pullnames[pull] : "same", | |
1802 | slpm_output ? (output ? "output" : "input") : "same", | |
1803 | slpm_val ? (val ? "high" : "low") : "same"); | |
1804 | } | |
1805 | ||
1806 | dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", | |
1807 | pin, cfg, pullnames[pull], slpmnames[slpm], | |
1808 | output ? "output " : "input", | |
1809 | output ? (val ? "high" : "low") : "", | |
1810 | lowemi ? "on" : "off" ); | |
1811 | ||
1812 | clk_enable(nmk_chip->clk); | |
1813 | bit = pin % NMK_GPIO_PER_CHIP; | |
1814 | if (gpiomode) | |
1815 | /* No glitch when going to GPIO mode */ | |
1816 | __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); | |
1817 | if (output) | |
1818 | __nmk_gpio_make_output(nmk_chip, bit, val); | |
1819 | else { | |
1820 | __nmk_gpio_make_input(nmk_chip, bit); | |
1821 | __nmk_gpio_set_pull(nmk_chip, bit, pull); | |
1822 | } | |
1823 | /* TODO: isn't this only applicable on output pins? */ | |
1824 | __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); | |
1825 | ||
1826 | __nmk_gpio_set_slpm(nmk_chip, bit, slpm); | |
1827 | clk_disable(nmk_chip->clk); | |
1828 | return 0; | |
1829 | } | |
1830 | ||
1831 | static struct pinconf_ops nmk_pinconf_ops = { | |
1832 | .pin_config_get = nmk_pin_config_get, | |
1833 | .pin_config_set = nmk_pin_config_set, | |
1834 | }; | |
1835 | ||
e98ea774 LW |
1836 | static struct pinctrl_desc nmk_pinctrl_desc = { |
1837 | .name = "pinctrl-nomadik", | |
1838 | .pctlops = &nmk_pinctrl_ops, | |
dbfe8ca2 | 1839 | .pmxops = &nmk_pinmux_ops, |
d41af627 | 1840 | .confops = &nmk_pinconf_ops, |
e98ea774 LW |
1841 | .owner = THIS_MODULE, |
1842 | }; | |
1843 | ||
855f80cd LJ |
1844 | static const struct of_device_id nmk_pinctrl_match[] = { |
1845 | { | |
1846 | .compatible = "stericsson,nmk_pinctrl", | |
1847 | .data = (void *)PINCTRL_NMK_DB8500, | |
1848 | }, | |
1849 | {}, | |
1850 | }; | |
1851 | ||
e98ea774 LW |
1852 | static int __devinit nmk_pinctrl_probe(struct platform_device *pdev) |
1853 | { | |
1854 | const struct platform_device_id *platid = platform_get_device_id(pdev); | |
855f80cd | 1855 | struct device_node *np = pdev->dev.of_node; |
e98ea774 | 1856 | struct nmk_pinctrl *npct; |
f1671bf5 | 1857 | struct resource *res; |
855f80cd | 1858 | unsigned int version = 0; |
e98ea774 LW |
1859 | int i; |
1860 | ||
1861 | npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); | |
1862 | if (!npct) | |
1863 | return -ENOMEM; | |
1864 | ||
855f80cd LJ |
1865 | if (platid) |
1866 | version = platid->driver_data; | |
1867 | else if (np) | |
1868 | version = (unsigned int) | |
1869 | of_match_device(nmk_pinctrl_match, &pdev->dev)->data; | |
1870 | ||
e98ea774 | 1871 | /* Poke in other ASIC variants here */ |
f79c5ed9 LW |
1872 | if (version == PINCTRL_NMK_STN8815) |
1873 | nmk_pinctrl_stn8815_init(&npct->soc); | |
855f80cd | 1874 | if (version == PINCTRL_NMK_DB8500) |
e98ea774 | 1875 | nmk_pinctrl_db8500_init(&npct->soc); |
45a1b531 PC |
1876 | if (version == PINCTRL_NMK_DB8540) |
1877 | nmk_pinctrl_db8540_init(&npct->soc); | |
e98ea774 | 1878 | |
f1671bf5 JA |
1879 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1880 | if (res) { | |
1881 | npct->prcm_base = devm_ioremap(&pdev->dev, res->start, | |
1882 | resource_size(res)); | |
1883 | if (!npct->prcm_base) { | |
1884 | dev_err(&pdev->dev, | |
1885 | "failed to ioremap PRCM registers\n"); | |
1886 | return -ENOMEM; | |
1887 | } | |
1888 | } else { | |
1889 | dev_info(&pdev->dev, | |
1890 | "No PRCM base, assume no ALT-Cx control is available\n"); | |
1891 | } | |
1892 | ||
e98ea774 LW |
1893 | /* |
1894 | * We need all the GPIO drivers to probe FIRST, or we will not be able | |
1895 | * to obtain references to the struct gpio_chip * for them, and we | |
1896 | * need this to proceed. | |
1897 | */ | |
1898 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) { | |
1d853ca5 | 1899 | if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) { |
e98ea774 | 1900 | dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); |
e98ea774 LW |
1901 | return -EPROBE_DEFER; |
1902 | } | |
1d853ca5 | 1903 | npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip; |
e98ea774 LW |
1904 | } |
1905 | ||
1906 | nmk_pinctrl_desc.pins = npct->soc->pins; | |
1907 | nmk_pinctrl_desc.npins = npct->soc->npins; | |
1908 | npct->dev = &pdev->dev; | |
f1671bf5 | 1909 | |
e98ea774 LW |
1910 | npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct); |
1911 | if (!npct->pctl) { | |
1912 | dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); | |
1913 | return -EINVAL; | |
1914 | } | |
1915 | ||
1916 | /* We will handle a range of GPIO pins */ | |
1917 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) | |
1918 | pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]); | |
1919 | ||
1920 | platform_set_drvdata(pdev, npct); | |
1921 | dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); | |
1922 | ||
1923 | return 0; | |
1924 | } | |
1925 | ||
513c27f8 LJ |
1926 | static const struct of_device_id nmk_gpio_match[] = { |
1927 | { .compatible = "st,nomadik-gpio", }, | |
1928 | {} | |
1929 | }; | |
1930 | ||
3e3c62ca RV |
1931 | static struct platform_driver nmk_gpio_driver = { |
1932 | .driver = { | |
2ec1d359 AR |
1933 | .owner = THIS_MODULE, |
1934 | .name = "gpio", | |
513c27f8 | 1935 | .of_match_table = nmk_gpio_match, |
5317e4d1 | 1936 | }, |
2ec1d359 | 1937 | .probe = nmk_gpio_probe, |
2ec1d359 AR |
1938 | }; |
1939 | ||
e98ea774 LW |
1940 | static const struct platform_device_id nmk_pinctrl_id[] = { |
1941 | { "pinctrl-stn8815", PINCTRL_NMK_STN8815 }, | |
1942 | { "pinctrl-db8500", PINCTRL_NMK_DB8500 }, | |
45a1b531 | 1943 | { "pinctrl-db8540", PINCTRL_NMK_DB8540 }, |
8c995d6d | 1944 | { } |
e98ea774 LW |
1945 | }; |
1946 | ||
1947 | static struct platform_driver nmk_pinctrl_driver = { | |
1948 | .driver = { | |
1949 | .owner = THIS_MODULE, | |
1950 | .name = "pinctrl-nomadik", | |
855f80cd | 1951 | .of_match_table = nmk_pinctrl_match, |
e98ea774 LW |
1952 | }, |
1953 | .probe = nmk_pinctrl_probe, | |
1954 | .id_table = nmk_pinctrl_id, | |
1955 | }; | |
1956 | ||
2ec1d359 AR |
1957 | static int __init nmk_gpio_init(void) |
1958 | { | |
e98ea774 LW |
1959 | int ret; |
1960 | ||
1961 | ret = platform_driver_register(&nmk_gpio_driver); | |
1962 | if (ret) | |
1963 | return ret; | |
1964 | return platform_driver_register(&nmk_pinctrl_driver); | |
2ec1d359 AR |
1965 | } |
1966 | ||
33f45ea9 | 1967 | core_initcall(nmk_gpio_init); |
2ec1d359 AR |
1968 | |
1969 | MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); | |
1970 | MODULE_DESCRIPTION("Nomadik GPIO Driver"); | |
1971 | MODULE_LICENSE("GPL"); |