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pinctrl: rockchip: add return value to rockchip_set_mux
[deliverable/linux.git] / drivers / pinctrl / pinctrl-rockchip.c
CommitLineData
d3e51161
HS		 1/*
2 * Pinctrl driver for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
12 *
13 * and pinctrl-at91:
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 */
25
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/io.h>
29#include <linux/bitops.h>
30#include <linux/gpio.h>
31#include <linux/of_address.h>
32#include <linux/of_irq.h>
33#include <linux/pinctrl/machine.h>
34#include <linux/pinctrl/pinconf.h>
35#include <linux/pinctrl/pinctrl.h>
36#include <linux/pinctrl/pinmux.h>
37#include <linux/pinctrl/pinconf-generic.h>
38#include <linux/irqchip/chained_irq.h>
7e865abb 39#include <linux/clk.h>
d3e51161
HS		 40#include <dt-bindings/pinctrl/rockchip.h>
41
42#include "core.h"
43#include "pinconf.h"
44
45/* GPIO control registers */
46#define GPIO_SWPORT_DR 0x00
47#define GPIO_SWPORT_DDR 0x04
48#define GPIO_INTEN 0x30
49#define GPIO_INTMASK 0x34
50#define GPIO_INTTYPE_LEVEL 0x38
51#define GPIO_INT_POLARITY 0x3c
52#define GPIO_INT_STATUS 0x40
53#define GPIO_INT_RAWSTATUS 0x44
54#define GPIO_DEBOUNCE 0x48
55#define GPIO_PORTS_EOI 0x4c
56#define GPIO_EXT_PORT 0x50
57#define GPIO_LS_SYNC 0x60
58
a282926d
HS		 59enum rockchip_pinctrl_type {
60 RK2928,
61 RK3066B,
62 RK3188,
63};
64
65fca613
HS		 65enum rockchip_pin_bank_type {
66 COMMON_BANK,
6ca5274d 67 RK3188_BANK0,
65fca613
HS		 68};
69
d3e51161
HS		 70/**
71 * @reg_base: register base of the gpio bank
6ca5274d 72 * @reg_pull: optional separate register for additional pull settings
d3e51161
HS		 73 * @clk: clock of the gpio bank
74 * @irq: interrupt of the gpio bank
75 * @pin_base: first pin number
76 * @nr_pins: number of pins in this bank
77 * @name: name of the bank
78 * @bank_num: number of the bank, to account for holes
79 * @valid: are all necessary informations present
80 * @of_node: dt node of this bank
81 * @drvdata: common pinctrl basedata
82 * @domain: irqdomain of the gpio bank
83 * @gpio_chip: gpiolib chip
84 * @grange: gpio range
85 * @slock: spinlock for the gpio bank
86 */
87struct rockchip_pin_bank {
88 void __iomem *reg_base;
6ca5274d 89 void __iomem *reg_pull;
d3e51161
HS		 90 struct clk *clk;
91 int irq;
92 u32 pin_base;
93 u8 nr_pins;
94 char *name;
95 u8 bank_num;
65fca613 96 enum rockchip_pin_bank_type bank_type;
d3e51161
HS		 97 bool valid;
98 struct device_node *of_node;
99 struct rockchip_pinctrl *drvdata;
100 struct irq_domain *domain;
101 struct gpio_chip gpio_chip;
102 struct pinctrl_gpio_range grange;
103 spinlock_t slock;
5a927501 104 u32 toggle_edge_mode;
d3e51161
HS		 105};
106
107#define PIN_BANK(id, pins, label) \
108 { \
109 .bank_num = id, \
110 .nr_pins = pins, \
111 .name = label, \
112 }
113
114/**
d3e51161
HS		 115 */
116struct rockchip_pin_ctrl {
117 struct rockchip_pin_bank *pin_banks;
118 u32 nr_banks;
119 u32 nr_pins;
120 char *label;
a282926d 121 enum rockchip_pinctrl_type type;
d3e51161 122 int mux_offset;
a282926d
HS		 123 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num,
124 void __iomem **reg, u8 *bit);
d3e51161
HS		 125};
126
127struct rockchip_pin_config {
128 unsigned int func;
129 unsigned long *configs;
130 unsigned int nconfigs;
131};
132
133/**
134 * struct rockchip_pin_group: represent group of pins of a pinmux function.
135 * @name: name of the pin group, used to lookup the group.
136 * @pins: the pins included in this group.
137 * @npins: number of pins included in this group.
138 * @func: the mux function number to be programmed when selected.
139 * @configs: the config values to be set for each pin
140 * @nconfigs: number of configs for each pin
141 */
142struct rockchip_pin_group {
143 const char *name;
144 unsigned int npins;
145 unsigned int *pins;
146 struct rockchip_pin_config *data;
147};
148
149/**
150 * struct rockchip_pmx_func: represent a pin function.
151 * @name: name of the pin function, used to lookup the function.
152 * @groups: one or more names of pin groups that provide this function.
153 * @num_groups: number of groups included in @groups.
154 */
155struct rockchip_pmx_func {
156 const char *name;
157 const char **groups;
158 u8 ngroups;
159};
160
161struct rockchip_pinctrl {
162 void __iomem *reg_base;
6ca5274d 163 void __iomem *reg_pull;
d3e51161
HS		 164 struct device *dev;
165 struct rockchip_pin_ctrl *ctrl;
166 struct pinctrl_desc pctl;
167 struct pinctrl_dev *pctl_dev;
168 struct rockchip_pin_group *groups;
169 unsigned int ngroups;
170 struct rockchip_pmx_func *functions;
171 unsigned int nfunctions;
172};
173
174static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
175{
176 return container_of(gc, struct rockchip_pin_bank, gpio_chip);
177}
178
179static const inline struct rockchip_pin_group *pinctrl_name_to_group(
180 const struct rockchip_pinctrl *info,
181 const char *name)
182{
d3e51161
HS		 183 int i;
184
185 for (i = 0; i < info->ngroups; i++) {
1cb95395
AL		 186 if (!strcmp(info->groups[i].name, name))
187 return &info->groups[i];
d3e51161
HS		 188 }
189
1cb95395 190 return NULL;
d3e51161
HS		 191}
192
193/*
194 * given a pin number that is local to a pin controller, find out the pin bank
195 * and the register base of the pin bank.
196 */
197static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
198 unsigned pin)
199{
200 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
201
51578b9b 202 while (pin >= (b->pin_base + b->nr_pins))
d3e51161
HS		 203 b++;
204
205 return b;
206}
207
208static struct rockchip_pin_bank *bank_num_to_bank(
209 struct rockchip_pinctrl *info,
210 unsigned num)
211{
212 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
213 int i;
214
1cb95395 215 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
d3e51161 216 if (b->bank_num == num)
1cb95395 217 return b;
d3e51161
HS		 218 }
219
1cb95395 220 return ERR_PTR(-EINVAL);
d3e51161
HS		 221}
222
223/*
224 * Pinctrl_ops handling
225 */
226
227static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
228{
229 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
230
231 return info->ngroups;
232}
233
234static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
235 unsigned selector)
236{
237 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
238
239 return info->groups[selector].name;
240}
241
242static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
243 unsigned selector, const unsigned **pins,
244 unsigned *npins)
245{
246 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
247
248 if (selector >= info->ngroups)
249 return -EINVAL;
250
251 *pins = info->groups[selector].pins;
252 *npins = info->groups[selector].npins;
253
254 return 0;
255}
256
257static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
258 struct device_node *np,
259 struct pinctrl_map **map, unsigned *num_maps)
260{
261 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
262 const struct rockchip_pin_group *grp;
263 struct pinctrl_map *new_map;
264 struct device_node *parent;
265 int map_num = 1;
266 int i;
267
268 /*
269 * first find the group of this node and check if we need to create
270 * config maps for pins
271 */
272 grp = pinctrl_name_to_group(info, np->name);
273 if (!grp) {
274 dev_err(info->dev, "unable to find group for node %s\n",
275 np->name);
276 return -EINVAL;
277 }
278
279 map_num += grp->npins;
280 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
281 GFP_KERNEL);
282 if (!new_map)
283 return -ENOMEM;
284
285 *map = new_map;
286 *num_maps = map_num;
287
288 /* create mux map */
289 parent = of_get_parent(np);
290 if (!parent) {
291 devm_kfree(pctldev->dev, new_map);
292 return -EINVAL;
293 }
294 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
295 new_map[0].data.mux.function = parent->name;
296 new_map[0].data.mux.group = np->name;
297 of_node_put(parent);
298
299 /* create config map */
300 new_map++;
301 for (i = 0; i < grp->npins; i++) {
302 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
303 new_map[i].data.configs.group_or_pin =
304 pin_get_name(pctldev, grp->pins[i]);
305 new_map[i].data.configs.configs = grp->data[i].configs;
306 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
307 }
308
309 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
310 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
311
312 return 0;
313}
314
315static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
316 struct pinctrl_map *map, unsigned num_maps)
317{
318}
319
320static const struct pinctrl_ops rockchip_pctrl_ops = {
321 .get_groups_count = rockchip_get_groups_count,
322 .get_group_name = rockchip_get_group_name,
323 .get_group_pins = rockchip_get_group_pins,
324 .dt_node_to_map = rockchip_dt_node_to_map,
325 .dt_free_map = rockchip_dt_free_map,
326};
327
328/*
329 * Hardware access
330 */
331
332/*
333 * Set a new mux function for a pin.
334 *
335 * The register is divided into the upper and lower 16 bit. When changing
336 * a value, the previous register value is not read and changed. Instead
337 * it seems the changed bits are marked in the upper 16 bit, while the
338 * changed value gets set in the same offset in the lower 16 bit.
339 * All pin settings seem to be 2 bit wide in both the upper and lower
340 * parts.
341 * @bank: pin bank to change
342 * @pin: pin to change
343 * @mux: new mux function to set
344 */
14797189 345static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
d3e51161
HS		 346{
347 struct rockchip_pinctrl *info = bank->drvdata;
348 void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
349 unsigned long flags;
350 u8 bit;
351 u32 data;
352
353 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
354 bank->bank_num, pin, mux);
355
356 /* get basic quadrupel of mux registers and the correct reg inside */
357 reg += bank->bank_num * 0x10;
358 reg += (pin / 8) * 4;
359 bit = (pin % 8) * 2;
360
361 spin_lock_irqsave(&bank->slock, flags);
362
363 data = (3 << (bit + 16));
364 data |= (mux & 3) << bit;
365 writel(data, reg);
366
367 spin_unlock_irqrestore(&bank->slock, flags);
14797189
HS		 368
369 return 0;
d3e51161
HS		 370}
371
a282926d
HS		 372#define RK2928_PULL_OFFSET 0x118
373#define RK2928_PULL_PINS_PER_REG 16
374#define RK2928_PULL_BANK_STRIDE 8
375
376static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
377 int pin_num, void __iomem **reg, u8 *bit)
378{
379 struct rockchip_pinctrl *info = bank->drvdata;
380
381 *reg = info->reg_base + RK2928_PULL_OFFSET;
382 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
383 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
384
385 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
386};
387
6ca5274d
HS		 388#define RK3188_PULL_BITS_PER_PIN 2
389#define RK3188_PULL_PINS_PER_REG 8
390#define RK3188_PULL_BANK_STRIDE 16
391
392static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
393 int pin_num, void __iomem **reg, u8 *bit)
394{
395 struct rockchip_pinctrl *info = bank->drvdata;
396
397 /* The first 12 pins of the first bank are located elsewhere */
398 if (bank->bank_type == RK3188_BANK0 && pin_num < 12) {
399 *reg = bank->reg_pull +
400 ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
401 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
402 *bit *= RK3188_PULL_BITS_PER_PIN;
403 } else {
404 *reg = info->reg_pull - 4;
405 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
406 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
407
408 /*
409 * The bits in these registers have an inverse ordering
410 * with the lowest pin being in bits 15:14 and the highest
411 * pin in bits 1:0
412 */
413 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
414 *bit *= RK3188_PULL_BITS_PER_PIN;
415 }
416}
417
d3e51161
HS		 418static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
419{
420 struct rockchip_pinctrl *info = bank->drvdata;
421 struct rockchip_pin_ctrl *ctrl = info->ctrl;
422 void __iomem *reg;
423 u8 bit;
6ca5274d 424 u32 data;
d3e51161
HS		 425
426 /* rk3066b does support any pulls */
a282926d 427 if (ctrl->type == RK3066B)
d3e51161
HS		 428 return PIN_CONFIG_BIAS_DISABLE;
429
6ca5274d
HS		 430 ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
431
a282926d
HS		 432 switch (ctrl->type) {
433 case RK2928:
d3e51161
HS		 434 return !(readl_relaxed(reg) & BIT(bit))
435 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
436 : PIN_CONFIG_BIAS_DISABLE;
a282926d 437 case RK3188:
6ca5274d
HS		 438 data = readl_relaxed(reg) >> bit;
439 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
440
441 switch (data) {
442 case 0:
443 return PIN_CONFIG_BIAS_DISABLE;
444 case 1:
445 return PIN_CONFIG_BIAS_PULL_UP;
446 case 2:
447 return PIN_CONFIG_BIAS_PULL_DOWN;
448 case 3:
449 return PIN_CONFIG_BIAS_BUS_HOLD;
450 }
451
452 dev_err(info->dev, "unknown pull setting\n");
d3e51161 453 return -EIO;
a282926d
HS		 454 default:
455 dev_err(info->dev, "unsupported pinctrl type\n");
456 return -EINVAL;
457 };
d3e51161
HS		 458}
459
460static int rockchip_set_pull(struct rockchip_pin_bank *bank,
461 int pin_num, int pull)
462{
463 struct rockchip_pinctrl *info = bank->drvdata;
464 struct rockchip_pin_ctrl *ctrl = info->ctrl;
465 void __iomem *reg;
466 unsigned long flags;
467 u8 bit;
468 u32 data;
469
470 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
471 bank->bank_num, pin_num, pull);
472
473 /* rk3066b does support any pulls */
a282926d 474 if (ctrl->type == RK3066B)
d3e51161
HS		 475 return pull ? -EINVAL : 0;
476
6ca5274d
HS		 477 ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
478
a282926d
HS		 479 switch (ctrl->type) {
480 case RK2928:
d3e51161
HS		 481 spin_lock_irqsave(&bank->slock, flags);
482
483 data = BIT(bit + 16);
484 if (pull == PIN_CONFIG_BIAS_DISABLE)
485 data |= BIT(bit);
486 writel(data, reg);
487
488 spin_unlock_irqrestore(&bank->slock, flags);
a282926d
HS		 489 break;
490 case RK3188:
6ca5274d
HS		 491 spin_lock_irqsave(&bank->slock, flags);
492
493 /* enable the write to the equivalent lower bits */
494 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
495
496 switch (pull) {
497 case PIN_CONFIG_BIAS_DISABLE:
498 break;
499 case PIN_CONFIG_BIAS_PULL_UP:
500 data |= (1 << bit);
501 break;
502 case PIN_CONFIG_BIAS_PULL_DOWN:
503 data |= (2 << bit);
504 break;
505 case PIN_CONFIG_BIAS_BUS_HOLD:
506 data |= (3 << bit);
507 break;
508 default:
d32c3e26 509 spin_unlock_irqrestore(&bank->slock, flags);
6ca5274d
HS		 510 dev_err(info->dev, "unsupported pull setting %d\n",
511 pull);
512 return -EINVAL;
513 }
514
515 writel(data, reg);
516
517 spin_unlock_irqrestore(&bank->slock, flags);
518 break;
a282926d
HS		 519 default:
520 dev_err(info->dev, "unsupported pinctrl type\n");
521 return -EINVAL;
d3e51161
HS		 522 }
523
524 return 0;
525}
526
527/*
528 * Pinmux_ops handling
529 */
530
531static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
532{
533 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
534
535 return info->nfunctions;
536}
537
538static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
539 unsigned selector)
540{
541 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
542
543 return info->functions[selector].name;
544}
545
546static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
547 unsigned selector, const char * const **groups,
548 unsigned * const num_groups)
549{
550 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
551
552 *groups = info->functions[selector].groups;
553 *num_groups = info->functions[selector].ngroups;
554
555 return 0;
556}
557
558static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
559 unsigned group)
560{
561 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
562 const unsigned int *pins = info->groups[group].pins;
563 const struct rockchip_pin_config *data = info->groups[group].data;
564 struct rockchip_pin_bank *bank;
14797189 565 int cnt, ret = 0;
d3e51161
HS		 566
567 dev_dbg(info->dev, "enable function %s group %s\n",
568 info->functions[selector].name, info->groups[group].name);
569
570 /*
571 * for each pin in the pin group selected, program the correspoding pin
572 * pin function number in the config register.
573 */
574 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
575 bank = pin_to_bank(info, pins[cnt]);
14797189
HS		 576 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
577 data[cnt].func);
578 if (ret)
579 break;
580 }
581
582 if (ret) {
583 /* revert the already done pin settings */
584 for (cnt--; cnt >= 0; cnt--)
585 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
586
587 return ret;
d3e51161
HS		 588 }
589
590 return 0;
591}
592
593static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
594 unsigned selector, unsigned group)
595{
596 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
597 const unsigned int *pins = info->groups[group].pins;
598 struct rockchip_pin_bank *bank;
599 int cnt;
600
601 dev_dbg(info->dev, "disable function %s group %s\n",
602 info->functions[selector].name, info->groups[group].name);
603
604 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
605 bank = pin_to_bank(info, pins[cnt]);
606 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
607 }
608}
609
610/*
611 * The calls to gpio_direction_output() and gpio_direction_input()
612 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
613 * function called from the gpiolib interface).
614 */
615static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
616 struct pinctrl_gpio_range *range,
617 unsigned offset, bool input)
618{
619 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
620 struct rockchip_pin_bank *bank;
621 struct gpio_chip *chip;
14797189 622 int pin, ret;
d3e51161
HS		 623 u32 data;
624
625 chip = range->gc;
626 bank = gc_to_pin_bank(chip);
627 pin = offset - chip->base;
628
629 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
630 offset, range->name, pin, input ? "input" : "output");
631
14797189
HS		 632 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
633 if (ret < 0)
634 return ret;
d3e51161
HS		 635
636 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
637 /* set bit to 1 for output, 0 for input */
638 if (!input)
639 data |= BIT(pin);
640 else
641 data &= ~BIT(pin);
642 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
643
644 return 0;
645}
646
647static const struct pinmux_ops rockchip_pmx_ops = {
648 .get_functions_count = rockchip_pmx_get_funcs_count,
649 .get_function_name = rockchip_pmx_get_func_name,
650 .get_function_groups = rockchip_pmx_get_groups,
651 .enable = rockchip_pmx_enable,
652 .disable = rockchip_pmx_disable,
653 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
654};
655
656/*
657 * Pinconf_ops handling
658 */
659
44b6d930
HS		 660static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
661 enum pin_config_param pull)
662{
a282926d
HS		 663 switch (ctrl->type) {
664 case RK2928:
665 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
666 pull == PIN_CONFIG_BIAS_DISABLE);
667 case RK3066B:
44b6d930 668 return pull ? false : true;
a282926d
HS		 669 case RK3188:
670 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
44b6d930
HS		 671 }
672
a282926d 673 return false;
44b6d930
HS		 674}
675
d3e51161
HS		 676/* set the pin config settings for a specified pin */
677static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
03b054e9 678 unsigned long *configs, unsigned num_configs)
d3e51161
HS		 679{
680 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
681 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
03b054e9
SY		 682 enum pin_config_param param;
683 u16 arg;
684 int i;
685 int rc;
686
687 for (i = 0; i < num_configs; i++) {
688 param = pinconf_to_config_param(configs[i]);
689 arg = pinconf_to_config_argument(configs[i]);
690
691 switch (param) {
692 case PIN_CONFIG_BIAS_DISABLE:
693 rc = rockchip_set_pull(bank, pin - bank->pin_base,
694 param);
695 if (rc)
696 return rc;
697 break;
698 case PIN_CONFIG_BIAS_PULL_UP:
699 case PIN_CONFIG_BIAS_PULL_DOWN:
700 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
6ca5274d 701 case PIN_CONFIG_BIAS_BUS_HOLD:
03b054e9
SY		 702 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
703 return -ENOTSUPP;
704
705 if (!arg)
706 return -EINVAL;
707
708 rc = rockchip_set_pull(bank, pin - bank->pin_base,
709 param);
710 if (rc)
711 return rc;
712 break;
713 default:
44b6d930 714 return -ENOTSUPP;
03b054e9
SY		 715 break;
716 }
717 } /* for each config */
d3e51161
HS		 718
719 return 0;
720}
721
722/* get the pin config settings for a specified pin */
723static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
724 unsigned long *config)
725{
726 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
727 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
728 enum pin_config_param param = pinconf_to_config_param(*config);
d3e51161
HS		 729
730 switch (param) {
731 case PIN_CONFIG_BIAS_DISABLE:
44b6d930
HS		 732 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
733 return -EINVAL;
734
735 *config = 0;
736 break;
d3e51161
HS		 737 case PIN_CONFIG_BIAS_PULL_UP:
738 case PIN_CONFIG_BIAS_PULL_DOWN:
739 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
6ca5274d 740 case PIN_CONFIG_BIAS_BUS_HOLD:
44b6d930
HS		 741 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
742 return -ENOTSUPP;
d3e51161 743
44b6d930 744 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
d3e51161
HS		 745 return -EINVAL;
746
44b6d930 747 *config = 1;
d3e51161
HS		 748 break;
749 default:
750 return -ENOTSUPP;
751 break;
752 }
753
754 return 0;
755}
756
757static const struct pinconf_ops rockchip_pinconf_ops = {
758 .pin_config_get = rockchip_pinconf_get,
759 .pin_config_set = rockchip_pinconf_set,
760};
761
65fca613
HS		 762static const struct of_device_id rockchip_bank_match[] = {
763 { .compatible = "rockchip,gpio-bank" },
6ca5274d 764 { .compatible = "rockchip,rk3188-gpio-bank0" },
65fca613
HS		 765 {},
766};
d3e51161
HS		 767
768static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
769 struct device_node *np)
770{
771 struct device_node *child;
772
773 for_each_child_of_node(np, child) {
65fca613 774 if (of_match_node(rockchip_bank_match, child))
d3e51161
HS		 775 continue;
776
777 info->nfunctions++;
778 info->ngroups += of_get_child_count(child);
779 }
780}
781
782static int rockchip_pinctrl_parse_groups(struct device_node *np,
783 struct rockchip_pin_group *grp,
784 struct rockchip_pinctrl *info,
785 u32 index)
786{
787 struct rockchip_pin_bank *bank;
788 int size;
789 const __be32 *list;
790 int num;
791 int i, j;
792 int ret;
793
794 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
795
796 /* Initialise group */
797 grp->name = np->name;
798
799 /*
800 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
801 * do sanity check and calculate pins number
802 */
803 list = of_get_property(np, "rockchip,pins", &size);
804 /* we do not check return since it's safe node passed down */
805 size /= sizeof(*list);
806 if (!size || size % 4) {
807 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
808 return -EINVAL;
809 }
810
811 grp->npins = size / 4;
812
813 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
814 GFP_KERNEL);
815 grp->data = devm_kzalloc(info->dev, grp->npins *
816 sizeof(struct rockchip_pin_config),
817 GFP_KERNEL);
818 if (!grp->pins || !grp->data)
819 return -ENOMEM;
820
821 for (i = 0, j = 0; i < size; i += 4, j++) {
822 const __be32 *phandle;
823 struct device_node *np_config;
824
825 num = be32_to_cpu(*list++);
826 bank = bank_num_to_bank(info, num);
827 if (IS_ERR(bank))
828 return PTR_ERR(bank);
829
830 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
831 grp->data[j].func = be32_to_cpu(*list++);
832
833 phandle = list++;
834 if (!phandle)
835 return -EINVAL;
836
837 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
838 ret = pinconf_generic_parse_dt_config(np_config,
839 &grp->data[j].configs, &grp->data[j].nconfigs);
840 if (ret)
841 return ret;
842 }
843
844 return 0;
845}
846
847static int rockchip_pinctrl_parse_functions(struct device_node *np,
848 struct rockchip_pinctrl *info,
849 u32 index)
850{
851 struct device_node *child;
852 struct rockchip_pmx_func *func;
853 struct rockchip_pin_group *grp;
854 int ret;
855 static u32 grp_index;
856 u32 i = 0;
857
858 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
859
860 func = &info->functions[index];
861
862 /* Initialise function */
863 func->name = np->name;
864 func->ngroups = of_get_child_count(np);
865 if (func->ngroups <= 0)
866 return 0;
867
868 func->groups = devm_kzalloc(info->dev,
869 func->ngroups * sizeof(char *), GFP_KERNEL);
870 if (!func->groups)
871 return -ENOMEM;
872
873 for_each_child_of_node(np, child) {
874 func->groups[i] = child->name;
875 grp = &info->groups[grp_index++];
876 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
877 if (ret)
878 return ret;
879 }
880
881 return 0;
882}
883
884static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
885 struct rockchip_pinctrl *info)
886{
887 struct device *dev = &pdev->dev;
888 struct device_node *np = dev->of_node;
889 struct device_node *child;
890 int ret;
891 int i;
892
893 rockchip_pinctrl_child_count(info, np);
894
895 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
896 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
897
898 info->functions = devm_kzalloc(dev, info->nfunctions *
899 sizeof(struct rockchip_pmx_func),
900 GFP_KERNEL);
901 if (!info->functions) {
902 dev_err(dev, "failed to allocate memory for function list\n");
903 return -EINVAL;
904 }
905
906 info->groups = devm_kzalloc(dev, info->ngroups *
907 sizeof(struct rockchip_pin_group),
908 GFP_KERNEL);
909 if (!info->groups) {
910 dev_err(dev, "failed allocate memory for ping group list\n");
911 return -EINVAL;
912 }
913
914 i = 0;
915
916 for_each_child_of_node(np, child) {
65fca613 917 if (of_match_node(rockchip_bank_match, child))
d3e51161 918 continue;
65fca613 919
d3e51161
HS		 920 ret = rockchip_pinctrl_parse_functions(child, info, i++);
921 if (ret) {
922 dev_err(&pdev->dev, "failed to parse function\n");
923 return ret;
924 }
925 }
926
927 return 0;
928}
929
930static int rockchip_pinctrl_register(struct platform_device *pdev,
931 struct rockchip_pinctrl *info)
932{
933 struct pinctrl_desc *ctrldesc = &info->pctl;
934 struct pinctrl_pin_desc *pindesc, *pdesc;
935 struct rockchip_pin_bank *pin_bank;
936 int pin, bank, ret;
937 int k;
938
939 ctrldesc->name = "rockchip-pinctrl";
940 ctrldesc->owner = THIS_MODULE;
941 ctrldesc->pctlops = &rockchip_pctrl_ops;
942 ctrldesc->pmxops = &rockchip_pmx_ops;
943 ctrldesc->confops = &rockchip_pinconf_ops;
944
945 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
946 info->ctrl->nr_pins, GFP_KERNEL);
947 if (!pindesc) {
948 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
949 return -ENOMEM;
950 }
951 ctrldesc->pins = pindesc;
952 ctrldesc->npins = info->ctrl->nr_pins;
953
954 pdesc = pindesc;
955 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
956 pin_bank = &info->ctrl->pin_banks[bank];
957 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
958 pdesc->number = k;
959 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
960 pin_bank->name, pin);
961 pdesc++;
962 }
963 }
964
965 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
966 if (!info->pctl_dev) {
967 dev_err(&pdev->dev, "could not register pinctrl driver\n");
968 return -EINVAL;
969 }
970
971 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
972 pin_bank = &info->ctrl->pin_banks[bank];
973 pin_bank->grange.name = pin_bank->name;
974 pin_bank->grange.id = bank;
975 pin_bank->grange.pin_base = pin_bank->pin_base;
976 pin_bank->grange.base = pin_bank->gpio_chip.base;
977 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
978 pin_bank->grange.gc = &pin_bank->gpio_chip;
979 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
980 }
981
982 ret = rockchip_pinctrl_parse_dt(pdev, info);
983 if (ret) {
984 pinctrl_unregister(info->pctl_dev);
985 return ret;
986 }
987
988 return 0;
989}
990
991/*
992 * GPIO handling
993 */
994
0351c287
AL		 995static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
996{
997 return pinctrl_request_gpio(chip->base + offset);
998}
999
1000static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
1001{
1002 pinctrl_free_gpio(chip->base + offset);
1003}
1004
d3e51161
HS		 1005static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1006{
1007 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1008 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1009 unsigned long flags;
1010 u32 data;
1011
1012 spin_lock_irqsave(&bank->slock, flags);
1013
1014 data = readl(reg);
1015 data &= ~BIT(offset);
1016 if (value)
1017 data |= BIT(offset);
1018 writel(data, reg);
1019
1020 spin_unlock_irqrestore(&bank->slock, flags);
1021}
1022
1023/*
1024 * Returns the level of the pin for input direction and setting of the DR
1025 * register for output gpios.
1026 */
1027static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1028{
1029 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1030 u32 data;
1031
1032 data = readl(bank->reg_base + GPIO_EXT_PORT);
1033 data >>= offset;
1034 data &= 1;
1035 return data;
1036}
1037
1038/*
1039 * gpiolib gpio_direction_input callback function. The setting of the pin
1040 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1041 * interface.
1042 */
1043static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1044{
1045 return pinctrl_gpio_direction_input(gc->base + offset);
1046}
1047
1048/*
1049 * gpiolib gpio_direction_output callback function. The setting of the pin
1050 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1051 * interface.
1052 */
1053static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1054 unsigned offset, int value)
1055{
1056 rockchip_gpio_set(gc, offset, value);
1057 return pinctrl_gpio_direction_output(gc->base + offset);
1058}
1059
1060/*
1061 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1062 * and a virtual IRQ, if not already present.
1063 */
1064static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1065{
1066 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1067 unsigned int virq;
1068
1069 if (!bank->domain)
1070 return -ENXIO;
1071
1072 virq = irq_create_mapping(bank->domain, offset);
1073
1074 return (virq) ? : -ENXIO;
1075}
1076
1077static const struct gpio_chip rockchip_gpiolib_chip = {
0351c287
AL		 1078 .request = rockchip_gpio_request,
1079 .free = rockchip_gpio_free,
d3e51161
HS		 1080 .set = rockchip_gpio_set,
1081 .get = rockchip_gpio_get,
1082 .direction_input = rockchip_gpio_direction_input,
1083 .direction_output = rockchip_gpio_direction_output,
1084 .to_irq = rockchip_gpio_to_irq,
1085 .owner = THIS_MODULE,
1086};
1087
1088/*
1089 * Interrupt handling
1090 */
1091
1092static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1093{
1094 struct irq_chip *chip = irq_get_chip(irq);
1095 struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
5a927501 1096 u32 polarity = 0, data = 0;
d3e51161 1097 u32 pend;
5a927501 1098 bool edge_changed = false;
d3e51161
HS		 1099
1100 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1101
1102 chained_irq_enter(chip, desc);
1103
1104 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1105
5a927501
HS		 1106 if (bank->toggle_edge_mode) {
1107 polarity = readl_relaxed(bank->reg_base +
1108 GPIO_INT_POLARITY);
1109 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1110 }
1111
d3e51161
HS		 1112 while (pend) {
1113 unsigned int virq;
1114
1115 irq = __ffs(pend);
1116 pend &= ~BIT(irq);
1117 virq = irq_linear_revmap(bank->domain, irq);
1118
1119 if (!virq) {
1120 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1121 continue;
1122 }
1123
1124 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1125
5a927501
HS		 1126 /*
1127 * Triggering IRQ on both rising and falling edge
1128 * needs manual intervention.
1129 */
1130 if (bank->toggle_edge_mode & BIT(irq)) {
1131 if (data & BIT(irq))
1132 polarity &= ~BIT(irq);
1133 else
1134 polarity |= BIT(irq);
1135
1136 edge_changed = true;
1137 }
1138
d3e51161
HS		 1139 generic_handle_irq(virq);
1140 }
1141
5a927501
HS		 1142 if (bank->toggle_edge_mode && edge_changed) {
1143 /* Interrupt params should only be set with ints disabled */
1144 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
1145 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
1146 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
1147 writel(data, bank->reg_base + GPIO_INTEN);
1148 }
1149
d3e51161
HS		 1150 chained_irq_exit(chip, desc);
1151}
1152
1153static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1154{
1155 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1156 struct rockchip_pin_bank *bank = gc->private;
1157 u32 mask = BIT(d->hwirq);
1158 u32 polarity;
1159 u32 level;
1160 u32 data;
14797189 1161 int ret;
d3e51161 1162
5a927501 1163 /* make sure the pin is configured as gpio input */
14797189
HS		 1164 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1165 if (ret < 0)
1166 return ret;
1167
5a927501
HS		 1168 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1169 data &= ~mask;
1170 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1171
d3e51161
HS		 1172 if (type & IRQ_TYPE_EDGE_BOTH)
1173 __irq_set_handler_locked(d->irq, handle_edge_irq);
1174 else
1175 __irq_set_handler_locked(d->irq, handle_level_irq);
1176
1177 irq_gc_lock(gc);
1178
1179 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1180 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1181
1182 switch (type) {
5a927501
HS		 1183 case IRQ_TYPE_EDGE_BOTH:
1184 bank->toggle_edge_mode |= mask;
1185 level |= mask;
1186
1187 /*
1188 * Determine gpio state. If 1 next interrupt should be falling
1189 * otherwise rising.
1190 */
1191 data = readl(bank->reg_base + GPIO_EXT_PORT);
1192 if (data & mask)
1193 polarity &= ~mask;
1194 else
1195 polarity |= mask;
1196 break;
d3e51161 1197 case IRQ_TYPE_EDGE_RISING:
5a927501 1198 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1199 level |= mask;
1200 polarity |= mask;
1201 break;
1202 case IRQ_TYPE_EDGE_FALLING:
5a927501 1203 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1204 level |= mask;
1205 polarity &= ~mask;
1206 break;
1207 case IRQ_TYPE_LEVEL_HIGH:
5a927501 1208 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1209 level &= ~mask;
1210 polarity |= mask;
1211 break;
1212 case IRQ_TYPE_LEVEL_LOW:
5a927501 1213 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1214 level &= ~mask;
1215 polarity &= ~mask;
1216 break;
1217 default:
7cc5f970 1218 irq_gc_unlock(gc);
d3e51161
HS		 1219 return -EINVAL;
1220 }
1221
1222 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1223 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1224
1225 irq_gc_unlock(gc);
1226
d3e51161
HS		 1227 return 0;
1228}
1229
1230static int rockchip_interrupts_register(struct platform_device *pdev,
1231 struct rockchip_pinctrl *info)
1232{
1233 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1234 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1235 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1236 struct irq_chip_generic *gc;
1237 int ret;
1238 int i;
1239
1240 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1241 if (!bank->valid) {
1242 dev_warn(&pdev->dev, "bank %s is not valid\n",
1243 bank->name);
1244 continue;
1245 }
1246
1247 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1248 &irq_generic_chip_ops, NULL);
1249 if (!bank->domain) {
1250 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1251 bank->name);
1252 continue;
1253 }
1254
1255 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1256 "rockchip_gpio_irq", handle_level_irq,
1257 clr, 0, IRQ_GC_INIT_MASK_CACHE);
1258 if (ret) {
1259 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1260 bank->name);
1261 irq_domain_remove(bank->domain);
1262 continue;
1263 }
1264
1265 gc = irq_get_domain_generic_chip(bank->domain, 0);
1266 gc->reg_base = bank->reg_base;
1267 gc->private = bank;
1268 gc->chip_types[0].regs.mask = GPIO_INTEN;
1269 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1270 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1271 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1272 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1273 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1274 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1275
1276 irq_set_handler_data(bank->irq, bank);
1277 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1278 }
1279
1280 return 0;
1281}
1282
1283static int rockchip_gpiolib_register(struct platform_device *pdev,
1284 struct rockchip_pinctrl *info)
1285{
1286 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1287 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1288 struct gpio_chip *gc;
1289 int ret;
1290 int i;
1291
1292 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1293 if (!bank->valid) {
1294 dev_warn(&pdev->dev, "bank %s is not valid\n",
1295 bank->name);
1296 continue;
1297 }
1298
1299 bank->gpio_chip = rockchip_gpiolib_chip;
1300
1301 gc = &bank->gpio_chip;
1302 gc->base = bank->pin_base;
1303 gc->ngpio = bank->nr_pins;
1304 gc->dev = &pdev->dev;
1305 gc->of_node = bank->of_node;
1306 gc->label = bank->name;
1307
1308 ret = gpiochip_add(gc);
1309 if (ret) {
1310 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1311 gc->label, ret);
1312 goto fail;
1313 }
1314 }
1315
1316 rockchip_interrupts_register(pdev, info);
1317
1318 return 0;
1319
1320fail:
1321 for (--i, --bank; i >= 0; --i, --bank) {
1322 if (!bank->valid)
1323 continue;
1324
1325 if (gpiochip_remove(&bank->gpio_chip))
1326 dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1327 bank->gpio_chip.label);
1328 }
1329 return ret;
1330}
1331
1332static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1333 struct rockchip_pinctrl *info)
1334{
1335 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1336 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1337 int ret = 0;
1338 int i;
1339
1340 for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1341 if (!bank->valid)
1342 continue;
1343
1344 ret = gpiochip_remove(&bank->gpio_chip);
1345 }
1346
1347 if (ret)
1348 dev_err(&pdev->dev, "gpio chip remove failed\n");
1349
1350 return ret;
1351}
1352
1353static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1354 struct device *dev)
1355{
1356 struct resource res;
1357
1358 if (of_address_to_resource(bank->of_node, 0, &res)) {
1359 dev_err(dev, "cannot find IO resource for bank\n");
1360 return -ENOENT;
1361 }
1362
1363 bank->reg_base = devm_ioremap_resource(dev, &res);
1364 if (IS_ERR(bank->reg_base))
1365 return PTR_ERR(bank->reg_base);
1366
6ca5274d
HS		 1367 /*
1368 * special case, where parts of the pull setting-registers are
1369 * part of the PMU register space
1370 */
1371 if (of_device_is_compatible(bank->of_node,
1372 "rockchip,rk3188-gpio-bank0")) {
1373 bank->bank_type = RK3188_BANK0;
1374
1375 if (of_address_to_resource(bank->of_node, 1, &res)) {
1376 dev_err(dev, "cannot find IO resource for bank\n");
1377 return -ENOENT;
1378 }
1379
1380 bank->reg_pull = devm_ioremap_resource(dev, &res);
1381 if (IS_ERR(bank->reg_pull))
1382 return PTR_ERR(bank->reg_pull);
1383 } else {
1384 bank->bank_type = COMMON_BANK;
1385 }
65fca613 1386
d3e51161
HS		 1387 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1388
1389 bank->clk = of_clk_get(bank->of_node, 0);
1390 if (IS_ERR(bank->clk))
1391 return PTR_ERR(bank->clk);
1392
1393 return clk_prepare_enable(bank->clk);
1394}
1395
1396static const struct of_device_id rockchip_pinctrl_dt_match[];
1397
1398/* retrieve the soc specific data */
1399static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1400 struct rockchip_pinctrl *d,
1401 struct platform_device *pdev)
1402{
1403 const struct of_device_id *match;
1404 struct device_node *node = pdev->dev.of_node;
1405 struct device_node *np;
1406 struct rockchip_pin_ctrl *ctrl;
1407 struct rockchip_pin_bank *bank;
1408 int i;
1409
1410 match = of_match_node(rockchip_pinctrl_dt_match, node);
1411 ctrl = (struct rockchip_pin_ctrl *)match->data;
1412
1413 for_each_child_of_node(node, np) {
1414 if (!of_find_property(np, "gpio-controller", NULL))
1415 continue;
1416
1417 bank = ctrl->pin_banks;
1418 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1419 if (!strcmp(bank->name, np->name)) {
1420 bank->of_node = np;
1421
1422 if (!rockchip_get_bank_data(bank, &pdev->dev))
1423 bank->valid = true;
1424
1425 break;
1426 }
1427 }
1428 }
1429
1430 bank = ctrl->pin_banks;
1431 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1432 spin_lock_init(&bank->slock);
1433 bank->drvdata = d;
1434 bank->pin_base = ctrl->nr_pins;
1435 ctrl->nr_pins += bank->nr_pins;
1436 }
1437
1438 return ctrl;
1439}
1440
1441static int rockchip_pinctrl_probe(struct platform_device *pdev)
1442{
1443 struct rockchip_pinctrl *info;
1444 struct device *dev = &pdev->dev;
1445 struct rockchip_pin_ctrl *ctrl;
1446 struct resource *res;
1447 int ret;
1448
1449 if (!dev->of_node) {
1450 dev_err(dev, "device tree node not found\n");
1451 return -ENODEV;
1452 }
1453
1454 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1455 if (!info)
1456 return -ENOMEM;
1457
1458 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1459 if (!ctrl) {
1460 dev_err(dev, "driver data not available\n");
1461 return -EINVAL;
1462 }
1463 info->ctrl = ctrl;
1464 info->dev = dev;
1465
1466 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d3e51161
HS		 1467 info->reg_base = devm_ioremap_resource(&pdev->dev, res);
1468 if (IS_ERR(info->reg_base))
1469 return PTR_ERR(info->reg_base);
1470
6ca5274d
HS		 1471 /* The RK3188 has its pull registers in a separate place */
1472 if (ctrl->type == RK3188) {
1473 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1474 info->reg_pull = devm_ioremap_resource(&pdev->dev, res);
38d321c8
DC		 1475 if (IS_ERR(info->reg_pull))
1476 return PTR_ERR(info->reg_pull);
6ca5274d
HS		 1477 }
1478
d3e51161
HS		 1479 ret = rockchip_gpiolib_register(pdev, info);
1480 if (ret)
1481 return ret;
1482
1483 ret = rockchip_pinctrl_register(pdev, info);
1484 if (ret) {
1485 rockchip_gpiolib_unregister(pdev, info);
1486 return ret;
1487 }
1488
1489 platform_set_drvdata(pdev, info);
1490
1491 return 0;
1492}
1493
1494static struct rockchip_pin_bank rk2928_pin_banks[] = {
1495 PIN_BANK(0, 32, "gpio0"),
1496 PIN_BANK(1, 32, "gpio1"),
1497 PIN_BANK(2, 32, "gpio2"),
1498 PIN_BANK(3, 32, "gpio3"),
1499};
1500
1501static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1502 .pin_banks = rk2928_pin_banks,
1503 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
1504 .label = "RK2928-GPIO",
a282926d 1505 .type = RK2928,
d3e51161 1506 .mux_offset = 0xa8,
a282926d 1507 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
d3e51161
HS		 1508};
1509
1510static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1511 PIN_BANK(0, 32, "gpio0"),
1512 PIN_BANK(1, 32, "gpio1"),
1513 PIN_BANK(2, 32, "gpio2"),
1514 PIN_BANK(3, 32, "gpio3"),
1515 PIN_BANK(4, 32, "gpio4"),
1516 PIN_BANK(6, 16, "gpio6"),
1517};
1518
1519static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1520 .pin_banks = rk3066a_pin_banks,
1521 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
1522 .label = "RK3066a-GPIO",
a282926d 1523 .type = RK2928,
d3e51161 1524 .mux_offset = 0xa8,
a282926d 1525 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
d3e51161
HS		 1526};
1527
1528static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1529 PIN_BANK(0, 32, "gpio0"),
1530 PIN_BANK(1, 32, "gpio1"),
1531 PIN_BANK(2, 32, "gpio2"),
1532 PIN_BANK(3, 32, "gpio3"),
1533};
1534
1535static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1536 .pin_banks = rk3066b_pin_banks,
1537 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
1538 .label = "RK3066b-GPIO",
a282926d 1539 .type = RK3066B,
d3e51161 1540 .mux_offset = 0x60,
d3e51161
HS		 1541};
1542
1543static struct rockchip_pin_bank rk3188_pin_banks[] = {
1544 PIN_BANK(0, 32, "gpio0"),
1545 PIN_BANK(1, 32, "gpio1"),
1546 PIN_BANK(2, 32, "gpio2"),
1547 PIN_BANK(3, 32, "gpio3"),
1548};
1549
1550static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1551 .pin_banks = rk3188_pin_banks,
1552 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
1553 .label = "RK3188-GPIO",
a282926d 1554 .type = RK3188,
22c0d7e3 1555 .mux_offset = 0x60,
6ca5274d 1556 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
d3e51161
HS		 1557};
1558
1559static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1560 { .compatible = "rockchip,rk2928-pinctrl",
1561 .data = (void *)&rk2928_pin_ctrl },
1562 { .compatible = "rockchip,rk3066a-pinctrl",
1563 .data = (void *)&rk3066a_pin_ctrl },
1564 { .compatible = "rockchip,rk3066b-pinctrl",
1565 .data = (void *)&rk3066b_pin_ctrl },
1566 { .compatible = "rockchip,rk3188-pinctrl",
1567 .data = (void *)&rk3188_pin_ctrl },
1568 {},
1569};
1570MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1571
1572static struct platform_driver rockchip_pinctrl_driver = {
1573 .probe = rockchip_pinctrl_probe,
1574 .driver = {
1575 .name = "rockchip-pinctrl",
1576 .owner = THIS_MODULE,
0be9e70d 1577 .of_match_table = rockchip_pinctrl_dt_match,
d3e51161
HS		 1578 },
1579};
1580
1581static int __init rockchip_pinctrl_drv_register(void)
1582{
1583 return platform_driver_register(&rockchip_pinctrl_driver);
1584}
1585postcore_initcall(rockchip_pinctrl_drv_register);
1586
1587MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1588MODULE_DESCRIPTION("Rockchip pinctrl driver");
1589MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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