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pinctrl: rockchip: implement PIN_CONFIG_OUTPUT handling
[deliverable/linux.git] / drivers / pinctrl / pinctrl-rockchip.c
CommitLineData
d3e51161
HS		 1/*
2 * Pinctrl driver for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
12 *
13 * and pinctrl-at91:
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 */
25
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/io.h>
29#include <linux/bitops.h>
30#include <linux/gpio.h>
31#include <linux/of_address.h>
32#include <linux/of_irq.h>
33#include <linux/pinctrl/machine.h>
34#include <linux/pinctrl/pinconf.h>
35#include <linux/pinctrl/pinctrl.h>
36#include <linux/pinctrl/pinmux.h>
37#include <linux/pinctrl/pinconf-generic.h>
38#include <linux/irqchip/chained_irq.h>
7e865abb 39#include <linux/clk.h>
d3e51161
HS		 40#include <dt-bindings/pinctrl/rockchip.h>
41
42#include "core.h"
43#include "pinconf.h"
44
45/* GPIO control registers */
46#define GPIO_SWPORT_DR 0x00
47#define GPIO_SWPORT_DDR 0x04
48#define GPIO_INTEN 0x30
49#define GPIO_INTMASK 0x34
50#define GPIO_INTTYPE_LEVEL 0x38
51#define GPIO_INT_POLARITY 0x3c
52#define GPIO_INT_STATUS 0x40
53#define GPIO_INT_RAWSTATUS 0x44
54#define GPIO_DEBOUNCE 0x48
55#define GPIO_PORTS_EOI 0x4c
56#define GPIO_EXT_PORT 0x50
57#define GPIO_LS_SYNC 0x60
58
a282926d
HS		 59enum rockchip_pinctrl_type {
60 RK2928,
61 RK3066B,
62 RK3188,
63};
64
65fca613
HS		 65enum rockchip_pin_bank_type {
66 COMMON_BANK,
6ca5274d 67 RK3188_BANK0,
65fca613
HS		 68};
69
d3e51161
HS		 70/**
71 * @reg_base: register base of the gpio bank
6ca5274d 72 * @reg_pull: optional separate register for additional pull settings
d3e51161
HS		 73 * @clk: clock of the gpio bank
74 * @irq: interrupt of the gpio bank
75 * @pin_base: first pin number
76 * @nr_pins: number of pins in this bank
77 * @name: name of the bank
78 * @bank_num: number of the bank, to account for holes
79 * @valid: are all necessary informations present
80 * @of_node: dt node of this bank
81 * @drvdata: common pinctrl basedata
82 * @domain: irqdomain of the gpio bank
83 * @gpio_chip: gpiolib chip
84 * @grange: gpio range
85 * @slock: spinlock for the gpio bank
86 */
87struct rockchip_pin_bank {
88 void __iomem *reg_base;
6ca5274d 89 void __iomem *reg_pull;
d3e51161
HS		 90 struct clk *clk;
91 int irq;
92 u32 pin_base;
93 u8 nr_pins;
94 char *name;
95 u8 bank_num;
65fca613 96 enum rockchip_pin_bank_type bank_type;
d3e51161
HS		 97 bool valid;
98 struct device_node *of_node;
99 struct rockchip_pinctrl *drvdata;
100 struct irq_domain *domain;
101 struct gpio_chip gpio_chip;
102 struct pinctrl_gpio_range grange;
103 spinlock_t slock;
5a927501 104 u32 toggle_edge_mode;
d3e51161
HS		 105};
106
107#define PIN_BANK(id, pins, label) \
108 { \
109 .bank_num = id, \
110 .nr_pins = pins, \
111 .name = label, \
112 }
113
114/**
d3e51161
HS		 115 */
116struct rockchip_pin_ctrl {
117 struct rockchip_pin_bank *pin_banks;
118 u32 nr_banks;
119 u32 nr_pins;
120 char *label;
a282926d 121 enum rockchip_pinctrl_type type;
d3e51161 122 int mux_offset;
a282926d
HS		 123 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num,
124 void __iomem **reg, u8 *bit);
d3e51161
HS		 125};
126
127struct rockchip_pin_config {
128 unsigned int func;
129 unsigned long *configs;
130 unsigned int nconfigs;
131};
132
133/**
134 * struct rockchip_pin_group: represent group of pins of a pinmux function.
135 * @name: name of the pin group, used to lookup the group.
136 * @pins: the pins included in this group.
137 * @npins: number of pins included in this group.
138 * @func: the mux function number to be programmed when selected.
139 * @configs: the config values to be set for each pin
140 * @nconfigs: number of configs for each pin
141 */
142struct rockchip_pin_group {
143 const char *name;
144 unsigned int npins;
145 unsigned int *pins;
146 struct rockchip_pin_config *data;
147};
148
149/**
150 * struct rockchip_pmx_func: represent a pin function.
151 * @name: name of the pin function, used to lookup the function.
152 * @groups: one or more names of pin groups that provide this function.
153 * @num_groups: number of groups included in @groups.
154 */
155struct rockchip_pmx_func {
156 const char *name;
157 const char **groups;
158 u8 ngroups;
159};
160
161struct rockchip_pinctrl {
162 void __iomem *reg_base;
6ca5274d 163 void __iomem *reg_pull;
d3e51161
HS		 164 struct device *dev;
165 struct rockchip_pin_ctrl *ctrl;
166 struct pinctrl_desc pctl;
167 struct pinctrl_dev *pctl_dev;
168 struct rockchip_pin_group *groups;
169 unsigned int ngroups;
170 struct rockchip_pmx_func *functions;
171 unsigned int nfunctions;
172};
173
174static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
175{
176 return container_of(gc, struct rockchip_pin_bank, gpio_chip);
177}
178
179static const inline struct rockchip_pin_group *pinctrl_name_to_group(
180 const struct rockchip_pinctrl *info,
181 const char *name)
182{
d3e51161
HS		 183 int i;
184
185 for (i = 0; i < info->ngroups; i++) {
1cb95395
AL		 186 if (!strcmp(info->groups[i].name, name))
187 return &info->groups[i];
d3e51161
HS		 188 }
189
1cb95395 190 return NULL;
d3e51161
HS		 191}
192
193/*
194 * given a pin number that is local to a pin controller, find out the pin bank
195 * and the register base of the pin bank.
196 */
197static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
198 unsigned pin)
199{
200 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
201
51578b9b 202 while (pin >= (b->pin_base + b->nr_pins))
d3e51161
HS		 203 b++;
204
205 return b;
206}
207
208static struct rockchip_pin_bank *bank_num_to_bank(
209 struct rockchip_pinctrl *info,
210 unsigned num)
211{
212 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
213 int i;
214
1cb95395 215 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
d3e51161 216 if (b->bank_num == num)
1cb95395 217 return b;
d3e51161
HS		 218 }
219
1cb95395 220 return ERR_PTR(-EINVAL);
d3e51161
HS		 221}
222
223/*
224 * Pinctrl_ops handling
225 */
226
227static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
228{
229 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
230
231 return info->ngroups;
232}
233
234static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
235 unsigned selector)
236{
237 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
238
239 return info->groups[selector].name;
240}
241
242static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
243 unsigned selector, const unsigned **pins,
244 unsigned *npins)
245{
246 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
247
248 if (selector >= info->ngroups)
249 return -EINVAL;
250
251 *pins = info->groups[selector].pins;
252 *npins = info->groups[selector].npins;
253
254 return 0;
255}
256
257static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
258 struct device_node *np,
259 struct pinctrl_map **map, unsigned *num_maps)
260{
261 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
262 const struct rockchip_pin_group *grp;
263 struct pinctrl_map *new_map;
264 struct device_node *parent;
265 int map_num = 1;
266 int i;
267
268 /*
269 * first find the group of this node and check if we need to create
270 * config maps for pins
271 */
272 grp = pinctrl_name_to_group(info, np->name);
273 if (!grp) {
274 dev_err(info->dev, "unable to find group for node %s\n",
275 np->name);
276 return -EINVAL;
277 }
278
279 map_num += grp->npins;
280 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
281 GFP_KERNEL);
282 if (!new_map)
283 return -ENOMEM;
284
285 *map = new_map;
286 *num_maps = map_num;
287
288 /* create mux map */
289 parent = of_get_parent(np);
290 if (!parent) {
291 devm_kfree(pctldev->dev, new_map);
292 return -EINVAL;
293 }
294 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
295 new_map[0].data.mux.function = parent->name;
296 new_map[0].data.mux.group = np->name;
297 of_node_put(parent);
298
299 /* create config map */
300 new_map++;
301 for (i = 0; i < grp->npins; i++) {
302 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
303 new_map[i].data.configs.group_or_pin =
304 pin_get_name(pctldev, grp->pins[i]);
305 new_map[i].data.configs.configs = grp->data[i].configs;
306 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
307 }
308
309 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
310 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
311
312 return 0;
313}
314
315static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
316 struct pinctrl_map *map, unsigned num_maps)
317{
318}
319
320static const struct pinctrl_ops rockchip_pctrl_ops = {
321 .get_groups_count = rockchip_get_groups_count,
322 .get_group_name = rockchip_get_group_name,
323 .get_group_pins = rockchip_get_group_pins,
324 .dt_node_to_map = rockchip_dt_node_to_map,
325 .dt_free_map = rockchip_dt_free_map,
326};
327
328/*
329 * Hardware access
330 */
331
a076e2ed
HS		 332static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
333{
334 struct rockchip_pinctrl *info = bank->drvdata;
335 void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
336 u8 bit;
337
338 if (bank->bank_type == RK3188_BANK0 && pin < 16)
339 return RK_FUNC_GPIO;
340
341 /* get basic quadrupel of mux registers and the correct reg inside */
342 reg += bank->bank_num * 0x10;
343 reg += (pin / 8) * 4;
344 bit = (pin % 8) * 2;
345
346 return ((readl(reg) >> bit) & 3);
347}
348
d3e51161
HS		 349/*
350 * Set a new mux function for a pin.
351 *
352 * The register is divided into the upper and lower 16 bit. When changing
353 * a value, the previous register value is not read and changed. Instead
354 * it seems the changed bits are marked in the upper 16 bit, while the
355 * changed value gets set in the same offset in the lower 16 bit.
356 * All pin settings seem to be 2 bit wide in both the upper and lower
357 * parts.
358 * @bank: pin bank to change
359 * @pin: pin to change
360 * @mux: new mux function to set
361 */
14797189 362static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
d3e51161
HS		 363{
364 struct rockchip_pinctrl *info = bank->drvdata;
365 void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
366 unsigned long flags;
367 u8 bit;
368 u32 data;
369
c4a532de
HS		 370 /*
371 * The first 16 pins of rk3188_bank0 are always gpios and do not have
372 * a mux register at all.
373 */
374 if (bank->bank_type == RK3188_BANK0 && pin < 16) {
375 if (mux != RK_FUNC_GPIO) {
376 dev_err(info->dev,
377 "pin %d only supports a gpio mux\n", pin);
378 return -ENOTSUPP;
379 } else {
380 return 0;
381 }
382 }
383
d3e51161
HS		 384 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
385 bank->bank_num, pin, mux);
386
387 /* get basic quadrupel of mux registers and the correct reg inside */
388 reg += bank->bank_num * 0x10;
389 reg += (pin / 8) * 4;
390 bit = (pin % 8) * 2;
391
392 spin_lock_irqsave(&bank->slock, flags);
393
394 data = (3 << (bit + 16));
395 data |= (mux & 3) << bit;
396 writel(data, reg);
397
398 spin_unlock_irqrestore(&bank->slock, flags);
14797189
HS		 399
400 return 0;
d3e51161
HS		 401}
402
a282926d
HS		 403#define RK2928_PULL_OFFSET 0x118
404#define RK2928_PULL_PINS_PER_REG 16
405#define RK2928_PULL_BANK_STRIDE 8
406
407static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
408 int pin_num, void __iomem **reg, u8 *bit)
409{
410 struct rockchip_pinctrl *info = bank->drvdata;
411
412 *reg = info->reg_base + RK2928_PULL_OFFSET;
413 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
414 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
415
416 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
417};
418
6ca5274d
HS		 419#define RK3188_PULL_BITS_PER_PIN 2
420#define RK3188_PULL_PINS_PER_REG 8
421#define RK3188_PULL_BANK_STRIDE 16
422
423static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
424 int pin_num, void __iomem **reg, u8 *bit)
425{
426 struct rockchip_pinctrl *info = bank->drvdata;
427
428 /* The first 12 pins of the first bank are located elsewhere */
429 if (bank->bank_type == RK3188_BANK0 && pin_num < 12) {
430 *reg = bank->reg_pull +
431 ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
432 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
433 *bit *= RK3188_PULL_BITS_PER_PIN;
434 } else {
435 *reg = info->reg_pull - 4;
436 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
437 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
438
439 /*
440 * The bits in these registers have an inverse ordering
441 * with the lowest pin being in bits 15:14 and the highest
442 * pin in bits 1:0
443 */
444 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
445 *bit *= RK3188_PULL_BITS_PER_PIN;
446 }
447}
448
d3e51161
HS		 449static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
450{
451 struct rockchip_pinctrl *info = bank->drvdata;
452 struct rockchip_pin_ctrl *ctrl = info->ctrl;
453 void __iomem *reg;
454 u8 bit;
6ca5274d 455 u32 data;
d3e51161
HS		 456
457 /* rk3066b does support any pulls */
a282926d 458 if (ctrl->type == RK3066B)
d3e51161
HS		 459 return PIN_CONFIG_BIAS_DISABLE;
460
6ca5274d
HS		 461 ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
462
a282926d
HS		 463 switch (ctrl->type) {
464 case RK2928:
d3e51161
HS		 465 return !(readl_relaxed(reg) & BIT(bit))
466 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
467 : PIN_CONFIG_BIAS_DISABLE;
a282926d 468 case RK3188:
6ca5274d
HS		 469 data = readl_relaxed(reg) >> bit;
470 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
471
472 switch (data) {
473 case 0:
474 return PIN_CONFIG_BIAS_DISABLE;
475 case 1:
476 return PIN_CONFIG_BIAS_PULL_UP;
477 case 2:
478 return PIN_CONFIG_BIAS_PULL_DOWN;
479 case 3:
480 return PIN_CONFIG_BIAS_BUS_HOLD;
481 }
482
483 dev_err(info->dev, "unknown pull setting\n");
d3e51161 484 return -EIO;
a282926d
HS		 485 default:
486 dev_err(info->dev, "unsupported pinctrl type\n");
487 return -EINVAL;
488 };
d3e51161
HS		 489}
490
491static int rockchip_set_pull(struct rockchip_pin_bank *bank,
492 int pin_num, int pull)
493{
494 struct rockchip_pinctrl *info = bank->drvdata;
495 struct rockchip_pin_ctrl *ctrl = info->ctrl;
496 void __iomem *reg;
497 unsigned long flags;
498 u8 bit;
499 u32 data;
500
501 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
502 bank->bank_num, pin_num, pull);
503
504 /* rk3066b does support any pulls */
a282926d 505 if (ctrl->type == RK3066B)
d3e51161
HS		 506 return pull ? -EINVAL : 0;
507
6ca5274d
HS		 508 ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
509
a282926d
HS		 510 switch (ctrl->type) {
511 case RK2928:
d3e51161
HS		 512 spin_lock_irqsave(&bank->slock, flags);
513
514 data = BIT(bit + 16);
515 if (pull == PIN_CONFIG_BIAS_DISABLE)
516 data |= BIT(bit);
517 writel(data, reg);
518
519 spin_unlock_irqrestore(&bank->slock, flags);
a282926d
HS		 520 break;
521 case RK3188:
6ca5274d
HS		 522 spin_lock_irqsave(&bank->slock, flags);
523
524 /* enable the write to the equivalent lower bits */
525 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
526
527 switch (pull) {
528 case PIN_CONFIG_BIAS_DISABLE:
529 break;
530 case PIN_CONFIG_BIAS_PULL_UP:
531 data |= (1 << bit);
532 break;
533 case PIN_CONFIG_BIAS_PULL_DOWN:
534 data |= (2 << bit);
535 break;
536 case PIN_CONFIG_BIAS_BUS_HOLD:
537 data |= (3 << bit);
538 break;
539 default:
d32c3e26 540 spin_unlock_irqrestore(&bank->slock, flags);
6ca5274d
HS		 541 dev_err(info->dev, "unsupported pull setting %d\n",
542 pull);
543 return -EINVAL;
544 }
545
546 writel(data, reg);
547
548 spin_unlock_irqrestore(&bank->slock, flags);
549 break;
a282926d
HS		 550 default:
551 dev_err(info->dev, "unsupported pinctrl type\n");
552 return -EINVAL;
d3e51161
HS		 553 }
554
555 return 0;
556}
557
558/*
559 * Pinmux_ops handling
560 */
561
562static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
563{
564 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
565
566 return info->nfunctions;
567}
568
569static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
570 unsigned selector)
571{
572 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
573
574 return info->functions[selector].name;
575}
576
577static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
578 unsigned selector, const char * const **groups,
579 unsigned * const num_groups)
580{
581 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
582
583 *groups = info->functions[selector].groups;
584 *num_groups = info->functions[selector].ngroups;
585
586 return 0;
587}
588
589static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
590 unsigned group)
591{
592 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
593 const unsigned int *pins = info->groups[group].pins;
594 const struct rockchip_pin_config *data = info->groups[group].data;
595 struct rockchip_pin_bank *bank;
14797189 596 int cnt, ret = 0;
d3e51161
HS		 597
598 dev_dbg(info->dev, "enable function %s group %s\n",
599 info->functions[selector].name, info->groups[group].name);
600
601 /*
602 * for each pin in the pin group selected, program the correspoding pin
603 * pin function number in the config register.
604 */
605 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
606 bank = pin_to_bank(info, pins[cnt]);
14797189
HS		 607 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
608 data[cnt].func);
609 if (ret)
610 break;
611 }
612
613 if (ret) {
614 /* revert the already done pin settings */
615 for (cnt--; cnt >= 0; cnt--)
616 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
617
618 return ret;
d3e51161
HS		 619 }
620
621 return 0;
622}
623
624static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
625 unsigned selector, unsigned group)
626{
627 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
628 const unsigned int *pins = info->groups[group].pins;
629 struct rockchip_pin_bank *bank;
630 int cnt;
631
632 dev_dbg(info->dev, "disable function %s group %s\n",
633 info->functions[selector].name, info->groups[group].name);
634
635 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
636 bank = pin_to_bank(info, pins[cnt]);
637 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
638 }
639}
640
641/*
642 * The calls to gpio_direction_output() and gpio_direction_input()
643 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
644 * function called from the gpiolib interface).
645 */
646static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
647 struct pinctrl_gpio_range *range,
648 unsigned offset, bool input)
649{
650 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
651 struct rockchip_pin_bank *bank;
652 struct gpio_chip *chip;
14797189 653 int pin, ret;
d3e51161
HS		 654 u32 data;
655
656 chip = range->gc;
657 bank = gc_to_pin_bank(chip);
658 pin = offset - chip->base;
659
660 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
661 offset, range->name, pin, input ? "input" : "output");
662
14797189
HS		 663 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
664 if (ret < 0)
665 return ret;
d3e51161
HS		 666
667 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
668 /* set bit to 1 for output, 0 for input */
669 if (!input)
670 data |= BIT(pin);
671 else
672 data &= ~BIT(pin);
673 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
674
675 return 0;
676}
677
678static const struct pinmux_ops rockchip_pmx_ops = {
679 .get_functions_count = rockchip_pmx_get_funcs_count,
680 .get_function_name = rockchip_pmx_get_func_name,
681 .get_function_groups = rockchip_pmx_get_groups,
682 .enable = rockchip_pmx_enable,
683 .disable = rockchip_pmx_disable,
684 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
685};
686
687/*
688 * Pinconf_ops handling
689 */
690
44b6d930
HS		 691static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
692 enum pin_config_param pull)
693{
a282926d
HS		 694 switch (ctrl->type) {
695 case RK2928:
696 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
697 pull == PIN_CONFIG_BIAS_DISABLE);
698 case RK3066B:
44b6d930 699 return pull ? false : true;
a282926d
HS		 700 case RK3188:
701 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
44b6d930
HS		 702 }
703
a282926d 704 return false;
44b6d930
HS		 705}
706
a076e2ed
HS		 707static int rockchip_gpio_direction_output(struct gpio_chip *gc,
708 unsigned offset, int value);
709static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
710
d3e51161
HS		 711/* set the pin config settings for a specified pin */
712static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
03b054e9 713 unsigned long *configs, unsigned num_configs)
d3e51161
HS		 714{
715 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
716 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
03b054e9
SY		 717 enum pin_config_param param;
718 u16 arg;
719 int i;
720 int rc;
721
722 for (i = 0; i < num_configs; i++) {
723 param = pinconf_to_config_param(configs[i]);
724 arg = pinconf_to_config_argument(configs[i]);
725
726 switch (param) {
727 case PIN_CONFIG_BIAS_DISABLE:
728 rc = rockchip_set_pull(bank, pin - bank->pin_base,
729 param);
730 if (rc)
731 return rc;
732 break;
733 case PIN_CONFIG_BIAS_PULL_UP:
734 case PIN_CONFIG_BIAS_PULL_DOWN:
735 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
6ca5274d 736 case PIN_CONFIG_BIAS_BUS_HOLD:
03b054e9
SY		 737 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
738 return -ENOTSUPP;
739
740 if (!arg)
741 return -EINVAL;
742
743 rc = rockchip_set_pull(bank, pin - bank->pin_base,
744 param);
745 if (rc)
746 return rc;
747 break;
a076e2ed
HS		 748 case PIN_CONFIG_OUTPUT:
749 rc = rockchip_gpio_direction_output(&bank->gpio_chip,
750 pin - bank->pin_base,
751 arg);
752 if (rc)
753 return rc;
754 break;
03b054e9 755 default:
44b6d930 756 return -ENOTSUPP;
03b054e9
SY		 757 break;
758 }
759 } /* for each config */
d3e51161
HS		 760
761 return 0;
762}
763
764/* get the pin config settings for a specified pin */
765static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
766 unsigned long *config)
767{
768 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
769 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
770 enum pin_config_param param = pinconf_to_config_param(*config);
dab3eba7 771 u16 arg;
a076e2ed 772 int rc;
d3e51161
HS		 773
774 switch (param) {
775 case PIN_CONFIG_BIAS_DISABLE:
44b6d930
HS		 776 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
777 return -EINVAL;
778
dab3eba7 779 arg = 0;
44b6d930 780 break;
d3e51161
HS		 781 case PIN_CONFIG_BIAS_PULL_UP:
782 case PIN_CONFIG_BIAS_PULL_DOWN:
783 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
6ca5274d 784 case PIN_CONFIG_BIAS_BUS_HOLD:
44b6d930
HS		 785 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
786 return -ENOTSUPP;
d3e51161 787
44b6d930 788 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
d3e51161
HS		 789 return -EINVAL;
790
dab3eba7 791 arg = 1;
d3e51161 792 break;
a076e2ed
HS		 793 case PIN_CONFIG_OUTPUT:
794 rc = rockchip_get_mux(bank, pin - bank->pin_base);
795 if (rc != RK_FUNC_GPIO)
796 return -EINVAL;
797
798 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
799 if (rc < 0)
800 return rc;
801
802 arg = rc ? 1 : 0;
803 break;
d3e51161
HS		 804 default:
805 return -ENOTSUPP;
806 break;
807 }
808
dab3eba7
HS		 809 *config = pinconf_to_config_packed(param, arg);
810
d3e51161
HS		 811 return 0;
812}
813
814static const struct pinconf_ops rockchip_pinconf_ops = {
815 .pin_config_get = rockchip_pinconf_get,
816 .pin_config_set = rockchip_pinconf_set,
817};
818
65fca613
HS		 819static const struct of_device_id rockchip_bank_match[] = {
820 { .compatible = "rockchip,gpio-bank" },
6ca5274d 821 { .compatible = "rockchip,rk3188-gpio-bank0" },
65fca613
HS		 822 {},
823};
d3e51161
HS		 824
825static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
826 struct device_node *np)
827{
828 struct device_node *child;
829
830 for_each_child_of_node(np, child) {
65fca613 831 if (of_match_node(rockchip_bank_match, child))
d3e51161
HS		 832 continue;
833
834 info->nfunctions++;
835 info->ngroups += of_get_child_count(child);
836 }
837}
838
839static int rockchip_pinctrl_parse_groups(struct device_node *np,
840 struct rockchip_pin_group *grp,
841 struct rockchip_pinctrl *info,
842 u32 index)
843{
844 struct rockchip_pin_bank *bank;
845 int size;
846 const __be32 *list;
847 int num;
848 int i, j;
849 int ret;
850
851 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
852
853 /* Initialise group */
854 grp->name = np->name;
855
856 /*
857 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
858 * do sanity check and calculate pins number
859 */
860 list = of_get_property(np, "rockchip,pins", &size);
861 /* we do not check return since it's safe node passed down */
862 size /= sizeof(*list);
863 if (!size || size % 4) {
864 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
865 return -EINVAL;
866 }
867
868 grp->npins = size / 4;
869
870 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
871 GFP_KERNEL);
872 grp->data = devm_kzalloc(info->dev, grp->npins *
873 sizeof(struct rockchip_pin_config),
874 GFP_KERNEL);
875 if (!grp->pins || !grp->data)
876 return -ENOMEM;
877
878 for (i = 0, j = 0; i < size; i += 4, j++) {
879 const __be32 *phandle;
880 struct device_node *np_config;
881
882 num = be32_to_cpu(*list++);
883 bank = bank_num_to_bank(info, num);
884 if (IS_ERR(bank))
885 return PTR_ERR(bank);
886
887 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
888 grp->data[j].func = be32_to_cpu(*list++);
889
890 phandle = list++;
891 if (!phandle)
892 return -EINVAL;
893
894 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
895 ret = pinconf_generic_parse_dt_config(np_config,
896 &grp->data[j].configs, &grp->data[j].nconfigs);
897 if (ret)
898 return ret;
899 }
900
901 return 0;
902}
903
904static int rockchip_pinctrl_parse_functions(struct device_node *np,
905 struct rockchip_pinctrl *info,
906 u32 index)
907{
908 struct device_node *child;
909 struct rockchip_pmx_func *func;
910 struct rockchip_pin_group *grp;
911 int ret;
912 static u32 grp_index;
913 u32 i = 0;
914
915 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
916
917 func = &info->functions[index];
918
919 /* Initialise function */
920 func->name = np->name;
921 func->ngroups = of_get_child_count(np);
922 if (func->ngroups <= 0)
923 return 0;
924
925 func->groups = devm_kzalloc(info->dev,
926 func->ngroups * sizeof(char *), GFP_KERNEL);
927 if (!func->groups)
928 return -ENOMEM;
929
930 for_each_child_of_node(np, child) {
931 func->groups[i] = child->name;
932 grp = &info->groups[grp_index++];
933 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
934 if (ret)
935 return ret;
936 }
937
938 return 0;
939}
940
941static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
942 struct rockchip_pinctrl *info)
943{
944 struct device *dev = &pdev->dev;
945 struct device_node *np = dev->of_node;
946 struct device_node *child;
947 int ret;
948 int i;
949
950 rockchip_pinctrl_child_count(info, np);
951
952 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
953 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
954
955 info->functions = devm_kzalloc(dev, info->nfunctions *
956 sizeof(struct rockchip_pmx_func),
957 GFP_KERNEL);
958 if (!info->functions) {
959 dev_err(dev, "failed to allocate memory for function list\n");
960 return -EINVAL;
961 }
962
963 info->groups = devm_kzalloc(dev, info->ngroups *
964 sizeof(struct rockchip_pin_group),
965 GFP_KERNEL);
966 if (!info->groups) {
967 dev_err(dev, "failed allocate memory for ping group list\n");
968 return -EINVAL;
969 }
970
971 i = 0;
972
973 for_each_child_of_node(np, child) {
65fca613 974 if (of_match_node(rockchip_bank_match, child))
d3e51161 975 continue;
65fca613 976
d3e51161
HS		 977 ret = rockchip_pinctrl_parse_functions(child, info, i++);
978 if (ret) {
979 dev_err(&pdev->dev, "failed to parse function\n");
980 return ret;
981 }
982 }
983
984 return 0;
985}
986
987static int rockchip_pinctrl_register(struct platform_device *pdev,
988 struct rockchip_pinctrl *info)
989{
990 struct pinctrl_desc *ctrldesc = &info->pctl;
991 struct pinctrl_pin_desc *pindesc, *pdesc;
992 struct rockchip_pin_bank *pin_bank;
993 int pin, bank, ret;
994 int k;
995
996 ctrldesc->name = "rockchip-pinctrl";
997 ctrldesc->owner = THIS_MODULE;
998 ctrldesc->pctlops = &rockchip_pctrl_ops;
999 ctrldesc->pmxops = &rockchip_pmx_ops;
1000 ctrldesc->confops = &rockchip_pinconf_ops;
1001
1002 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1003 info->ctrl->nr_pins, GFP_KERNEL);
1004 if (!pindesc) {
1005 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1006 return -ENOMEM;
1007 }
1008 ctrldesc->pins = pindesc;
1009 ctrldesc->npins = info->ctrl->nr_pins;
1010
1011 pdesc = pindesc;
1012 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1013 pin_bank = &info->ctrl->pin_banks[bank];
1014 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1015 pdesc->number = k;
1016 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1017 pin_bank->name, pin);
1018 pdesc++;
1019 }
1020 }
1021
1022 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
1023 if (!info->pctl_dev) {
1024 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1025 return -EINVAL;
1026 }
1027
1028 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1029 pin_bank = &info->ctrl->pin_banks[bank];
1030 pin_bank->grange.name = pin_bank->name;
1031 pin_bank->grange.id = bank;
1032 pin_bank->grange.pin_base = pin_bank->pin_base;
1033 pin_bank->grange.base = pin_bank->gpio_chip.base;
1034 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1035 pin_bank->grange.gc = &pin_bank->gpio_chip;
1036 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1037 }
1038
1039 ret = rockchip_pinctrl_parse_dt(pdev, info);
1040 if (ret) {
1041 pinctrl_unregister(info->pctl_dev);
1042 return ret;
1043 }
1044
1045 return 0;
1046}
1047
1048/*
1049 * GPIO handling
1050 */
1051
0351c287
AL		 1052static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
1053{
1054 return pinctrl_request_gpio(chip->base + offset);
1055}
1056
1057static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
1058{
1059 pinctrl_free_gpio(chip->base + offset);
1060}
1061
d3e51161
HS		 1062static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1063{
1064 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1065 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1066 unsigned long flags;
1067 u32 data;
1068
1069 spin_lock_irqsave(&bank->slock, flags);
1070
1071 data = readl(reg);
1072 data &= ~BIT(offset);
1073 if (value)
1074 data |= BIT(offset);
1075 writel(data, reg);
1076
1077 spin_unlock_irqrestore(&bank->slock, flags);
1078}
1079
1080/*
1081 * Returns the level of the pin for input direction and setting of the DR
1082 * register for output gpios.
1083 */
1084static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1085{
1086 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1087 u32 data;
1088
1089 data = readl(bank->reg_base + GPIO_EXT_PORT);
1090 data >>= offset;
1091 data &= 1;
1092 return data;
1093}
1094
1095/*
1096 * gpiolib gpio_direction_input callback function. The setting of the pin
1097 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1098 * interface.
1099 */
1100static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1101{
1102 return pinctrl_gpio_direction_input(gc->base + offset);
1103}
1104
1105/*
1106 * gpiolib gpio_direction_output callback function. The setting of the pin
1107 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1108 * interface.
1109 */
1110static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1111 unsigned offset, int value)
1112{
1113 rockchip_gpio_set(gc, offset, value);
1114 return pinctrl_gpio_direction_output(gc->base + offset);
1115}
1116
1117/*
1118 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1119 * and a virtual IRQ, if not already present.
1120 */
1121static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1122{
1123 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1124 unsigned int virq;
1125
1126 if (!bank->domain)
1127 return -ENXIO;
1128
1129 virq = irq_create_mapping(bank->domain, offset);
1130
1131 return (virq) ? : -ENXIO;
1132}
1133
1134static const struct gpio_chip rockchip_gpiolib_chip = {
0351c287
AL		 1135 .request = rockchip_gpio_request,
1136 .free = rockchip_gpio_free,
d3e51161
HS		 1137 .set = rockchip_gpio_set,
1138 .get = rockchip_gpio_get,
1139 .direction_input = rockchip_gpio_direction_input,
1140 .direction_output = rockchip_gpio_direction_output,
1141 .to_irq = rockchip_gpio_to_irq,
1142 .owner = THIS_MODULE,
1143};
1144
1145/*
1146 * Interrupt handling
1147 */
1148
1149static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1150{
1151 struct irq_chip *chip = irq_get_chip(irq);
1152 struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
5a927501 1153 u32 polarity = 0, data = 0;
d3e51161 1154 u32 pend;
5a927501 1155 bool edge_changed = false;
d3e51161
HS		 1156
1157 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1158
1159 chained_irq_enter(chip, desc);
1160
1161 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1162
5a927501
HS		 1163 if (bank->toggle_edge_mode) {
1164 polarity = readl_relaxed(bank->reg_base +
1165 GPIO_INT_POLARITY);
1166 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1167 }
1168
d3e51161
HS		 1169 while (pend) {
1170 unsigned int virq;
1171
1172 irq = __ffs(pend);
1173 pend &= ~BIT(irq);
1174 virq = irq_linear_revmap(bank->domain, irq);
1175
1176 if (!virq) {
1177 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1178 continue;
1179 }
1180
1181 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1182
5a927501
HS		 1183 /*
1184 * Triggering IRQ on both rising and falling edge
1185 * needs manual intervention.
1186 */
1187 if (bank->toggle_edge_mode & BIT(irq)) {
1188 if (data & BIT(irq))
1189 polarity &= ~BIT(irq);
1190 else
1191 polarity |= BIT(irq);
1192
1193 edge_changed = true;
1194 }
1195
d3e51161
HS		 1196 generic_handle_irq(virq);
1197 }
1198
5a927501
HS		 1199 if (bank->toggle_edge_mode && edge_changed) {
1200 /* Interrupt params should only be set with ints disabled */
1201 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
1202 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
1203 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
1204 writel(data, bank->reg_base + GPIO_INTEN);
1205 }
1206
d3e51161
HS		 1207 chained_irq_exit(chip, desc);
1208}
1209
1210static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1211{
1212 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1213 struct rockchip_pin_bank *bank = gc->private;
1214 u32 mask = BIT(d->hwirq);
1215 u32 polarity;
1216 u32 level;
1217 u32 data;
14797189 1218 int ret;
d3e51161 1219
5a927501 1220 /* make sure the pin is configured as gpio input */
14797189
HS		 1221 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1222 if (ret < 0)
1223 return ret;
1224
5a927501
HS		 1225 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1226 data &= ~mask;
1227 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1228
d3e51161
HS		 1229 if (type & IRQ_TYPE_EDGE_BOTH)
1230 __irq_set_handler_locked(d->irq, handle_edge_irq);
1231 else
1232 __irq_set_handler_locked(d->irq, handle_level_irq);
1233
1234 irq_gc_lock(gc);
1235
1236 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1237 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1238
1239 switch (type) {
5a927501
HS		 1240 case IRQ_TYPE_EDGE_BOTH:
1241 bank->toggle_edge_mode |= mask;
1242 level |= mask;
1243
1244 /*
1245 * Determine gpio state. If 1 next interrupt should be falling
1246 * otherwise rising.
1247 */
1248 data = readl(bank->reg_base + GPIO_EXT_PORT);
1249 if (data & mask)
1250 polarity &= ~mask;
1251 else
1252 polarity |= mask;
1253 break;
d3e51161 1254 case IRQ_TYPE_EDGE_RISING:
5a927501 1255 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1256 level |= mask;
1257 polarity |= mask;
1258 break;
1259 case IRQ_TYPE_EDGE_FALLING:
5a927501 1260 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1261 level |= mask;
1262 polarity &= ~mask;
1263 break;
1264 case IRQ_TYPE_LEVEL_HIGH:
5a927501 1265 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1266 level &= ~mask;
1267 polarity |= mask;
1268 break;
1269 case IRQ_TYPE_LEVEL_LOW:
5a927501 1270 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1271 level &= ~mask;
1272 polarity &= ~mask;
1273 break;
1274 default:
7cc5f970 1275 irq_gc_unlock(gc);
d3e51161
HS		 1276 return -EINVAL;
1277 }
1278
1279 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1280 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1281
1282 irq_gc_unlock(gc);
1283
d3e51161
HS		 1284 return 0;
1285}
1286
1287static int rockchip_interrupts_register(struct platform_device *pdev,
1288 struct rockchip_pinctrl *info)
1289{
1290 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1291 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1292 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1293 struct irq_chip_generic *gc;
1294 int ret;
1295 int i;
1296
1297 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1298 if (!bank->valid) {
1299 dev_warn(&pdev->dev, "bank %s is not valid\n",
1300 bank->name);
1301 continue;
1302 }
1303
1304 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1305 &irq_generic_chip_ops, NULL);
1306 if (!bank->domain) {
1307 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1308 bank->name);
1309 continue;
1310 }
1311
1312 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1313 "rockchip_gpio_irq", handle_level_irq,
1314 clr, 0, IRQ_GC_INIT_MASK_CACHE);
1315 if (ret) {
1316 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1317 bank->name);
1318 irq_domain_remove(bank->domain);
1319 continue;
1320 }
1321
1322 gc = irq_get_domain_generic_chip(bank->domain, 0);
1323 gc->reg_base = bank->reg_base;
1324 gc->private = bank;
1325 gc->chip_types[0].regs.mask = GPIO_INTEN;
1326 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1327 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1328 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1329 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1330 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1331 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1332
1333 irq_set_handler_data(bank->irq, bank);
1334 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1335 }
1336
1337 return 0;
1338}
1339
1340static int rockchip_gpiolib_register(struct platform_device *pdev,
1341 struct rockchip_pinctrl *info)
1342{
1343 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1344 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1345 struct gpio_chip *gc;
1346 int ret;
1347 int i;
1348
1349 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1350 if (!bank->valid) {
1351 dev_warn(&pdev->dev, "bank %s is not valid\n",
1352 bank->name);
1353 continue;
1354 }
1355
1356 bank->gpio_chip = rockchip_gpiolib_chip;
1357
1358 gc = &bank->gpio_chip;
1359 gc->base = bank->pin_base;
1360 gc->ngpio = bank->nr_pins;
1361 gc->dev = &pdev->dev;
1362 gc->of_node = bank->of_node;
1363 gc->label = bank->name;
1364
1365 ret = gpiochip_add(gc);
1366 if (ret) {
1367 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1368 gc->label, ret);
1369 goto fail;
1370 }
1371 }
1372
1373 rockchip_interrupts_register(pdev, info);
1374
1375 return 0;
1376
1377fail:
1378 for (--i, --bank; i >= 0; --i, --bank) {
1379 if (!bank->valid)
1380 continue;
1381
1382 if (gpiochip_remove(&bank->gpio_chip))
1383 dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1384 bank->gpio_chip.label);
1385 }
1386 return ret;
1387}
1388
1389static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1390 struct rockchip_pinctrl *info)
1391{
1392 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1393 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1394 int ret = 0;
1395 int i;
1396
1397 for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1398 if (!bank->valid)
1399 continue;
1400
1401 ret = gpiochip_remove(&bank->gpio_chip);
1402 }
1403
1404 if (ret)
1405 dev_err(&pdev->dev, "gpio chip remove failed\n");
1406
1407 return ret;
1408}
1409
1410static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1411 struct device *dev)
1412{
1413 struct resource res;
1414
1415 if (of_address_to_resource(bank->of_node, 0, &res)) {
1416 dev_err(dev, "cannot find IO resource for bank\n");
1417 return -ENOENT;
1418 }
1419
1420 bank->reg_base = devm_ioremap_resource(dev, &res);
1421 if (IS_ERR(bank->reg_base))
1422 return PTR_ERR(bank->reg_base);
1423
6ca5274d
HS		 1424 /*
1425 * special case, where parts of the pull setting-registers are
1426 * part of the PMU register space
1427 */
1428 if (of_device_is_compatible(bank->of_node,
1429 "rockchip,rk3188-gpio-bank0")) {
1430 bank->bank_type = RK3188_BANK0;
1431
1432 if (of_address_to_resource(bank->of_node, 1, &res)) {
1433 dev_err(dev, "cannot find IO resource for bank\n");
1434 return -ENOENT;
1435 }
1436
1437 bank->reg_pull = devm_ioremap_resource(dev, &res);
1438 if (IS_ERR(bank->reg_pull))
1439 return PTR_ERR(bank->reg_pull);
1440 } else {
1441 bank->bank_type = COMMON_BANK;
1442 }
65fca613 1443
d3e51161
HS		 1444 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1445
1446 bank->clk = of_clk_get(bank->of_node, 0);
1447 if (IS_ERR(bank->clk))
1448 return PTR_ERR(bank->clk);
1449
1450 return clk_prepare_enable(bank->clk);
1451}
1452
1453static const struct of_device_id rockchip_pinctrl_dt_match[];
1454
1455/* retrieve the soc specific data */
1456static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1457 struct rockchip_pinctrl *d,
1458 struct platform_device *pdev)
1459{
1460 const struct of_device_id *match;
1461 struct device_node *node = pdev->dev.of_node;
1462 struct device_node *np;
1463 struct rockchip_pin_ctrl *ctrl;
1464 struct rockchip_pin_bank *bank;
1465 int i;
1466
1467 match = of_match_node(rockchip_pinctrl_dt_match, node);
1468 ctrl = (struct rockchip_pin_ctrl *)match->data;
1469
1470 for_each_child_of_node(node, np) {
1471 if (!of_find_property(np, "gpio-controller", NULL))
1472 continue;
1473
1474 bank = ctrl->pin_banks;
1475 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1476 if (!strcmp(bank->name, np->name)) {
1477 bank->of_node = np;
1478
1479 if (!rockchip_get_bank_data(bank, &pdev->dev))
1480 bank->valid = true;
1481
1482 break;
1483 }
1484 }
1485 }
1486
1487 bank = ctrl->pin_banks;
1488 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1489 spin_lock_init(&bank->slock);
1490 bank->drvdata = d;
1491 bank->pin_base = ctrl->nr_pins;
1492 ctrl->nr_pins += bank->nr_pins;
1493 }
1494
1495 return ctrl;
1496}
1497
1498static int rockchip_pinctrl_probe(struct platform_device *pdev)
1499{
1500 struct rockchip_pinctrl *info;
1501 struct device *dev = &pdev->dev;
1502 struct rockchip_pin_ctrl *ctrl;
1503 struct resource *res;
1504 int ret;
1505
1506 if (!dev->of_node) {
1507 dev_err(dev, "device tree node not found\n");
1508 return -ENODEV;
1509 }
1510
1511 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1512 if (!info)
1513 return -ENOMEM;
1514
1515 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1516 if (!ctrl) {
1517 dev_err(dev, "driver data not available\n");
1518 return -EINVAL;
1519 }
1520 info->ctrl = ctrl;
1521 info->dev = dev;
1522
1523 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d3e51161
HS		 1524 info->reg_base = devm_ioremap_resource(&pdev->dev, res);
1525 if (IS_ERR(info->reg_base))
1526 return PTR_ERR(info->reg_base);
1527
6ca5274d
HS		 1528 /* The RK3188 has its pull registers in a separate place */
1529 if (ctrl->type == RK3188) {
1530 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1531 info->reg_pull = devm_ioremap_resource(&pdev->dev, res);
38d321c8
DC		 1532 if (IS_ERR(info->reg_pull))
1533 return PTR_ERR(info->reg_pull);
6ca5274d
HS		 1534 }
1535
d3e51161
HS		 1536 ret = rockchip_gpiolib_register(pdev, info);
1537 if (ret)
1538 return ret;
1539
1540 ret = rockchip_pinctrl_register(pdev, info);
1541 if (ret) {
1542 rockchip_gpiolib_unregister(pdev, info);
1543 return ret;
1544 }
1545
1546 platform_set_drvdata(pdev, info);
1547
1548 return 0;
1549}
1550
1551static struct rockchip_pin_bank rk2928_pin_banks[] = {
1552 PIN_BANK(0, 32, "gpio0"),
1553 PIN_BANK(1, 32, "gpio1"),
1554 PIN_BANK(2, 32, "gpio2"),
1555 PIN_BANK(3, 32, "gpio3"),
1556};
1557
1558static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1559 .pin_banks = rk2928_pin_banks,
1560 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
1561 .label = "RK2928-GPIO",
a282926d 1562 .type = RK2928,
d3e51161 1563 .mux_offset = 0xa8,
a282926d 1564 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
d3e51161
HS		 1565};
1566
1567static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1568 PIN_BANK(0, 32, "gpio0"),
1569 PIN_BANK(1, 32, "gpio1"),
1570 PIN_BANK(2, 32, "gpio2"),
1571 PIN_BANK(3, 32, "gpio3"),
1572 PIN_BANK(4, 32, "gpio4"),
1573 PIN_BANK(6, 16, "gpio6"),
1574};
1575
1576static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1577 .pin_banks = rk3066a_pin_banks,
1578 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
1579 .label = "RK3066a-GPIO",
a282926d 1580 .type = RK2928,
d3e51161 1581 .mux_offset = 0xa8,
a282926d 1582 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
d3e51161
HS		 1583};
1584
1585static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1586 PIN_BANK(0, 32, "gpio0"),
1587 PIN_BANK(1, 32, "gpio1"),
1588 PIN_BANK(2, 32, "gpio2"),
1589 PIN_BANK(3, 32, "gpio3"),
1590};
1591
1592static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1593 .pin_banks = rk3066b_pin_banks,
1594 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
1595 .label = "RK3066b-GPIO",
a282926d 1596 .type = RK3066B,
d3e51161 1597 .mux_offset = 0x60,
d3e51161
HS		 1598};
1599
1600static struct rockchip_pin_bank rk3188_pin_banks[] = {
1601 PIN_BANK(0, 32, "gpio0"),
1602 PIN_BANK(1, 32, "gpio1"),
1603 PIN_BANK(2, 32, "gpio2"),
1604 PIN_BANK(3, 32, "gpio3"),
1605};
1606
1607static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1608 .pin_banks = rk3188_pin_banks,
1609 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
1610 .label = "RK3188-GPIO",
a282926d 1611 .type = RK3188,
22c0d7e3 1612 .mux_offset = 0x60,
6ca5274d 1613 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
d3e51161
HS		 1614};
1615
1616static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1617 { .compatible = "rockchip,rk2928-pinctrl",
1618 .data = (void *)&rk2928_pin_ctrl },
1619 { .compatible = "rockchip,rk3066a-pinctrl",
1620 .data = (void *)&rk3066a_pin_ctrl },
1621 { .compatible = "rockchip,rk3066b-pinctrl",
1622 .data = (void *)&rk3066b_pin_ctrl },
1623 { .compatible = "rockchip,rk3188-pinctrl",
1624 .data = (void *)&rk3188_pin_ctrl },
1625 {},
1626};
1627MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1628
1629static struct platform_driver rockchip_pinctrl_driver = {
1630 .probe = rockchip_pinctrl_probe,
1631 .driver = {
1632 .name = "rockchip-pinctrl",
1633 .owner = THIS_MODULE,
0be9e70d 1634 .of_match_table = rockchip_pinctrl_dt_match,
d3e51161
HS		 1635 },
1636};
1637
1638static int __init rockchip_pinctrl_drv_register(void)
1639{
1640 return platform_driver_register(&rockchip_pinctrl_driver);
1641}
1642postcore_initcall(rockchip_pinctrl_drv_register);
1643
1644MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1645MODULE_DESCRIPTION("Rockchip pinctrl driver");
1646MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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