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701016c0 SK |
1 | /* |
2 | * Copyright (C) 2013 STMicroelectronics (R&D) Limited. | |
3 | * Authors: | |
4 | * Srinivas Kandagatla <srinivas.kandagatla@st.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/err.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/of.h> | |
727b0f71 | 17 | #include <linux/of_irq.h> |
701016c0 SK |
18 | #include <linux/of_gpio.h> |
19 | #include <linux/of_address.h> | |
20 | #include <linux/regmap.h> | |
21 | #include <linux/mfd/syscon.h> | |
22 | #include <linux/pinctrl/pinctrl.h> | |
23 | #include <linux/pinctrl/pinmux.h> | |
24 | #include <linux/pinctrl/pinconf.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include "core.h" | |
27 | ||
28 | /* PIO Block registers */ | |
29 | /* PIO output */ | |
30 | #define REG_PIO_POUT 0x00 | |
31 | /* Set bits of POUT */ | |
32 | #define REG_PIO_SET_POUT 0x04 | |
33 | /* Clear bits of POUT */ | |
34 | #define REG_PIO_CLR_POUT 0x08 | |
35 | /* PIO input */ | |
36 | #define REG_PIO_PIN 0x10 | |
37 | /* PIO configuration */ | |
38 | #define REG_PIO_PC(n) (0x20 + (n) * 0x10) | |
39 | /* Set bits of PC[2:0] */ | |
40 | #define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10) | |
41 | /* Clear bits of PC[2:0] */ | |
42 | #define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10) | |
43 | /* PIO input comparison */ | |
44 | #define REG_PIO_PCOMP 0x50 | |
45 | /* Set bits of PCOMP */ | |
46 | #define REG_PIO_SET_PCOMP 0x54 | |
47 | /* Clear bits of PCOMP */ | |
48 | #define REG_PIO_CLR_PCOMP 0x58 | |
49 | /* PIO input comparison mask */ | |
50 | #define REG_PIO_PMASK 0x60 | |
51 | /* Set bits of PMASK */ | |
52 | #define REG_PIO_SET_PMASK 0x64 | |
53 | /* Clear bits of PMASK */ | |
54 | #define REG_PIO_CLR_PMASK 0x68 | |
55 | ||
56 | #define ST_GPIO_DIRECTION_BIDIR 0x1 | |
57 | #define ST_GPIO_DIRECTION_OUT 0x2 | |
58 | #define ST_GPIO_DIRECTION_IN 0x4 | |
59 | ||
60 | /** | |
61 | * Packed style retime configuration. | |
62 | * There are two registers cfg0 and cfg1 in this style for each bank. | |
63 | * Each field in this register is 8 bit corresponding to 8 pins in the bank. | |
64 | */ | |
65 | #define RT_P_CFGS_PER_BANK 2 | |
66 | #define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7) | |
67 | #define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23) | |
68 | #define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31) | |
69 | #define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7) | |
70 | #define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15) | |
71 | #define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23) | |
72 | #define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31) | |
73 | ||
74 | /** | |
75 | * Dedicated style retime Configuration register | |
76 | * each register is dedicated per pin. | |
77 | */ | |
78 | #define RT_D_CFGS_PER_BANK 8 | |
79 | #define RT_D_CFG_CLK_SHIFT 0 | |
80 | #define RT_D_CFG_CLK_MASK (0x3 << 0) | |
81 | #define RT_D_CFG_CLKNOTDATA_SHIFT 2 | |
82 | #define RT_D_CFG_CLKNOTDATA_MASK BIT(2) | |
83 | #define RT_D_CFG_DELAY_SHIFT 3 | |
84 | #define RT_D_CFG_DELAY_MASK (0xf << 3) | |
85 | #define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7 | |
86 | #define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7) | |
87 | #define RT_D_CFG_DOUBLE_EDGE_SHIFT 8 | |
88 | #define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8) | |
89 | #define RT_D_CFG_INVERTCLK_SHIFT 9 | |
90 | #define RT_D_CFG_INVERTCLK_MASK BIT(9) | |
91 | #define RT_D_CFG_RETIME_SHIFT 10 | |
92 | #define RT_D_CFG_RETIME_MASK BIT(10) | |
93 | ||
94 | /* | |
95 | * Pinconf is represented in an opaque unsigned long variable. | |
96 | * Below is the bit allocation details for each possible configuration. | |
97 | * All the bit fields can be encapsulated into four variables | |
98 | * (direction, retime-type, retime-clk, retime-delay) | |
99 | * | |
100 | * +----------------+ | |
101 | *[31:28]| reserved-3 | | |
102 | * +----------------+------------- | |
103 | *[27] | oe | | | |
104 | * +----------------+ v | |
105 | *[26] | pu | [Direction ] | |
106 | * +----------------+ ^ | |
107 | *[25] | od | | | |
108 | * +----------------+------------- | |
109 | *[24] | reserved-2 | | |
110 | * +----------------+------------- | |
111 | *[23] | retime | | | |
112 | * +----------------+ | | |
113 | *[22] | retime-invclk | | | |
114 | * +----------------+ v | |
115 | *[21] |retime-clknotdat| [Retime-type ] | |
116 | * +----------------+ ^ | |
117 | *[20] | retime-de | | | |
118 | * +----------------+------------- | |
119 | *[19:18]| retime-clk |------>[Retime-Clk ] | |
120 | * +----------------+ | |
121 | *[17:16]| reserved-1 | | |
122 | * +----------------+ | |
123 | *[15..0]| retime-delay |------>[Retime Delay] | |
124 | * +----------------+ | |
125 | */ | |
126 | ||
127 | #define ST_PINCONF_UNPACK(conf, param)\ | |
128 | ((conf >> ST_PINCONF_ ##param ##_SHIFT) \ | |
129 | & ST_PINCONF_ ##param ##_MASK) | |
130 | ||
131 | #define ST_PINCONF_PACK(conf, val, param) (conf |=\ | |
132 | ((val & ST_PINCONF_ ##param ##_MASK) << \ | |
133 | ST_PINCONF_ ##param ##_SHIFT)) | |
134 | ||
135 | /* Output enable */ | |
136 | #define ST_PINCONF_OE_MASK 0x1 | |
137 | #define ST_PINCONF_OE_SHIFT 27 | |
138 | #define ST_PINCONF_OE BIT(27) | |
139 | #define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE) | |
140 | #define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE) | |
141 | ||
142 | /* Pull Up */ | |
143 | #define ST_PINCONF_PU_MASK 0x1 | |
144 | #define ST_PINCONF_PU_SHIFT 26 | |
145 | #define ST_PINCONF_PU BIT(26) | |
146 | #define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU) | |
147 | #define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU) | |
148 | ||
149 | /* Open Drain */ | |
150 | #define ST_PINCONF_OD_MASK 0x1 | |
151 | #define ST_PINCONF_OD_SHIFT 25 | |
152 | #define ST_PINCONF_OD BIT(25) | |
153 | #define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD) | |
154 | #define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD) | |
155 | ||
156 | #define ST_PINCONF_RT_MASK 0x1 | |
157 | #define ST_PINCONF_RT_SHIFT 23 | |
158 | #define ST_PINCONF_RT BIT(23) | |
159 | #define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT) | |
160 | #define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT) | |
161 | ||
162 | #define ST_PINCONF_RT_INVERTCLK_MASK 0x1 | |
163 | #define ST_PINCONF_RT_INVERTCLK_SHIFT 22 | |
164 | #define ST_PINCONF_RT_INVERTCLK BIT(22) | |
165 | #define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \ | |
166 | ST_PINCONF_UNPACK(conf, RT_INVERTCLK) | |
167 | #define ST_PINCONF_PACK_RT_INVERTCLK(conf) \ | |
168 | ST_PINCONF_PACK(conf, 1, RT_INVERTCLK) | |
169 | ||
170 | #define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1 | |
171 | #define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21 | |
172 | #define ST_PINCONF_RT_CLKNOTDATA BIT(21) | |
173 | #define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \ | |
174 | ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA) | |
175 | #define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \ | |
176 | ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA) | |
177 | ||
178 | #define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1 | |
179 | #define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20 | |
180 | #define ST_PINCONF_RT_DOUBLE_EDGE BIT(20) | |
181 | #define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \ | |
182 | ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE) | |
183 | #define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \ | |
184 | ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE) | |
185 | ||
186 | #define ST_PINCONF_RT_CLK_MASK 0x3 | |
187 | #define ST_PINCONF_RT_CLK_SHIFT 18 | |
188 | #define ST_PINCONF_RT_CLK BIT(18) | |
189 | #define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK) | |
190 | #define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK) | |
191 | ||
192 | /* RETIME_DELAY in Pico Secs */ | |
193 | #define ST_PINCONF_RT_DELAY_MASK 0xffff | |
194 | #define ST_PINCONF_RT_DELAY_SHIFT 0 | |
195 | #define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY) | |
196 | #define ST_PINCONF_PACK_RT_DELAY(conf, val) \ | |
197 | ST_PINCONF_PACK(conf, val, RT_DELAY) | |
198 | ||
199 | #define ST_GPIO_PINS_PER_BANK (8) | |
200 | #define OF_GPIO_ARGS_MIN (4) | |
201 | #define OF_RT_ARGS_MIN (2) | |
202 | ||
203 | #define gpio_range_to_bank(chip) \ | |
204 | container_of(chip, struct st_gpio_bank, range) | |
205 | ||
e2ed0e88 LJ |
206 | #define pc_to_bank(pc) \ |
207 | container_of(pc, struct st_gpio_bank, pc) | |
208 | ||
701016c0 SK |
209 | enum st_retime_style { |
210 | st_retime_style_none, | |
211 | st_retime_style_packed, | |
212 | st_retime_style_dedicated, | |
213 | }; | |
214 | ||
215 | struct st_retime_dedicated { | |
216 | struct regmap_field *rt[ST_GPIO_PINS_PER_BANK]; | |
217 | }; | |
218 | ||
219 | struct st_retime_packed { | |
220 | struct regmap_field *clk1notclk0; | |
221 | struct regmap_field *delay_0; | |
222 | struct regmap_field *delay_1; | |
223 | struct regmap_field *invertclk; | |
224 | struct regmap_field *retime; | |
225 | struct regmap_field *clknotdata; | |
226 | struct regmap_field *double_edge; | |
227 | }; | |
228 | ||
229 | struct st_pio_control { | |
230 | u32 rt_pin_mask; | |
231 | struct regmap_field *alt, *oe, *pu, *od; | |
232 | /* retiming */ | |
233 | union { | |
234 | struct st_retime_packed rt_p; | |
235 | struct st_retime_dedicated rt_d; | |
236 | } rt; | |
237 | }; | |
238 | ||
239 | struct st_pctl_data { | |
a4bc1f57 MC |
240 | const enum st_retime_style rt_style; |
241 | const unsigned int *input_delays; | |
242 | const int ninput_delays; | |
243 | const unsigned int *output_delays; | |
244 | const int noutput_delays; | |
701016c0 | 245 | /* register offset information */ |
a4bc1f57 | 246 | const int alt, oe, pu, od, rt; |
701016c0 SK |
247 | }; |
248 | ||
249 | struct st_pinconf { | |
250 | int pin; | |
251 | const char *name; | |
252 | unsigned long config; | |
253 | int altfunc; | |
254 | }; | |
255 | ||
256 | struct st_pmx_func { | |
257 | const char *name; | |
258 | const char **groups; | |
259 | unsigned ngroups; | |
260 | }; | |
261 | ||
262 | struct st_pctl_group { | |
263 | const char *name; | |
264 | unsigned int *pins; | |
265 | unsigned npins; | |
266 | struct st_pinconf *pin_conf; | |
267 | }; | |
268 | ||
155795b9 SK |
269 | /* |
270 | * Edge triggers are not supported at hardware level, it is supported by | |
271 | * software by exploiting the level trigger support in hardware. | |
272 | * Software uses a virtual register (EDGE_CONF) for edge trigger configuration | |
273 | * of each gpio pin in a GPIO bank. | |
274 | * | |
275 | * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of | |
276 | * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank. | |
277 | * | |
278 | * bit allocation per pin is: | |
279 | * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31] | |
280 | * -------------------------------------------------------- | |
281 | * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 | | |
282 | * -------------------------------------------------------- | |
283 | * | |
284 | * A pin can have one of following the values in its edge configuration field. | |
285 | * | |
286 | * ------- ---------------------------- | |
287 | * [0-3] - Description | |
288 | * ------- ---------------------------- | |
289 | * 0000 - No edge IRQ. | |
290 | * 0001 - Falling edge IRQ. | |
291 | * 0010 - Rising edge IRQ. | |
292 | * 0011 - Rising and Falling edge IRQ. | |
293 | * ------- ---------------------------- | |
294 | */ | |
295 | ||
296 | #define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4 | |
297 | #define ST_IRQ_EDGE_MASK 0xf | |
298 | #define ST_IRQ_EDGE_FALLING BIT(0) | |
299 | #define ST_IRQ_EDGE_RISING BIT(1) | |
300 | #define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1)) | |
301 | ||
302 | #define ST_IRQ_RISING_EDGE_CONF(pin) \ | |
303 | (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) | |
304 | ||
305 | #define ST_IRQ_FALLING_EDGE_CONF(pin) \ | |
306 | (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) | |
307 | ||
308 | #define ST_IRQ_BOTH_EDGE_CONF(pin) \ | |
309 | (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) | |
310 | ||
311 | #define ST_IRQ_EDGE_CONF(conf, pin) \ | |
312 | (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK) | |
313 | ||
701016c0 SK |
314 | struct st_gpio_bank { |
315 | struct gpio_chip gpio_chip; | |
316 | struct pinctrl_gpio_range range; | |
317 | void __iomem *base; | |
318 | struct st_pio_control pc; | |
155795b9 SK |
319 | unsigned long irq_edge_conf; |
320 | spinlock_t lock; | |
701016c0 SK |
321 | }; |
322 | ||
323 | struct st_pinctrl { | |
324 | struct device *dev; | |
325 | struct pinctrl_dev *pctl; | |
326 | struct st_gpio_bank *banks; | |
327 | int nbanks; | |
328 | struct st_pmx_func *functions; | |
329 | int nfunctions; | |
330 | struct st_pctl_group *groups; | |
331 | int ngroups; | |
332 | struct regmap *regmap; | |
333 | const struct st_pctl_data *data; | |
727b0f71 | 334 | void __iomem *irqmux_base; |
701016c0 SK |
335 | }; |
336 | ||
337 | /* SOC specific data */ | |
338 | /* STiH415 data */ | |
a4bc1f57 MC |
339 | static const unsigned int stih415_input_delays[] = {0, 500, 1000, 1500}; |
340 | static const unsigned int stih415_output_delays[] = {0, 1000, 2000, 3000}; | |
701016c0 SK |
341 | |
342 | #define STIH415_PCTRL_COMMON_DATA \ | |
343 | .rt_style = st_retime_style_packed, \ | |
344 | .input_delays = stih415_input_delays, \ | |
3b02dad2 | 345 | .ninput_delays = ARRAY_SIZE(stih415_input_delays), \ |
701016c0 | 346 | .output_delays = stih415_output_delays, \ |
3b02dad2 | 347 | .noutput_delays = ARRAY_SIZE(stih415_output_delays) |
701016c0 SK |
348 | |
349 | static const struct st_pctl_data stih415_sbc_data = { | |
350 | STIH415_PCTRL_COMMON_DATA, | |
351 | .alt = 0, .oe = 5, .pu = 7, .od = 9, .rt = 16, | |
352 | }; | |
353 | ||
354 | static const struct st_pctl_data stih415_front_data = { | |
355 | STIH415_PCTRL_COMMON_DATA, | |
356 | .alt = 0, .oe = 8, .pu = 10, .od = 12, .rt = 16, | |
357 | }; | |
358 | ||
359 | static const struct st_pctl_data stih415_rear_data = { | |
360 | STIH415_PCTRL_COMMON_DATA, | |
361 | .alt = 0, .oe = 6, .pu = 8, .od = 10, .rt = 38, | |
362 | }; | |
363 | ||
364 | static const struct st_pctl_data stih415_left_data = { | |
365 | STIH415_PCTRL_COMMON_DATA, | |
366 | .alt = 0, .oe = 3, .pu = 4, .od = 5, .rt = 6, | |
367 | }; | |
368 | ||
369 | static const struct st_pctl_data stih415_right_data = { | |
370 | STIH415_PCTRL_COMMON_DATA, | |
371 | .alt = 0, .oe = 5, .pu = 7, .od = 9, .rt = 11, | |
372 | }; | |
373 | ||
374 | /* STiH416 data */ | |
a4bc1f57 MC |
375 | static const unsigned int stih416_delays[] = {0, 300, 500, 750, 1000, 1250, |
376 | 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 }; | |
701016c0 SK |
377 | |
378 | static const struct st_pctl_data stih416_data = { | |
379 | .rt_style = st_retime_style_dedicated, | |
380 | .input_delays = stih416_delays, | |
88430acf | 381 | .ninput_delays = ARRAY_SIZE(stih416_delays), |
701016c0 | 382 | .output_delays = stih416_delays, |
88430acf | 383 | .noutput_delays = ARRAY_SIZE(stih416_delays), |
701016c0 SK |
384 | .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100, |
385 | }; | |
386 | ||
7ce717db GC |
387 | static const struct st_pctl_data stih407_flashdata = { |
388 | .rt_style = st_retime_style_none, | |
389 | .input_delays = stih416_delays, | |
390 | .ninput_delays = ARRAY_SIZE(stih416_delays), | |
391 | .output_delays = stih416_delays, | |
392 | .noutput_delays = ARRAY_SIZE(stih416_delays), | |
393 | .alt = 0, | |
394 | .oe = -1, /* Not Available */ | |
395 | .pu = -1, /* Not Available */ | |
396 | .od = 60, | |
397 | .rt = 100, | |
398 | }; | |
399 | ||
f89e68fc LJ |
400 | static struct st_pio_control *st_get_pio_control( |
401 | struct pinctrl_dev *pctldev, int pin) | |
402 | { | |
403 | struct pinctrl_gpio_range *range = | |
404 | pinctrl_find_gpio_range_from_pin(pctldev, pin); | |
405 | struct st_gpio_bank *bank = gpio_range_to_bank(range); | |
406 | ||
407 | return &bank->pc; | |
408 | } | |
409 | ||
701016c0 SK |
410 | /* Low level functions.. */ |
411 | static inline int st_gpio_bank(int gpio) | |
412 | { | |
413 | return gpio/ST_GPIO_PINS_PER_BANK; | |
414 | } | |
415 | ||
416 | static inline int st_gpio_pin(int gpio) | |
417 | { | |
418 | return gpio%ST_GPIO_PINS_PER_BANK; | |
419 | } | |
420 | ||
421 | static void st_pinconf_set_config(struct st_pio_control *pc, | |
422 | int pin, unsigned long config) | |
423 | { | |
424 | struct regmap_field *output_enable = pc->oe; | |
425 | struct regmap_field *pull_up = pc->pu; | |
426 | struct regmap_field *open_drain = pc->od; | |
427 | unsigned int oe_value, pu_value, od_value; | |
428 | unsigned long mask = BIT(pin); | |
429 | ||
4e6a609f GC |
430 | if (output_enable) { |
431 | regmap_field_read(output_enable, &oe_value); | |
432 | oe_value &= ~mask; | |
433 | if (config & ST_PINCONF_OE) | |
434 | oe_value |= mask; | |
435 | regmap_field_write(output_enable, oe_value); | |
436 | } | |
437 | ||
438 | if (pull_up) { | |
439 | regmap_field_read(pull_up, &pu_value); | |
440 | pu_value &= ~mask; | |
441 | if (config & ST_PINCONF_PU) | |
442 | pu_value |= mask; | |
443 | regmap_field_write(pull_up, pu_value); | |
444 | } | |
445 | ||
446 | if (open_drain) { | |
447 | regmap_field_read(open_drain, &od_value); | |
448 | od_value &= ~mask; | |
449 | if (config & ST_PINCONF_OD) | |
450 | od_value |= mask; | |
451 | regmap_field_write(open_drain, od_value); | |
452 | } | |
701016c0 SK |
453 | } |
454 | ||
455 | static void st_pctl_set_function(struct st_pio_control *pc, | |
456 | int pin_id, int function) | |
457 | { | |
458 | struct regmap_field *alt = pc->alt; | |
459 | unsigned int val; | |
460 | int pin = st_gpio_pin(pin_id); | |
461 | int offset = pin * 4; | |
462 | ||
4e6a609f GC |
463 | if (!alt) |
464 | return; | |
465 | ||
701016c0 SK |
466 | regmap_field_read(alt, &val); |
467 | val &= ~(0xf << offset); | |
468 | val |= function << offset; | |
469 | regmap_field_write(alt, val); | |
470 | } | |
471 | ||
c2a4bf47 LJ |
472 | static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin) |
473 | { | |
474 | struct regmap_field *alt = pc->alt; | |
475 | unsigned int val; | |
476 | int offset = pin * 4; | |
477 | ||
478 | if (!alt) | |
479 | return 0; | |
480 | ||
481 | regmap_field_read(alt, &val); | |
482 | ||
483 | return (val >> offset) & 0xf; | |
484 | } | |
485 | ||
701016c0 SK |
486 | static unsigned long st_pinconf_delay_to_bit(unsigned int delay, |
487 | const struct st_pctl_data *data, unsigned long config) | |
488 | { | |
a4bc1f57 | 489 | const unsigned int *delay_times; |
701016c0 SK |
490 | int num_delay_times, i, closest_index = -1; |
491 | unsigned int closest_divergence = UINT_MAX; | |
492 | ||
493 | if (ST_PINCONF_UNPACK_OE(config)) { | |
494 | delay_times = data->output_delays; | |
495 | num_delay_times = data->noutput_delays; | |
496 | } else { | |
497 | delay_times = data->input_delays; | |
498 | num_delay_times = data->ninput_delays; | |
499 | } | |
500 | ||
501 | for (i = 0; i < num_delay_times; i++) { | |
502 | unsigned int divergence = abs(delay - delay_times[i]); | |
503 | ||
504 | if (divergence == 0) | |
505 | return i; | |
506 | ||
507 | if (divergence < closest_divergence) { | |
508 | closest_divergence = divergence; | |
509 | closest_index = i; | |
510 | } | |
511 | } | |
512 | ||
513 | pr_warn("Attempt to set delay %d, closest available %d\n", | |
514 | delay, delay_times[closest_index]); | |
515 | ||
516 | return closest_index; | |
517 | } | |
518 | ||
519 | static unsigned long st_pinconf_bit_to_delay(unsigned int index, | |
520 | const struct st_pctl_data *data, unsigned long output) | |
521 | { | |
a4bc1f57 | 522 | const unsigned int *delay_times; |
701016c0 SK |
523 | int num_delay_times; |
524 | ||
525 | if (output) { | |
526 | delay_times = data->output_delays; | |
527 | num_delay_times = data->noutput_delays; | |
528 | } else { | |
529 | delay_times = data->input_delays; | |
530 | num_delay_times = data->ninput_delays; | |
531 | } | |
532 | ||
533 | if (index < num_delay_times) { | |
534 | return delay_times[index]; | |
535 | } else { | |
536 | pr_warn("Delay not found in/out delay list\n"); | |
537 | return 0; | |
538 | } | |
539 | } | |
540 | ||
541 | static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field, | |
542 | int enable, int pin) | |
543 | { | |
544 | unsigned int val = 0; | |
545 | ||
546 | regmap_field_read(field, &val); | |
547 | if (enable) | |
548 | val |= BIT(pin); | |
549 | else | |
550 | val &= ~BIT(pin); | |
551 | regmap_field_write(field, val); | |
552 | } | |
553 | ||
554 | static void st_pinconf_set_retime_packed(struct st_pinctrl *info, | |
555 | struct st_pio_control *pc, unsigned long config, int pin) | |
556 | { | |
557 | const struct st_pctl_data *data = info->data; | |
558 | struct st_retime_packed *rt_p = &pc->rt.rt_p; | |
559 | unsigned int delay; | |
560 | ||
561 | st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0, | |
562 | ST_PINCONF_UNPACK_RT_CLK(config), pin); | |
563 | ||
564 | st_regmap_field_bit_set_clear_pin(rt_p->clknotdata, | |
565 | ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin); | |
566 | ||
567 | st_regmap_field_bit_set_clear_pin(rt_p->double_edge, | |
568 | ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin); | |
569 | ||
570 | st_regmap_field_bit_set_clear_pin(rt_p->invertclk, | |
571 | ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin); | |
572 | ||
573 | st_regmap_field_bit_set_clear_pin(rt_p->retime, | |
574 | ST_PINCONF_UNPACK_RT(config), pin); | |
575 | ||
576 | delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config), | |
577 | data, config); | |
578 | /* 2 bit delay, lsb */ | |
579 | st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin); | |
580 | /* 2 bit delay, msb */ | |
581 | st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin); | |
582 | ||
583 | } | |
584 | ||
585 | static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info, | |
586 | struct st_pio_control *pc, unsigned long config, int pin) | |
587 | { | |
588 | int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1; | |
589 | int clk = ST_PINCONF_UNPACK_RT_CLK(config); | |
590 | int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config); | |
591 | int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config); | |
592 | int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config); | |
593 | int retime = ST_PINCONF_UNPACK_RT(config); | |
594 | ||
595 | unsigned long delay = st_pinconf_delay_to_bit( | |
596 | ST_PINCONF_UNPACK_RT_DELAY(config), | |
597 | info->data, config); | |
598 | struct st_retime_dedicated *rt_d = &pc->rt.rt_d; | |
599 | ||
600 | unsigned long retime_config = | |
601 | ((clk) << RT_D_CFG_CLK_SHIFT) | | |
602 | ((delay) << RT_D_CFG_DELAY_SHIFT) | | |
603 | ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) | | |
604 | ((retime) << RT_D_CFG_RETIME_SHIFT) | | |
605 | ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) | | |
606 | ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) | | |
607 | ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT); | |
608 | ||
609 | regmap_field_write(rt_d->rt[pin], retime_config); | |
610 | } | |
611 | ||
612 | static void st_pinconf_get_direction(struct st_pio_control *pc, | |
613 | int pin, unsigned long *config) | |
614 | { | |
615 | unsigned int oe_value, pu_value, od_value; | |
616 | ||
4e6a609f GC |
617 | if (pc->oe) { |
618 | regmap_field_read(pc->oe, &oe_value); | |
619 | if (oe_value & BIT(pin)) | |
620 | ST_PINCONF_PACK_OE(*config); | |
621 | } | |
701016c0 | 622 | |
4e6a609f GC |
623 | if (pc->pu) { |
624 | regmap_field_read(pc->pu, &pu_value); | |
625 | if (pu_value & BIT(pin)) | |
626 | ST_PINCONF_PACK_PU(*config); | |
627 | } | |
701016c0 | 628 | |
4e6a609f GC |
629 | if (pc->od) { |
630 | regmap_field_read(pc->od, &od_value); | |
631 | if (od_value & BIT(pin)) | |
632 | ST_PINCONF_PACK_OD(*config); | |
633 | } | |
701016c0 SK |
634 | } |
635 | ||
636 | static int st_pinconf_get_retime_packed(struct st_pinctrl *info, | |
637 | struct st_pio_control *pc, int pin, unsigned long *config) | |
638 | { | |
639 | const struct st_pctl_data *data = info->data; | |
640 | struct st_retime_packed *rt_p = &pc->rt.rt_p; | |
641 | unsigned int delay_bits, delay, delay0, delay1, val; | |
642 | int output = ST_PINCONF_UNPACK_OE(*config); | |
643 | ||
644 | if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin))) | |
645 | ST_PINCONF_PACK_RT(*config); | |
646 | ||
647 | if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin))) | |
648 | ST_PINCONF_PACK_RT_CLK(*config, 1); | |
649 | ||
650 | if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin))) | |
651 | ST_PINCONF_PACK_RT_CLKNOTDATA(*config); | |
652 | ||
653 | if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin))) | |
654 | ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); | |
655 | ||
656 | if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin))) | |
657 | ST_PINCONF_PACK_RT_INVERTCLK(*config); | |
658 | ||
659 | regmap_field_read(rt_p->delay_0, &delay0); | |
660 | regmap_field_read(rt_p->delay_1, &delay1); | |
661 | delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) | | |
662 | (((delay0 & BIT(pin)) ? 1 : 0)); | |
663 | delay = st_pinconf_bit_to_delay(delay_bits, data, output); | |
664 | ST_PINCONF_PACK_RT_DELAY(*config, delay); | |
665 | ||
666 | return 0; | |
667 | } | |
668 | ||
669 | static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info, | |
670 | struct st_pio_control *pc, int pin, unsigned long *config) | |
671 | { | |
672 | unsigned int value; | |
673 | unsigned long delay_bits, delay, rt_clk; | |
674 | int output = ST_PINCONF_UNPACK_OE(*config); | |
675 | struct st_retime_dedicated *rt_d = &pc->rt.rt_d; | |
676 | ||
677 | regmap_field_read(rt_d->rt[pin], &value); | |
678 | ||
679 | rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT; | |
680 | ST_PINCONF_PACK_RT_CLK(*config, rt_clk); | |
681 | ||
682 | delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT; | |
683 | delay = st_pinconf_bit_to_delay(delay_bits, info->data, output); | |
684 | ST_PINCONF_PACK_RT_DELAY(*config, delay); | |
685 | ||
686 | if (value & RT_D_CFG_CLKNOTDATA_MASK) | |
687 | ST_PINCONF_PACK_RT_CLKNOTDATA(*config); | |
688 | ||
689 | if (value & RT_D_CFG_DOUBLE_EDGE_MASK) | |
690 | ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); | |
691 | ||
692 | if (value & RT_D_CFG_INVERTCLK_MASK) | |
693 | ST_PINCONF_PACK_RT_INVERTCLK(*config); | |
694 | ||
695 | if (value & RT_D_CFG_RETIME_MASK) | |
696 | ST_PINCONF_PACK_RT(*config); | |
697 | ||
698 | return 0; | |
699 | } | |
700 | ||
701 | /* GPIO related functions */ | |
702 | ||
703 | static inline void __st_gpio_set(struct st_gpio_bank *bank, | |
704 | unsigned offset, int value) | |
705 | { | |
706 | if (value) | |
707 | writel(BIT(offset), bank->base + REG_PIO_SET_POUT); | |
708 | else | |
709 | writel(BIT(offset), bank->base + REG_PIO_CLR_POUT); | |
710 | } | |
711 | ||
712 | static void st_gpio_direction(struct st_gpio_bank *bank, | |
713 | unsigned int gpio, unsigned int direction) | |
714 | { | |
715 | int offset = st_gpio_pin(gpio); | |
716 | int i = 0; | |
717 | /** | |
718 | * There are three configuration registers (PIOn_PC0, PIOn_PC1 | |
719 | * and PIOn_PC2) for each port. These are used to configure the | |
720 | * PIO port pins. Each pin can be configured as an input, output, | |
721 | * bidirectional, or alternative function pin. Three bits, one bit | |
722 | * from each of the three registers, configure the corresponding bit of | |
723 | * the port. Valid bit settings is: | |
724 | * | |
725 | * PC2 PC1 PC0 Direction. | |
726 | * 0 0 0 [Input Weak pull-up] | |
727 | * 0 0 or 1 1 [Bidirection] | |
728 | * 0 1 0 [Output] | |
729 | * 1 0 0 [Input] | |
730 | * | |
731 | * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits | |
732 | * individually. | |
733 | */ | |
734 | for (i = 0; i <= 2; i++) { | |
735 | if (direction & BIT(i)) | |
736 | writel(BIT(offset), bank->base + REG_PIO_SET_PC(i)); | |
737 | else | |
738 | writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i)); | |
739 | } | |
740 | } | |
741 | ||
701016c0 SK |
742 | static int st_gpio_get(struct gpio_chip *chip, unsigned offset) |
743 | { | |
2e862a7b | 744 | struct st_gpio_bank *bank = gpiochip_get_data(chip); |
701016c0 SK |
745 | |
746 | return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset)); | |
747 | } | |
748 | ||
749 | static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
750 | { | |
2e862a7b | 751 | struct st_gpio_bank *bank = gpiochip_get_data(chip); |
701016c0 SK |
752 | __st_gpio_set(bank, offset, value); |
753 | } | |
754 | ||
755 | static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
756 | { | |
757 | pinctrl_gpio_direction_input(chip->base + offset); | |
758 | ||
759 | return 0; | |
760 | } | |
761 | ||
762 | static int st_gpio_direction_output(struct gpio_chip *chip, | |
763 | unsigned offset, int value) | |
764 | { | |
2e862a7b | 765 | struct st_gpio_bank *bank = gpiochip_get_data(chip); |
701016c0 SK |
766 | |
767 | __st_gpio_set(bank, offset, value); | |
768 | pinctrl_gpio_direction_output(chip->base + offset); | |
769 | ||
770 | return 0; | |
771 | } | |
772 | ||
1e702ec2 LJ |
773 | static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
774 | { | |
2e862a7b | 775 | struct st_gpio_bank *bank = gpiochip_get_data(chip); |
1e702ec2 LJ |
776 | struct st_pio_control pc = bank->pc; |
777 | unsigned long config; | |
778 | unsigned int direction = 0; | |
779 | unsigned int function; | |
780 | unsigned int value; | |
781 | int i = 0; | |
782 | ||
783 | /* Alternate function direction is handled by Pinctrl */ | |
784 | function = st_pctl_get_pin_function(&pc, offset); | |
785 | if (function) { | |
786 | st_pinconf_get_direction(&pc, offset, &config); | |
787 | return !ST_PINCONF_UNPACK_OE(config); | |
788 | } | |
789 | ||
790 | /* | |
791 | * GPIO direction is handled differently | |
792 | * - See st_gpio_direction() above for an explanation | |
793 | */ | |
794 | for (i = 0; i <= 2; i++) { | |
795 | value = readl(bank->base + REG_PIO_PC(i)); | |
796 | direction |= ((value >> offset) & 0x1) << i; | |
797 | } | |
798 | ||
799 | return (direction == ST_GPIO_DIRECTION_IN); | |
800 | } | |
801 | ||
701016c0 SK |
802 | static int st_gpio_xlate(struct gpio_chip *gc, |
803 | const struct of_phandle_args *gpiospec, u32 *flags) | |
804 | { | |
805 | if (WARN_ON(gc->of_gpio_n_cells < 1)) | |
806 | return -EINVAL; | |
807 | ||
808 | if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells)) | |
809 | return -EINVAL; | |
810 | ||
811 | if (gpiospec->args[0] > gc->ngpio) | |
812 | return -EINVAL; | |
813 | ||
814 | return gpiospec->args[0]; | |
815 | } | |
816 | ||
817 | /* Pinctrl Groups */ | |
818 | static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev) | |
819 | { | |
820 | struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
821 | ||
822 | return info->ngroups; | |
823 | } | |
824 | ||
825 | static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev, | |
826 | unsigned selector) | |
827 | { | |
828 | struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
829 | ||
830 | return info->groups[selector].name; | |
831 | } | |
832 | ||
833 | static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev, | |
834 | unsigned selector, const unsigned **pins, unsigned *npins) | |
835 | { | |
836 | struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
837 | ||
838 | if (selector >= info->ngroups) | |
839 | return -EINVAL; | |
840 | ||
841 | *pins = info->groups[selector].pins; | |
842 | *npins = info->groups[selector].npins; | |
843 | ||
844 | return 0; | |
845 | } | |
846 | ||
847 | static const inline struct st_pctl_group *st_pctl_find_group_by_name( | |
848 | const struct st_pinctrl *info, const char *name) | |
849 | { | |
850 | int i; | |
851 | ||
852 | for (i = 0; i < info->ngroups; i++) { | |
853 | if (!strcmp(info->groups[i].name, name)) | |
854 | return &info->groups[i]; | |
855 | } | |
856 | ||
857 | return NULL; | |
858 | } | |
859 | ||
860 | static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, | |
861 | struct device_node *np, struct pinctrl_map **map, unsigned *num_maps) | |
862 | { | |
863 | struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
864 | const struct st_pctl_group *grp; | |
865 | struct pinctrl_map *new_map; | |
866 | struct device_node *parent; | |
867 | int map_num, i; | |
868 | ||
869 | grp = st_pctl_find_group_by_name(info, np->name); | |
870 | if (!grp) { | |
871 | dev_err(info->dev, "unable to find group for node %s\n", | |
872 | np->name); | |
873 | return -EINVAL; | |
874 | } | |
875 | ||
876 | map_num = grp->npins + 1; | |
877 | new_map = devm_kzalloc(pctldev->dev, | |
878 | sizeof(*new_map) * map_num, GFP_KERNEL); | |
879 | if (!new_map) | |
880 | return -ENOMEM; | |
881 | ||
882 | parent = of_get_parent(np); | |
883 | if (!parent) { | |
884 | devm_kfree(pctldev->dev, new_map); | |
885 | return -EINVAL; | |
886 | } | |
887 | ||
888 | *map = new_map; | |
889 | *num_maps = map_num; | |
890 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; | |
891 | new_map[0].data.mux.function = parent->name; | |
892 | new_map[0].data.mux.group = np->name; | |
893 | of_node_put(parent); | |
894 | ||
895 | /* create config map per pin */ | |
896 | new_map++; | |
897 | for (i = 0; i < grp->npins; i++) { | |
898 | new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; | |
899 | new_map[i].data.configs.group_or_pin = | |
900 | pin_get_name(pctldev, grp->pins[i]); | |
901 | new_map[i].data.configs.configs = &grp->pin_conf[i].config; | |
902 | new_map[i].data.configs.num_configs = 1; | |
903 | } | |
904 | dev_info(pctldev->dev, "maps: function %s group %s num %d\n", | |
905 | (*map)->data.mux.function, grp->name, map_num); | |
906 | ||
907 | return 0; | |
908 | } | |
909 | ||
910 | static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev, | |
911 | struct pinctrl_map *map, unsigned num_maps) | |
912 | { | |
913 | } | |
914 | ||
915 | static struct pinctrl_ops st_pctlops = { | |
916 | .get_groups_count = st_pctl_get_groups_count, | |
917 | .get_group_pins = st_pctl_get_group_pins, | |
918 | .get_group_name = st_pctl_get_group_name, | |
919 | .dt_node_to_map = st_pctl_dt_node_to_map, | |
920 | .dt_free_map = st_pctl_dt_free_map, | |
921 | }; | |
922 | ||
923 | /* Pinmux */ | |
924 | static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev) | |
925 | { | |
926 | struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
927 | ||
928 | return info->nfunctions; | |
929 | } | |
930 | ||
ef75bfd5 | 931 | static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev, |
701016c0 SK |
932 | unsigned selector) |
933 | { | |
934 | struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
935 | ||
936 | return info->functions[selector].name; | |
937 | } | |
938 | ||
939 | static int st_pmx_get_groups(struct pinctrl_dev *pctldev, | |
940 | unsigned selector, const char * const **grps, unsigned * const ngrps) | |
941 | { | |
942 | struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
943 | *grps = info->functions[selector].groups; | |
944 | *ngrps = info->functions[selector].ngroups; | |
945 | ||
946 | return 0; | |
947 | } | |
948 | ||
03e9f0ca LW |
949 | static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector, |
950 | unsigned group) | |
701016c0 SK |
951 | { |
952 | struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
953 | struct st_pinconf *conf = info->groups[group].pin_conf; | |
954 | struct st_pio_control *pc; | |
955 | int i; | |
956 | ||
957 | for (i = 0; i < info->groups[group].npins; i++) { | |
958 | pc = st_get_pio_control(pctldev, conf[i].pin); | |
959 | st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc); | |
960 | } | |
961 | ||
962 | return 0; | |
963 | } | |
964 | ||
701016c0 SK |
965 | static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev, |
966 | struct pinctrl_gpio_range *range, unsigned gpio, | |
967 | bool input) | |
968 | { | |
969 | struct st_gpio_bank *bank = gpio_range_to_bank(range); | |
970 | /* | |
971 | * When a PIO bank is used in its primary function mode (altfunc = 0) | |
972 | * Output Enable (OE), Open Drain(OD), and Pull Up (PU) | |
973 | * for the primary PIO functions are driven by the related PIO block | |
974 | */ | |
975 | st_pctl_set_function(&bank->pc, gpio, 0); | |
976 | st_gpio_direction(bank, gpio, input ? | |
977 | ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT); | |
978 | ||
979 | return 0; | |
980 | } | |
981 | ||
982 | static struct pinmux_ops st_pmxops = { | |
983 | .get_functions_count = st_pmx_get_funcs_count, | |
984 | .get_function_name = st_pmx_get_fname, | |
985 | .get_function_groups = st_pmx_get_groups, | |
03e9f0ca | 986 | .set_mux = st_pmx_set_mux, |
701016c0 | 987 | .gpio_set_direction = st_pmx_set_gpio_direction, |
8ba5905c | 988 | .strict = true, |
701016c0 SK |
989 | }; |
990 | ||
991 | /* Pinconf */ | |
992 | static void st_pinconf_get_retime(struct st_pinctrl *info, | |
993 | struct st_pio_control *pc, int pin, unsigned long *config) | |
994 | { | |
995 | if (info->data->rt_style == st_retime_style_packed) | |
996 | st_pinconf_get_retime_packed(info, pc, pin, config); | |
997 | else if (info->data->rt_style == st_retime_style_dedicated) | |
998 | if ((BIT(pin) & pc->rt_pin_mask)) | |
999 | st_pinconf_get_retime_dedicated(info, pc, | |
1000 | pin, config); | |
1001 | } | |
1002 | ||
1003 | static void st_pinconf_set_retime(struct st_pinctrl *info, | |
1004 | struct st_pio_control *pc, int pin, unsigned long config) | |
1005 | { | |
1006 | if (info->data->rt_style == st_retime_style_packed) | |
1007 | st_pinconf_set_retime_packed(info, pc, config, pin); | |
1008 | else if (info->data->rt_style == st_retime_style_dedicated) | |
1009 | if ((BIT(pin) & pc->rt_pin_mask)) | |
1010 | st_pinconf_set_retime_dedicated(info, pc, | |
1011 | config, pin); | |
1012 | } | |
1013 | ||
03b054e9 SY |
1014 | static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id, |
1015 | unsigned long *configs, unsigned num_configs) | |
701016c0 SK |
1016 | { |
1017 | int pin = st_gpio_pin(pin_id); | |
1018 | struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
1019 | struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); | |
03b054e9 | 1020 | int i; |
701016c0 | 1021 | |
03b054e9 SY |
1022 | for (i = 0; i < num_configs; i++) { |
1023 | st_pinconf_set_config(pc, pin, configs[i]); | |
1024 | st_pinconf_set_retime(info, pc, pin, configs[i]); | |
1025 | } /* for each config */ | |
701016c0 SK |
1026 | |
1027 | return 0; | |
1028 | } | |
1029 | ||
1030 | static int st_pinconf_get(struct pinctrl_dev *pctldev, | |
1031 | unsigned pin_id, unsigned long *config) | |
1032 | { | |
1033 | int pin = st_gpio_pin(pin_id); | |
1034 | struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
1035 | struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); | |
1036 | ||
1037 | *config = 0; | |
1038 | st_pinconf_get_direction(pc, pin, config); | |
1039 | st_pinconf_get_retime(info, pc, pin, config); | |
1040 | ||
1041 | return 0; | |
1042 | } | |
1043 | ||
1044 | static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev, | |
1045 | struct seq_file *s, unsigned pin_id) | |
1046 | { | |
e2ed0e88 | 1047 | struct st_pio_control *pc; |
701016c0 | 1048 | unsigned long config; |
a8381fac | 1049 | unsigned int function; |
e2ed0e88 | 1050 | int offset = st_gpio_pin(pin_id); |
a8381fac | 1051 | char f[16]; |
701016c0 | 1052 | |
96d16c30 | 1053 | mutex_unlock(&pctldev->mutex); |
e2ed0e88 | 1054 | pc = st_get_pio_control(pctldev, pin_id); |
96d16c30 FV |
1055 | st_pinconf_get(pctldev, pin_id, &config); |
1056 | mutex_lock(&pctldev->mutex); | |
a8381fac LJ |
1057 | |
1058 | function = st_pctl_get_pin_function(pc, offset); | |
1059 | if (function) | |
1060 | snprintf(f, 10, "Alt Fn %d", function); | |
1061 | else | |
1062 | snprintf(f, 5, "GPIO"); | |
1063 | ||
1064 | seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n" | |
701016c0 SK |
1065 | "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld," |
1066 | "de:%ld,rt-clk:%ld,rt-delay:%ld]", | |
e2ed0e88 | 1067 | !st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset), |
701016c0 SK |
1068 | ST_PINCONF_UNPACK_PU(config), |
1069 | ST_PINCONF_UNPACK_OD(config), | |
a8381fac | 1070 | f, |
701016c0 SK |
1071 | ST_PINCONF_UNPACK_RT(config), |
1072 | ST_PINCONF_UNPACK_RT_INVERTCLK(config), | |
1073 | ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), | |
1074 | ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), | |
1075 | ST_PINCONF_UNPACK_RT_CLK(config), | |
1076 | ST_PINCONF_UNPACK_RT_DELAY(config)); | |
1077 | } | |
1078 | ||
1079 | static struct pinconf_ops st_confops = { | |
1080 | .pin_config_get = st_pinconf_get, | |
1081 | .pin_config_set = st_pinconf_set, | |
1082 | .pin_config_dbg_show = st_pinconf_dbg_show, | |
1083 | }; | |
1084 | ||
1085 | static void st_pctl_dt_child_count(struct st_pinctrl *info, | |
1086 | struct device_node *np) | |
1087 | { | |
1088 | struct device_node *child; | |
1089 | for_each_child_of_node(np, child) { | |
1090 | if (of_property_read_bool(child, "gpio-controller")) { | |
1091 | info->nbanks++; | |
1092 | } else { | |
1093 | info->nfunctions++; | |
1094 | info->ngroups += of_get_child_count(child); | |
1095 | } | |
1096 | } | |
1097 | } | |
1098 | ||
1099 | static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info, | |
1100 | int bank, struct st_pio_control *pc) | |
1101 | { | |
1102 | struct device *dev = info->dev; | |
1103 | struct regmap *rm = info->regmap; | |
1104 | const struct st_pctl_data *data = info->data; | |
1105 | /* 2 registers per bank */ | |
1106 | int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4; | |
1107 | struct st_retime_packed *rt_p = &pc->rt.rt_p; | |
1108 | /* cfg0 */ | |
1109 | struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg); | |
1110 | struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg); | |
1111 | struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg); | |
1112 | /* cfg1 */ | |
1113 | struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4); | |
1114 | struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4); | |
1115 | struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4); | |
1116 | struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4); | |
1117 | ||
1118 | rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0); | |
1119 | rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0); | |
1120 | rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1); | |
1121 | rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk); | |
1122 | rt_p->retime = devm_regmap_field_alloc(dev, rm, retime); | |
1123 | rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata); | |
1124 | rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge); | |
1125 | ||
1126 | if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) || | |
1127 | IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) || | |
1128 | IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) || | |
1129 | IS_ERR(rt_p->double_edge)) | |
1130 | return -EINVAL; | |
1131 | ||
1132 | return 0; | |
1133 | } | |
1134 | ||
1135 | static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info, | |
1136 | int bank, struct st_pio_control *pc) | |
1137 | { | |
1138 | struct device *dev = info->dev; | |
1139 | struct regmap *rm = info->regmap; | |
1140 | const struct st_pctl_data *data = info->data; | |
1141 | /* 8 registers per bank */ | |
1142 | int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; | |
1143 | struct st_retime_dedicated *rt_d = &pc->rt.rt_d; | |
1144 | unsigned int j; | |
1145 | u32 pin_mask = pc->rt_pin_mask; | |
1146 | ||
1147 | for (j = 0; j < RT_D_CFGS_PER_BANK; j++) { | |
1148 | if (BIT(j) & pin_mask) { | |
1149 | struct reg_field reg = REG_FIELD(reg_offset, 0, 31); | |
1150 | rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg); | |
1151 | if (IS_ERR(rt_d->rt[j])) | |
1152 | return -EINVAL; | |
1153 | reg_offset += 4; | |
1154 | } | |
1155 | } | |
1156 | return 0; | |
1157 | } | |
1158 | ||
1159 | static int st_pctl_dt_setup_retime(struct st_pinctrl *info, | |
1160 | int bank, struct st_pio_control *pc) | |
1161 | { | |
1162 | const struct st_pctl_data *data = info->data; | |
1163 | if (data->rt_style == st_retime_style_packed) | |
1164 | return st_pctl_dt_setup_retime_packed(info, bank, pc); | |
1165 | else if (data->rt_style == st_retime_style_dedicated) | |
1166 | return st_pctl_dt_setup_retime_dedicated(info, bank, pc); | |
1167 | ||
1168 | return -EINVAL; | |
1169 | } | |
1170 | ||
4e6a609f GC |
1171 | |
1172 | static struct regmap_field *st_pc_get_value(struct device *dev, | |
1173 | struct regmap *regmap, int bank, | |
1174 | int data, int lsb, int msb) | |
1175 | { | |
1176 | struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb); | |
1177 | ||
1178 | if (data < 0) | |
1179 | return NULL; | |
1180 | ||
1181 | return devm_regmap_field_alloc(dev, regmap, reg); | |
1182 | } | |
1183 | ||
1184 | static void st_parse_syscfgs(struct st_pinctrl *info, int bank, | |
1185 | struct device_node *np) | |
701016c0 SK |
1186 | { |
1187 | const struct st_pctl_data *data = info->data; | |
1188 | /** | |
1189 | * For a given shared register like OE/PU/OD, there are 8 bits per bank | |
1190 | * 0:7 belongs to bank0, 8:15 belongs to bank1 ... | |
1191 | * So each register is shared across 4 banks. | |
1192 | */ | |
1193 | int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK; | |
1194 | int msb = lsb + ST_GPIO_PINS_PER_BANK - 1; | |
701016c0 SK |
1195 | struct st_pio_control *pc = &info->banks[bank].pc; |
1196 | struct device *dev = info->dev; | |
1197 | struct regmap *regmap = info->regmap; | |
1198 | ||
4e6a609f GC |
1199 | pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31); |
1200 | pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb); | |
1201 | pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb); | |
1202 | pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb); | |
701016c0 SK |
1203 | |
1204 | /* retime avaiable for all pins by default */ | |
1205 | pc->rt_pin_mask = 0xff; | |
1206 | of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask); | |
1207 | st_pctl_dt_setup_retime(info, bank, pc); | |
1208 | ||
4e6a609f | 1209 | return; |
701016c0 SK |
1210 | } |
1211 | ||
1212 | /* | |
1213 | * Each pin is represented in of the below forms. | |
1214 | * <bank offset mux direction rt_type rt_delay rt_clk> | |
1215 | */ | |
1216 | static int st_pctl_dt_parse_groups(struct device_node *np, | |
1217 | struct st_pctl_group *grp, struct st_pinctrl *info, int idx) | |
1218 | { | |
1219 | /* bank pad direction val altfunction */ | |
1220 | const __be32 *list; | |
1221 | struct property *pp; | |
1222 | struct st_pinconf *conf; | |
701016c0 | 1223 | struct device_node *pins; |
701016c0 SK |
1224 | int i = 0, npins = 0, nr_props; |
1225 | ||
1226 | pins = of_get_child_by_name(np, "st,pins"); | |
1227 | if (!pins) | |
1228 | return -ENODATA; | |
1229 | ||
1230 | for_each_property_of_node(pins, pp) { | |
1231 | /* Skip those we do not want to proceed */ | |
1232 | if (!strcmp(pp->name, "name")) | |
1233 | continue; | |
1234 | ||
1235 | if (pp && (pp->length/sizeof(__be32)) >= OF_GPIO_ARGS_MIN) { | |
1236 | npins++; | |
1237 | } else { | |
1238 | pr_warn("Invalid st,pins in %s node\n", np->name); | |
1239 | return -EINVAL; | |
1240 | } | |
1241 | } | |
1242 | ||
1243 | grp->npins = npins; | |
1244 | grp->name = np->name; | |
1245 | grp->pins = devm_kzalloc(info->dev, npins * sizeof(u32), GFP_KERNEL); | |
1246 | grp->pin_conf = devm_kzalloc(info->dev, | |
1247 | npins * sizeof(*conf), GFP_KERNEL); | |
1248 | ||
1249 | if (!grp->pins || !grp->pin_conf) | |
1250 | return -ENOMEM; | |
1251 | ||
1252 | /* <bank offset mux direction rt_type rt_delay rt_clk> */ | |
1253 | for_each_property_of_node(pins, pp) { | |
1254 | if (!strcmp(pp->name, "name")) | |
1255 | continue; | |
1256 | nr_props = pp->length/sizeof(u32); | |
1257 | list = pp->value; | |
1258 | conf = &grp->pin_conf[i]; | |
1259 | ||
1260 | /* bank & offset */ | |
1f978217 RS |
1261 | be32_to_cpup(list++); |
1262 | be32_to_cpup(list++); | |
701016c0 SK |
1263 | conf->pin = of_get_named_gpio(pins, pp->name, 0); |
1264 | conf->name = pp->name; | |
1265 | grp->pins[i] = conf->pin; | |
1266 | /* mux */ | |
1267 | conf->altfunc = be32_to_cpup(list++); | |
1268 | conf->config = 0; | |
1269 | /* direction */ | |
1270 | conf->config |= be32_to_cpup(list++); | |
1271 | /* rt_type rt_delay rt_clk */ | |
1272 | if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) { | |
1273 | /* rt_type */ | |
1274 | conf->config |= be32_to_cpup(list++); | |
1275 | /* rt_delay */ | |
1276 | conf->config |= be32_to_cpup(list++); | |
1277 | /* rt_clk */ | |
1278 | if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) | |
1279 | conf->config |= be32_to_cpup(list++); | |
1280 | } | |
1281 | i++; | |
1282 | } | |
1283 | of_node_put(pins); | |
1284 | ||
1285 | return 0; | |
1286 | } | |
1287 | ||
1288 | static int st_pctl_parse_functions(struct device_node *np, | |
1289 | struct st_pinctrl *info, u32 index, int *grp_index) | |
1290 | { | |
1291 | struct device_node *child; | |
1292 | struct st_pmx_func *func; | |
1293 | struct st_pctl_group *grp; | |
1294 | int ret, i; | |
1295 | ||
1296 | func = &info->functions[index]; | |
1297 | func->name = np->name; | |
1298 | func->ngroups = of_get_child_count(np); | |
8b0c107c | 1299 | if (func->ngroups == 0) { |
701016c0 SK |
1300 | dev_err(info->dev, "No groups defined\n"); |
1301 | return -EINVAL; | |
1302 | } | |
1303 | func->groups = devm_kzalloc(info->dev, | |
1304 | func->ngroups * sizeof(char *), GFP_KERNEL); | |
1305 | if (!func->groups) | |
1306 | return -ENOMEM; | |
1307 | ||
1308 | i = 0; | |
1309 | for_each_child_of_node(np, child) { | |
1310 | func->groups[i] = child->name; | |
1311 | grp = &info->groups[*grp_index]; | |
1312 | *grp_index += 1; | |
1313 | ret = st_pctl_dt_parse_groups(child, grp, info, i++); | |
1314 | if (ret) | |
1315 | return ret; | |
1316 | } | |
1317 | dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n", | |
1318 | index, func->name, func->ngroups); | |
1319 | ||
1320 | return 0; | |
1321 | } | |
1322 | ||
727b0f71 SK |
1323 | static void st_gpio_irq_mask(struct irq_data *d) |
1324 | { | |
130cbe30 | 1325 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
2e862a7b | 1326 | struct st_gpio_bank *bank = gpiochip_get_data(gc); |
727b0f71 SK |
1327 | |
1328 | writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK); | |
1329 | } | |
1330 | ||
1331 | static void st_gpio_irq_unmask(struct irq_data *d) | |
1332 | { | |
130cbe30 | 1333 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
2e862a7b | 1334 | struct st_gpio_bank *bank = gpiochip_get_data(gc); |
727b0f71 SK |
1335 | |
1336 | writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK); | |
1337 | } | |
1338 | ||
727b0f71 SK |
1339 | static int st_gpio_irq_set_type(struct irq_data *d, unsigned type) |
1340 | { | |
130cbe30 | 1341 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
2e862a7b | 1342 | struct st_gpio_bank *bank = gpiochip_get_data(gc); |
727b0f71 SK |
1343 | unsigned long flags; |
1344 | int comp, pin = d->hwirq; | |
1345 | u32 val; | |
155795b9 | 1346 | u32 pin_edge_conf = 0; |
727b0f71 SK |
1347 | |
1348 | switch (type) { | |
1349 | case IRQ_TYPE_LEVEL_HIGH: | |
1350 | comp = 0; | |
1351 | break; | |
155795b9 SK |
1352 | case IRQ_TYPE_EDGE_FALLING: |
1353 | comp = 0; | |
1354 | pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin); | |
1355 | break; | |
727b0f71 SK |
1356 | case IRQ_TYPE_LEVEL_LOW: |
1357 | comp = 1; | |
1358 | break; | |
155795b9 SK |
1359 | case IRQ_TYPE_EDGE_RISING: |
1360 | comp = 1; | |
1361 | pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin); | |
1362 | break; | |
1363 | case IRQ_TYPE_EDGE_BOTH: | |
1364 | comp = st_gpio_get(&bank->gpio_chip, pin); | |
1365 | pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin); | |
1366 | break; | |
727b0f71 SK |
1367 | default: |
1368 | return -EINVAL; | |
1369 | } | |
1370 | ||
155795b9 SK |
1371 | spin_lock_irqsave(&bank->lock, flags); |
1372 | bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << ( | |
1373 | pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)); | |
1374 | bank->irq_edge_conf |= pin_edge_conf; | |
1375 | spin_unlock_irqrestore(&bank->lock, flags); | |
1376 | ||
727b0f71 SK |
1377 | val = readl(bank->base + REG_PIO_PCOMP); |
1378 | val &= ~BIT(pin); | |
1379 | val |= (comp << pin); | |
1380 | writel(val, bank->base + REG_PIO_PCOMP); | |
1381 | ||
1382 | return 0; | |
1383 | } | |
1384 | ||
155795b9 SK |
1385 | /* |
1386 | * As edge triggers are not supported at hardware level, it is supported by | |
1387 | * software by exploiting the level trigger support in hardware. | |
1388 | * | |
1389 | * Steps for detection raising edge interrupt in software. | |
1390 | * | |
1391 | * Step 1: CONFIGURE pin to detect level LOW interrupts. | |
1392 | * | |
1393 | * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler, | |
1394 | * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt. | |
1395 | * IGNORE calling the actual interrupt handler for the pin at this stage. | |
1396 | * | |
1397 | * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler | |
1398 | * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then | |
1399 | * DISPATCH the interrupt to the interrupt handler of the pin. | |
1400 | * | |
1401 | * step-1 ________ __________ | |
1402 | * | | step - 3 | |
1403 | * | | | |
1404 | * step -2 |_____| | |
1405 | * | |
1406 | * falling edge is also detected int the same way. | |
1407 | * | |
1408 | */ | |
727b0f71 SK |
1409 | static void __gpio_irq_handler(struct st_gpio_bank *bank) |
1410 | { | |
1411 | unsigned long port_in, port_mask, port_comp, active_irqs; | |
155795b9 SK |
1412 | unsigned long bank_edge_mask, flags; |
1413 | int n, val, ecfg; | |
1414 | ||
1415 | spin_lock_irqsave(&bank->lock, flags); | |
1416 | bank_edge_mask = bank->irq_edge_conf; | |
1417 | spin_unlock_irqrestore(&bank->lock, flags); | |
727b0f71 SK |
1418 | |
1419 | for (;;) { | |
1420 | port_in = readl(bank->base + REG_PIO_PIN); | |
1421 | port_comp = readl(bank->base + REG_PIO_PCOMP); | |
1422 | port_mask = readl(bank->base + REG_PIO_PMASK); | |
1423 | ||
1424 | active_irqs = (port_in ^ port_comp) & port_mask; | |
1425 | ||
1426 | if (active_irqs == 0) | |
1427 | break; | |
1428 | ||
1429 | for_each_set_bit(n, &active_irqs, BITS_PER_LONG) { | |
155795b9 SK |
1430 | /* check if we are detecting fake edges ... */ |
1431 | ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n); | |
1432 | ||
1433 | if (ecfg) { | |
1434 | /* edge detection. */ | |
1435 | val = st_gpio_get(&bank->gpio_chip, n); | |
1436 | ||
1437 | writel(BIT(n), | |
1438 | val ? bank->base + REG_PIO_SET_PCOMP : | |
1439 | bank->base + REG_PIO_CLR_PCOMP); | |
1440 | ||
1441 | if (ecfg != ST_IRQ_EDGE_BOTH && | |
1442 | !((ecfg & ST_IRQ_EDGE_FALLING) ^ val)) | |
1443 | continue; | |
1444 | } | |
1445 | ||
130cbe30 | 1446 | generic_handle_irq(irq_find_mapping(bank->gpio_chip.irqdomain, n)); |
727b0f71 SK |
1447 | } |
1448 | } | |
1449 | } | |
1450 | ||
bd0b9ac4 | 1451 | static void st_gpio_irq_handler(struct irq_desc *desc) |
727b0f71 SK |
1452 | { |
1453 | /* interrupt dedicated per bank */ | |
5663bb27 | 1454 | struct irq_chip *chip = irq_desc_get_chip(desc); |
130cbe30 | 1455 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
2e862a7b | 1456 | struct st_gpio_bank *bank = gpiochip_get_data(gc); |
727b0f71 SK |
1457 | |
1458 | chained_irq_enter(chip, desc); | |
1459 | __gpio_irq_handler(bank); | |
1460 | chained_irq_exit(chip, desc); | |
1461 | } | |
1462 | ||
bd0b9ac4 | 1463 | static void st_gpio_irqmux_handler(struct irq_desc *desc) |
727b0f71 | 1464 | { |
5663bb27 JL |
1465 | struct irq_chip *chip = irq_desc_get_chip(desc); |
1466 | struct st_pinctrl *info = irq_desc_get_handler_data(desc); | |
727b0f71 SK |
1467 | unsigned long status; |
1468 | int n; | |
1469 | ||
1470 | chained_irq_enter(chip, desc); | |
1471 | ||
1472 | status = readl(info->irqmux_base); | |
1473 | ||
7a2deccf | 1474 | for_each_set_bit(n, &status, info->nbanks) |
727b0f71 SK |
1475 | __gpio_irq_handler(&info->banks[n]); |
1476 | ||
1477 | chained_irq_exit(chip, desc); | |
1478 | } | |
1479 | ||
701016c0 | 1480 | static struct gpio_chip st_gpio_template = { |
98c85d58 JG |
1481 | .request = gpiochip_generic_request, |
1482 | .free = gpiochip_generic_free, | |
701016c0 SK |
1483 | .get = st_gpio_get, |
1484 | .set = st_gpio_set, | |
1485 | .direction_input = st_gpio_direction_input, | |
1486 | .direction_output = st_gpio_direction_output, | |
1e702ec2 | 1487 | .get_direction = st_gpio_get_direction, |
701016c0 SK |
1488 | .ngpio = ST_GPIO_PINS_PER_BANK, |
1489 | .of_gpio_n_cells = 1, | |
1490 | .of_xlate = st_gpio_xlate, | |
727b0f71 SK |
1491 | }; |
1492 | ||
1493 | static struct irq_chip st_gpio_irqchip = { | |
1494 | .name = "GPIO", | |
fce7fcc7 | 1495 | .irq_disable = st_gpio_irq_mask, |
727b0f71 SK |
1496 | .irq_mask = st_gpio_irq_mask, |
1497 | .irq_unmask = st_gpio_irq_unmask, | |
1498 | .irq_set_type = st_gpio_irq_set_type, | |
8708ebca | 1499 | .flags = IRQCHIP_SKIP_SET_WAKE, |
701016c0 SK |
1500 | }; |
1501 | ||
1502 | static int st_gpiolib_register_bank(struct st_pinctrl *info, | |
1503 | int bank_nr, struct device_node *np) | |
1504 | { | |
1505 | struct st_gpio_bank *bank = &info->banks[bank_nr]; | |
1506 | struct pinctrl_gpio_range *range = &bank->range; | |
1507 | struct device *dev = info->dev; | |
1508 | int bank_num = of_alias_get_id(np, "gpio"); | |
727b0f71 | 1509 | struct resource res, irq_res; |
130cbe30 | 1510 | int gpio_irq = 0, err; |
701016c0 SK |
1511 | |
1512 | if (of_address_to_resource(np, 0, &res)) | |
1513 | return -ENODEV; | |
1514 | ||
656445f3 SK |
1515 | bank->base = devm_ioremap_resource(dev, &res); |
1516 | if (IS_ERR(bank->base)) | |
1517 | return PTR_ERR(bank->base); | |
701016c0 SK |
1518 | |
1519 | bank->gpio_chip = st_gpio_template; | |
1520 | bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; | |
1521 | bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; | |
1522 | bank->gpio_chip.of_node = np; | |
58383c78 | 1523 | bank->gpio_chip.parent = dev; |
155795b9 | 1524 | spin_lock_init(&bank->lock); |
701016c0 SK |
1525 | |
1526 | of_property_read_string(np, "st,bank-name", &range->name); | |
1527 | bank->gpio_chip.label = range->name; | |
1528 | ||
1529 | range->id = bank_num; | |
1530 | range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK; | |
1531 | range->npins = bank->gpio_chip.ngpio; | |
1532 | range->gc = &bank->gpio_chip; | |
2e862a7b | 1533 | err = gpiochip_add_data(&bank->gpio_chip, bank); |
701016c0 SK |
1534 | if (err) { |
1535 | dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num); | |
1536 | return err; | |
1537 | } | |
1538 | dev_info(dev, "%s bank added.\n", range->name); | |
1539 | ||
727b0f71 SK |
1540 | /** |
1541 | * GPIO bank can have one of the two possible types of | |
1542 | * interrupt-wirings. | |
1543 | * | |
1544 | * First type is via irqmux, single interrupt is used by multiple | |
1545 | * gpio banks. This reduces number of overall interrupts numbers | |
1546 | * required. All these banks belong to a single pincontroller. | |
1547 | * _________ | |
1548 | * | |----> [gpio-bank (n) ] | |
1549 | * | |----> [gpio-bank (n + 1)] | |
1550 | * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] | |
1551 | * | |----> [gpio-bank (... )] | |
1552 | * |_________|----> [gpio-bank (n + 7)] | |
1553 | * | |
1554 | * Second type has a dedicated interrupt per each gpio bank. | |
1555 | * | |
1556 | * [irqN]----> [gpio-bank (n)] | |
1557 | */ | |
1558 | ||
bcca9220 | 1559 | if (of_irq_to_resource(np, 0, &irq_res)) { |
727b0f71 | 1560 | gpio_irq = irq_res.start; |
130cbe30 LW |
1561 | gpiochip_set_chained_irqchip(&bank->gpio_chip, &st_gpio_irqchip, |
1562 | gpio_irq, st_gpio_irq_handler); | |
727b0f71 SK |
1563 | } |
1564 | ||
2e537276 | 1565 | if (info->irqmux_base || gpio_irq > 0) { |
130cbe30 LW |
1566 | err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip, |
1567 | 0, handle_simple_irq, | |
1568 | IRQ_TYPE_LEVEL_LOW); | |
1569 | if (err) { | |
7471725f | 1570 | gpiochip_remove(&bank->gpio_chip); |
130cbe30 LW |
1571 | dev_info(dev, "could not add irqchip\n"); |
1572 | return err; | |
727b0f71 | 1573 | } |
727b0f71 SK |
1574 | } else { |
1575 | dev_info(dev, "No IRQ support for %s bank\n", np->full_name); | |
1576 | } | |
1577 | ||
701016c0 SK |
1578 | return 0; |
1579 | } | |
1580 | ||
baa9946e | 1581 | static const struct of_device_id st_pctl_of_match[] = { |
701016c0 SK |
1582 | { .compatible = "st,stih415-sbc-pinctrl", .data = &stih415_sbc_data }, |
1583 | { .compatible = "st,stih415-rear-pinctrl", .data = &stih415_rear_data }, | |
1584 | { .compatible = "st,stih415-left-pinctrl", .data = &stih415_left_data }, | |
1585 | { .compatible = "st,stih415-right-pinctrl", | |
1586 | .data = &stih415_right_data }, | |
1587 | { .compatible = "st,stih415-front-pinctrl", | |
1588 | .data = &stih415_front_data }, | |
1589 | { .compatible = "st,stih416-sbc-pinctrl", .data = &stih416_data}, | |
1590 | { .compatible = "st,stih416-front-pinctrl", .data = &stih416_data}, | |
1591 | { .compatible = "st,stih416-rear-pinctrl", .data = &stih416_data}, | |
1592 | { .compatible = "st,stih416-fvdp-fe-pinctrl", .data = &stih416_data}, | |
1593 | { .compatible = "st,stih416-fvdp-lite-pinctrl", .data = &stih416_data}, | |
7ce717db GC |
1594 | { .compatible = "st,stih407-sbc-pinctrl", .data = &stih416_data}, |
1595 | { .compatible = "st,stih407-front-pinctrl", .data = &stih416_data}, | |
1596 | { .compatible = "st,stih407-rear-pinctrl", .data = &stih416_data}, | |
1597 | { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata}, | |
701016c0 SK |
1598 | { /* sentinel */ } |
1599 | }; | |
1600 | ||
1601 | static int st_pctl_probe_dt(struct platform_device *pdev, | |
1602 | struct pinctrl_desc *pctl_desc, struct st_pinctrl *info) | |
1603 | { | |
1604 | int ret = 0; | |
1605 | int i = 0, j = 0, k = 0, bank; | |
1606 | struct pinctrl_pin_desc *pdesc; | |
1607 | struct device_node *np = pdev->dev.of_node; | |
1608 | struct device_node *child; | |
1609 | int grp_index = 0; | |
727b0f71 SK |
1610 | int irq = 0; |
1611 | struct resource *res; | |
701016c0 SK |
1612 | |
1613 | st_pctl_dt_child_count(info, np); | |
1614 | if (!info->nbanks) { | |
1615 | dev_err(&pdev->dev, "you need atleast one gpio bank\n"); | |
1616 | return -EINVAL; | |
1617 | } | |
1618 | ||
1619 | dev_info(&pdev->dev, "nbanks = %d\n", info->nbanks); | |
1620 | dev_info(&pdev->dev, "nfunctions = %d\n", info->nfunctions); | |
1621 | dev_info(&pdev->dev, "ngroups = %d\n", info->ngroups); | |
1622 | ||
1623 | info->functions = devm_kzalloc(&pdev->dev, | |
1624 | info->nfunctions * sizeof(*info->functions), GFP_KERNEL); | |
1625 | ||
1626 | info->groups = devm_kzalloc(&pdev->dev, | |
1627 | info->ngroups * sizeof(*info->groups) , GFP_KERNEL); | |
1628 | ||
1629 | info->banks = devm_kzalloc(&pdev->dev, | |
1630 | info->nbanks * sizeof(*info->banks), GFP_KERNEL); | |
1631 | ||
1632 | if (!info->functions || !info->groups || !info->banks) | |
1633 | return -ENOMEM; | |
1634 | ||
1635 | info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); | |
5c75acdc | 1636 | if (IS_ERR(info->regmap)) { |
701016c0 | 1637 | dev_err(info->dev, "No syscfg phandle specified\n"); |
5c75acdc | 1638 | return PTR_ERR(info->regmap); |
701016c0 SK |
1639 | } |
1640 | info->data = of_match_node(st_pctl_of_match, np)->data; | |
1641 | ||
727b0f71 SK |
1642 | irq = platform_get_irq(pdev, 0); |
1643 | ||
1644 | if (irq > 0) { | |
1645 | res = platform_get_resource_byname(pdev, | |
1646 | IORESOURCE_MEM, "irqmux"); | |
1647 | info->irqmux_base = devm_ioremap_resource(&pdev->dev, res); | |
1648 | ||
1649 | if (IS_ERR(info->irqmux_base)) | |
1650 | return PTR_ERR(info->irqmux_base); | |
1651 | ||
1b11b0cb TG |
1652 | irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler, |
1653 | info); | |
727b0f71 SK |
1654 | |
1655 | } | |
1656 | ||
701016c0 SK |
1657 | pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; |
1658 | pdesc = devm_kzalloc(&pdev->dev, | |
1659 | sizeof(*pdesc) * pctl_desc->npins, GFP_KERNEL); | |
1660 | if (!pdesc) | |
1661 | return -ENOMEM; | |
1662 | ||
1663 | pctl_desc->pins = pdesc; | |
1664 | ||
1665 | bank = 0; | |
1666 | for_each_child_of_node(np, child) { | |
1667 | if (of_property_read_bool(child, "gpio-controller")) { | |
1668 | const char *bank_name = NULL; | |
1669 | ret = st_gpiolib_register_bank(info, bank, child); | |
1670 | if (ret) | |
1671 | return ret; | |
1672 | ||
1673 | k = info->banks[bank].range.pin_base; | |
1674 | bank_name = info->banks[bank].range.name; | |
1675 | for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) { | |
1676 | pdesc->number = k; | |
1677 | pdesc->name = kasprintf(GFP_KERNEL, "%s[%d]", | |
1678 | bank_name, j); | |
1679 | pdesc++; | |
1680 | } | |
1681 | st_parse_syscfgs(info, bank, child); | |
1682 | bank++; | |
1683 | } else { | |
1684 | ret = st_pctl_parse_functions(child, info, | |
1685 | i++, &grp_index); | |
1686 | if (ret) { | |
1687 | dev_err(&pdev->dev, "No functions found.\n"); | |
1688 | return ret; | |
1689 | } | |
1690 | } | |
1691 | } | |
1692 | ||
1693 | return 0; | |
1694 | } | |
1695 | ||
1696 | static int st_pctl_probe(struct platform_device *pdev) | |
1697 | { | |
1698 | struct st_pinctrl *info; | |
1699 | struct pinctrl_desc *pctl_desc; | |
1700 | int ret, i; | |
1701 | ||
1702 | if (!pdev->dev.of_node) { | |
1703 | dev_err(&pdev->dev, "device node not found.\n"); | |
1704 | return -EINVAL; | |
1705 | } | |
1706 | ||
1707 | pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); | |
1708 | if (!pctl_desc) | |
1709 | return -ENOMEM; | |
1710 | ||
1711 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); | |
1712 | if (!info) | |
1713 | return -ENOMEM; | |
1714 | ||
1715 | info->dev = &pdev->dev; | |
1716 | platform_set_drvdata(pdev, info); | |
1717 | ret = st_pctl_probe_dt(pdev, pctl_desc, info); | |
1718 | if (ret) | |
1719 | return ret; | |
1720 | ||
c9dd66b7 SK |
1721 | pctl_desc->owner = THIS_MODULE; |
1722 | pctl_desc->pctlops = &st_pctlops; | |
1723 | pctl_desc->pmxops = &st_pmxops; | |
1724 | pctl_desc->confops = &st_confops; | |
701016c0 SK |
1725 | pctl_desc->name = dev_name(&pdev->dev); |
1726 | ||
e8e2cb23 | 1727 | info->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, info); |
323de9ef | 1728 | if (IS_ERR(info->pctl)) { |
701016c0 | 1729 | dev_err(&pdev->dev, "Failed pinctrl registration\n"); |
323de9ef | 1730 | return PTR_ERR(info->pctl); |
701016c0 SK |
1731 | } |
1732 | ||
1733 | for (i = 0; i < info->nbanks; i++) | |
1734 | pinctrl_add_gpio_range(info->pctl, &info->banks[i].range); | |
1735 | ||
1736 | return 0; | |
1737 | } | |
1738 | ||
1739 | static struct platform_driver st_pctl_driver = { | |
1740 | .driver = { | |
1741 | .name = "st-pinctrl", | |
539fde59 | 1742 | .of_match_table = st_pctl_of_match, |
701016c0 SK |
1743 | }, |
1744 | .probe = st_pctl_probe, | |
1745 | }; | |
1746 | ||
1747 | static int __init st_pctl_init(void) | |
1748 | { | |
1749 | return platform_driver_register(&st_pctl_driver); | |
1750 | } | |
1751 | arch_initcall(st_pctl_init); |