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701016c0 SK |
1 | /* |
2 | * Copyright (C) 2013 STMicroelectronics (R&D) Limited. | |
3 | * Authors: | |
4 | * Srinivas Kandagatla <srinivas.kandagatla@st.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/err.h> | |
15 | #include <linux/io.h> | |
727b0f71 SK |
16 | #include <linux/irq.h> |
17 | #include <linux/irqdesc.h> | |
18 | #include <linux/irqdomain.h> | |
19 | #include <linux/irqchip/chained_irq.h> | |
701016c0 | 20 | #include <linux/of.h> |
727b0f71 | 21 | #include <linux/of_irq.h> |
701016c0 SK |
22 | #include <linux/of_gpio.h> |
23 | #include <linux/of_address.h> | |
24 | #include <linux/regmap.h> | |
25 | #include <linux/mfd/syscon.h> | |
26 | #include <linux/pinctrl/pinctrl.h> | |
27 | #include <linux/pinctrl/pinmux.h> | |
28 | #include <linux/pinctrl/pinconf.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include "core.h" | |
31 | ||
32 | /* PIO Block registers */ | |
33 | /* PIO output */ | |
34 | #define REG_PIO_POUT 0x00 | |
35 | /* Set bits of POUT */ | |
36 | #define REG_PIO_SET_POUT 0x04 | |
37 | /* Clear bits of POUT */ | |
38 | #define REG_PIO_CLR_POUT 0x08 | |
39 | /* PIO input */ | |
40 | #define REG_PIO_PIN 0x10 | |
41 | /* PIO configuration */ | |
42 | #define REG_PIO_PC(n) (0x20 + (n) * 0x10) | |
43 | /* Set bits of PC[2:0] */ | |
44 | #define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10) | |
45 | /* Clear bits of PC[2:0] */ | |
46 | #define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10) | |
47 | /* PIO input comparison */ | |
48 | #define REG_PIO_PCOMP 0x50 | |
49 | /* Set bits of PCOMP */ | |
50 | #define REG_PIO_SET_PCOMP 0x54 | |
51 | /* Clear bits of PCOMP */ | |
52 | #define REG_PIO_CLR_PCOMP 0x58 | |
53 | /* PIO input comparison mask */ | |
54 | #define REG_PIO_PMASK 0x60 | |
55 | /* Set bits of PMASK */ | |
56 | #define REG_PIO_SET_PMASK 0x64 | |
57 | /* Clear bits of PMASK */ | |
58 | #define REG_PIO_CLR_PMASK 0x68 | |
59 | ||
60 | #define ST_GPIO_DIRECTION_BIDIR 0x1 | |
61 | #define ST_GPIO_DIRECTION_OUT 0x2 | |
62 | #define ST_GPIO_DIRECTION_IN 0x4 | |
63 | ||
64 | /** | |
65 | * Packed style retime configuration. | |
66 | * There are two registers cfg0 and cfg1 in this style for each bank. | |
67 | * Each field in this register is 8 bit corresponding to 8 pins in the bank. | |
68 | */ | |
69 | #define RT_P_CFGS_PER_BANK 2 | |
70 | #define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7) | |
71 | #define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23) | |
72 | #define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31) | |
73 | #define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7) | |
74 | #define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15) | |
75 | #define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23) | |
76 | #define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31) | |
77 | ||
78 | /** | |
79 | * Dedicated style retime Configuration register | |
80 | * each register is dedicated per pin. | |
81 | */ | |
82 | #define RT_D_CFGS_PER_BANK 8 | |
83 | #define RT_D_CFG_CLK_SHIFT 0 | |
84 | #define RT_D_CFG_CLK_MASK (0x3 << 0) | |
85 | #define RT_D_CFG_CLKNOTDATA_SHIFT 2 | |
86 | #define RT_D_CFG_CLKNOTDATA_MASK BIT(2) | |
87 | #define RT_D_CFG_DELAY_SHIFT 3 | |
88 | #define RT_D_CFG_DELAY_MASK (0xf << 3) | |
89 | #define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7 | |
90 | #define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7) | |
91 | #define RT_D_CFG_DOUBLE_EDGE_SHIFT 8 | |
92 | #define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8) | |
93 | #define RT_D_CFG_INVERTCLK_SHIFT 9 | |
94 | #define RT_D_CFG_INVERTCLK_MASK BIT(9) | |
95 | #define RT_D_CFG_RETIME_SHIFT 10 | |
96 | #define RT_D_CFG_RETIME_MASK BIT(10) | |
97 | ||
98 | /* | |
99 | * Pinconf is represented in an opaque unsigned long variable. | |
100 | * Below is the bit allocation details for each possible configuration. | |
101 | * All the bit fields can be encapsulated into four variables | |
102 | * (direction, retime-type, retime-clk, retime-delay) | |
103 | * | |
104 | * +----------------+ | |
105 | *[31:28]| reserved-3 | | |
106 | * +----------------+------------- | |
107 | *[27] | oe | | | |
108 | * +----------------+ v | |
109 | *[26] | pu | [Direction ] | |
110 | * +----------------+ ^ | |
111 | *[25] | od | | | |
112 | * +----------------+------------- | |
113 | *[24] | reserved-2 | | |
114 | * +----------------+------------- | |
115 | *[23] | retime | | | |
116 | * +----------------+ | | |
117 | *[22] | retime-invclk | | | |
118 | * +----------------+ v | |
119 | *[21] |retime-clknotdat| [Retime-type ] | |
120 | * +----------------+ ^ | |
121 | *[20] | retime-de | | | |
122 | * +----------------+------------- | |
123 | *[19:18]| retime-clk |------>[Retime-Clk ] | |
124 | * +----------------+ | |
125 | *[17:16]| reserved-1 | | |
126 | * +----------------+ | |
127 | *[15..0]| retime-delay |------>[Retime Delay] | |
128 | * +----------------+ | |
129 | */ | |
130 | ||
131 | #define ST_PINCONF_UNPACK(conf, param)\ | |
132 | ((conf >> ST_PINCONF_ ##param ##_SHIFT) \ | |
133 | & ST_PINCONF_ ##param ##_MASK) | |
134 | ||
135 | #define ST_PINCONF_PACK(conf, val, param) (conf |=\ | |
136 | ((val & ST_PINCONF_ ##param ##_MASK) << \ | |
137 | ST_PINCONF_ ##param ##_SHIFT)) | |
138 | ||
139 | /* Output enable */ | |
140 | #define ST_PINCONF_OE_MASK 0x1 | |
141 | #define ST_PINCONF_OE_SHIFT 27 | |
142 | #define ST_PINCONF_OE BIT(27) | |
143 | #define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE) | |
144 | #define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE) | |
145 | ||
146 | /* Pull Up */ | |
147 | #define ST_PINCONF_PU_MASK 0x1 | |
148 | #define ST_PINCONF_PU_SHIFT 26 | |
149 | #define ST_PINCONF_PU BIT(26) | |
150 | #define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU) | |
151 | #define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU) | |
152 | ||
153 | /* Open Drain */ | |
154 | #define ST_PINCONF_OD_MASK 0x1 | |
155 | #define ST_PINCONF_OD_SHIFT 25 | |
156 | #define ST_PINCONF_OD BIT(25) | |
157 | #define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD) | |
158 | #define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD) | |
159 | ||
160 | #define ST_PINCONF_RT_MASK 0x1 | |
161 | #define ST_PINCONF_RT_SHIFT 23 | |
162 | #define ST_PINCONF_RT BIT(23) | |
163 | #define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT) | |
164 | #define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT) | |
165 | ||
166 | #define ST_PINCONF_RT_INVERTCLK_MASK 0x1 | |
167 | #define ST_PINCONF_RT_INVERTCLK_SHIFT 22 | |
168 | #define ST_PINCONF_RT_INVERTCLK BIT(22) | |
169 | #define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \ | |
170 | ST_PINCONF_UNPACK(conf, RT_INVERTCLK) | |
171 | #define ST_PINCONF_PACK_RT_INVERTCLK(conf) \ | |
172 | ST_PINCONF_PACK(conf, 1, RT_INVERTCLK) | |
173 | ||
174 | #define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1 | |
175 | #define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21 | |
176 | #define ST_PINCONF_RT_CLKNOTDATA BIT(21) | |
177 | #define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \ | |
178 | ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA) | |
179 | #define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \ | |
180 | ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA) | |
181 | ||
182 | #define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1 | |
183 | #define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20 | |
184 | #define ST_PINCONF_RT_DOUBLE_EDGE BIT(20) | |
185 | #define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \ | |
186 | ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE) | |
187 | #define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \ | |
188 | ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE) | |
189 | ||
190 | #define ST_PINCONF_RT_CLK_MASK 0x3 | |
191 | #define ST_PINCONF_RT_CLK_SHIFT 18 | |
192 | #define ST_PINCONF_RT_CLK BIT(18) | |
193 | #define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK) | |
194 | #define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK) | |
195 | ||
196 | /* RETIME_DELAY in Pico Secs */ | |
197 | #define ST_PINCONF_RT_DELAY_MASK 0xffff | |
198 | #define ST_PINCONF_RT_DELAY_SHIFT 0 | |
199 | #define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY) | |
200 | #define ST_PINCONF_PACK_RT_DELAY(conf, val) \ | |
201 | ST_PINCONF_PACK(conf, val, RT_DELAY) | |
202 | ||
203 | #define ST_GPIO_PINS_PER_BANK (8) | |
204 | #define OF_GPIO_ARGS_MIN (4) | |
205 | #define OF_RT_ARGS_MIN (2) | |
206 | ||
207 | #define gpio_range_to_bank(chip) \ | |
208 | container_of(chip, struct st_gpio_bank, range) | |
209 | ||
210 | #define gpio_chip_to_bank(chip) \ | |
211 | container_of(chip, struct st_gpio_bank, gpio_chip) | |
212 | ||
213 | ||
214 | enum st_retime_style { | |
215 | st_retime_style_none, | |
216 | st_retime_style_packed, | |
217 | st_retime_style_dedicated, | |
218 | }; | |
219 | ||
220 | struct st_retime_dedicated { | |
221 | struct regmap_field *rt[ST_GPIO_PINS_PER_BANK]; | |
222 | }; | |
223 | ||
224 | struct st_retime_packed { | |
225 | struct regmap_field *clk1notclk0; | |
226 | struct regmap_field *delay_0; | |
227 | struct regmap_field *delay_1; | |
228 | struct regmap_field *invertclk; | |
229 | struct regmap_field *retime; | |
230 | struct regmap_field *clknotdata; | |
231 | struct regmap_field *double_edge; | |
232 | }; | |
233 | ||
234 | struct st_pio_control { | |
235 | u32 rt_pin_mask; | |
236 | struct regmap_field *alt, *oe, *pu, *od; | |
237 | /* retiming */ | |
238 | union { | |
239 | struct st_retime_packed rt_p; | |
240 | struct st_retime_dedicated rt_d; | |
241 | } rt; | |
242 | }; | |
243 | ||
244 | struct st_pctl_data { | |
245 | enum st_retime_style rt_style; | |
246 | unsigned int *input_delays; | |
247 | int ninput_delays; | |
248 | unsigned int *output_delays; | |
249 | int noutput_delays; | |
250 | /* register offset information */ | |
251 | int alt, oe, pu, od, rt; | |
252 | }; | |
253 | ||
254 | struct st_pinconf { | |
255 | int pin; | |
256 | const char *name; | |
257 | unsigned long config; | |
258 | int altfunc; | |
259 | }; | |
260 | ||
261 | struct st_pmx_func { | |
262 | const char *name; | |
263 | const char **groups; | |
264 | unsigned ngroups; | |
265 | }; | |
266 | ||
267 | struct st_pctl_group { | |
268 | const char *name; | |
269 | unsigned int *pins; | |
270 | unsigned npins; | |
271 | struct st_pinconf *pin_conf; | |
272 | }; | |
273 | ||
155795b9 SK |
274 | /* |
275 | * Edge triggers are not supported at hardware level, it is supported by | |
276 | * software by exploiting the level trigger support in hardware. | |
277 | * Software uses a virtual register (EDGE_CONF) for edge trigger configuration | |
278 | * of each gpio pin in a GPIO bank. | |
279 | * | |
280 | * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of | |
281 | * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank. | |
282 | * | |
283 | * bit allocation per pin is: | |
284 | * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31] | |
285 | * -------------------------------------------------------- | |
286 | * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 | | |
287 | * -------------------------------------------------------- | |
288 | * | |
289 | * A pin can have one of following the values in its edge configuration field. | |
290 | * | |
291 | * ------- ---------------------------- | |
292 | * [0-3] - Description | |
293 | * ------- ---------------------------- | |
294 | * 0000 - No edge IRQ. | |
295 | * 0001 - Falling edge IRQ. | |
296 | * 0010 - Rising edge IRQ. | |
297 | * 0011 - Rising and Falling edge IRQ. | |
298 | * ------- ---------------------------- | |
299 | */ | |
300 | ||
301 | #define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4 | |
302 | #define ST_IRQ_EDGE_MASK 0xf | |
303 | #define ST_IRQ_EDGE_FALLING BIT(0) | |
304 | #define ST_IRQ_EDGE_RISING BIT(1) | |
305 | #define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1)) | |
306 | ||
307 | #define ST_IRQ_RISING_EDGE_CONF(pin) \ | |
308 | (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) | |
309 | ||
310 | #define ST_IRQ_FALLING_EDGE_CONF(pin) \ | |
311 | (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) | |
312 | ||
313 | #define ST_IRQ_BOTH_EDGE_CONF(pin) \ | |
314 | (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) | |
315 | ||
316 | #define ST_IRQ_EDGE_CONF(conf, pin) \ | |
317 | (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK) | |
318 | ||
701016c0 SK |
319 | struct st_gpio_bank { |
320 | struct gpio_chip gpio_chip; | |
321 | struct pinctrl_gpio_range range; | |
322 | void __iomem *base; | |
323 | struct st_pio_control pc; | |
727b0f71 | 324 | struct irq_domain *domain; |
155795b9 SK |
325 | unsigned long irq_edge_conf; |
326 | spinlock_t lock; | |
701016c0 SK |
327 | }; |
328 | ||
329 | struct st_pinctrl { | |
330 | struct device *dev; | |
331 | struct pinctrl_dev *pctl; | |
332 | struct st_gpio_bank *banks; | |
333 | int nbanks; | |
334 | struct st_pmx_func *functions; | |
335 | int nfunctions; | |
336 | struct st_pctl_group *groups; | |
337 | int ngroups; | |
338 | struct regmap *regmap; | |
339 | const struct st_pctl_data *data; | |
727b0f71 | 340 | void __iomem *irqmux_base; |
701016c0 SK |
341 | }; |
342 | ||
343 | /* SOC specific data */ | |
344 | /* STiH415 data */ | |
ef75bfd5 SK |
345 | static unsigned int stih415_input_delays[] = {0, 500, 1000, 1500}; |
346 | static unsigned int stih415_output_delays[] = {0, 1000, 2000, 3000}; | |
701016c0 SK |
347 | |
348 | #define STIH415_PCTRL_COMMON_DATA \ | |
349 | .rt_style = st_retime_style_packed, \ | |
350 | .input_delays = stih415_input_delays, \ | |
351 | .ninput_delays = 4, \ | |
352 | .output_delays = stih415_output_delays, \ | |
353 | .noutput_delays = 4 | |
354 | ||
355 | static const struct st_pctl_data stih415_sbc_data = { | |
356 | STIH415_PCTRL_COMMON_DATA, | |
357 | .alt = 0, .oe = 5, .pu = 7, .od = 9, .rt = 16, | |
358 | }; | |
359 | ||
360 | static const struct st_pctl_data stih415_front_data = { | |
361 | STIH415_PCTRL_COMMON_DATA, | |
362 | .alt = 0, .oe = 8, .pu = 10, .od = 12, .rt = 16, | |
363 | }; | |
364 | ||
365 | static const struct st_pctl_data stih415_rear_data = { | |
366 | STIH415_PCTRL_COMMON_DATA, | |
367 | .alt = 0, .oe = 6, .pu = 8, .od = 10, .rt = 38, | |
368 | }; | |
369 | ||
370 | static const struct st_pctl_data stih415_left_data = { | |
371 | STIH415_PCTRL_COMMON_DATA, | |
372 | .alt = 0, .oe = 3, .pu = 4, .od = 5, .rt = 6, | |
373 | }; | |
374 | ||
375 | static const struct st_pctl_data stih415_right_data = { | |
376 | STIH415_PCTRL_COMMON_DATA, | |
377 | .alt = 0, .oe = 5, .pu = 7, .od = 9, .rt = 11, | |
378 | }; | |
379 | ||
380 | /* STiH416 data */ | |
ef75bfd5 | 381 | static unsigned int stih416_delays[] = {0, 300, 500, 750, 1000, 1250, 1500, |
701016c0 SK |
382 | 1750, 2000, 2250, 2500, 2750, 3000, 3250 }; |
383 | ||
384 | static const struct st_pctl_data stih416_data = { | |
385 | .rt_style = st_retime_style_dedicated, | |
386 | .input_delays = stih416_delays, | |
387 | .ninput_delays = 14, | |
388 | .output_delays = stih416_delays, | |
389 | .noutput_delays = 14, | |
390 | .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100, | |
391 | }; | |
392 | ||
7ce717db GC |
393 | static const struct st_pctl_data stih407_flashdata = { |
394 | .rt_style = st_retime_style_none, | |
395 | .input_delays = stih416_delays, | |
396 | .ninput_delays = ARRAY_SIZE(stih416_delays), | |
397 | .output_delays = stih416_delays, | |
398 | .noutput_delays = ARRAY_SIZE(stih416_delays), | |
399 | .alt = 0, | |
400 | .oe = -1, /* Not Available */ | |
401 | .pu = -1, /* Not Available */ | |
402 | .od = 60, | |
403 | .rt = 100, | |
404 | }; | |
405 | ||
701016c0 SK |
406 | /* Low level functions.. */ |
407 | static inline int st_gpio_bank(int gpio) | |
408 | { | |
409 | return gpio/ST_GPIO_PINS_PER_BANK; | |
410 | } | |
411 | ||
412 | static inline int st_gpio_pin(int gpio) | |
413 | { | |
414 | return gpio%ST_GPIO_PINS_PER_BANK; | |
415 | } | |
416 | ||
417 | static void st_pinconf_set_config(struct st_pio_control *pc, | |
418 | int pin, unsigned long config) | |
419 | { | |
420 | struct regmap_field *output_enable = pc->oe; | |
421 | struct regmap_field *pull_up = pc->pu; | |
422 | struct regmap_field *open_drain = pc->od; | |
423 | unsigned int oe_value, pu_value, od_value; | |
424 | unsigned long mask = BIT(pin); | |
425 | ||
4e6a609f GC |
426 | if (output_enable) { |
427 | regmap_field_read(output_enable, &oe_value); | |
428 | oe_value &= ~mask; | |
429 | if (config & ST_PINCONF_OE) | |
430 | oe_value |= mask; | |
431 | regmap_field_write(output_enable, oe_value); | |
432 | } | |
433 | ||
434 | if (pull_up) { | |
435 | regmap_field_read(pull_up, &pu_value); | |
436 | pu_value &= ~mask; | |
437 | if (config & ST_PINCONF_PU) | |
438 | pu_value |= mask; | |
439 | regmap_field_write(pull_up, pu_value); | |
440 | } | |
441 | ||
442 | if (open_drain) { | |
443 | regmap_field_read(open_drain, &od_value); | |
444 | od_value &= ~mask; | |
445 | if (config & ST_PINCONF_OD) | |
446 | od_value |= mask; | |
447 | regmap_field_write(open_drain, od_value); | |
448 | } | |
701016c0 SK |
449 | } |
450 | ||
451 | static void st_pctl_set_function(struct st_pio_control *pc, | |
452 | int pin_id, int function) | |
453 | { | |
454 | struct regmap_field *alt = pc->alt; | |
455 | unsigned int val; | |
456 | int pin = st_gpio_pin(pin_id); | |
457 | int offset = pin * 4; | |
458 | ||
4e6a609f GC |
459 | if (!alt) |
460 | return; | |
461 | ||
701016c0 SK |
462 | regmap_field_read(alt, &val); |
463 | val &= ~(0xf << offset); | |
464 | val |= function << offset; | |
465 | regmap_field_write(alt, val); | |
466 | } | |
467 | ||
468 | static unsigned long st_pinconf_delay_to_bit(unsigned int delay, | |
469 | const struct st_pctl_data *data, unsigned long config) | |
470 | { | |
471 | unsigned int *delay_times; | |
472 | int num_delay_times, i, closest_index = -1; | |
473 | unsigned int closest_divergence = UINT_MAX; | |
474 | ||
475 | if (ST_PINCONF_UNPACK_OE(config)) { | |
476 | delay_times = data->output_delays; | |
477 | num_delay_times = data->noutput_delays; | |
478 | } else { | |
479 | delay_times = data->input_delays; | |
480 | num_delay_times = data->ninput_delays; | |
481 | } | |
482 | ||
483 | for (i = 0; i < num_delay_times; i++) { | |
484 | unsigned int divergence = abs(delay - delay_times[i]); | |
485 | ||
486 | if (divergence == 0) | |
487 | return i; | |
488 | ||
489 | if (divergence < closest_divergence) { | |
490 | closest_divergence = divergence; | |
491 | closest_index = i; | |
492 | } | |
493 | } | |
494 | ||
495 | pr_warn("Attempt to set delay %d, closest available %d\n", | |
496 | delay, delay_times[closest_index]); | |
497 | ||
498 | return closest_index; | |
499 | } | |
500 | ||
501 | static unsigned long st_pinconf_bit_to_delay(unsigned int index, | |
502 | const struct st_pctl_data *data, unsigned long output) | |
503 | { | |
504 | unsigned int *delay_times; | |
505 | int num_delay_times; | |
506 | ||
507 | if (output) { | |
508 | delay_times = data->output_delays; | |
509 | num_delay_times = data->noutput_delays; | |
510 | } else { | |
511 | delay_times = data->input_delays; | |
512 | num_delay_times = data->ninput_delays; | |
513 | } | |
514 | ||
515 | if (index < num_delay_times) { | |
516 | return delay_times[index]; | |
517 | } else { | |
518 | pr_warn("Delay not found in/out delay list\n"); | |
519 | return 0; | |
520 | } | |
521 | } | |
522 | ||
523 | static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field, | |
524 | int enable, int pin) | |
525 | { | |
526 | unsigned int val = 0; | |
527 | ||
528 | regmap_field_read(field, &val); | |
529 | if (enable) | |
530 | val |= BIT(pin); | |
531 | else | |
532 | val &= ~BIT(pin); | |
533 | regmap_field_write(field, val); | |
534 | } | |
535 | ||
536 | static void st_pinconf_set_retime_packed(struct st_pinctrl *info, | |
537 | struct st_pio_control *pc, unsigned long config, int pin) | |
538 | { | |
539 | const struct st_pctl_data *data = info->data; | |
540 | struct st_retime_packed *rt_p = &pc->rt.rt_p; | |
541 | unsigned int delay; | |
542 | ||
543 | st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0, | |
544 | ST_PINCONF_UNPACK_RT_CLK(config), pin); | |
545 | ||
546 | st_regmap_field_bit_set_clear_pin(rt_p->clknotdata, | |
547 | ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin); | |
548 | ||
549 | st_regmap_field_bit_set_clear_pin(rt_p->double_edge, | |
550 | ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin); | |
551 | ||
552 | st_regmap_field_bit_set_clear_pin(rt_p->invertclk, | |
553 | ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin); | |
554 | ||
555 | st_regmap_field_bit_set_clear_pin(rt_p->retime, | |
556 | ST_PINCONF_UNPACK_RT(config), pin); | |
557 | ||
558 | delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config), | |
559 | data, config); | |
560 | /* 2 bit delay, lsb */ | |
561 | st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin); | |
562 | /* 2 bit delay, msb */ | |
563 | st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin); | |
564 | ||
565 | } | |
566 | ||
567 | static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info, | |
568 | struct st_pio_control *pc, unsigned long config, int pin) | |
569 | { | |
570 | int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1; | |
571 | int clk = ST_PINCONF_UNPACK_RT_CLK(config); | |
572 | int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config); | |
573 | int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config); | |
574 | int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config); | |
575 | int retime = ST_PINCONF_UNPACK_RT(config); | |
576 | ||
577 | unsigned long delay = st_pinconf_delay_to_bit( | |
578 | ST_PINCONF_UNPACK_RT_DELAY(config), | |
579 | info->data, config); | |
580 | struct st_retime_dedicated *rt_d = &pc->rt.rt_d; | |
581 | ||
582 | unsigned long retime_config = | |
583 | ((clk) << RT_D_CFG_CLK_SHIFT) | | |
584 | ((delay) << RT_D_CFG_DELAY_SHIFT) | | |
585 | ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) | | |
586 | ((retime) << RT_D_CFG_RETIME_SHIFT) | | |
587 | ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) | | |
588 | ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) | | |
589 | ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT); | |
590 | ||
591 | regmap_field_write(rt_d->rt[pin], retime_config); | |
592 | } | |
593 | ||
594 | static void st_pinconf_get_direction(struct st_pio_control *pc, | |
595 | int pin, unsigned long *config) | |
596 | { | |
597 | unsigned int oe_value, pu_value, od_value; | |
598 | ||
4e6a609f GC |
599 | if (pc->oe) { |
600 | regmap_field_read(pc->oe, &oe_value); | |
601 | if (oe_value & BIT(pin)) | |
602 | ST_PINCONF_PACK_OE(*config); | |
603 | } | |
701016c0 | 604 | |
4e6a609f GC |
605 | if (pc->pu) { |
606 | regmap_field_read(pc->pu, &pu_value); | |
607 | if (pu_value & BIT(pin)) | |
608 | ST_PINCONF_PACK_PU(*config); | |
609 | } | |
701016c0 | 610 | |
4e6a609f GC |
611 | if (pc->od) { |
612 | regmap_field_read(pc->od, &od_value); | |
613 | if (od_value & BIT(pin)) | |
614 | ST_PINCONF_PACK_OD(*config); | |
615 | } | |
701016c0 SK |
616 | } |
617 | ||
618 | static int st_pinconf_get_retime_packed(struct st_pinctrl *info, | |
619 | struct st_pio_control *pc, int pin, unsigned long *config) | |
620 | { | |
621 | const struct st_pctl_data *data = info->data; | |
622 | struct st_retime_packed *rt_p = &pc->rt.rt_p; | |
623 | unsigned int delay_bits, delay, delay0, delay1, val; | |
624 | int output = ST_PINCONF_UNPACK_OE(*config); | |
625 | ||
626 | if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin))) | |
627 | ST_PINCONF_PACK_RT(*config); | |
628 | ||
629 | if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin))) | |
630 | ST_PINCONF_PACK_RT_CLK(*config, 1); | |
631 | ||
632 | if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin))) | |
633 | ST_PINCONF_PACK_RT_CLKNOTDATA(*config); | |
634 | ||
635 | if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin))) | |
636 | ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); | |
637 | ||
638 | if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin))) | |
639 | ST_PINCONF_PACK_RT_INVERTCLK(*config); | |
640 | ||
641 | regmap_field_read(rt_p->delay_0, &delay0); | |
642 | regmap_field_read(rt_p->delay_1, &delay1); | |
643 | delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) | | |
644 | (((delay0 & BIT(pin)) ? 1 : 0)); | |
645 | delay = st_pinconf_bit_to_delay(delay_bits, data, output); | |
646 | ST_PINCONF_PACK_RT_DELAY(*config, delay); | |
647 | ||
648 | return 0; | |
649 | } | |
650 | ||
651 | static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info, | |
652 | struct st_pio_control *pc, int pin, unsigned long *config) | |
653 | { | |
654 | unsigned int value; | |
655 | unsigned long delay_bits, delay, rt_clk; | |
656 | int output = ST_PINCONF_UNPACK_OE(*config); | |
657 | struct st_retime_dedicated *rt_d = &pc->rt.rt_d; | |
658 | ||
659 | regmap_field_read(rt_d->rt[pin], &value); | |
660 | ||
661 | rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT; | |
662 | ST_PINCONF_PACK_RT_CLK(*config, rt_clk); | |
663 | ||
664 | delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT; | |
665 | delay = st_pinconf_bit_to_delay(delay_bits, info->data, output); | |
666 | ST_PINCONF_PACK_RT_DELAY(*config, delay); | |
667 | ||
668 | if (value & RT_D_CFG_CLKNOTDATA_MASK) | |
669 | ST_PINCONF_PACK_RT_CLKNOTDATA(*config); | |
670 | ||
671 | if (value & RT_D_CFG_DOUBLE_EDGE_MASK) | |
672 | ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); | |
673 | ||
674 | if (value & RT_D_CFG_INVERTCLK_MASK) | |
675 | ST_PINCONF_PACK_RT_INVERTCLK(*config); | |
676 | ||
677 | if (value & RT_D_CFG_RETIME_MASK) | |
678 | ST_PINCONF_PACK_RT(*config); | |
679 | ||
680 | return 0; | |
681 | } | |
682 | ||
683 | /* GPIO related functions */ | |
684 | ||
685 | static inline void __st_gpio_set(struct st_gpio_bank *bank, | |
686 | unsigned offset, int value) | |
687 | { | |
688 | if (value) | |
689 | writel(BIT(offset), bank->base + REG_PIO_SET_POUT); | |
690 | else | |
691 | writel(BIT(offset), bank->base + REG_PIO_CLR_POUT); | |
692 | } | |
693 | ||
694 | static void st_gpio_direction(struct st_gpio_bank *bank, | |
695 | unsigned int gpio, unsigned int direction) | |
696 | { | |
697 | int offset = st_gpio_pin(gpio); | |
698 | int i = 0; | |
699 | /** | |
700 | * There are three configuration registers (PIOn_PC0, PIOn_PC1 | |
701 | * and PIOn_PC2) for each port. These are used to configure the | |
702 | * PIO port pins. Each pin can be configured as an input, output, | |
703 | * bidirectional, or alternative function pin. Three bits, one bit | |
704 | * from each of the three registers, configure the corresponding bit of | |
705 | * the port. Valid bit settings is: | |
706 | * | |
707 | * PC2 PC1 PC0 Direction. | |
708 | * 0 0 0 [Input Weak pull-up] | |
709 | * 0 0 or 1 1 [Bidirection] | |
710 | * 0 1 0 [Output] | |
711 | * 1 0 0 [Input] | |
712 | * | |
713 | * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits | |
714 | * individually. | |
715 | */ | |
716 | for (i = 0; i <= 2; i++) { | |
717 | if (direction & BIT(i)) | |
718 | writel(BIT(offset), bank->base + REG_PIO_SET_PC(i)); | |
719 | else | |
720 | writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i)); | |
721 | } | |
722 | } | |
723 | ||
724 | static int st_gpio_request(struct gpio_chip *chip, unsigned offset) | |
725 | { | |
726 | return pinctrl_request_gpio(chip->base + offset); | |
727 | } | |
728 | ||
729 | static void st_gpio_free(struct gpio_chip *chip, unsigned offset) | |
730 | { | |
731 | pinctrl_free_gpio(chip->base + offset); | |
732 | } | |
733 | ||
734 | static int st_gpio_get(struct gpio_chip *chip, unsigned offset) | |
735 | { | |
736 | struct st_gpio_bank *bank = gpio_chip_to_bank(chip); | |
737 | ||
738 | return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset)); | |
739 | } | |
740 | ||
741 | static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
742 | { | |
743 | struct st_gpio_bank *bank = gpio_chip_to_bank(chip); | |
744 | __st_gpio_set(bank, offset, value); | |
745 | } | |
746 | ||
747 | static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
748 | { | |
749 | pinctrl_gpio_direction_input(chip->base + offset); | |
750 | ||
751 | return 0; | |
752 | } | |
753 | ||
754 | static int st_gpio_direction_output(struct gpio_chip *chip, | |
755 | unsigned offset, int value) | |
756 | { | |
757 | struct st_gpio_bank *bank = gpio_chip_to_bank(chip); | |
758 | ||
759 | __st_gpio_set(bank, offset, value); | |
760 | pinctrl_gpio_direction_output(chip->base + offset); | |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
765 | static int st_gpio_xlate(struct gpio_chip *gc, | |
766 | const struct of_phandle_args *gpiospec, u32 *flags) | |
767 | { | |
768 | if (WARN_ON(gc->of_gpio_n_cells < 1)) | |
769 | return -EINVAL; | |
770 | ||
771 | if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells)) | |
772 | return -EINVAL; | |
773 | ||
774 | if (gpiospec->args[0] > gc->ngpio) | |
775 | return -EINVAL; | |
776 | ||
777 | return gpiospec->args[0]; | |
778 | } | |
779 | ||
780 | /* Pinctrl Groups */ | |
781 | static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev) | |
782 | { | |
783 | struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
784 | ||
785 | return info->ngroups; | |
786 | } | |
787 | ||
788 | static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev, | |
789 | unsigned selector) | |
790 | { | |
791 | struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
792 | ||
793 | return info->groups[selector].name; | |
794 | } | |
795 | ||
796 | static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev, | |
797 | unsigned selector, const unsigned **pins, unsigned *npins) | |
798 | { | |
799 | struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
800 | ||
801 | if (selector >= info->ngroups) | |
802 | return -EINVAL; | |
803 | ||
804 | *pins = info->groups[selector].pins; | |
805 | *npins = info->groups[selector].npins; | |
806 | ||
807 | return 0; | |
808 | } | |
809 | ||
810 | static const inline struct st_pctl_group *st_pctl_find_group_by_name( | |
811 | const struct st_pinctrl *info, const char *name) | |
812 | { | |
813 | int i; | |
814 | ||
815 | for (i = 0; i < info->ngroups; i++) { | |
816 | if (!strcmp(info->groups[i].name, name)) | |
817 | return &info->groups[i]; | |
818 | } | |
819 | ||
820 | return NULL; | |
821 | } | |
822 | ||
823 | static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, | |
824 | struct device_node *np, struct pinctrl_map **map, unsigned *num_maps) | |
825 | { | |
826 | struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
827 | const struct st_pctl_group *grp; | |
828 | struct pinctrl_map *new_map; | |
829 | struct device_node *parent; | |
830 | int map_num, i; | |
831 | ||
832 | grp = st_pctl_find_group_by_name(info, np->name); | |
833 | if (!grp) { | |
834 | dev_err(info->dev, "unable to find group for node %s\n", | |
835 | np->name); | |
836 | return -EINVAL; | |
837 | } | |
838 | ||
839 | map_num = grp->npins + 1; | |
840 | new_map = devm_kzalloc(pctldev->dev, | |
841 | sizeof(*new_map) * map_num, GFP_KERNEL); | |
842 | if (!new_map) | |
843 | return -ENOMEM; | |
844 | ||
845 | parent = of_get_parent(np); | |
846 | if (!parent) { | |
847 | devm_kfree(pctldev->dev, new_map); | |
848 | return -EINVAL; | |
849 | } | |
850 | ||
851 | *map = new_map; | |
852 | *num_maps = map_num; | |
853 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; | |
854 | new_map[0].data.mux.function = parent->name; | |
855 | new_map[0].data.mux.group = np->name; | |
856 | of_node_put(parent); | |
857 | ||
858 | /* create config map per pin */ | |
859 | new_map++; | |
860 | for (i = 0; i < grp->npins; i++) { | |
861 | new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; | |
862 | new_map[i].data.configs.group_or_pin = | |
863 | pin_get_name(pctldev, grp->pins[i]); | |
864 | new_map[i].data.configs.configs = &grp->pin_conf[i].config; | |
865 | new_map[i].data.configs.num_configs = 1; | |
866 | } | |
867 | dev_info(pctldev->dev, "maps: function %s group %s num %d\n", | |
868 | (*map)->data.mux.function, grp->name, map_num); | |
869 | ||
870 | return 0; | |
871 | } | |
872 | ||
873 | static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev, | |
874 | struct pinctrl_map *map, unsigned num_maps) | |
875 | { | |
876 | } | |
877 | ||
878 | static struct pinctrl_ops st_pctlops = { | |
879 | .get_groups_count = st_pctl_get_groups_count, | |
880 | .get_group_pins = st_pctl_get_group_pins, | |
881 | .get_group_name = st_pctl_get_group_name, | |
882 | .dt_node_to_map = st_pctl_dt_node_to_map, | |
883 | .dt_free_map = st_pctl_dt_free_map, | |
884 | }; | |
885 | ||
886 | /* Pinmux */ | |
887 | static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev) | |
888 | { | |
889 | struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
890 | ||
891 | return info->nfunctions; | |
892 | } | |
893 | ||
ef75bfd5 | 894 | static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev, |
701016c0 SK |
895 | unsigned selector) |
896 | { | |
897 | struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
898 | ||
899 | return info->functions[selector].name; | |
900 | } | |
901 | ||
902 | static int st_pmx_get_groups(struct pinctrl_dev *pctldev, | |
903 | unsigned selector, const char * const **grps, unsigned * const ngrps) | |
904 | { | |
905 | struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
906 | *grps = info->functions[selector].groups; | |
907 | *ngrps = info->functions[selector].ngroups; | |
908 | ||
909 | return 0; | |
910 | } | |
911 | ||
912 | static struct st_pio_control *st_get_pio_control( | |
913 | struct pinctrl_dev *pctldev, int pin) | |
914 | { | |
915 | struct pinctrl_gpio_range *range = | |
916 | pinctrl_find_gpio_range_from_pin(pctldev, pin); | |
917 | struct st_gpio_bank *bank = gpio_range_to_bank(range); | |
918 | ||
919 | return &bank->pc; | |
920 | } | |
921 | ||
922 | static int st_pmx_enable(struct pinctrl_dev *pctldev, unsigned fselector, | |
923 | unsigned group) | |
924 | { | |
925 | struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
926 | struct st_pinconf *conf = info->groups[group].pin_conf; | |
927 | struct st_pio_control *pc; | |
928 | int i; | |
929 | ||
930 | for (i = 0; i < info->groups[group].npins; i++) { | |
931 | pc = st_get_pio_control(pctldev, conf[i].pin); | |
932 | st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc); | |
933 | } | |
934 | ||
935 | return 0; | |
936 | } | |
937 | ||
938 | static void st_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector, | |
939 | unsigned group) | |
940 | { | |
941 | } | |
942 | ||
943 | static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev, | |
944 | struct pinctrl_gpio_range *range, unsigned gpio, | |
945 | bool input) | |
946 | { | |
947 | struct st_gpio_bank *bank = gpio_range_to_bank(range); | |
948 | /* | |
949 | * When a PIO bank is used in its primary function mode (altfunc = 0) | |
950 | * Output Enable (OE), Open Drain(OD), and Pull Up (PU) | |
951 | * for the primary PIO functions are driven by the related PIO block | |
952 | */ | |
953 | st_pctl_set_function(&bank->pc, gpio, 0); | |
954 | st_gpio_direction(bank, gpio, input ? | |
955 | ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT); | |
956 | ||
957 | return 0; | |
958 | } | |
959 | ||
960 | static struct pinmux_ops st_pmxops = { | |
961 | .get_functions_count = st_pmx_get_funcs_count, | |
962 | .get_function_name = st_pmx_get_fname, | |
963 | .get_function_groups = st_pmx_get_groups, | |
964 | .enable = st_pmx_enable, | |
965 | .disable = st_pmx_disable, | |
966 | .gpio_set_direction = st_pmx_set_gpio_direction, | |
967 | }; | |
968 | ||
969 | /* Pinconf */ | |
970 | static void st_pinconf_get_retime(struct st_pinctrl *info, | |
971 | struct st_pio_control *pc, int pin, unsigned long *config) | |
972 | { | |
973 | if (info->data->rt_style == st_retime_style_packed) | |
974 | st_pinconf_get_retime_packed(info, pc, pin, config); | |
975 | else if (info->data->rt_style == st_retime_style_dedicated) | |
976 | if ((BIT(pin) & pc->rt_pin_mask)) | |
977 | st_pinconf_get_retime_dedicated(info, pc, | |
978 | pin, config); | |
979 | } | |
980 | ||
981 | static void st_pinconf_set_retime(struct st_pinctrl *info, | |
982 | struct st_pio_control *pc, int pin, unsigned long config) | |
983 | { | |
984 | if (info->data->rt_style == st_retime_style_packed) | |
985 | st_pinconf_set_retime_packed(info, pc, config, pin); | |
986 | else if (info->data->rt_style == st_retime_style_dedicated) | |
987 | if ((BIT(pin) & pc->rt_pin_mask)) | |
988 | st_pinconf_set_retime_dedicated(info, pc, | |
989 | config, pin); | |
990 | } | |
991 | ||
03b054e9 SY |
992 | static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id, |
993 | unsigned long *configs, unsigned num_configs) | |
701016c0 SK |
994 | { |
995 | int pin = st_gpio_pin(pin_id); | |
996 | struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
997 | struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); | |
03b054e9 | 998 | int i; |
701016c0 | 999 | |
03b054e9 SY |
1000 | for (i = 0; i < num_configs; i++) { |
1001 | st_pinconf_set_config(pc, pin, configs[i]); | |
1002 | st_pinconf_set_retime(info, pc, pin, configs[i]); | |
1003 | } /* for each config */ | |
701016c0 SK |
1004 | |
1005 | return 0; | |
1006 | } | |
1007 | ||
1008 | static int st_pinconf_get(struct pinctrl_dev *pctldev, | |
1009 | unsigned pin_id, unsigned long *config) | |
1010 | { | |
1011 | int pin = st_gpio_pin(pin_id); | |
1012 | struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
1013 | struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); | |
1014 | ||
1015 | *config = 0; | |
1016 | st_pinconf_get_direction(pc, pin, config); | |
1017 | st_pinconf_get_retime(info, pc, pin, config); | |
1018 | ||
1019 | return 0; | |
1020 | } | |
1021 | ||
1022 | static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev, | |
1023 | struct seq_file *s, unsigned pin_id) | |
1024 | { | |
1025 | unsigned long config; | |
1026 | st_pinconf_get(pctldev, pin_id, &config); | |
1027 | ||
1028 | seq_printf(s, "[OE:%ld,PU:%ld,OD:%ld]\n" | |
1029 | "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld," | |
1030 | "de:%ld,rt-clk:%ld,rt-delay:%ld]", | |
1031 | ST_PINCONF_UNPACK_OE(config), | |
1032 | ST_PINCONF_UNPACK_PU(config), | |
1033 | ST_PINCONF_UNPACK_OD(config), | |
1034 | ST_PINCONF_UNPACK_RT(config), | |
1035 | ST_PINCONF_UNPACK_RT_INVERTCLK(config), | |
1036 | ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), | |
1037 | ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), | |
1038 | ST_PINCONF_UNPACK_RT_CLK(config), | |
1039 | ST_PINCONF_UNPACK_RT_DELAY(config)); | |
1040 | } | |
1041 | ||
1042 | static struct pinconf_ops st_confops = { | |
1043 | .pin_config_get = st_pinconf_get, | |
1044 | .pin_config_set = st_pinconf_set, | |
1045 | .pin_config_dbg_show = st_pinconf_dbg_show, | |
1046 | }; | |
1047 | ||
1048 | static void st_pctl_dt_child_count(struct st_pinctrl *info, | |
1049 | struct device_node *np) | |
1050 | { | |
1051 | struct device_node *child; | |
1052 | for_each_child_of_node(np, child) { | |
1053 | if (of_property_read_bool(child, "gpio-controller")) { | |
1054 | info->nbanks++; | |
1055 | } else { | |
1056 | info->nfunctions++; | |
1057 | info->ngroups += of_get_child_count(child); | |
1058 | } | |
1059 | } | |
1060 | } | |
1061 | ||
1062 | static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info, | |
1063 | int bank, struct st_pio_control *pc) | |
1064 | { | |
1065 | struct device *dev = info->dev; | |
1066 | struct regmap *rm = info->regmap; | |
1067 | const struct st_pctl_data *data = info->data; | |
1068 | /* 2 registers per bank */ | |
1069 | int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4; | |
1070 | struct st_retime_packed *rt_p = &pc->rt.rt_p; | |
1071 | /* cfg0 */ | |
1072 | struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg); | |
1073 | struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg); | |
1074 | struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg); | |
1075 | /* cfg1 */ | |
1076 | struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4); | |
1077 | struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4); | |
1078 | struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4); | |
1079 | struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4); | |
1080 | ||
1081 | rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0); | |
1082 | rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0); | |
1083 | rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1); | |
1084 | rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk); | |
1085 | rt_p->retime = devm_regmap_field_alloc(dev, rm, retime); | |
1086 | rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata); | |
1087 | rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge); | |
1088 | ||
1089 | if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) || | |
1090 | IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) || | |
1091 | IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) || | |
1092 | IS_ERR(rt_p->double_edge)) | |
1093 | return -EINVAL; | |
1094 | ||
1095 | return 0; | |
1096 | } | |
1097 | ||
1098 | static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info, | |
1099 | int bank, struct st_pio_control *pc) | |
1100 | { | |
1101 | struct device *dev = info->dev; | |
1102 | struct regmap *rm = info->regmap; | |
1103 | const struct st_pctl_data *data = info->data; | |
1104 | /* 8 registers per bank */ | |
1105 | int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; | |
1106 | struct st_retime_dedicated *rt_d = &pc->rt.rt_d; | |
1107 | unsigned int j; | |
1108 | u32 pin_mask = pc->rt_pin_mask; | |
1109 | ||
1110 | for (j = 0; j < RT_D_CFGS_PER_BANK; j++) { | |
1111 | if (BIT(j) & pin_mask) { | |
1112 | struct reg_field reg = REG_FIELD(reg_offset, 0, 31); | |
1113 | rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg); | |
1114 | if (IS_ERR(rt_d->rt[j])) | |
1115 | return -EINVAL; | |
1116 | reg_offset += 4; | |
1117 | } | |
1118 | } | |
1119 | return 0; | |
1120 | } | |
1121 | ||
1122 | static int st_pctl_dt_setup_retime(struct st_pinctrl *info, | |
1123 | int bank, struct st_pio_control *pc) | |
1124 | { | |
1125 | const struct st_pctl_data *data = info->data; | |
1126 | if (data->rt_style == st_retime_style_packed) | |
1127 | return st_pctl_dt_setup_retime_packed(info, bank, pc); | |
1128 | else if (data->rt_style == st_retime_style_dedicated) | |
1129 | return st_pctl_dt_setup_retime_dedicated(info, bank, pc); | |
1130 | ||
1131 | return -EINVAL; | |
1132 | } | |
1133 | ||
4e6a609f GC |
1134 | |
1135 | static struct regmap_field *st_pc_get_value(struct device *dev, | |
1136 | struct regmap *regmap, int bank, | |
1137 | int data, int lsb, int msb) | |
1138 | { | |
1139 | struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb); | |
1140 | ||
1141 | if (data < 0) | |
1142 | return NULL; | |
1143 | ||
1144 | return devm_regmap_field_alloc(dev, regmap, reg); | |
1145 | } | |
1146 | ||
1147 | static void st_parse_syscfgs(struct st_pinctrl *info, int bank, | |
1148 | struct device_node *np) | |
701016c0 SK |
1149 | { |
1150 | const struct st_pctl_data *data = info->data; | |
1151 | /** | |
1152 | * For a given shared register like OE/PU/OD, there are 8 bits per bank | |
1153 | * 0:7 belongs to bank0, 8:15 belongs to bank1 ... | |
1154 | * So each register is shared across 4 banks. | |
1155 | */ | |
1156 | int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK; | |
1157 | int msb = lsb + ST_GPIO_PINS_PER_BANK - 1; | |
701016c0 SK |
1158 | struct st_pio_control *pc = &info->banks[bank].pc; |
1159 | struct device *dev = info->dev; | |
1160 | struct regmap *regmap = info->regmap; | |
1161 | ||
4e6a609f GC |
1162 | pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31); |
1163 | pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb); | |
1164 | pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb); | |
1165 | pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb); | |
701016c0 SK |
1166 | |
1167 | /* retime avaiable for all pins by default */ | |
1168 | pc->rt_pin_mask = 0xff; | |
1169 | of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask); | |
1170 | st_pctl_dt_setup_retime(info, bank, pc); | |
1171 | ||
4e6a609f | 1172 | return; |
701016c0 SK |
1173 | } |
1174 | ||
1175 | /* | |
1176 | * Each pin is represented in of the below forms. | |
1177 | * <bank offset mux direction rt_type rt_delay rt_clk> | |
1178 | */ | |
1179 | static int st_pctl_dt_parse_groups(struct device_node *np, | |
1180 | struct st_pctl_group *grp, struct st_pinctrl *info, int idx) | |
1181 | { | |
1182 | /* bank pad direction val altfunction */ | |
1183 | const __be32 *list; | |
1184 | struct property *pp; | |
1185 | struct st_pinconf *conf; | |
1186 | phandle phandle; | |
1187 | struct device_node *pins; | |
1188 | u32 pin; | |
1189 | int i = 0, npins = 0, nr_props; | |
1190 | ||
1191 | pins = of_get_child_by_name(np, "st,pins"); | |
1192 | if (!pins) | |
1193 | return -ENODATA; | |
1194 | ||
1195 | for_each_property_of_node(pins, pp) { | |
1196 | /* Skip those we do not want to proceed */ | |
1197 | if (!strcmp(pp->name, "name")) | |
1198 | continue; | |
1199 | ||
1200 | if (pp && (pp->length/sizeof(__be32)) >= OF_GPIO_ARGS_MIN) { | |
1201 | npins++; | |
1202 | } else { | |
1203 | pr_warn("Invalid st,pins in %s node\n", np->name); | |
1204 | return -EINVAL; | |
1205 | } | |
1206 | } | |
1207 | ||
1208 | grp->npins = npins; | |
1209 | grp->name = np->name; | |
1210 | grp->pins = devm_kzalloc(info->dev, npins * sizeof(u32), GFP_KERNEL); | |
1211 | grp->pin_conf = devm_kzalloc(info->dev, | |
1212 | npins * sizeof(*conf), GFP_KERNEL); | |
1213 | ||
1214 | if (!grp->pins || !grp->pin_conf) | |
1215 | return -ENOMEM; | |
1216 | ||
1217 | /* <bank offset mux direction rt_type rt_delay rt_clk> */ | |
1218 | for_each_property_of_node(pins, pp) { | |
1219 | if (!strcmp(pp->name, "name")) | |
1220 | continue; | |
1221 | nr_props = pp->length/sizeof(u32); | |
1222 | list = pp->value; | |
1223 | conf = &grp->pin_conf[i]; | |
1224 | ||
1225 | /* bank & offset */ | |
1226 | phandle = be32_to_cpup(list++); | |
1227 | pin = be32_to_cpup(list++); | |
1228 | conf->pin = of_get_named_gpio(pins, pp->name, 0); | |
1229 | conf->name = pp->name; | |
1230 | grp->pins[i] = conf->pin; | |
1231 | /* mux */ | |
1232 | conf->altfunc = be32_to_cpup(list++); | |
1233 | conf->config = 0; | |
1234 | /* direction */ | |
1235 | conf->config |= be32_to_cpup(list++); | |
1236 | /* rt_type rt_delay rt_clk */ | |
1237 | if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) { | |
1238 | /* rt_type */ | |
1239 | conf->config |= be32_to_cpup(list++); | |
1240 | /* rt_delay */ | |
1241 | conf->config |= be32_to_cpup(list++); | |
1242 | /* rt_clk */ | |
1243 | if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) | |
1244 | conf->config |= be32_to_cpup(list++); | |
1245 | } | |
1246 | i++; | |
1247 | } | |
1248 | of_node_put(pins); | |
1249 | ||
1250 | return 0; | |
1251 | } | |
1252 | ||
1253 | static int st_pctl_parse_functions(struct device_node *np, | |
1254 | struct st_pinctrl *info, u32 index, int *grp_index) | |
1255 | { | |
1256 | struct device_node *child; | |
1257 | struct st_pmx_func *func; | |
1258 | struct st_pctl_group *grp; | |
1259 | int ret, i; | |
1260 | ||
1261 | func = &info->functions[index]; | |
1262 | func->name = np->name; | |
1263 | func->ngroups = of_get_child_count(np); | |
1264 | if (func->ngroups <= 0) { | |
1265 | dev_err(info->dev, "No groups defined\n"); | |
1266 | return -EINVAL; | |
1267 | } | |
1268 | func->groups = devm_kzalloc(info->dev, | |
1269 | func->ngroups * sizeof(char *), GFP_KERNEL); | |
1270 | if (!func->groups) | |
1271 | return -ENOMEM; | |
1272 | ||
1273 | i = 0; | |
1274 | for_each_child_of_node(np, child) { | |
1275 | func->groups[i] = child->name; | |
1276 | grp = &info->groups[*grp_index]; | |
1277 | *grp_index += 1; | |
1278 | ret = st_pctl_dt_parse_groups(child, grp, info, i++); | |
1279 | if (ret) | |
1280 | return ret; | |
1281 | } | |
1282 | dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n", | |
1283 | index, func->name, func->ngroups); | |
1284 | ||
1285 | return 0; | |
1286 | } | |
1287 | ||
727b0f71 SK |
1288 | static int st_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
1289 | { | |
1290 | struct st_gpio_bank *bank = gpio_chip_to_bank(chip); | |
1291 | int irq = -ENXIO; | |
1292 | ||
1293 | if (offset < chip->ngpio) | |
1294 | irq = irq_find_mapping(bank->domain, offset); | |
1295 | ||
1296 | dev_info(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", | |
1297 | chip->label, offset + chip->base, irq); | |
1298 | return irq; | |
1299 | } | |
1300 | ||
1301 | static void st_gpio_irq_mask(struct irq_data *d) | |
1302 | { | |
1303 | struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
1304 | ||
1305 | writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK); | |
1306 | } | |
1307 | ||
1308 | static void st_gpio_irq_unmask(struct irq_data *d) | |
1309 | { | |
1310 | struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
1311 | ||
1312 | writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK); | |
1313 | } | |
1314 | ||
1315 | static unsigned int st_gpio_irq_startup(struct irq_data *d) | |
1316 | { | |
1317 | struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
1318 | ||
1319 | if (gpio_lock_as_irq(&bank->gpio_chip, d->hwirq)) | |
1320 | dev_err(bank->gpio_chip.dev, | |
1321 | "unable to lock HW IRQ %lu for IRQ\n", | |
1322 | d->hwirq); | |
1323 | ||
1324 | st_gpio_irq_unmask(d); | |
1325 | ||
1326 | return 0; | |
1327 | } | |
1328 | ||
1329 | static void st_gpio_irq_shutdown(struct irq_data *d) | |
1330 | { | |
1331 | struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
1332 | ||
1333 | st_gpio_irq_mask(d); | |
1334 | gpio_unlock_as_irq(&bank->gpio_chip, d->hwirq); | |
1335 | } | |
1336 | ||
1337 | static int st_gpio_irq_set_type(struct irq_data *d, unsigned type) | |
1338 | { | |
1339 | struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
1340 | unsigned long flags; | |
1341 | int comp, pin = d->hwirq; | |
1342 | u32 val; | |
155795b9 | 1343 | u32 pin_edge_conf = 0; |
727b0f71 SK |
1344 | |
1345 | switch (type) { | |
1346 | case IRQ_TYPE_LEVEL_HIGH: | |
1347 | comp = 0; | |
1348 | break; | |
155795b9 SK |
1349 | case IRQ_TYPE_EDGE_FALLING: |
1350 | comp = 0; | |
1351 | pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin); | |
1352 | break; | |
727b0f71 SK |
1353 | case IRQ_TYPE_LEVEL_LOW: |
1354 | comp = 1; | |
1355 | break; | |
155795b9 SK |
1356 | case IRQ_TYPE_EDGE_RISING: |
1357 | comp = 1; | |
1358 | pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin); | |
1359 | break; | |
1360 | case IRQ_TYPE_EDGE_BOTH: | |
1361 | comp = st_gpio_get(&bank->gpio_chip, pin); | |
1362 | pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin); | |
1363 | break; | |
727b0f71 SK |
1364 | default: |
1365 | return -EINVAL; | |
1366 | } | |
1367 | ||
155795b9 SK |
1368 | spin_lock_irqsave(&bank->lock, flags); |
1369 | bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << ( | |
1370 | pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)); | |
1371 | bank->irq_edge_conf |= pin_edge_conf; | |
1372 | spin_unlock_irqrestore(&bank->lock, flags); | |
1373 | ||
727b0f71 SK |
1374 | val = readl(bank->base + REG_PIO_PCOMP); |
1375 | val &= ~BIT(pin); | |
1376 | val |= (comp << pin); | |
1377 | writel(val, bank->base + REG_PIO_PCOMP); | |
1378 | ||
1379 | return 0; | |
1380 | } | |
1381 | ||
155795b9 SK |
1382 | /* |
1383 | * As edge triggers are not supported at hardware level, it is supported by | |
1384 | * software by exploiting the level trigger support in hardware. | |
1385 | * | |
1386 | * Steps for detection raising edge interrupt in software. | |
1387 | * | |
1388 | * Step 1: CONFIGURE pin to detect level LOW interrupts. | |
1389 | * | |
1390 | * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler, | |
1391 | * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt. | |
1392 | * IGNORE calling the actual interrupt handler for the pin at this stage. | |
1393 | * | |
1394 | * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler | |
1395 | * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then | |
1396 | * DISPATCH the interrupt to the interrupt handler of the pin. | |
1397 | * | |
1398 | * step-1 ________ __________ | |
1399 | * | | step - 3 | |
1400 | * | | | |
1401 | * step -2 |_____| | |
1402 | * | |
1403 | * falling edge is also detected int the same way. | |
1404 | * | |
1405 | */ | |
727b0f71 SK |
1406 | static void __gpio_irq_handler(struct st_gpio_bank *bank) |
1407 | { | |
1408 | unsigned long port_in, port_mask, port_comp, active_irqs; | |
155795b9 SK |
1409 | unsigned long bank_edge_mask, flags; |
1410 | int n, val, ecfg; | |
1411 | ||
1412 | spin_lock_irqsave(&bank->lock, flags); | |
1413 | bank_edge_mask = bank->irq_edge_conf; | |
1414 | spin_unlock_irqrestore(&bank->lock, flags); | |
727b0f71 SK |
1415 | |
1416 | for (;;) { | |
1417 | port_in = readl(bank->base + REG_PIO_PIN); | |
1418 | port_comp = readl(bank->base + REG_PIO_PCOMP); | |
1419 | port_mask = readl(bank->base + REG_PIO_PMASK); | |
1420 | ||
1421 | active_irqs = (port_in ^ port_comp) & port_mask; | |
1422 | ||
1423 | if (active_irqs == 0) | |
1424 | break; | |
1425 | ||
1426 | for_each_set_bit(n, &active_irqs, BITS_PER_LONG) { | |
155795b9 SK |
1427 | /* check if we are detecting fake edges ... */ |
1428 | ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n); | |
1429 | ||
1430 | if (ecfg) { | |
1431 | /* edge detection. */ | |
1432 | val = st_gpio_get(&bank->gpio_chip, n); | |
1433 | ||
1434 | writel(BIT(n), | |
1435 | val ? bank->base + REG_PIO_SET_PCOMP : | |
1436 | bank->base + REG_PIO_CLR_PCOMP); | |
1437 | ||
1438 | if (ecfg != ST_IRQ_EDGE_BOTH && | |
1439 | !((ecfg & ST_IRQ_EDGE_FALLING) ^ val)) | |
1440 | continue; | |
1441 | } | |
1442 | ||
727b0f71 SK |
1443 | generic_handle_irq(irq_find_mapping(bank->domain, n)); |
1444 | } | |
1445 | } | |
1446 | } | |
1447 | ||
1448 | static void st_gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |
1449 | { | |
1450 | /* interrupt dedicated per bank */ | |
1451 | struct irq_chip *chip = irq_get_chip(irq); | |
1452 | struct st_gpio_bank *bank = irq_get_handler_data(irq); | |
1453 | ||
1454 | chained_irq_enter(chip, desc); | |
1455 | __gpio_irq_handler(bank); | |
1456 | chained_irq_exit(chip, desc); | |
1457 | } | |
1458 | ||
1459 | static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc) | |
1460 | { | |
1461 | struct irq_chip *chip = irq_get_chip(irq); | |
1462 | struct st_pinctrl *info = irq_get_handler_data(irq); | |
1463 | unsigned long status; | |
1464 | int n; | |
1465 | ||
1466 | chained_irq_enter(chip, desc); | |
1467 | ||
1468 | status = readl(info->irqmux_base); | |
1469 | ||
1470 | for_each_set_bit(n, &status, ST_GPIO_PINS_PER_BANK) | |
1471 | __gpio_irq_handler(&info->banks[n]); | |
1472 | ||
1473 | chained_irq_exit(chip, desc); | |
1474 | } | |
1475 | ||
701016c0 SK |
1476 | static struct gpio_chip st_gpio_template = { |
1477 | .request = st_gpio_request, | |
1478 | .free = st_gpio_free, | |
1479 | .get = st_gpio_get, | |
1480 | .set = st_gpio_set, | |
1481 | .direction_input = st_gpio_direction_input, | |
1482 | .direction_output = st_gpio_direction_output, | |
1483 | .ngpio = ST_GPIO_PINS_PER_BANK, | |
1484 | .of_gpio_n_cells = 1, | |
1485 | .of_xlate = st_gpio_xlate, | |
727b0f71 SK |
1486 | .to_irq = st_gpio_to_irq, |
1487 | }; | |
1488 | ||
1489 | static struct irq_chip st_gpio_irqchip = { | |
1490 | .name = "GPIO", | |
1491 | .irq_mask = st_gpio_irq_mask, | |
1492 | .irq_unmask = st_gpio_irq_unmask, | |
1493 | .irq_set_type = st_gpio_irq_set_type, | |
1494 | .irq_startup = st_gpio_irq_startup, | |
1495 | .irq_shutdown = st_gpio_irq_shutdown, | |
1496 | }; | |
1497 | ||
1498 | static int st_gpio_irq_domain_map(struct irq_domain *h, | |
1499 | unsigned int virq, irq_hw_number_t hw) | |
1500 | { | |
1501 | struct st_gpio_bank *bank = h->host_data; | |
1502 | ||
1503 | irq_set_chip(virq, &st_gpio_irqchip); | |
155795b9 | 1504 | irq_set_handler(virq, handle_simple_irq); |
727b0f71 SK |
1505 | set_irq_flags(virq, IRQF_VALID); |
1506 | irq_set_chip_data(virq, bank); | |
1507 | ||
1508 | return 0; | |
1509 | } | |
1510 | ||
1511 | static struct irq_domain_ops st_gpio_irq_ops = { | |
1512 | .map = st_gpio_irq_domain_map, | |
1513 | .xlate = irq_domain_xlate_twocell, | |
701016c0 SK |
1514 | }; |
1515 | ||
1516 | static int st_gpiolib_register_bank(struct st_pinctrl *info, | |
1517 | int bank_nr, struct device_node *np) | |
1518 | { | |
1519 | struct st_gpio_bank *bank = &info->banks[bank_nr]; | |
1520 | struct pinctrl_gpio_range *range = &bank->range; | |
1521 | struct device *dev = info->dev; | |
1522 | int bank_num = of_alias_get_id(np, "gpio"); | |
727b0f71 SK |
1523 | struct resource res, irq_res; |
1524 | int gpio_irq = 0, err, i; | |
701016c0 SK |
1525 | |
1526 | if (of_address_to_resource(np, 0, &res)) | |
1527 | return -ENODEV; | |
1528 | ||
656445f3 SK |
1529 | bank->base = devm_ioremap_resource(dev, &res); |
1530 | if (IS_ERR(bank->base)) | |
1531 | return PTR_ERR(bank->base); | |
701016c0 SK |
1532 | |
1533 | bank->gpio_chip = st_gpio_template; | |
1534 | bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; | |
1535 | bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; | |
1536 | bank->gpio_chip.of_node = np; | |
155795b9 | 1537 | spin_lock_init(&bank->lock); |
701016c0 SK |
1538 | |
1539 | of_property_read_string(np, "st,bank-name", &range->name); | |
1540 | bank->gpio_chip.label = range->name; | |
1541 | ||
1542 | range->id = bank_num; | |
1543 | range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK; | |
1544 | range->npins = bank->gpio_chip.ngpio; | |
1545 | range->gc = &bank->gpio_chip; | |
1546 | err = gpiochip_add(&bank->gpio_chip); | |
1547 | if (err) { | |
1548 | dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num); | |
1549 | return err; | |
1550 | } | |
1551 | dev_info(dev, "%s bank added.\n", range->name); | |
1552 | ||
727b0f71 SK |
1553 | /** |
1554 | * GPIO bank can have one of the two possible types of | |
1555 | * interrupt-wirings. | |
1556 | * | |
1557 | * First type is via irqmux, single interrupt is used by multiple | |
1558 | * gpio banks. This reduces number of overall interrupts numbers | |
1559 | * required. All these banks belong to a single pincontroller. | |
1560 | * _________ | |
1561 | * | |----> [gpio-bank (n) ] | |
1562 | * | |----> [gpio-bank (n + 1)] | |
1563 | * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] | |
1564 | * | |----> [gpio-bank (... )] | |
1565 | * |_________|----> [gpio-bank (n + 7)] | |
1566 | * | |
1567 | * Second type has a dedicated interrupt per each gpio bank. | |
1568 | * | |
1569 | * [irqN]----> [gpio-bank (n)] | |
1570 | */ | |
1571 | ||
1572 | if (!of_irq_to_resource(np, 0, &irq_res)) { | |
1573 | gpio_irq = irq_res.start; | |
1574 | irq_set_chained_handler(gpio_irq, st_gpio_irq_handler); | |
1575 | irq_set_handler_data(gpio_irq, bank); | |
1576 | } | |
1577 | ||
1578 | if (info->irqmux_base > 0 || gpio_irq > 0) { | |
1579 | /* Setup IRQ domain */ | |
1580 | bank->domain = irq_domain_add_linear(np, | |
1581 | ST_GPIO_PINS_PER_BANK, | |
1582 | &st_gpio_irq_ops, bank); | |
1583 | if (!bank->domain) { | |
1584 | dev_err(dev, "Failed to add irq domain for %s\n", | |
1585 | np->full_name); | |
1586 | } else { | |
1587 | for (i = 0; i < ST_GPIO_PINS_PER_BANK; i++) { | |
1588 | if (irq_create_mapping(bank->domain, i) < 0) | |
1589 | dev_err(dev, | |
1590 | "Failed to map IRQ %i\n", i); | |
1591 | } | |
1592 | } | |
1593 | ||
1594 | } else { | |
1595 | dev_info(dev, "No IRQ support for %s bank\n", np->full_name); | |
1596 | } | |
1597 | ||
701016c0 SK |
1598 | return 0; |
1599 | } | |
1600 | ||
1601 | static struct of_device_id st_pctl_of_match[] = { | |
1602 | { .compatible = "st,stih415-sbc-pinctrl", .data = &stih415_sbc_data }, | |
1603 | { .compatible = "st,stih415-rear-pinctrl", .data = &stih415_rear_data }, | |
1604 | { .compatible = "st,stih415-left-pinctrl", .data = &stih415_left_data }, | |
1605 | { .compatible = "st,stih415-right-pinctrl", | |
1606 | .data = &stih415_right_data }, | |
1607 | { .compatible = "st,stih415-front-pinctrl", | |
1608 | .data = &stih415_front_data }, | |
1609 | { .compatible = "st,stih416-sbc-pinctrl", .data = &stih416_data}, | |
1610 | { .compatible = "st,stih416-front-pinctrl", .data = &stih416_data}, | |
1611 | { .compatible = "st,stih416-rear-pinctrl", .data = &stih416_data}, | |
1612 | { .compatible = "st,stih416-fvdp-fe-pinctrl", .data = &stih416_data}, | |
1613 | { .compatible = "st,stih416-fvdp-lite-pinctrl", .data = &stih416_data}, | |
7ce717db GC |
1614 | { .compatible = "st,stih407-sbc-pinctrl", .data = &stih416_data}, |
1615 | { .compatible = "st,stih407-front-pinctrl", .data = &stih416_data}, | |
1616 | { .compatible = "st,stih407-rear-pinctrl", .data = &stih416_data}, | |
1617 | { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata}, | |
701016c0 SK |
1618 | { /* sentinel */ } |
1619 | }; | |
1620 | ||
1621 | static int st_pctl_probe_dt(struct platform_device *pdev, | |
1622 | struct pinctrl_desc *pctl_desc, struct st_pinctrl *info) | |
1623 | { | |
1624 | int ret = 0; | |
1625 | int i = 0, j = 0, k = 0, bank; | |
1626 | struct pinctrl_pin_desc *pdesc; | |
1627 | struct device_node *np = pdev->dev.of_node; | |
1628 | struct device_node *child; | |
1629 | int grp_index = 0; | |
727b0f71 SK |
1630 | int irq = 0; |
1631 | struct resource *res; | |
701016c0 SK |
1632 | |
1633 | st_pctl_dt_child_count(info, np); | |
1634 | if (!info->nbanks) { | |
1635 | dev_err(&pdev->dev, "you need atleast one gpio bank\n"); | |
1636 | return -EINVAL; | |
1637 | } | |
1638 | ||
1639 | dev_info(&pdev->dev, "nbanks = %d\n", info->nbanks); | |
1640 | dev_info(&pdev->dev, "nfunctions = %d\n", info->nfunctions); | |
1641 | dev_info(&pdev->dev, "ngroups = %d\n", info->ngroups); | |
1642 | ||
1643 | info->functions = devm_kzalloc(&pdev->dev, | |
1644 | info->nfunctions * sizeof(*info->functions), GFP_KERNEL); | |
1645 | ||
1646 | info->groups = devm_kzalloc(&pdev->dev, | |
1647 | info->ngroups * sizeof(*info->groups) , GFP_KERNEL); | |
1648 | ||
1649 | info->banks = devm_kzalloc(&pdev->dev, | |
1650 | info->nbanks * sizeof(*info->banks), GFP_KERNEL); | |
1651 | ||
1652 | if (!info->functions || !info->groups || !info->banks) | |
1653 | return -ENOMEM; | |
1654 | ||
1655 | info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); | |
5c75acdc | 1656 | if (IS_ERR(info->regmap)) { |
701016c0 | 1657 | dev_err(info->dev, "No syscfg phandle specified\n"); |
5c75acdc | 1658 | return PTR_ERR(info->regmap); |
701016c0 SK |
1659 | } |
1660 | info->data = of_match_node(st_pctl_of_match, np)->data; | |
1661 | ||
727b0f71 SK |
1662 | irq = platform_get_irq(pdev, 0); |
1663 | ||
1664 | if (irq > 0) { | |
1665 | res = platform_get_resource_byname(pdev, | |
1666 | IORESOURCE_MEM, "irqmux"); | |
1667 | info->irqmux_base = devm_ioremap_resource(&pdev->dev, res); | |
1668 | ||
1669 | if (IS_ERR(info->irqmux_base)) | |
1670 | return PTR_ERR(info->irqmux_base); | |
1671 | ||
1672 | irq_set_chained_handler(irq, st_gpio_irqmux_handler); | |
1673 | irq_set_handler_data(irq, info); | |
1674 | ||
1675 | } | |
1676 | ||
701016c0 SK |
1677 | pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; |
1678 | pdesc = devm_kzalloc(&pdev->dev, | |
1679 | sizeof(*pdesc) * pctl_desc->npins, GFP_KERNEL); | |
1680 | if (!pdesc) | |
1681 | return -ENOMEM; | |
1682 | ||
1683 | pctl_desc->pins = pdesc; | |
1684 | ||
1685 | bank = 0; | |
1686 | for_each_child_of_node(np, child) { | |
1687 | if (of_property_read_bool(child, "gpio-controller")) { | |
1688 | const char *bank_name = NULL; | |
1689 | ret = st_gpiolib_register_bank(info, bank, child); | |
1690 | if (ret) | |
1691 | return ret; | |
1692 | ||
1693 | k = info->banks[bank].range.pin_base; | |
1694 | bank_name = info->banks[bank].range.name; | |
1695 | for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) { | |
1696 | pdesc->number = k; | |
1697 | pdesc->name = kasprintf(GFP_KERNEL, "%s[%d]", | |
1698 | bank_name, j); | |
1699 | pdesc++; | |
1700 | } | |
1701 | st_parse_syscfgs(info, bank, child); | |
1702 | bank++; | |
1703 | } else { | |
1704 | ret = st_pctl_parse_functions(child, info, | |
1705 | i++, &grp_index); | |
1706 | if (ret) { | |
1707 | dev_err(&pdev->dev, "No functions found.\n"); | |
1708 | return ret; | |
1709 | } | |
1710 | } | |
1711 | } | |
1712 | ||
1713 | return 0; | |
1714 | } | |
1715 | ||
1716 | static int st_pctl_probe(struct platform_device *pdev) | |
1717 | { | |
1718 | struct st_pinctrl *info; | |
1719 | struct pinctrl_desc *pctl_desc; | |
1720 | int ret, i; | |
1721 | ||
1722 | if (!pdev->dev.of_node) { | |
1723 | dev_err(&pdev->dev, "device node not found.\n"); | |
1724 | return -EINVAL; | |
1725 | } | |
1726 | ||
1727 | pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); | |
1728 | if (!pctl_desc) | |
1729 | return -ENOMEM; | |
1730 | ||
1731 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); | |
1732 | if (!info) | |
1733 | return -ENOMEM; | |
1734 | ||
1735 | info->dev = &pdev->dev; | |
1736 | platform_set_drvdata(pdev, info); | |
1737 | ret = st_pctl_probe_dt(pdev, pctl_desc, info); | |
1738 | if (ret) | |
1739 | return ret; | |
1740 | ||
c9dd66b7 SK |
1741 | pctl_desc->owner = THIS_MODULE; |
1742 | pctl_desc->pctlops = &st_pctlops; | |
1743 | pctl_desc->pmxops = &st_pmxops; | |
1744 | pctl_desc->confops = &st_confops; | |
701016c0 SK |
1745 | pctl_desc->name = dev_name(&pdev->dev); |
1746 | ||
1747 | info->pctl = pinctrl_register(pctl_desc, &pdev->dev, info); | |
5c75acdc | 1748 | if (!info->pctl) { |
701016c0 | 1749 | dev_err(&pdev->dev, "Failed pinctrl registration\n"); |
5c75acdc | 1750 | return -EINVAL; |
701016c0 SK |
1751 | } |
1752 | ||
1753 | for (i = 0; i < info->nbanks; i++) | |
1754 | pinctrl_add_gpio_range(info->pctl, &info->banks[i].range); | |
1755 | ||
1756 | return 0; | |
1757 | } | |
1758 | ||
1759 | static struct platform_driver st_pctl_driver = { | |
1760 | .driver = { | |
1761 | .name = "st-pinctrl", | |
1762 | .owner = THIS_MODULE, | |
539fde59 | 1763 | .of_match_table = st_pctl_of_match, |
701016c0 SK |
1764 | }, |
1765 | .probe = st_pctl_probe, | |
1766 | }; | |
1767 | ||
1768 | static int __init st_pctl_init(void) | |
1769 | { | |
1770 | return platform_driver_register(&st_pctl_driver); | |
1771 | } | |
1772 | arch_initcall(st_pctl_init); |