Commit | Line | Data |
---|---|---|
971dac71 SW |
1 | /* |
2 | * Driver for the NVIDIA Tegra pinmux | |
3 | * | |
52f48fe0 | 4 | * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. |
971dac71 SW |
5 | * |
6 | * Derived from code: | |
7 | * Copyright (C) 2010 Google, Inc. | |
8 | * Copyright (C) 2010 NVIDIA Corporation | |
9 | * Copyright (C) 2009-2011 ST-Ericsson AB | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms and conditions of the GNU General Public License, | |
13 | * version 2, as published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope it will be useful, but WITHOUT | |
16 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
18 | * more details. | |
19 | */ | |
20 | ||
21 | #include <linux/err.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/module.h> | |
52f48fe0 SW |
25 | #include <linux/of.h> |
26 | #include <linux/platform_device.h> | |
60f7f500 | 27 | #include <linux/pinctrl/machine.h> |
971dac71 SW |
28 | #include <linux/pinctrl/pinctrl.h> |
29 | #include <linux/pinctrl/pinmux.h> | |
30 | #include <linux/pinctrl/pinconf.h> | |
60f7f500 | 31 | #include <linux/slab.h> |
971dac71 | 32 | |
52f48fe0 | 33 | #include "core.h" |
971dac71 | 34 | #include "pinctrl-tegra.h" |
1ede12d4 | 35 | #include "pinctrl-utils.h" |
971dac71 | 36 | |
971dac71 SW |
37 | struct tegra_pmx { |
38 | struct device *dev; | |
39 | struct pinctrl_dev *pctl; | |
40 | ||
41 | const struct tegra_pinctrl_soc_data *soc; | |
ce436254 | 42 | const char **group_pins; |
971dac71 SW |
43 | |
44 | int nbanks; | |
45 | void __iomem **regs; | |
46 | }; | |
47 | ||
48 | static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg) | |
49 | { | |
50 | return readl(pmx->regs[bank] + reg); | |
51 | } | |
52 | ||
53 | static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg) | |
54 | { | |
55 | writel(val, pmx->regs[bank] + reg); | |
56 | } | |
57 | ||
d1e90e9e | 58 | static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) |
971dac71 SW |
59 | { |
60 | struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
61 | ||
d1e90e9e | 62 | return pmx->soc->ngroups; |
971dac71 SW |
63 | } |
64 | ||
65 | static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev, | |
66 | unsigned group) | |
67 | { | |
68 | struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
69 | ||
971dac71 SW |
70 | return pmx->soc->groups[group].name; |
71 | } | |
72 | ||
73 | static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, | |
74 | unsigned group, | |
75 | const unsigned **pins, | |
76 | unsigned *num_pins) | |
77 | { | |
78 | struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
79 | ||
971dac71 SW |
80 | *pins = pmx->soc->groups[group].pins; |
81 | *num_pins = pmx->soc->groups[group].npins; | |
82 | ||
83 | return 0; | |
84 | } | |
85 | ||
b5badbaa | 86 | #ifdef CONFIG_DEBUG_FS |
971dac71 SW |
87 | static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, |
88 | struct seq_file *s, | |
89 | unsigned offset) | |
90 | { | |
52f48fe0 | 91 | seq_printf(s, " %s", dev_name(pctldev->dev)); |
971dac71 | 92 | } |
b5badbaa | 93 | #endif |
971dac71 | 94 | |
60f7f500 SW |
95 | static const struct cfg_param { |
96 | const char *property; | |
97 | enum tegra_pinconf_param param; | |
98 | } cfg_params[] = { | |
99 | {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL}, | |
100 | {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE}, | |
101 | {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT}, | |
102 | {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN}, | |
103 | {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK}, | |
104 | {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET}, | |
348d1bf7 | 105 | {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL}, |
ec654e50 | 106 | {"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL}, |
60f7f500 SW |
107 | {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE}, |
108 | {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT}, | |
109 | {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE}, | |
110 | {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH}, | |
111 | {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH}, | |
112 | {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING}, | |
113 | {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING}, | |
348d1bf7 | 114 | {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE}, |
60f7f500 SW |
115 | }; |
116 | ||
1ede12d4 | 117 | static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, |
102caad9 AL |
118 | struct device_node *np, |
119 | struct pinctrl_map **map, | |
120 | unsigned *reserved_maps, | |
121 | unsigned *num_maps) | |
60f7f500 | 122 | { |
1ede12d4 | 123 | struct device *dev = pctldev->dev; |
60f7f500 SW |
124 | int ret, i; |
125 | const char *function; | |
126 | u32 val; | |
127 | unsigned long config; | |
128 | unsigned long *configs = NULL; | |
129 | unsigned num_configs = 0; | |
130 | unsigned reserve; | |
131 | struct property *prop; | |
132 | const char *group; | |
133 | ||
134 | ret = of_property_read_string(np, "nvidia,function", &function); | |
aef7704c SW |
135 | if (ret < 0) { |
136 | /* EINVAL=missing, which is fine since it's optional */ | |
137 | if (ret != -EINVAL) | |
138 | dev_err(dev, | |
139 | "could not parse property nvidia,function\n"); | |
60f7f500 | 140 | function = NULL; |
aef7704c | 141 | } |
60f7f500 SW |
142 | |
143 | for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { | |
144 | ret = of_property_read_u32(np, cfg_params[i].property, &val); | |
145 | if (!ret) { | |
146 | config = TEGRA_PINCONF_PACK(cfg_params[i].param, val); | |
1ede12d4 LD |
147 | ret = pinctrl_utils_add_config(pctldev, &configs, |
148 | &num_configs, config); | |
60f7f500 SW |
149 | if (ret < 0) |
150 | goto exit; | |
aef7704c SW |
151 | /* EINVAL=missing, which is fine since it's optional */ |
152 | } else if (ret != -EINVAL) { | |
153 | dev_err(dev, "could not parse property %s\n", | |
154 | cfg_params[i].property); | |
60f7f500 SW |
155 | } |
156 | } | |
157 | ||
158 | reserve = 0; | |
159 | if (function != NULL) | |
160 | reserve++; | |
161 | if (num_configs) | |
162 | reserve++; | |
163 | ret = of_property_count_strings(np, "nvidia,pins"); | |
aef7704c SW |
164 | if (ret < 0) { |
165 | dev_err(dev, "could not parse property nvidia,pins\n"); | |
60f7f500 | 166 | goto exit; |
aef7704c | 167 | } |
60f7f500 SW |
168 | reserve *= ret; |
169 | ||
1ede12d4 LD |
170 | ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, |
171 | num_maps, reserve); | |
60f7f500 SW |
172 | if (ret < 0) |
173 | goto exit; | |
174 | ||
175 | of_property_for_each_string(np, "nvidia,pins", prop, group) { | |
176 | if (function) { | |
1ede12d4 LD |
177 | ret = pinctrl_utils_add_map_mux(pctldev, map, |
178 | reserved_maps, num_maps, group, | |
179 | function); | |
60f7f500 SW |
180 | if (ret < 0) |
181 | goto exit; | |
182 | } | |
183 | ||
184 | if (num_configs) { | |
1ede12d4 LD |
185 | ret = pinctrl_utils_add_map_configs(pctldev, map, |
186 | reserved_maps, num_maps, group, | |
187 | configs, num_configs, | |
188 | PIN_MAP_TYPE_CONFIGS_GROUP); | |
60f7f500 SW |
189 | if (ret < 0) |
190 | goto exit; | |
191 | } | |
192 | } | |
193 | ||
194 | ret = 0; | |
195 | ||
196 | exit: | |
197 | kfree(configs); | |
198 | return ret; | |
199 | } | |
200 | ||
102caad9 AL |
201 | static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, |
202 | struct device_node *np_config, | |
203 | struct pinctrl_map **map, | |
204 | unsigned *num_maps) | |
60f7f500 SW |
205 | { |
206 | unsigned reserved_maps; | |
207 | struct device_node *np; | |
208 | int ret; | |
209 | ||
210 | reserved_maps = 0; | |
211 | *map = NULL; | |
212 | *num_maps = 0; | |
213 | ||
214 | for_each_child_of_node(np_config, np) { | |
1ede12d4 | 215 | ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map, |
aef7704c | 216 | &reserved_maps, num_maps); |
60f7f500 | 217 | if (ret < 0) { |
1ede12d4 LD |
218 | pinctrl_utils_dt_free_map(pctldev, *map, |
219 | *num_maps); | |
60f7f500 SW |
220 | return ret; |
221 | } | |
222 | } | |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
022ab148 | 227 | static const struct pinctrl_ops tegra_pinctrl_ops = { |
d1e90e9e | 228 | .get_groups_count = tegra_pinctrl_get_groups_count, |
971dac71 SW |
229 | .get_group_name = tegra_pinctrl_get_group_name, |
230 | .get_group_pins = tegra_pinctrl_get_group_pins, | |
b5badbaa | 231 | #ifdef CONFIG_DEBUG_FS |
971dac71 | 232 | .pin_dbg_show = tegra_pinctrl_pin_dbg_show, |
b5badbaa | 233 | #endif |
60f7f500 | 234 | .dt_node_to_map = tegra_pinctrl_dt_node_to_map, |
1ede12d4 | 235 | .dt_free_map = pinctrl_utils_dt_free_map, |
971dac71 SW |
236 | }; |
237 | ||
d1e90e9e | 238 | static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) |
971dac71 SW |
239 | { |
240 | struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
241 | ||
d1e90e9e | 242 | return pmx->soc->nfunctions; |
971dac71 SW |
243 | } |
244 | ||
245 | static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev, | |
246 | unsigned function) | |
247 | { | |
248 | struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
249 | ||
971dac71 SW |
250 | return pmx->soc->functions[function].name; |
251 | } | |
252 | ||
253 | static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, | |
254 | unsigned function, | |
255 | const char * const **groups, | |
256 | unsigned * const num_groups) | |
257 | { | |
258 | struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
259 | ||
971dac71 SW |
260 | *groups = pmx->soc->functions[function].groups; |
261 | *num_groups = pmx->soc->functions[function].ngroups; | |
262 | ||
263 | return 0; | |
264 | } | |
265 | ||
03e9f0ca LW |
266 | static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev, |
267 | unsigned function, | |
268 | unsigned group) | |
971dac71 SW |
269 | { |
270 | struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
271 | const struct tegra_pingroup *g; | |
272 | int i; | |
273 | u32 val; | |
274 | ||
971dac71 SW |
275 | g = &pmx->soc->groups[group]; |
276 | ||
aef7704c | 277 | if (WARN_ON(g->mux_reg < 0)) |
971dac71 SW |
278 | return -EINVAL; |
279 | ||
280 | for (i = 0; i < ARRAY_SIZE(g->funcs); i++) { | |
281 | if (g->funcs[i] == function) | |
282 | break; | |
283 | } | |
aef7704c | 284 | if (WARN_ON(i == ARRAY_SIZE(g->funcs))) |
971dac71 SW |
285 | return -EINVAL; |
286 | ||
287 | val = pmx_readl(pmx, g->mux_bank, g->mux_reg); | |
288 | val &= ~(0x3 << g->mux_bit); | |
289 | val |= i << g->mux_bit; | |
290 | pmx_writel(pmx, val, g->mux_bank, g->mux_reg); | |
291 | ||
292 | return 0; | |
293 | } | |
294 | ||
022ab148 | 295 | static const struct pinmux_ops tegra_pinmux_ops = { |
d1e90e9e | 296 | .get_functions_count = tegra_pinctrl_get_funcs_count, |
971dac71 SW |
297 | .get_function_name = tegra_pinctrl_get_func_name, |
298 | .get_function_groups = tegra_pinctrl_get_func_groups, | |
03e9f0ca | 299 | .set_mux = tegra_pinctrl_set_mux, |
971dac71 SW |
300 | }; |
301 | ||
302 | static int tegra_pinconf_reg(struct tegra_pmx *pmx, | |
303 | const struct tegra_pingroup *g, | |
304 | enum tegra_pinconf_param param, | |
b5badbaa | 305 | bool report_err, |
971dac71 SW |
306 | s8 *bank, s16 *reg, s8 *bit, s8 *width) |
307 | { | |
308 | switch (param) { | |
309 | case TEGRA_PINCONF_PARAM_PULL: | |
310 | *bank = g->pupd_bank; | |
311 | *reg = g->pupd_reg; | |
312 | *bit = g->pupd_bit; | |
313 | *width = 2; | |
314 | break; | |
315 | case TEGRA_PINCONF_PARAM_TRISTATE: | |
316 | *bank = g->tri_bank; | |
317 | *reg = g->tri_reg; | |
318 | *bit = g->tri_bit; | |
319 | *width = 1; | |
320 | break; | |
321 | case TEGRA_PINCONF_PARAM_ENABLE_INPUT: | |
e53b7974 SW |
322 | *bank = g->mux_bank; |
323 | *reg = g->mux_reg; | |
971dac71 SW |
324 | *bit = g->einput_bit; |
325 | *width = 1; | |
326 | break; | |
327 | case TEGRA_PINCONF_PARAM_OPEN_DRAIN: | |
e53b7974 SW |
328 | *bank = g->mux_bank; |
329 | *reg = g->mux_reg; | |
971dac71 SW |
330 | *bit = g->odrain_bit; |
331 | *width = 1; | |
332 | break; | |
333 | case TEGRA_PINCONF_PARAM_LOCK: | |
e53b7974 SW |
334 | *bank = g->mux_bank; |
335 | *reg = g->mux_reg; | |
971dac71 SW |
336 | *bit = g->lock_bit; |
337 | *width = 1; | |
338 | break; | |
339 | case TEGRA_PINCONF_PARAM_IORESET: | |
e53b7974 SW |
340 | *bank = g->mux_bank; |
341 | *reg = g->mux_reg; | |
971dac71 SW |
342 | *bit = g->ioreset_bit; |
343 | *width = 1; | |
344 | break; | |
348d1bf7 | 345 | case TEGRA_PINCONF_PARAM_RCV_SEL: |
e53b7974 SW |
346 | *bank = g->mux_bank; |
347 | *reg = g->mux_reg; | |
348d1bf7 PR |
348 | *bit = g->rcv_sel_bit; |
349 | *width = 1; | |
350 | break; | |
971dac71 | 351 | case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE: |
ea623061 SW |
352 | if (pmx->soc->hsm_in_mux) { |
353 | *bank = g->mux_bank; | |
354 | *reg = g->mux_reg; | |
355 | } else { | |
356 | *bank = g->drv_bank; | |
357 | *reg = g->drv_reg; | |
358 | } | |
971dac71 SW |
359 | *bit = g->hsm_bit; |
360 | *width = 1; | |
361 | break; | |
362 | case TEGRA_PINCONF_PARAM_SCHMITT: | |
ea623061 SW |
363 | if (pmx->soc->schmitt_in_mux) { |
364 | *bank = g->mux_bank; | |
365 | *reg = g->mux_reg; | |
366 | } else { | |
367 | *bank = g->drv_bank; | |
368 | *reg = g->drv_reg; | |
369 | } | |
971dac71 SW |
370 | *bit = g->schmitt_bit; |
371 | *width = 1; | |
372 | break; | |
373 | case TEGRA_PINCONF_PARAM_LOW_POWER_MODE: | |
374 | *bank = g->drv_bank; | |
375 | *reg = g->drv_reg; | |
376 | *bit = g->lpmd_bit; | |
154f3ebf | 377 | *width = 2; |
971dac71 SW |
378 | break; |
379 | case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH: | |
380 | *bank = g->drv_bank; | |
381 | *reg = g->drv_reg; | |
382 | *bit = g->drvdn_bit; | |
383 | *width = g->drvdn_width; | |
384 | break; | |
385 | case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH: | |
386 | *bank = g->drv_bank; | |
387 | *reg = g->drv_reg; | |
388 | *bit = g->drvup_bit; | |
389 | *width = g->drvup_width; | |
390 | break; | |
391 | case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING: | |
392 | *bank = g->drv_bank; | |
393 | *reg = g->drv_reg; | |
394 | *bit = g->slwf_bit; | |
395 | *width = g->slwf_width; | |
396 | break; | |
397 | case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING: | |
398 | *bank = g->drv_bank; | |
399 | *reg = g->drv_reg; | |
400 | *bit = g->slwr_bit; | |
401 | *width = g->slwr_width; | |
402 | break; | |
348d1bf7 | 403 | case TEGRA_PINCONF_PARAM_DRIVE_TYPE: |
ea623061 SW |
404 | if (pmx->soc->drvtype_in_mux) { |
405 | *bank = g->mux_bank; | |
406 | *reg = g->mux_reg; | |
407 | } else { | |
408 | *bank = g->drv_bank; | |
409 | *reg = g->drv_reg; | |
410 | } | |
348d1bf7 PR |
411 | *bit = g->drvtype_bit; |
412 | *width = 2; | |
413 | break; | |
971dac71 SW |
414 | default: |
415 | dev_err(pmx->dev, "Invalid config param %04x\n", param); | |
416 | return -ENOTSUPP; | |
417 | } | |
418 | ||
e53b7974 | 419 | if (*reg < 0 || *bit > 31) { |
36e80dca SW |
420 | if (report_err) { |
421 | const char *prop = "unknown"; | |
422 | int i; | |
423 | ||
424 | for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { | |
425 | if (cfg_params[i].param == param) { | |
426 | prop = cfg_params[i].property; | |
427 | break; | |
428 | } | |
429 | } | |
430 | ||
b5badbaa | 431 | dev_err(pmx->dev, |
36e80dca SW |
432 | "Config param %04x (%s) not supported on group %s\n", |
433 | param, prop, g->name); | |
434 | } | |
971dac71 SW |
435 | return -ENOTSUPP; |
436 | } | |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
441 | static int tegra_pinconf_get(struct pinctrl_dev *pctldev, | |
442 | unsigned pin, unsigned long *config) | |
443 | { | |
aef7704c | 444 | dev_err(pctldev->dev, "pin_config_get op not supported\n"); |
971dac71 SW |
445 | return -ENOTSUPP; |
446 | } | |
447 | ||
448 | static int tegra_pinconf_set(struct pinctrl_dev *pctldev, | |
03b054e9 SY |
449 | unsigned pin, unsigned long *configs, |
450 | unsigned num_configs) | |
971dac71 | 451 | { |
aef7704c | 452 | dev_err(pctldev->dev, "pin_config_set op not supported\n"); |
971dac71 SW |
453 | return -ENOTSUPP; |
454 | } | |
455 | ||
456 | static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev, | |
457 | unsigned group, unsigned long *config) | |
458 | { | |
459 | struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
460 | enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config); | |
461 | u16 arg; | |
462 | const struct tegra_pingroup *g; | |
463 | int ret; | |
464 | s8 bank, bit, width; | |
465 | s16 reg; | |
466 | u32 val, mask; | |
467 | ||
971dac71 SW |
468 | g = &pmx->soc->groups[group]; |
469 | ||
b5badbaa SW |
470 | ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, |
471 | &width); | |
971dac71 SW |
472 | if (ret < 0) |
473 | return ret; | |
474 | ||
475 | val = pmx_readl(pmx, bank, reg); | |
476 | mask = (1 << width) - 1; | |
477 | arg = (val >> bit) & mask; | |
478 | ||
479 | *config = TEGRA_PINCONF_PACK(param, arg); | |
480 | ||
481 | return 0; | |
482 | } | |
483 | ||
484 | static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, | |
03b054e9 SY |
485 | unsigned group, unsigned long *configs, |
486 | unsigned num_configs) | |
971dac71 SW |
487 | { |
488 | struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
03b054e9 SY |
489 | enum tegra_pinconf_param param; |
490 | u16 arg; | |
971dac71 | 491 | const struct tegra_pingroup *g; |
03b054e9 | 492 | int ret, i; |
971dac71 SW |
493 | s8 bank, bit, width; |
494 | s16 reg; | |
495 | u32 val, mask; | |
496 | ||
971dac71 SW |
497 | g = &pmx->soc->groups[group]; |
498 | ||
03b054e9 SY |
499 | for (i = 0; i < num_configs; i++) { |
500 | param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]); | |
501 | arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]); | |
971dac71 | 502 | |
03b054e9 SY |
503 | ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, |
504 | &width); | |
505 | if (ret < 0) | |
506 | return ret; | |
971dac71 | 507 | |
03b054e9 SY |
508 | val = pmx_readl(pmx, bank, reg); |
509 | ||
510 | /* LOCK can't be cleared */ | |
511 | if (param == TEGRA_PINCONF_PARAM_LOCK) { | |
512 | if ((val & BIT(bit)) && !arg) { | |
513 | dev_err(pctldev->dev, "LOCK bit cannot be cleared\n"); | |
514 | return -EINVAL; | |
515 | } | |
aef7704c | 516 | } |
971dac71 | 517 | |
03b054e9 SY |
518 | /* Special-case Boolean values; allow any non-zero as true */ |
519 | if (width == 1) | |
520 | arg = !!arg; | |
971dac71 | 521 | |
03b054e9 SY |
522 | /* Range-check user-supplied value */ |
523 | mask = (1 << width) - 1; | |
524 | if (arg & ~mask) { | |
525 | dev_err(pctldev->dev, | |
526 | "config %lx: %x too big for %d bit register\n", | |
527 | configs[i], arg, width); | |
528 | return -EINVAL; | |
529 | } | |
971dac71 | 530 | |
03b054e9 SY |
531 | /* Update register */ |
532 | val &= ~(mask << bit); | |
533 | val |= arg << bit; | |
534 | pmx_writel(pmx, val, bank, reg); | |
535 | } /* for each config */ | |
971dac71 SW |
536 | |
537 | return 0; | |
538 | } | |
539 | ||
b5badbaa | 540 | #ifdef CONFIG_DEBUG_FS |
971dac71 SW |
541 | static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev, |
542 | struct seq_file *s, unsigned offset) | |
543 | { | |
544 | } | |
545 | ||
b5badbaa SW |
546 | static const char *strip_prefix(const char *s) |
547 | { | |
548 | const char *comma = strchr(s, ','); | |
549 | if (!comma) | |
550 | return s; | |
551 | ||
552 | return comma + 1; | |
553 | } | |
554 | ||
971dac71 | 555 | static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, |
b5badbaa SW |
556 | struct seq_file *s, unsigned group) |
557 | { | |
558 | struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
559 | const struct tegra_pingroup *g; | |
560 | int i, ret; | |
561 | s8 bank, bit, width; | |
562 | s16 reg; | |
563 | u32 val; | |
564 | ||
565 | g = &pmx->soc->groups[group]; | |
566 | ||
567 | for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { | |
568 | ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false, | |
569 | &bank, ®, &bit, &width); | |
570 | if (ret < 0) | |
571 | continue; | |
572 | ||
573 | val = pmx_readl(pmx, bank, reg); | |
574 | val >>= bit; | |
575 | val &= (1 << width) - 1; | |
576 | ||
577 | seq_printf(s, "\n\t%s=%u", | |
578 | strip_prefix(cfg_params[i].property), val); | |
579 | } | |
580 | } | |
581 | ||
582 | static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev, | |
583 | struct seq_file *s, | |
584 | unsigned long config) | |
971dac71 | 585 | { |
b5badbaa SW |
586 | enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config); |
587 | u16 arg = TEGRA_PINCONF_UNPACK_ARG(config); | |
588 | const char *pname = "unknown"; | |
589 | int i; | |
590 | ||
591 | for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { | |
592 | if (cfg_params[i].param == param) { | |
593 | pname = cfg_params[i].property; | |
594 | break; | |
595 | } | |
596 | } | |
597 | ||
598 | seq_printf(s, "%s=%d", strip_prefix(pname), arg); | |
971dac71 | 599 | } |
b5badbaa | 600 | #endif |
971dac71 | 601 | |
022ab148 | 602 | static const struct pinconf_ops tegra_pinconf_ops = { |
971dac71 SW |
603 | .pin_config_get = tegra_pinconf_get, |
604 | .pin_config_set = tegra_pinconf_set, | |
605 | .pin_config_group_get = tegra_pinconf_group_get, | |
606 | .pin_config_group_set = tegra_pinconf_group_set, | |
b5badbaa | 607 | #ifdef CONFIG_DEBUG_FS |
971dac71 SW |
608 | .pin_config_dbg_show = tegra_pinconf_dbg_show, |
609 | .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show, | |
b5badbaa SW |
610 | .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show, |
611 | #endif | |
971dac71 SW |
612 | }; |
613 | ||
614 | static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = { | |
615 | .name = "Tegra GPIOs", | |
616 | .id = 0, | |
617 | .base = 0, | |
618 | }; | |
619 | ||
620 | static struct pinctrl_desc tegra_pinctrl_desc = { | |
971dac71 SW |
621 | .pctlops = &tegra_pinctrl_ops, |
622 | .pmxops = &tegra_pinmux_ops, | |
623 | .confops = &tegra_pinconf_ops, | |
624 | .owner = THIS_MODULE, | |
625 | }; | |
626 | ||
9462510c TV |
627 | static bool gpio_node_has_range(void) |
628 | { | |
629 | struct device_node *np; | |
630 | bool has_prop = false; | |
631 | ||
632 | np = of_find_compatible_node(NULL, NULL, "nvidia,tegra30-gpio"); | |
633 | if (!np) | |
634 | return has_prop; | |
635 | ||
636 | has_prop = of_find_property(np, "gpio-ranges", NULL); | |
637 | ||
638 | of_node_put(np); | |
639 | ||
640 | return has_prop; | |
641 | } | |
642 | ||
150632b0 | 643 | int tegra_pinctrl_probe(struct platform_device *pdev, |
52f48fe0 | 644 | const struct tegra_pinctrl_soc_data *soc_data) |
971dac71 | 645 | { |
971dac71 SW |
646 | struct tegra_pmx *pmx; |
647 | struct resource *res; | |
648 | int i; | |
ce436254 SW |
649 | const char **group_pins; |
650 | int fn, gn, gfn; | |
971dac71 | 651 | |
971dac71 SW |
652 | pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); |
653 | if (!pmx) { | |
654 | dev_err(&pdev->dev, "Can't alloc tegra_pmx\n"); | |
655 | return -ENOMEM; | |
656 | } | |
657 | pmx->dev = &pdev->dev; | |
52f48fe0 | 658 | pmx->soc = soc_data; |
971dac71 | 659 | |
ce436254 SW |
660 | /* |
661 | * Each mux group will appear in 4 functions' list of groups. | |
662 | * This over-allocates slightly, since not all groups are mux groups. | |
663 | */ | |
664 | pmx->group_pins = devm_kzalloc(&pdev->dev, | |
665 | soc_data->ngroups * 4 * sizeof(*pmx->group_pins), | |
666 | GFP_KERNEL); | |
667 | if (!pmx->group_pins) | |
668 | return -ENOMEM; | |
669 | ||
670 | group_pins = pmx->group_pins; | |
671 | for (fn = 0; fn < soc_data->nfunctions; fn++) { | |
672 | struct tegra_function *func = &soc_data->functions[fn]; | |
673 | ||
674 | func->groups = group_pins; | |
675 | ||
676 | for (gn = 0; gn < soc_data->ngroups; gn++) { | |
677 | const struct tegra_pingroup *g = &soc_data->groups[gn]; | |
678 | ||
679 | if (g->mux_reg == -1) | |
680 | continue; | |
681 | ||
682 | for (gfn = 0; gfn < 4; gfn++) | |
683 | if (g->funcs[gfn] == fn) | |
684 | break; | |
685 | if (gfn == 4) | |
686 | continue; | |
687 | ||
688 | BUG_ON(group_pins - pmx->group_pins >= | |
689 | soc_data->ngroups * 4); | |
690 | *group_pins++ = g->name; | |
691 | func->ngroups++; | |
692 | } | |
693 | } | |
694 | ||
971dac71 | 695 | tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios; |
52f48fe0 | 696 | tegra_pinctrl_desc.name = dev_name(&pdev->dev); |
971dac71 SW |
697 | tegra_pinctrl_desc.pins = pmx->soc->pins; |
698 | tegra_pinctrl_desc.npins = pmx->soc->npins; | |
699 | ||
700 | for (i = 0; ; i++) { | |
701 | res = platform_get_resource(pdev, IORESOURCE_MEM, i); | |
702 | if (!res) | |
703 | break; | |
704 | } | |
705 | pmx->nbanks = i; | |
706 | ||
707 | pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs), | |
708 | GFP_KERNEL); | |
709 | if (!pmx->regs) { | |
710 | dev_err(&pdev->dev, "Can't alloc regs pointer\n"); | |
5b232c5a | 711 | return -ENOMEM; |
971dac71 SW |
712 | } |
713 | ||
714 | for (i = 0; i < pmx->nbanks; i++) { | |
715 | res = platform_get_resource(pdev, IORESOURCE_MEM, i); | |
394a8ff8 AL |
716 | pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res); |
717 | if (IS_ERR(pmx->regs[i])) | |
718 | return PTR_ERR(pmx->regs[i]); | |
971dac71 SW |
719 | } |
720 | ||
721 | pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx); | |
323de9ef | 722 | if (IS_ERR(pmx->pctl)) { |
971dac71 | 723 | dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); |
323de9ef | 724 | return PTR_ERR(pmx->pctl); |
971dac71 SW |
725 | } |
726 | ||
9462510c TV |
727 | if (!gpio_node_has_range()) |
728 | pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range); | |
971dac71 SW |
729 | |
730 | platform_set_drvdata(pdev, pmx); | |
731 | ||
732 | dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n"); | |
733 | ||
734 | return 0; | |
735 | } | |
52f48fe0 | 736 | EXPORT_SYMBOL_GPL(tegra_pinctrl_probe); |
971dac71 | 737 | |
f90f54b3 | 738 | int tegra_pinctrl_remove(struct platform_device *pdev) |
971dac71 SW |
739 | { |
740 | struct tegra_pmx *pmx = platform_get_drvdata(pdev); | |
741 | ||
971dac71 SW |
742 | pinctrl_unregister(pmx->pctl); |
743 | ||
744 | return 0; | |
745 | } | |
52f48fe0 | 746 | EXPORT_SYMBOL_GPL(tegra_pinctrl_remove); |