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3f8c50c9 JC |
1 | /* |
2 | * linux/drivers/pinctrl/pinmux-xway.c | |
3 | * based on linux/drivers/pinctrl/pinmux-pxa910.c | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * publishhed by the Free Software Foundation. | |
8 | * | |
9 | * Copyright (C) 2012 John Crispin <blogic@openwrt.org> | |
10 | */ | |
11 | ||
12 | #include <linux/slab.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/of_platform.h> | |
15 | #include <linux/of_address.h> | |
16 | #include <linux/of_gpio.h> | |
17 | #include <linux/ioport.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/device.h> | |
3f8c50c9 JC |
20 | #include <linux/platform_device.h> |
21 | ||
22 | #include "pinctrl-lantiq.h" | |
23 | ||
24 | #include <lantiq_soc.h> | |
25 | ||
26 | /* we have 3 1/2 banks of 16 bit each */ | |
27 | #define PINS 16 | |
28 | #define PORT3 3 | |
29 | #define PORT(x) (x / PINS) | |
30 | #define PORT_PIN(x) (x % PINS) | |
31 | ||
32 | /* we have 2 mux bits that can be set for each pin */ | |
33 | #define MUX_ALT0 0x1 | |
34 | #define MUX_ALT1 0x2 | |
35 | ||
36 | /* | |
37 | * each bank has this offset apart from the 1/2 bank that is mixed into the | |
38 | * other 3 ranges | |
39 | */ | |
40 | #define REG_OFF 0x30 | |
41 | ||
42 | /* these are the offsets to our registers */ | |
43 | #define GPIO_BASE(p) (REG_OFF * PORT(p)) | |
44 | #define GPIO_OUT(p) GPIO_BASE(p) | |
45 | #define GPIO_IN(p) (GPIO_BASE(p) + 0x04) | |
46 | #define GPIO_DIR(p) (GPIO_BASE(p) + 0x08) | |
47 | #define GPIO_ALT0(p) (GPIO_BASE(p) + 0x0C) | |
48 | #define GPIO_ALT1(p) (GPIO_BASE(p) + 0x10) | |
49 | #define GPIO_OD(p) (GPIO_BASE(p) + 0x14) | |
50 | #define GPIO_PUDSEL(p) (GPIO_BASE(p) + 0x1c) | |
51 | #define GPIO_PUDEN(p) (GPIO_BASE(p) + 0x20) | |
52 | ||
53 | /* the 1/2 port needs special offsets for some registers */ | |
54 | #define GPIO3_OD (GPIO_BASE(0) + 0x24) | |
55 | #define GPIO3_PUDSEL (GPIO_BASE(0) + 0x28) | |
56 | #define GPIO3_PUDEN (GPIO_BASE(0) + 0x2C) | |
57 | #define GPIO3_ALT1 (GPIO_BASE(PINS) + 0x24) | |
58 | ||
59 | /* macros to help us access the registers */ | |
60 | #define gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & BIT(p))) | |
61 | #define gpio_setbit(m, r, p) ltq_w32_mask(0, BIT(p), m + r) | |
62 | #define gpio_clearbit(m, r, p) ltq_w32_mask(BIT(p), 0, m + r) | |
63 | ||
64 | #define MFP_XWAY(a, f0, f1, f2, f3) \ | |
65 | { \ | |
66 | .name = #a, \ | |
67 | .pin = a, \ | |
68 | .func = { \ | |
69 | XWAY_MUX_##f0, \ | |
70 | XWAY_MUX_##f1, \ | |
71 | XWAY_MUX_##f2, \ | |
72 | XWAY_MUX_##f3, \ | |
73 | }, \ | |
74 | } | |
75 | ||
76 | #define GRP_MUX(a, m, p) \ | |
77 | { .name = a, .mux = XWAY_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), } | |
78 | ||
79 | #define FUNC_MUX(f, m) \ | |
80 | { .func = f, .mux = XWAY_MUX_##m, } | |
81 | ||
82 | #define XWAY_MAX_PIN 32 | |
83 | #define XR9_MAX_PIN 56 | |
84 | ||
85 | enum xway_mux { | |
86 | XWAY_MUX_GPIO = 0, | |
87 | XWAY_MUX_SPI, | |
88 | XWAY_MUX_ASC, | |
89 | XWAY_MUX_PCI, | |
90 | XWAY_MUX_CGU, | |
91 | XWAY_MUX_EBU, | |
92 | XWAY_MUX_JTAG, | |
93 | XWAY_MUX_EXIN, | |
94 | XWAY_MUX_TDM, | |
95 | XWAY_MUX_STP, | |
96 | XWAY_MUX_SIN, | |
97 | XWAY_MUX_GPT, | |
98 | XWAY_MUX_NMI, | |
99 | XWAY_MUX_MDIO, | |
100 | XWAY_MUX_MII, | |
101 | XWAY_MUX_EPHY, | |
102 | XWAY_MUX_DFE, | |
103 | XWAY_MUX_SDIO, | |
104 | XWAY_MUX_NONE = 0xffff, | |
105 | }; | |
106 | ||
107 | static const struct ltq_mfp_pin xway_mfp[] = { | |
108 | /* pin f0 f1 f2 f3 */ | |
109 | MFP_XWAY(GPIO0, GPIO, EXIN, NONE, TDM), | |
110 | MFP_XWAY(GPIO1, GPIO, EXIN, NONE, NONE), | |
111 | MFP_XWAY(GPIO2, GPIO, CGU, EXIN, NONE), | |
112 | MFP_XWAY(GPIO3, GPIO, CGU, NONE, PCI), | |
113 | MFP_XWAY(GPIO4, GPIO, STP, NONE, ASC), | |
114 | MFP_XWAY(GPIO5, GPIO, STP, NONE, NONE), | |
115 | MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC), | |
116 | MFP_XWAY(GPIO7, GPIO, CGU, PCI, NONE), | |
117 | MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE), | |
118 | MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN), | |
119 | MFP_XWAY(GPIO10, GPIO, ASC, SPI, NONE), | |
120 | MFP_XWAY(GPIO11, GPIO, ASC, PCI, SPI), | |
121 | MFP_XWAY(GPIO12, GPIO, ASC, NONE, NONE), | |
122 | MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE), | |
123 | MFP_XWAY(GPIO14, GPIO, CGU, PCI, NONE), | |
124 | MFP_XWAY(GPIO15, GPIO, SPI, JTAG, NONE), | |
125 | MFP_XWAY(GPIO16, GPIO, SPI, NONE, JTAG), | |
126 | MFP_XWAY(GPIO17, GPIO, SPI, NONE, JTAG), | |
127 | MFP_XWAY(GPIO18, GPIO, SPI, NONE, JTAG), | |
128 | MFP_XWAY(GPIO19, GPIO, PCI, NONE, NONE), | |
129 | MFP_XWAY(GPIO20, GPIO, JTAG, NONE, NONE), | |
130 | MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT), | |
131 | MFP_XWAY(GPIO22, GPIO, SPI, NONE, NONE), | |
132 | MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP), | |
133 | MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI), | |
134 | MFP_XWAY(GPIO25, GPIO, TDM, NONE, ASC), | |
135 | MFP_XWAY(GPIO26, GPIO, EBU, NONE, TDM), | |
136 | MFP_XWAY(GPIO27, GPIO, TDM, NONE, ASC), | |
137 | MFP_XWAY(GPIO28, GPIO, GPT, NONE, NONE), | |
138 | MFP_XWAY(GPIO29, GPIO, PCI, NONE, NONE), | |
139 | MFP_XWAY(GPIO30, GPIO, PCI, NONE, NONE), | |
140 | MFP_XWAY(GPIO31, GPIO, EBU, PCI, NONE), | |
141 | MFP_XWAY(GPIO32, GPIO, NONE, NONE, EBU), | |
142 | MFP_XWAY(GPIO33, GPIO, NONE, NONE, EBU), | |
143 | MFP_XWAY(GPIO34, GPIO, NONE, NONE, EBU), | |
144 | MFP_XWAY(GPIO35, GPIO, NONE, NONE, EBU), | |
145 | MFP_XWAY(GPIO36, GPIO, SIN, NONE, EBU), | |
146 | MFP_XWAY(GPIO37, GPIO, PCI, NONE, NONE), | |
147 | MFP_XWAY(GPIO38, GPIO, PCI, NONE, NONE), | |
148 | MFP_XWAY(GPIO39, GPIO, EXIN, NONE, NONE), | |
149 | MFP_XWAY(GPIO40, GPIO, NONE, NONE, NONE), | |
150 | MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE), | |
151 | MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE), | |
152 | MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE), | |
153 | MFP_XWAY(GPIO44, GPIO, NONE, NONE, SIN), | |
154 | MFP_XWAY(GPIO45, GPIO, NONE, NONE, SIN), | |
155 | MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN), | |
156 | MFP_XWAY(GPIO47, GPIO, NONE, NONE, SIN), | |
157 | MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE), | |
158 | MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE), | |
159 | MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE), | |
160 | MFP_XWAY(GPIO51, GPIO, NONE, NONE, NONE), | |
161 | MFP_XWAY(GPIO52, GPIO, NONE, NONE, NONE), | |
162 | MFP_XWAY(GPIO53, GPIO, NONE, NONE, NONE), | |
163 | MFP_XWAY(GPIO54, GPIO, NONE, NONE, NONE), | |
164 | MFP_XWAY(GPIO55, GPIO, NONE, NONE, NONE), | |
165 | }; | |
166 | ||
167 | static const struct ltq_mfp_pin ase_mfp[] = { | |
168 | /* pin f0 f1 f2 f3 */ | |
169 | MFP_XWAY(GPIO0, GPIO, EXIN, MII, TDM), | |
170 | MFP_XWAY(GPIO1, GPIO, STP, DFE, EBU), | |
171 | MFP_XWAY(GPIO2, GPIO, STP, DFE, EPHY), | |
172 | MFP_XWAY(GPIO3, GPIO, STP, EPHY, EBU), | |
173 | MFP_XWAY(GPIO4, GPIO, GPT, EPHY, MII), | |
174 | MFP_XWAY(GPIO5, GPIO, MII, ASC, GPT), | |
175 | MFP_XWAY(GPIO6, GPIO, MII, ASC, EXIN), | |
176 | MFP_XWAY(GPIO7, GPIO, SPI, MII, JTAG), | |
177 | MFP_XWAY(GPIO8, GPIO, SPI, MII, JTAG), | |
178 | MFP_XWAY(GPIO9, GPIO, SPI, MII, JTAG), | |
179 | MFP_XWAY(GPIO10, GPIO, SPI, MII, JTAG), | |
180 | MFP_XWAY(GPIO11, GPIO, EBU, CGU, JTAG), | |
181 | MFP_XWAY(GPIO12, GPIO, EBU, MII, SDIO), | |
182 | MFP_XWAY(GPIO13, GPIO, EBU, MII, CGU), | |
183 | MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU), | |
184 | MFP_XWAY(GPIO15, GPIO, EBU, SPI, SDIO), | |
185 | MFP_XWAY(GPIO16, GPIO, NONE, NONE, NONE), | |
186 | MFP_XWAY(GPIO17, GPIO, NONE, NONE, NONE), | |
187 | MFP_XWAY(GPIO18, GPIO, NONE, NONE, NONE), | |
188 | MFP_XWAY(GPIO19, GPIO, EBU, MII, SDIO), | |
189 | MFP_XWAY(GPIO20, GPIO, EBU, MII, SDIO), | |
190 | MFP_XWAY(GPIO21, GPIO, EBU, MII, SDIO), | |
191 | MFP_XWAY(GPIO22, GPIO, EBU, MII, CGU), | |
192 | MFP_XWAY(GPIO23, GPIO, EBU, MII, CGU), | |
193 | MFP_XWAY(GPIO24, GPIO, EBU, NONE, MII), | |
194 | MFP_XWAY(GPIO25, GPIO, EBU, MII, GPT), | |
195 | MFP_XWAY(GPIO26, GPIO, EBU, MII, SDIO), | |
196 | MFP_XWAY(GPIO27, GPIO, EBU, NONE, MII), | |
197 | MFP_XWAY(GPIO28, GPIO, MII, EBU, SDIO), | |
198 | MFP_XWAY(GPIO29, GPIO, EBU, MII, EXIN), | |
199 | MFP_XWAY(GPIO30, GPIO, NONE, NONE, NONE), | |
200 | MFP_XWAY(GPIO31, GPIO, NONE, NONE, NONE), | |
201 | }; | |
202 | ||
203 | static const unsigned pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO19, GPIO35}; | |
204 | static const unsigned pins_asc0[] = {GPIO11, GPIO12}; | |
205 | static const unsigned pins_asc0_cts_rts[] = {GPIO9, GPIO10}; | |
206 | static const unsigned pins_stp[] = {GPIO4, GPIO5, GPIO6}; | |
207 | static const unsigned pins_nmi[] = {GPIO8}; | |
208 | static const unsigned pins_mdio[] = {GPIO42, GPIO43}; | |
209 | ||
210 | static const unsigned pins_ebu_a24[] = {GPIO13}; | |
211 | static const unsigned pins_ebu_clk[] = {GPIO21}; | |
212 | static const unsigned pins_ebu_cs1[] = {GPIO23}; | |
213 | static const unsigned pins_ebu_a23[] = {GPIO24}; | |
214 | static const unsigned pins_ebu_wait[] = {GPIO26}; | |
215 | static const unsigned pins_ebu_a25[] = {GPIO31}; | |
216 | static const unsigned pins_ebu_rdy[] = {GPIO48}; | |
217 | static const unsigned pins_ebu_rd[] = {GPIO49}; | |
218 | ||
219 | static const unsigned pins_nand_ale[] = {GPIO13}; | |
220 | static const unsigned pins_nand_cs1[] = {GPIO23}; | |
221 | static const unsigned pins_nand_cle[] = {GPIO24}; | |
222 | static const unsigned pins_nand_rdy[] = {GPIO48}; | |
223 | static const unsigned pins_nand_rd[] = {GPIO49}; | |
224 | ||
225 | static const unsigned pins_exin0[] = {GPIO0}; | |
226 | static const unsigned pins_exin1[] = {GPIO1}; | |
227 | static const unsigned pins_exin2[] = {GPIO2}; | |
228 | static const unsigned pins_exin3[] = {GPIO39}; | |
229 | static const unsigned pins_exin4[] = {GPIO46}; | |
230 | static const unsigned pins_exin5[] = {GPIO9}; | |
231 | ||
232 | static const unsigned pins_spi[] = {GPIO16, GPIO17, GPIO18}; | |
233 | static const unsigned pins_spi_cs1[] = {GPIO15}; | |
234 | static const unsigned pins_spi_cs2[] = {GPIO21}; | |
235 | static const unsigned pins_spi_cs3[] = {GPIO13}; | |
236 | static const unsigned pins_spi_cs4[] = {GPIO10}; | |
237 | static const unsigned pins_spi_cs5[] = {GPIO9}; | |
238 | static const unsigned pins_spi_cs6[] = {GPIO11}; | |
239 | ||
240 | static const unsigned pins_gpt1[] = {GPIO28}; | |
241 | static const unsigned pins_gpt2[] = {GPIO21}; | |
242 | static const unsigned pins_gpt3[] = {GPIO6}; | |
243 | ||
244 | static const unsigned pins_clkout0[] = {GPIO8}; | |
245 | static const unsigned pins_clkout1[] = {GPIO7}; | |
246 | static const unsigned pins_clkout2[] = {GPIO3}; | |
247 | static const unsigned pins_clkout3[] = {GPIO2}; | |
248 | ||
249 | static const unsigned pins_pci_gnt1[] = {GPIO30}; | |
250 | static const unsigned pins_pci_gnt2[] = {GPIO23}; | |
251 | static const unsigned pins_pci_gnt3[] = {GPIO19}; | |
252 | static const unsigned pins_pci_gnt4[] = {GPIO38}; | |
253 | static const unsigned pins_pci_req1[] = {GPIO29}; | |
254 | static const unsigned pins_pci_req2[] = {GPIO31}; | |
255 | static const unsigned pins_pci_req3[] = {GPIO3}; | |
256 | static const unsigned pins_pci_req4[] = {GPIO37}; | |
257 | ||
258 | static const unsigned ase_pins_jtag[] = {GPIO7, GPIO8, GPIO9, GPIO10, GPIO11}; | |
259 | static const unsigned ase_pins_asc[] = {GPIO5, GPIO6}; | |
260 | static const unsigned ase_pins_stp[] = {GPIO1, GPIO2, GPIO3}; | |
261 | static const unsigned ase_pins_ephy[] = {GPIO2, GPIO3, GPIO4}; | |
262 | static const unsigned ase_pins_dfe[] = {GPIO1, GPIO2}; | |
263 | ||
264 | static const unsigned ase_pins_spi[] = {GPIO8, GPIO9, GPIO10}; | |
265 | static const unsigned ase_pins_spi_cs1[] = {GPIO7}; | |
266 | static const unsigned ase_pins_spi_cs2[] = {GPIO15}; | |
267 | static const unsigned ase_pins_spi_cs3[] = {GPIO14}; | |
268 | ||
269 | static const unsigned ase_pins_exin0[] = {GPIO6}; | |
270 | static const unsigned ase_pins_exin1[] = {GPIO29}; | |
271 | static const unsigned ase_pins_exin2[] = {GPIO0}; | |
272 | ||
273 | static const unsigned ase_pins_gpt1[] = {GPIO5}; | |
274 | static const unsigned ase_pins_gpt2[] = {GPIO4}; | |
275 | static const unsigned ase_pins_gpt3[] = {GPIO25}; | |
276 | ||
277 | static const struct ltq_pin_group xway_grps[] = { | |
278 | GRP_MUX("exin0", EXIN, pins_exin0), | |
279 | GRP_MUX("exin1", EXIN, pins_exin1), | |
280 | GRP_MUX("exin2", EXIN, pins_exin2), | |
281 | GRP_MUX("jtag", JTAG, pins_jtag), | |
282 | GRP_MUX("ebu a23", EBU, pins_ebu_a23), | |
283 | GRP_MUX("ebu a24", EBU, pins_ebu_a24), | |
284 | GRP_MUX("ebu a25", EBU, pins_ebu_a25), | |
285 | GRP_MUX("ebu clk", EBU, pins_ebu_clk), | |
286 | GRP_MUX("ebu cs1", EBU, pins_ebu_cs1), | |
287 | GRP_MUX("ebu wait", EBU, pins_ebu_wait), | |
288 | GRP_MUX("nand ale", EBU, pins_nand_ale), | |
289 | GRP_MUX("nand cs1", EBU, pins_nand_cs1), | |
290 | GRP_MUX("nand cle", EBU, pins_nand_cle), | |
291 | GRP_MUX("spi", SPI, pins_spi), | |
292 | GRP_MUX("spi_cs1", SPI, pins_spi_cs1), | |
293 | GRP_MUX("spi_cs2", SPI, pins_spi_cs2), | |
294 | GRP_MUX("spi_cs3", SPI, pins_spi_cs3), | |
295 | GRP_MUX("spi_cs4", SPI, pins_spi_cs4), | |
296 | GRP_MUX("spi_cs5", SPI, pins_spi_cs5), | |
297 | GRP_MUX("spi_cs6", SPI, pins_spi_cs6), | |
298 | GRP_MUX("asc0", ASC, pins_asc0), | |
299 | GRP_MUX("asc0 cts rts", ASC, pins_asc0_cts_rts), | |
300 | GRP_MUX("stp", STP, pins_stp), | |
301 | GRP_MUX("nmi", NMI, pins_nmi), | |
302 | GRP_MUX("gpt1", GPT, pins_gpt1), | |
303 | GRP_MUX("gpt2", GPT, pins_gpt2), | |
304 | GRP_MUX("gpt3", GPT, pins_gpt3), | |
305 | GRP_MUX("clkout0", CGU, pins_clkout0), | |
306 | GRP_MUX("clkout1", CGU, pins_clkout1), | |
307 | GRP_MUX("clkout2", CGU, pins_clkout2), | |
308 | GRP_MUX("clkout3", CGU, pins_clkout3), | |
309 | GRP_MUX("gnt1", PCI, pins_pci_gnt1), | |
310 | GRP_MUX("gnt2", PCI, pins_pci_gnt2), | |
311 | GRP_MUX("gnt3", PCI, pins_pci_gnt3), | |
312 | GRP_MUX("req1", PCI, pins_pci_req1), | |
313 | GRP_MUX("req2", PCI, pins_pci_req2), | |
314 | GRP_MUX("req3", PCI, pins_pci_req3), | |
315 | /* xrx only */ | |
316 | GRP_MUX("nand rdy", EBU, pins_nand_rdy), | |
317 | GRP_MUX("nand rd", EBU, pins_nand_rd), | |
318 | GRP_MUX("exin3", EXIN, pins_exin3), | |
319 | GRP_MUX("exin4", EXIN, pins_exin4), | |
320 | GRP_MUX("exin5", EXIN, pins_exin5), | |
321 | GRP_MUX("gnt4", PCI, pins_pci_gnt4), | |
322 | GRP_MUX("req4", PCI, pins_pci_gnt4), | |
323 | GRP_MUX("mdio", MDIO, pins_mdio), | |
324 | }; | |
325 | ||
326 | static const struct ltq_pin_group ase_grps[] = { | |
327 | GRP_MUX("exin0", EXIN, ase_pins_exin0), | |
328 | GRP_MUX("exin1", EXIN, ase_pins_exin1), | |
329 | GRP_MUX("exin2", EXIN, ase_pins_exin2), | |
330 | GRP_MUX("jtag", JTAG, ase_pins_jtag), | |
331 | GRP_MUX("stp", STP, ase_pins_stp), | |
332 | GRP_MUX("asc", ASC, ase_pins_asc), | |
333 | GRP_MUX("gpt1", GPT, ase_pins_gpt1), | |
334 | GRP_MUX("gpt2", GPT, ase_pins_gpt2), | |
335 | GRP_MUX("gpt3", GPT, ase_pins_gpt3), | |
336 | GRP_MUX("ephy", EPHY, ase_pins_ephy), | |
337 | GRP_MUX("dfe", DFE, ase_pins_dfe), | |
338 | GRP_MUX("spi", SPI, ase_pins_spi), | |
339 | GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1), | |
340 | GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2), | |
341 | GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3), | |
342 | }; | |
343 | ||
344 | static const char * const xway_pci_grps[] = {"gnt1", "gnt2", | |
345 | "gnt3", "req1", | |
346 | "req2", "req3"}; | |
347 | static const char * const xway_spi_grps[] = {"spi", "spi_cs1", | |
348 | "spi_cs2", "spi_cs3", | |
349 | "spi_cs4", "spi_cs5", | |
350 | "spi_cs6"}; | |
351 | static const char * const xway_cgu_grps[] = {"clkout0", "clkout1", | |
352 | "clkout2", "clkout3"}; | |
353 | static const char * const xway_ebu_grps[] = {"ebu a23", "ebu a24", | |
354 | "ebu a25", "ebu cs1", | |
355 | "ebu wait", "ebu clk", | |
356 | "nand ale", "nand cs1", | |
357 | "nand cle"}; | |
358 | static const char * const xway_exin_grps[] = {"exin0", "exin1", "exin2"}; | |
359 | static const char * const xway_gpt_grps[] = {"gpt1", "gpt2", "gpt3"}; | |
360 | static const char * const xway_asc_grps[] = {"asc0", "asc0 cts rts"}; | |
361 | static const char * const xway_jtag_grps[] = {"jtag"}; | |
362 | static const char * const xway_stp_grps[] = {"stp"}; | |
363 | static const char * const xway_nmi_grps[] = {"nmi"}; | |
364 | ||
365 | /* ar9/vr9/gr9 */ | |
366 | static const char * const xrx_mdio_grps[] = {"mdio"}; | |
367 | static const char * const xrx_ebu_grps[] = {"ebu a23", "ebu a24", | |
368 | "ebu a25", "ebu cs1", | |
369 | "ebu wait", "ebu clk", | |
370 | "nand ale", "nand cs1", | |
371 | "nand cle", "nand rdy", | |
372 | "nand rd"}; | |
373 | static const char * const xrx_exin_grps[] = {"exin0", "exin1", "exin2", | |
374 | "exin3", "exin4", "exin5"}; | |
375 | static const char * const xrx_pci_grps[] = {"gnt1", "gnt2", | |
376 | "gnt3", "gnt4", | |
377 | "req1", "req2", | |
378 | "req3", "req4"}; | |
379 | ||
380 | /* ase */ | |
381 | static const char * const ase_exin_grps[] = {"exin0", "exin1", "exin2"}; | |
382 | static const char * const ase_gpt_grps[] = {"gpt1", "gpt2", "gpt3"}; | |
383 | static const char * const ase_dfe_grps[] = {"dfe"}; | |
384 | static const char * const ase_ephy_grps[] = {"ephy"}; | |
385 | static const char * const ase_asc_grps[] = {"asc"}; | |
386 | static const char * const ase_jtag_grps[] = {"jtag"}; | |
387 | static const char * const ase_stp_grps[] = {"stp"}; | |
388 | static const char * const ase_spi_grps[] = {"spi", "spi_cs1", | |
389 | "spi_cs2", "spi_cs3"}; | |
390 | ||
391 | static const struct ltq_pmx_func danube_funcs[] = { | |
392 | {"spi", ARRAY_AND_SIZE(xway_spi_grps)}, | |
393 | {"asc", ARRAY_AND_SIZE(xway_asc_grps)}, | |
394 | {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)}, | |
395 | {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)}, | |
396 | {"exin", ARRAY_AND_SIZE(xway_exin_grps)}, | |
397 | {"stp", ARRAY_AND_SIZE(xway_stp_grps)}, | |
398 | {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)}, | |
399 | {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)}, | |
400 | {"pci", ARRAY_AND_SIZE(xway_pci_grps)}, | |
401 | {"ebu", ARRAY_AND_SIZE(xway_ebu_grps)}, | |
402 | }; | |
403 | ||
404 | static const struct ltq_pmx_func xrx_funcs[] = { | |
405 | {"spi", ARRAY_AND_SIZE(xway_spi_grps)}, | |
406 | {"asc", ARRAY_AND_SIZE(xway_asc_grps)}, | |
407 | {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)}, | |
408 | {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)}, | |
409 | {"exin", ARRAY_AND_SIZE(xrx_exin_grps)}, | |
410 | {"stp", ARRAY_AND_SIZE(xway_stp_grps)}, | |
411 | {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)}, | |
412 | {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)}, | |
413 | {"pci", ARRAY_AND_SIZE(xrx_pci_grps)}, | |
414 | {"ebu", ARRAY_AND_SIZE(xrx_ebu_grps)}, | |
415 | {"mdio", ARRAY_AND_SIZE(xrx_mdio_grps)}, | |
416 | }; | |
417 | ||
418 | static const struct ltq_pmx_func ase_funcs[] = { | |
419 | {"spi", ARRAY_AND_SIZE(ase_spi_grps)}, | |
420 | {"asc", ARRAY_AND_SIZE(ase_asc_grps)}, | |
421 | {"jtag", ARRAY_AND_SIZE(ase_jtag_grps)}, | |
422 | {"exin", ARRAY_AND_SIZE(ase_exin_grps)}, | |
423 | {"stp", ARRAY_AND_SIZE(ase_stp_grps)}, | |
424 | {"gpt", ARRAY_AND_SIZE(ase_gpt_grps)}, | |
425 | {"ephy", ARRAY_AND_SIZE(ase_ephy_grps)}, | |
426 | {"dfe", ARRAY_AND_SIZE(ase_dfe_grps)}, | |
427 | }; | |
428 | ||
429 | /* --------- pinconf related code --------- */ | |
430 | static int xway_pinconf_get(struct pinctrl_dev *pctldev, | |
431 | unsigned pin, | |
432 | unsigned long *config) | |
433 | { | |
434 | struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); | |
435 | enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config); | |
436 | int port = PORT(pin); | |
437 | u32 reg; | |
438 | ||
439 | switch (param) { | |
440 | case LTQ_PINCONF_PARAM_OPEN_DRAIN: | |
441 | if (port == PORT3) | |
442 | reg = GPIO3_OD; | |
443 | else | |
362ba3cf | 444 | reg = GPIO_OD(pin); |
3f8c50c9 | 445 | *config = LTQ_PINCONF_PACK(param, |
7541083f | 446 | !gpio_getbit(info->membase[0], reg, PORT_PIN(pin))); |
3f8c50c9 JC |
447 | break; |
448 | ||
449 | case LTQ_PINCONF_PARAM_PULL: | |
450 | if (port == PORT3) | |
451 | reg = GPIO3_PUDEN; | |
452 | else | |
362ba3cf JC |
453 | reg = GPIO_PUDEN(pin); |
454 | if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) { | |
3f8c50c9 JC |
455 | *config = LTQ_PINCONF_PACK(param, 0); |
456 | break; | |
457 | } | |
458 | ||
459 | if (port == PORT3) | |
460 | reg = GPIO3_PUDSEL; | |
461 | else | |
362ba3cf JC |
462 | reg = GPIO_PUDSEL(pin); |
463 | if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) | |
3f8c50c9 JC |
464 | *config = LTQ_PINCONF_PACK(param, 2); |
465 | else | |
466 | *config = LTQ_PINCONF_PACK(param, 1); | |
467 | break; | |
468 | ||
6360350c JC |
469 | case LTQ_PINCONF_PARAM_OUTPUT: |
470 | reg = GPIO_DIR(pin); | |
471 | *config = LTQ_PINCONF_PACK(param, | |
472 | gpio_getbit(info->membase[0], reg, PORT_PIN(pin))); | |
473 | break; | |
3f8c50c9 JC |
474 | default: |
475 | dev_err(pctldev->dev, "Invalid config param %04x\n", param); | |
476 | return -ENOTSUPP; | |
477 | } | |
478 | return 0; | |
479 | } | |
480 | ||
481 | static int xway_pinconf_set(struct pinctrl_dev *pctldev, | |
482 | unsigned pin, | |
483 | unsigned long config) | |
484 | { | |
485 | struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); | |
486 | enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(config); | |
487 | int arg = LTQ_PINCONF_UNPACK_ARG(config); | |
488 | int port = PORT(pin); | |
489 | u32 reg; | |
490 | ||
491 | switch (param) { | |
492 | case LTQ_PINCONF_PARAM_OPEN_DRAIN: | |
493 | if (port == PORT3) | |
494 | reg = GPIO3_OD; | |
495 | else | |
362ba3cf | 496 | reg = GPIO_OD(pin); |
93386287 JC |
497 | if (arg == 0) |
498 | gpio_setbit(info->membase[0], reg, PORT_PIN(pin)); | |
499 | else | |
500 | gpio_clearbit(info->membase[0], reg, PORT_PIN(pin)); | |
3f8c50c9 JC |
501 | break; |
502 | ||
503 | case LTQ_PINCONF_PARAM_PULL: | |
504 | if (port == PORT3) | |
505 | reg = GPIO3_PUDEN; | |
506 | else | |
362ba3cf | 507 | reg = GPIO_PUDEN(pin); |
3f8c50c9 | 508 | if (arg == 0) { |
362ba3cf | 509 | gpio_clearbit(info->membase[0], reg, PORT_PIN(pin)); |
3f8c50c9 JC |
510 | break; |
511 | } | |
362ba3cf | 512 | gpio_setbit(info->membase[0], reg, PORT_PIN(pin)); |
3f8c50c9 JC |
513 | |
514 | if (port == PORT3) | |
515 | reg = GPIO3_PUDSEL; | |
516 | else | |
362ba3cf | 517 | reg = GPIO_PUDSEL(pin); |
3f8c50c9 | 518 | if (arg == 1) |
362ba3cf | 519 | gpio_clearbit(info->membase[0], reg, PORT_PIN(pin)); |
3f8c50c9 | 520 | else if (arg == 2) |
362ba3cf | 521 | gpio_setbit(info->membase[0], reg, PORT_PIN(pin)); |
3f8c50c9 JC |
522 | else |
523 | dev_err(pctldev->dev, "Invalid pull value %d\n", arg); | |
524 | break; | |
525 | ||
6360350c JC |
526 | case LTQ_PINCONF_PARAM_OUTPUT: |
527 | reg = GPIO_DIR(pin); | |
528 | if (arg == 0) | |
529 | gpio_clearbit(info->membase[0], reg, PORT_PIN(pin)); | |
530 | else | |
531 | gpio_setbit(info->membase[0], reg, PORT_PIN(pin)); | |
532 | break; | |
533 | ||
3f8c50c9 JC |
534 | default: |
535 | dev_err(pctldev->dev, "Invalid config param %04x\n", param); | |
536 | return -ENOTSUPP; | |
537 | } | |
538 | return 0; | |
539 | } | |
540 | ||
3a6b04ca JC |
541 | int xway_pinconf_group_set(struct pinctrl_dev *pctldev, |
542 | unsigned selector, | |
543 | unsigned long config) | |
544 | { | |
545 | struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); | |
546 | int i, ret = 0; | |
547 | ||
548 | for (i = 0; i < info->grps[selector].npins && !ret; i++) | |
549 | ret = xway_pinconf_set(pctldev, | |
550 | info->grps[selector].pins[i], config); | |
551 | ||
552 | return ret; | |
553 | } | |
554 | ||
6bb0700b | 555 | static struct pinconf_ops xway_pinconf_ops = { |
3f8c50c9 JC |
556 | .pin_config_get = xway_pinconf_get, |
557 | .pin_config_set = xway_pinconf_set, | |
3a6b04ca | 558 | .pin_config_group_set = xway_pinconf_group_set, |
3f8c50c9 JC |
559 | }; |
560 | ||
561 | static struct pinctrl_desc xway_pctrl_desc = { | |
562 | .owner = THIS_MODULE, | |
563 | .confops = &xway_pinconf_ops, | |
564 | }; | |
565 | ||
566 | static inline int xway_mux_apply(struct pinctrl_dev *pctrldev, | |
567 | int pin, int mux) | |
568 | { | |
569 | struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); | |
570 | int port = PORT(pin); | |
571 | u32 alt1_reg = GPIO_ALT1(pin); | |
572 | ||
573 | if (port == PORT3) | |
574 | alt1_reg = GPIO3_ALT1; | |
575 | ||
576 | if (mux & MUX_ALT0) | |
577 | gpio_setbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); | |
578 | else | |
579 | gpio_clearbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); | |
580 | ||
581 | if (mux & MUX_ALT1) | |
582 | gpio_setbit(info->membase[0], alt1_reg, PORT_PIN(pin)); | |
583 | else | |
584 | gpio_clearbit(info->membase[0], alt1_reg, PORT_PIN(pin)); | |
585 | ||
586 | return 0; | |
587 | } | |
588 | ||
589 | static const struct ltq_cfg_param xway_cfg_params[] = { | |
590 | {"lantiq,pull", LTQ_PINCONF_PARAM_PULL}, | |
591 | {"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN}, | |
6360350c | 592 | {"lantiq,output", LTQ_PINCONF_PARAM_OUTPUT}, |
3f8c50c9 JC |
593 | }; |
594 | ||
595 | static struct ltq_pinmux_info xway_info = { | |
596 | .desc = &xway_pctrl_desc, | |
597 | .apply_mux = xway_mux_apply, | |
598 | .params = xway_cfg_params, | |
599 | .num_params = ARRAY_SIZE(xway_cfg_params), | |
600 | }; | |
601 | ||
602 | /* --------- gpio_chip related code --------- */ | |
603 | static void xway_gpio_set(struct gpio_chip *chip, unsigned int pin, int val) | |
604 | { | |
605 | struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); | |
606 | ||
607 | if (val) | |
608 | gpio_setbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin)); | |
609 | else | |
610 | gpio_clearbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin)); | |
611 | } | |
612 | ||
613 | static int xway_gpio_get(struct gpio_chip *chip, unsigned int pin) | |
614 | { | |
615 | struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); | |
616 | ||
617 | return gpio_getbit(info->membase[0], GPIO_IN(pin), PORT_PIN(pin)); | |
618 | } | |
619 | ||
620 | static int xway_gpio_dir_in(struct gpio_chip *chip, unsigned int pin) | |
621 | { | |
622 | struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); | |
623 | ||
624 | gpio_clearbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); | |
625 | ||
626 | return 0; | |
627 | } | |
628 | ||
629 | static int xway_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, int val) | |
630 | { | |
631 | struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); | |
632 | ||
633 | gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); | |
634 | xway_gpio_set(chip, pin, val); | |
635 | ||
636 | return 0; | |
637 | } | |
638 | ||
639 | static int xway_gpio_req(struct gpio_chip *chip, unsigned offset) | |
640 | { | |
641 | int gpio = chip->base + offset; | |
642 | ||
643 | return pinctrl_request_gpio(gpio); | |
644 | } | |
645 | ||
646 | static void xway_gpio_free(struct gpio_chip *chip, unsigned offset) | |
647 | { | |
648 | int gpio = chip->base + offset; | |
649 | ||
650 | pinctrl_free_gpio(gpio); | |
651 | } | |
652 | ||
653 | static struct gpio_chip xway_chip = { | |
654 | .label = "gpio-xway", | |
655 | .direction_input = xway_gpio_dir_in, | |
656 | .direction_output = xway_gpio_dir_out, | |
657 | .get = xway_gpio_get, | |
658 | .set = xway_gpio_set, | |
659 | .request = xway_gpio_req, | |
660 | .free = xway_gpio_free, | |
661 | .base = -1, | |
662 | }; | |
663 | ||
664 | ||
665 | /* --------- register the pinctrl layer --------- */ | |
666 | static const unsigned xway_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO46, GPIO9}; | |
667 | static const unsigned ase_exin_pins_map[] = {GPIO6, GPIO29, GPIO0}; | |
668 | ||
669 | static struct pinctrl_xway_soc { | |
670 | int pin_count; | |
671 | const struct ltq_mfp_pin *mfp; | |
672 | const struct ltq_pin_group *grps; | |
673 | unsigned int num_grps; | |
674 | const struct ltq_pmx_func *funcs; | |
675 | unsigned int num_funcs; | |
676 | const unsigned *exin; | |
677 | unsigned int num_exin; | |
678 | } soc_cfg[] = { | |
679 | /* legacy xway */ | |
680 | {XWAY_MAX_PIN, xway_mfp, | |
681 | xway_grps, ARRAY_SIZE(xway_grps), | |
682 | danube_funcs, ARRAY_SIZE(danube_funcs), | |
683 | xway_exin_pin_map, 3}, | |
684 | /* xway xr9 series */ | |
685 | {XR9_MAX_PIN, xway_mfp, | |
686 | xway_grps, ARRAY_SIZE(xway_grps), | |
687 | xrx_funcs, ARRAY_SIZE(xrx_funcs), | |
688 | xway_exin_pin_map, 6}, | |
689 | /* xway ase series */ | |
690 | {XWAY_MAX_PIN, ase_mfp, | |
691 | ase_grps, ARRAY_SIZE(ase_grps), | |
692 | ase_funcs, ARRAY_SIZE(ase_funcs), | |
693 | ase_exin_pins_map, 3}, | |
694 | }; | |
695 | ||
696 | static struct pinctrl_gpio_range xway_gpio_range = { | |
697 | .name = "XWAY GPIO", | |
698 | .gc = &xway_chip, | |
699 | }; | |
700 | ||
701 | static const struct of_device_id xway_match[] = { | |
702 | { .compatible = "lantiq,pinctrl-xway", .data = &soc_cfg[0]}, | |
703 | { .compatible = "lantiq,pinctrl-xr9", .data = &soc_cfg[1]}, | |
704 | { .compatible = "lantiq,pinctrl-ase", .data = &soc_cfg[2]}, | |
705 | {}, | |
706 | }; | |
707 | MODULE_DEVICE_TABLE(of, xway_match); | |
708 | ||
150632b0 | 709 | static int pinmux_xway_probe(struct platform_device *pdev) |
3f8c50c9 JC |
710 | { |
711 | const struct of_device_id *match; | |
712 | const struct pinctrl_xway_soc *xway_soc; | |
713 | struct resource *res; | |
714 | int ret, i; | |
715 | ||
716 | /* get and remap our register range */ | |
717 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
718 | if (!res) { | |
719 | dev_err(&pdev->dev, "Failed to get resource\n"); | |
720 | return -ENOENT; | |
721 | } | |
722 | xway_info.membase[0] = devm_request_and_ioremap(&pdev->dev, res); | |
723 | if (!xway_info.membase[0]) { | |
724 | dev_err(&pdev->dev, "Failed to remap resource\n"); | |
725 | return -ENOMEM; | |
726 | } | |
727 | ||
728 | match = of_match_device(xway_match, &pdev->dev); | |
729 | if (match) | |
730 | xway_soc = (const struct pinctrl_xway_soc *) match->data; | |
731 | else | |
732 | xway_soc = &soc_cfg[0]; | |
733 | ||
734 | /* find out how many pads we have */ | |
735 | xway_chip.ngpio = xway_soc->pin_count; | |
736 | ||
737 | /* load our pad descriptors */ | |
738 | xway_info.pads = devm_kzalloc(&pdev->dev, | |
739 | sizeof(struct pinctrl_pin_desc) * xway_chip.ngpio, | |
740 | GFP_KERNEL); | |
741 | if (!xway_info.pads) { | |
742 | dev_err(&pdev->dev, "Failed to allocate pads\n"); | |
743 | return -ENOMEM; | |
744 | } | |
745 | for (i = 0; i < xway_chip.ngpio; i++) { | |
746 | /* strlen("ioXY") + 1 = 5 */ | |
747 | char *name = devm_kzalloc(&pdev->dev, 5, GFP_KERNEL); | |
748 | ||
749 | if (!name) { | |
750 | dev_err(&pdev->dev, "Failed to allocate pad name\n"); | |
751 | return -ENOMEM; | |
752 | } | |
753 | snprintf(name, 5, "io%d", i); | |
754 | xway_info.pads[i].number = GPIO0 + i; | |
755 | xway_info.pads[i].name = name; | |
756 | } | |
757 | xway_pctrl_desc.pins = xway_info.pads; | |
758 | ||
759 | /* load the gpio chip */ | |
760 | xway_chip.dev = &pdev->dev; | |
761 | of_gpiochip_add(&xway_chip); | |
762 | ret = gpiochip_add(&xway_chip); | |
763 | if (ret) { | |
764 | dev_err(&pdev->dev, "Failed to register gpio chip\n"); | |
765 | return ret; | |
766 | } | |
767 | ||
768 | /* setup the data needed by pinctrl */ | |
769 | xway_pctrl_desc.name = dev_name(&pdev->dev); | |
770 | xway_pctrl_desc.npins = xway_chip.ngpio; | |
771 | ||
772 | xway_info.num_pads = xway_chip.ngpio; | |
773 | xway_info.num_mfp = xway_chip.ngpio; | |
774 | xway_info.mfp = xway_soc->mfp; | |
775 | xway_info.grps = xway_soc->grps; | |
776 | xway_info.num_grps = xway_soc->num_grps; | |
777 | xway_info.funcs = xway_soc->funcs; | |
778 | xway_info.num_funcs = xway_soc->num_funcs; | |
779 | xway_info.exin = xway_soc->exin; | |
780 | xway_info.num_exin = xway_soc->num_exin; | |
781 | ||
782 | /* register with the generic lantiq layer */ | |
783 | ret = ltq_pinctrl_register(pdev, &xway_info); | |
784 | if (ret) { | |
785 | dev_err(&pdev->dev, "Failed to register pinctrl driver\n"); | |
786 | return ret; | |
787 | } | |
788 | ||
789 | /* finish with registering the gpio range in pinctrl */ | |
790 | xway_gpio_range.npins = xway_chip.ngpio; | |
791 | xway_gpio_range.base = xway_chip.base; | |
792 | pinctrl_add_gpio_range(xway_info.pctrl, &xway_gpio_range); | |
793 | dev_info(&pdev->dev, "Init done\n"); | |
794 | return 0; | |
795 | } | |
796 | ||
797 | static struct platform_driver pinmux_xway_driver = { | |
798 | .probe = pinmux_xway_probe, | |
799 | .driver = { | |
800 | .name = "pinctrl-xway", | |
801 | .owner = THIS_MODULE, | |
802 | .of_match_table = xway_match, | |
803 | }, | |
804 | }; | |
805 | ||
806 | static int __init pinmux_xway_init(void) | |
807 | { | |
808 | return platform_driver_register(&pinmux_xway_driver); | |
809 | } | |
810 | ||
811 | core_initcall_sync(pinmux_xway_init); |