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f365be09 BA |
1 | /* |
2 | * Copyright (c) 2013, Sony Mobile Communications AB. | |
3 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 and | |
7 | * only version 2 as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
32745581 | 15 | #include <linux/delay.h> |
f365be09 | 16 | #include <linux/err.h> |
f365be09 BA |
17 | #include <linux/io.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/pinctrl/machine.h> | |
22 | #include <linux/pinctrl/pinctrl.h> | |
23 | #include <linux/pinctrl/pinmux.h> | |
24 | #include <linux/pinctrl/pinconf.h> | |
25 | #include <linux/pinctrl/pinconf-generic.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/gpio.h> | |
28 | #include <linux/interrupt.h> | |
f365be09 | 29 | #include <linux/spinlock.h> |
cf1fc187 | 30 | #include <linux/reboot.h> |
ad644987 | 31 | #include <linux/pm.h> |
32745581 | 32 | |
69b78b8d LW |
33 | #include "../core.h" |
34 | #include "../pinconf.h" | |
f365be09 | 35 | #include "pinctrl-msm.h" |
69b78b8d | 36 | #include "../pinctrl-utils.h" |
f365be09 | 37 | |
408e3c66 | 38 | #define MAX_NR_GPIO 300 |
32745581 | 39 | #define PS_HOLD_OFFSET 0x820 |
408e3c66 | 40 | |
f365be09 BA |
41 | /** |
42 | * struct msm_pinctrl - state for a pinctrl-msm device | |
43 | * @dev: device handle. | |
44 | * @pctrl: pinctrl handle. | |
f365be09 | 45 | * @chip: gpiochip handle. |
cf1fc187 | 46 | * @restart_nb: restart notifier block. |
f365be09 BA |
47 | * @irq: parent irq for the TLMM irq_chip. |
48 | * @lock: Spinlock to protect register resources as well | |
49 | * as msm_pinctrl data structures. | |
50 | * @enabled_irqs: Bitmap of currently enabled irqs. | |
51 | * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge | |
52 | * detection. | |
f365be09 BA |
53 | * @soc; Reference to soc_data of platform specific data. |
54 | * @regs: Base address for the TLMM register map. | |
55 | */ | |
56 | struct msm_pinctrl { | |
57 | struct device *dev; | |
58 | struct pinctrl_dev *pctrl; | |
f365be09 | 59 | struct gpio_chip chip; |
cf1fc187 | 60 | struct notifier_block restart_nb; |
f393e489 | 61 | int irq; |
f365be09 BA |
62 | |
63 | spinlock_t lock; | |
64 | ||
408e3c66 BA |
65 | DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); |
66 | DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); | |
f365be09 BA |
67 | |
68 | const struct msm_pinctrl_soc_data *soc; | |
69 | void __iomem *regs; | |
70 | }; | |
71 | ||
72 | static int msm_get_groups_count(struct pinctrl_dev *pctldev) | |
73 | { | |
74 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
75 | ||
76 | return pctrl->soc->ngroups; | |
77 | } | |
78 | ||
79 | static const char *msm_get_group_name(struct pinctrl_dev *pctldev, | |
80 | unsigned group) | |
81 | { | |
82 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
83 | ||
84 | return pctrl->soc->groups[group].name; | |
85 | } | |
86 | ||
87 | static int msm_get_group_pins(struct pinctrl_dev *pctldev, | |
88 | unsigned group, | |
89 | const unsigned **pins, | |
90 | unsigned *num_pins) | |
91 | { | |
92 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
93 | ||
94 | *pins = pctrl->soc->groups[group].pins; | |
95 | *num_pins = pctrl->soc->groups[group].npins; | |
96 | return 0; | |
97 | } | |
98 | ||
1f2b2398 | 99 | static const struct pinctrl_ops msm_pinctrl_ops = { |
f365be09 BA |
100 | .get_groups_count = msm_get_groups_count, |
101 | .get_group_name = msm_get_group_name, | |
102 | .get_group_pins = msm_get_group_pins, | |
103 | .dt_node_to_map = pinconf_generic_dt_node_to_map_group, | |
104 | .dt_free_map = pinctrl_utils_dt_free_map, | |
105 | }; | |
106 | ||
107 | static int msm_get_functions_count(struct pinctrl_dev *pctldev) | |
108 | { | |
109 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
110 | ||
111 | return pctrl->soc->nfunctions; | |
112 | } | |
113 | ||
114 | static const char *msm_get_function_name(struct pinctrl_dev *pctldev, | |
115 | unsigned function) | |
116 | { | |
117 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
118 | ||
119 | return pctrl->soc->functions[function].name; | |
120 | } | |
121 | ||
122 | static int msm_get_function_groups(struct pinctrl_dev *pctldev, | |
123 | unsigned function, | |
124 | const char * const **groups, | |
125 | unsigned * const num_groups) | |
126 | { | |
127 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
128 | ||
129 | *groups = pctrl->soc->functions[function].groups; | |
130 | *num_groups = pctrl->soc->functions[function].ngroups; | |
131 | return 0; | |
132 | } | |
133 | ||
03e9f0ca LW |
134 | static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, |
135 | unsigned function, | |
136 | unsigned group) | |
f365be09 BA |
137 | { |
138 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
139 | const struct msm_pingroup *g; | |
140 | unsigned long flags; | |
141 | u32 val; | |
142 | int i; | |
143 | ||
144 | g = &pctrl->soc->groups[group]; | |
145 | ||
3c25381f | 146 | for (i = 0; i < g->nfuncs; i++) { |
f365be09 BA |
147 | if (g->funcs[i] == function) |
148 | break; | |
149 | } | |
150 | ||
3c25381f | 151 | if (WARN_ON(i == g->nfuncs)) |
f365be09 BA |
152 | return -EINVAL; |
153 | ||
154 | spin_lock_irqsave(&pctrl->lock, flags); | |
155 | ||
156 | val = readl(pctrl->regs + g->ctl_reg); | |
157 | val &= ~(0x7 << g->mux_bit); | |
158 | val |= i << g->mux_bit; | |
159 | writel(val, pctrl->regs + g->ctl_reg); | |
160 | ||
161 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
162 | ||
163 | return 0; | |
164 | } | |
165 | ||
1f2b2398 | 166 | static const struct pinmux_ops msm_pinmux_ops = { |
f365be09 BA |
167 | .get_functions_count = msm_get_functions_count, |
168 | .get_function_name = msm_get_function_name, | |
169 | .get_function_groups = msm_get_function_groups, | |
03e9f0ca | 170 | .set_mux = msm_pinmux_set_mux, |
f365be09 BA |
171 | }; |
172 | ||
173 | static int msm_config_reg(struct msm_pinctrl *pctrl, | |
174 | const struct msm_pingroup *g, | |
175 | unsigned param, | |
f365be09 BA |
176 | unsigned *mask, |
177 | unsigned *bit) | |
178 | { | |
179 | switch (param) { | |
180 | case PIN_CONFIG_BIAS_DISABLE: | |
f365be09 | 181 | case PIN_CONFIG_BIAS_PULL_DOWN: |
b831a15e | 182 | case PIN_CONFIG_BIAS_BUS_HOLD: |
f365be09 | 183 | case PIN_CONFIG_BIAS_PULL_UP: |
f365be09 BA |
184 | *bit = g->pull_bit; |
185 | *mask = 3; | |
186 | break; | |
187 | case PIN_CONFIG_DRIVE_STRENGTH: | |
f365be09 BA |
188 | *bit = g->drv_bit; |
189 | *mask = 7; | |
190 | break; | |
ed118a5f | 191 | case PIN_CONFIG_OUTPUT: |
407f5e39 | 192 | case PIN_CONFIG_INPUT_ENABLE: |
ed118a5f BA |
193 | *bit = g->oe_bit; |
194 | *mask = 1; | |
195 | break; | |
f365be09 | 196 | default: |
f365be09 BA |
197 | return -ENOTSUPP; |
198 | } | |
199 | ||
f365be09 BA |
200 | return 0; |
201 | } | |
202 | ||
f365be09 BA |
203 | #define MSM_NO_PULL 0 |
204 | #define MSM_PULL_DOWN 1 | |
b831a15e | 205 | #define MSM_KEEPER 2 |
f365be09 BA |
206 | #define MSM_PULL_UP 3 |
207 | ||
7cc34e2e SB |
208 | static unsigned msm_regval_to_drive(u32 val) |
209 | { | |
210 | return (val + 1) * 2; | |
211 | } | |
f365be09 BA |
212 | |
213 | static int msm_config_group_get(struct pinctrl_dev *pctldev, | |
214 | unsigned int group, | |
215 | unsigned long *config) | |
216 | { | |
217 | const struct msm_pingroup *g; | |
218 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
219 | unsigned param = pinconf_to_config_param(*config); | |
220 | unsigned mask; | |
221 | unsigned arg; | |
222 | unsigned bit; | |
f365be09 BA |
223 | int ret; |
224 | u32 val; | |
225 | ||
226 | g = &pctrl->soc->groups[group]; | |
227 | ||
051a58b4 | 228 | ret = msm_config_reg(pctrl, g, param, &mask, &bit); |
f365be09 BA |
229 | if (ret < 0) |
230 | return ret; | |
231 | ||
051a58b4 | 232 | val = readl(pctrl->regs + g->ctl_reg); |
f365be09 BA |
233 | arg = (val >> bit) & mask; |
234 | ||
235 | /* Convert register value to pinconf value */ | |
236 | switch (param) { | |
237 | case PIN_CONFIG_BIAS_DISABLE: | |
238 | arg = arg == MSM_NO_PULL; | |
239 | break; | |
240 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
241 | arg = arg == MSM_PULL_DOWN; | |
242 | break; | |
b831a15e AG |
243 | case PIN_CONFIG_BIAS_BUS_HOLD: |
244 | arg = arg == MSM_KEEPER; | |
245 | break; | |
f365be09 BA |
246 | case PIN_CONFIG_BIAS_PULL_UP: |
247 | arg = arg == MSM_PULL_UP; | |
248 | break; | |
249 | case PIN_CONFIG_DRIVE_STRENGTH: | |
7cc34e2e | 250 | arg = msm_regval_to_drive(arg); |
f365be09 | 251 | break; |
ed118a5f BA |
252 | case PIN_CONFIG_OUTPUT: |
253 | /* Pin is not output */ | |
254 | if (!arg) | |
255 | return -EINVAL; | |
256 | ||
257 | val = readl(pctrl->regs + g->io_reg); | |
258 | arg = !!(val & BIT(g->in_bit)); | |
259 | break; | |
407f5e39 SV |
260 | case PIN_CONFIG_INPUT_ENABLE: |
261 | /* Pin is output */ | |
262 | if (arg) | |
263 | return -EINVAL; | |
264 | arg = 1; | |
265 | break; | |
f365be09 | 266 | default: |
38d756af | 267 | return -ENOTSUPP; |
f365be09 BA |
268 | } |
269 | ||
270 | *config = pinconf_to_config_packed(param, arg); | |
271 | ||
272 | return 0; | |
273 | } | |
274 | ||
275 | static int msm_config_group_set(struct pinctrl_dev *pctldev, | |
276 | unsigned group, | |
277 | unsigned long *configs, | |
278 | unsigned num_configs) | |
279 | { | |
280 | const struct msm_pingroup *g; | |
281 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
282 | unsigned long flags; | |
283 | unsigned param; | |
284 | unsigned mask; | |
285 | unsigned arg; | |
286 | unsigned bit; | |
f365be09 BA |
287 | int ret; |
288 | u32 val; | |
289 | int i; | |
290 | ||
291 | g = &pctrl->soc->groups[group]; | |
292 | ||
293 | for (i = 0; i < num_configs; i++) { | |
294 | param = pinconf_to_config_param(configs[i]); | |
295 | arg = pinconf_to_config_argument(configs[i]); | |
296 | ||
051a58b4 | 297 | ret = msm_config_reg(pctrl, g, param, &mask, &bit); |
f365be09 BA |
298 | if (ret < 0) |
299 | return ret; | |
300 | ||
301 | /* Convert pinconf values to register values */ | |
302 | switch (param) { | |
303 | case PIN_CONFIG_BIAS_DISABLE: | |
304 | arg = MSM_NO_PULL; | |
305 | break; | |
306 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
307 | arg = MSM_PULL_DOWN; | |
308 | break; | |
b831a15e AG |
309 | case PIN_CONFIG_BIAS_BUS_HOLD: |
310 | arg = MSM_KEEPER; | |
311 | break; | |
f365be09 BA |
312 | case PIN_CONFIG_BIAS_PULL_UP: |
313 | arg = MSM_PULL_UP; | |
314 | break; | |
315 | case PIN_CONFIG_DRIVE_STRENGTH: | |
316 | /* Check for invalid values */ | |
7cc34e2e | 317 | if (arg > 16 || arg < 2 || (arg % 2) != 0) |
f365be09 BA |
318 | arg = -1; |
319 | else | |
7cc34e2e | 320 | arg = (arg / 2) - 1; |
f365be09 | 321 | break; |
ed118a5f BA |
322 | case PIN_CONFIG_OUTPUT: |
323 | /* set output value */ | |
324 | spin_lock_irqsave(&pctrl->lock, flags); | |
325 | val = readl(pctrl->regs + g->io_reg); | |
326 | if (arg) | |
327 | val |= BIT(g->out_bit); | |
328 | else | |
329 | val &= ~BIT(g->out_bit); | |
330 | writel(val, pctrl->regs + g->io_reg); | |
331 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
332 | ||
333 | /* enable output */ | |
334 | arg = 1; | |
335 | break; | |
407f5e39 SV |
336 | case PIN_CONFIG_INPUT_ENABLE: |
337 | /* disable output */ | |
338 | arg = 0; | |
339 | break; | |
f365be09 BA |
340 | default: |
341 | dev_err(pctrl->dev, "Unsupported config parameter: %x\n", | |
342 | param); | |
343 | return -EINVAL; | |
344 | } | |
345 | ||
346 | /* Range-check user-supplied value */ | |
347 | if (arg & ~mask) { | |
348 | dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); | |
349 | return -EINVAL; | |
350 | } | |
351 | ||
352 | spin_lock_irqsave(&pctrl->lock, flags); | |
051a58b4 | 353 | val = readl(pctrl->regs + g->ctl_reg); |
f365be09 BA |
354 | val &= ~(mask << bit); |
355 | val |= arg << bit; | |
051a58b4 | 356 | writel(val, pctrl->regs + g->ctl_reg); |
f365be09 BA |
357 | spin_unlock_irqrestore(&pctrl->lock, flags); |
358 | } | |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
1f2b2398 | 363 | static const struct pinconf_ops msm_pinconf_ops = { |
38d756af | 364 | .is_generic = true, |
f365be09 BA |
365 | .pin_config_group_get = msm_config_group_get, |
366 | .pin_config_group_set = msm_config_group_set, | |
367 | }; | |
368 | ||
369 | static struct pinctrl_desc msm_pinctrl_desc = { | |
370 | .pctlops = &msm_pinctrl_ops, | |
371 | .pmxops = &msm_pinmux_ops, | |
372 | .confops = &msm_pinconf_ops, | |
373 | .owner = THIS_MODULE, | |
374 | }; | |
375 | ||
376 | static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
377 | { | |
378 | const struct msm_pingroup *g; | |
fded3f40 | 379 | struct msm_pinctrl *pctrl = gpiochip_get_data(chip); |
f365be09 BA |
380 | unsigned long flags; |
381 | u32 val; | |
382 | ||
f365be09 | 383 | g = &pctrl->soc->groups[offset]; |
f365be09 BA |
384 | |
385 | spin_lock_irqsave(&pctrl->lock, flags); | |
386 | ||
387 | val = readl(pctrl->regs + g->ctl_reg); | |
388 | val &= ~BIT(g->oe_bit); | |
389 | writel(val, pctrl->regs + g->ctl_reg); | |
390 | ||
391 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
396 | static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) | |
397 | { | |
398 | const struct msm_pingroup *g; | |
fded3f40 | 399 | struct msm_pinctrl *pctrl = gpiochip_get_data(chip); |
f365be09 BA |
400 | unsigned long flags; |
401 | u32 val; | |
402 | ||
f365be09 | 403 | g = &pctrl->soc->groups[offset]; |
f365be09 BA |
404 | |
405 | spin_lock_irqsave(&pctrl->lock, flags); | |
406 | ||
e476e77f AL |
407 | val = readl(pctrl->regs + g->io_reg); |
408 | if (value) | |
409 | val |= BIT(g->out_bit); | |
410 | else | |
411 | val &= ~BIT(g->out_bit); | |
412 | writel(val, pctrl->regs + g->io_reg); | |
f365be09 BA |
413 | |
414 | val = readl(pctrl->regs + g->ctl_reg); | |
415 | val |= BIT(g->oe_bit); | |
416 | writel(val, pctrl->regs + g->ctl_reg); | |
417 | ||
418 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
419 | ||
420 | return 0; | |
421 | } | |
422 | ||
423 | static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) | |
424 | { | |
425 | const struct msm_pingroup *g; | |
fded3f40 | 426 | struct msm_pinctrl *pctrl = gpiochip_get_data(chip); |
f365be09 BA |
427 | u32 val; |
428 | ||
f365be09 BA |
429 | g = &pctrl->soc->groups[offset]; |
430 | ||
431 | val = readl(pctrl->regs + g->io_reg); | |
432 | return !!(val & BIT(g->in_bit)); | |
433 | } | |
434 | ||
435 | static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
436 | { | |
437 | const struct msm_pingroup *g; | |
fded3f40 | 438 | struct msm_pinctrl *pctrl = gpiochip_get_data(chip); |
f365be09 BA |
439 | unsigned long flags; |
440 | u32 val; | |
441 | ||
f365be09 BA |
442 | g = &pctrl->soc->groups[offset]; |
443 | ||
444 | spin_lock_irqsave(&pctrl->lock, flags); | |
445 | ||
446 | val = readl(pctrl->regs + g->io_reg); | |
e476e77f AL |
447 | if (value) |
448 | val |= BIT(g->out_bit); | |
449 | else | |
450 | val &= ~BIT(g->out_bit); | |
f365be09 BA |
451 | writel(val, pctrl->regs + g->io_reg); |
452 | ||
453 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
454 | } | |
455 | ||
f365be09 BA |
456 | #ifdef CONFIG_DEBUG_FS |
457 | #include <linux/seq_file.h> | |
458 | ||
459 | static void msm_gpio_dbg_show_one(struct seq_file *s, | |
460 | struct pinctrl_dev *pctldev, | |
461 | struct gpio_chip *chip, | |
462 | unsigned offset, | |
463 | unsigned gpio) | |
464 | { | |
465 | const struct msm_pingroup *g; | |
fded3f40 | 466 | struct msm_pinctrl *pctrl = gpiochip_get_data(chip); |
f365be09 BA |
467 | unsigned func; |
468 | int is_out; | |
469 | int drive; | |
470 | int pull; | |
471 | u32 ctl_reg; | |
472 | ||
1f2b2398 | 473 | static const char * const pulls[] = { |
f365be09 BA |
474 | "no pull", |
475 | "pull down", | |
476 | "keeper", | |
477 | "pull up" | |
478 | }; | |
479 | ||
480 | g = &pctrl->soc->groups[offset]; | |
481 | ctl_reg = readl(pctrl->regs + g->ctl_reg); | |
482 | ||
483 | is_out = !!(ctl_reg & BIT(g->oe_bit)); | |
484 | func = (ctl_reg >> g->mux_bit) & 7; | |
485 | drive = (ctl_reg >> g->drv_bit) & 7; | |
486 | pull = (ctl_reg >> g->pull_bit) & 3; | |
487 | ||
488 | seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); | |
7cc34e2e | 489 | seq_printf(s, " %dmA", msm_regval_to_drive(drive)); |
f365be09 BA |
490 | seq_printf(s, " %s", pulls[pull]); |
491 | } | |
492 | ||
493 | static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
494 | { | |
495 | unsigned gpio = chip->base; | |
496 | unsigned i; | |
497 | ||
498 | for (i = 0; i < chip->ngpio; i++, gpio++) { | |
499 | msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); | |
1f2b2398 | 500 | seq_puts(s, "\n"); |
f365be09 BA |
501 | } |
502 | } | |
503 | ||
504 | #else | |
505 | #define msm_gpio_dbg_show NULL | |
506 | #endif | |
507 | ||
508 | static struct gpio_chip msm_gpio_template = { | |
509 | .direction_input = msm_gpio_direction_input, | |
510 | .direction_output = msm_gpio_direction_output, | |
511 | .get = msm_gpio_get, | |
512 | .set = msm_gpio_set, | |
98c85d58 JG |
513 | .request = gpiochip_generic_request, |
514 | .free = gpiochip_generic_free, | |
f365be09 BA |
515 | .dbg_show = msm_gpio_dbg_show, |
516 | }; | |
517 | ||
518 | /* For dual-edge interrupts in software, since some hardware has no | |
519 | * such support: | |
520 | * | |
521 | * At appropriate moments, this function may be called to flip the polarity | |
522 | * settings of both-edge irq lines to try and catch the next edge. | |
523 | * | |
524 | * The attempt is considered successful if: | |
525 | * - the status bit goes high, indicating that an edge was caught, or | |
526 | * - the input value of the gpio doesn't change during the attempt. | |
527 | * If the value changes twice during the process, that would cause the first | |
528 | * test to fail but would force the second, as two opposite | |
529 | * transitions would cause a detection no matter the polarity setting. | |
530 | * | |
531 | * The do-loop tries to sledge-hammer closed the timing hole between | |
532 | * the initial value-read and the polarity-write - if the line value changes | |
533 | * during that window, an interrupt is lost, the new polarity setting is | |
534 | * incorrect, and the first success test will fail, causing a retry. | |
535 | * | |
536 | * Algorithm comes from Google's msmgpio driver. | |
537 | */ | |
538 | static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, | |
539 | const struct msm_pingroup *g, | |
540 | struct irq_data *d) | |
541 | { | |
542 | int loop_limit = 100; | |
543 | unsigned val, val2, intstat; | |
544 | unsigned pol; | |
545 | ||
546 | do { | |
547 | val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); | |
548 | ||
549 | pol = readl(pctrl->regs + g->intr_cfg_reg); | |
550 | pol ^= BIT(g->intr_polarity_bit); | |
551 | writel(pol, pctrl->regs + g->intr_cfg_reg); | |
552 | ||
553 | val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); | |
554 | intstat = readl(pctrl->regs + g->intr_status_reg); | |
555 | if (intstat || (val == val2)) | |
556 | return; | |
557 | } while (loop_limit-- > 0); | |
558 | dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", | |
559 | val, val2); | |
560 | } | |
561 | ||
562 | static void msm_gpio_irq_mask(struct irq_data *d) | |
563 | { | |
cdcb0ab6 | 564 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
fded3f40 | 565 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
f365be09 | 566 | const struct msm_pingroup *g; |
f365be09 BA |
567 | unsigned long flags; |
568 | u32 val; | |
569 | ||
f365be09 BA |
570 | g = &pctrl->soc->groups[d->hwirq]; |
571 | ||
572 | spin_lock_irqsave(&pctrl->lock, flags); | |
573 | ||
574 | val = readl(pctrl->regs + g->intr_cfg_reg); | |
575 | val &= ~BIT(g->intr_enable_bit); | |
576 | writel(val, pctrl->regs + g->intr_cfg_reg); | |
577 | ||
578 | clear_bit(d->hwirq, pctrl->enabled_irqs); | |
579 | ||
580 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
581 | } | |
582 | ||
583 | static void msm_gpio_irq_unmask(struct irq_data *d) | |
584 | { | |
cdcb0ab6 | 585 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
fded3f40 | 586 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
f365be09 | 587 | const struct msm_pingroup *g; |
f365be09 BA |
588 | unsigned long flags; |
589 | u32 val; | |
590 | ||
f365be09 BA |
591 | g = &pctrl->soc->groups[d->hwirq]; |
592 | ||
593 | spin_lock_irqsave(&pctrl->lock, flags); | |
594 | ||
595 | val = readl(pctrl->regs + g->intr_status_reg); | |
596 | val &= ~BIT(g->intr_status_bit); | |
597 | writel(val, pctrl->regs + g->intr_status_reg); | |
598 | ||
599 | val = readl(pctrl->regs + g->intr_cfg_reg); | |
600 | val |= BIT(g->intr_enable_bit); | |
601 | writel(val, pctrl->regs + g->intr_cfg_reg); | |
602 | ||
603 | set_bit(d->hwirq, pctrl->enabled_irqs); | |
604 | ||
605 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
606 | } | |
607 | ||
608 | static void msm_gpio_irq_ack(struct irq_data *d) | |
609 | { | |
cdcb0ab6 | 610 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
fded3f40 | 611 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
f365be09 | 612 | const struct msm_pingroup *g; |
f365be09 BA |
613 | unsigned long flags; |
614 | u32 val; | |
615 | ||
f365be09 BA |
616 | g = &pctrl->soc->groups[d->hwirq]; |
617 | ||
618 | spin_lock_irqsave(&pctrl->lock, flags); | |
619 | ||
620 | val = readl(pctrl->regs + g->intr_status_reg); | |
48f15e94 BA |
621 | if (g->intr_ack_high) |
622 | val |= BIT(g->intr_status_bit); | |
623 | else | |
624 | val &= ~BIT(g->intr_status_bit); | |
f365be09 BA |
625 | writel(val, pctrl->regs + g->intr_status_reg); |
626 | ||
627 | if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) | |
628 | msm_gpio_update_dual_edge_pos(pctrl, g, d); | |
629 | ||
630 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
631 | } | |
632 | ||
f365be09 BA |
633 | static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
634 | { | |
cdcb0ab6 | 635 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
fded3f40 | 636 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
f365be09 | 637 | const struct msm_pingroup *g; |
f365be09 BA |
638 | unsigned long flags; |
639 | u32 val; | |
640 | ||
f365be09 BA |
641 | g = &pctrl->soc->groups[d->hwirq]; |
642 | ||
643 | spin_lock_irqsave(&pctrl->lock, flags); | |
644 | ||
645 | /* | |
646 | * For hw without possibility of detecting both edges | |
647 | */ | |
648 | if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) | |
649 | set_bit(d->hwirq, pctrl->dual_edge_irqs); | |
650 | else | |
651 | clear_bit(d->hwirq, pctrl->dual_edge_irqs); | |
652 | ||
653 | /* Route interrupts to application cpu */ | |
654 | val = readl(pctrl->regs + g->intr_target_reg); | |
655 | val &= ~(7 << g->intr_target_bit); | |
f712c554 | 656 | val |= g->intr_target_kpss_val << g->intr_target_bit; |
f365be09 BA |
657 | writel(val, pctrl->regs + g->intr_target_reg); |
658 | ||
659 | /* Update configuration for gpio. | |
660 | * RAW_STATUS_EN is left on for all gpio irqs. Due to the | |
661 | * internal circuitry of TLMM, toggling the RAW_STATUS | |
662 | * could cause the INTR_STATUS to be set for EDGE interrupts. | |
663 | */ | |
664 | val = readl(pctrl->regs + g->intr_cfg_reg); | |
665 | val |= BIT(g->intr_raw_status_bit); | |
666 | if (g->intr_detection_width == 2) { | |
667 | val &= ~(3 << g->intr_detection_bit); | |
668 | val &= ~(1 << g->intr_polarity_bit); | |
669 | switch (type) { | |
670 | case IRQ_TYPE_EDGE_RISING: | |
671 | val |= 1 << g->intr_detection_bit; | |
672 | val |= BIT(g->intr_polarity_bit); | |
673 | break; | |
674 | case IRQ_TYPE_EDGE_FALLING: | |
675 | val |= 2 << g->intr_detection_bit; | |
676 | val |= BIT(g->intr_polarity_bit); | |
677 | break; | |
678 | case IRQ_TYPE_EDGE_BOTH: | |
679 | val |= 3 << g->intr_detection_bit; | |
680 | val |= BIT(g->intr_polarity_bit); | |
681 | break; | |
682 | case IRQ_TYPE_LEVEL_LOW: | |
683 | break; | |
684 | case IRQ_TYPE_LEVEL_HIGH: | |
685 | val |= BIT(g->intr_polarity_bit); | |
686 | break; | |
687 | } | |
688 | } else if (g->intr_detection_width == 1) { | |
689 | val &= ~(1 << g->intr_detection_bit); | |
690 | val &= ~(1 << g->intr_polarity_bit); | |
691 | switch (type) { | |
692 | case IRQ_TYPE_EDGE_RISING: | |
693 | val |= BIT(g->intr_detection_bit); | |
694 | val |= BIT(g->intr_polarity_bit); | |
695 | break; | |
696 | case IRQ_TYPE_EDGE_FALLING: | |
697 | val |= BIT(g->intr_detection_bit); | |
698 | break; | |
699 | case IRQ_TYPE_EDGE_BOTH: | |
700 | val |= BIT(g->intr_detection_bit); | |
48f15e94 | 701 | val |= BIT(g->intr_polarity_bit); |
f365be09 BA |
702 | break; |
703 | case IRQ_TYPE_LEVEL_LOW: | |
704 | break; | |
705 | case IRQ_TYPE_LEVEL_HIGH: | |
706 | val |= BIT(g->intr_polarity_bit); | |
707 | break; | |
708 | } | |
709 | } else { | |
710 | BUG(); | |
711 | } | |
712 | writel(val, pctrl->regs + g->intr_cfg_reg); | |
713 | ||
714 | if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) | |
715 | msm_gpio_update_dual_edge_pos(pctrl, g, d); | |
716 | ||
717 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
718 | ||
719 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
34c0ad84 | 720 | irq_set_handler_locked(d, handle_level_irq); |
f365be09 | 721 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
34c0ad84 | 722 | irq_set_handler_locked(d, handle_edge_irq); |
f365be09 BA |
723 | |
724 | return 0; | |
725 | } | |
726 | ||
727 | static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) | |
728 | { | |
cdcb0ab6 | 729 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
fded3f40 | 730 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
f365be09 | 731 | unsigned long flags; |
f365be09 | 732 | |
f365be09 BA |
733 | spin_lock_irqsave(&pctrl->lock, flags); |
734 | ||
6aced33f | 735 | irq_set_irq_wake(pctrl->irq, on); |
f365be09 BA |
736 | |
737 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
738 | ||
739 | return 0; | |
740 | } | |
741 | ||
f365be09 BA |
742 | static struct irq_chip msm_gpio_irq_chip = { |
743 | .name = "msmgpio", | |
744 | .irq_mask = msm_gpio_irq_mask, | |
745 | .irq_unmask = msm_gpio_irq_unmask, | |
746 | .irq_ack = msm_gpio_irq_ack, | |
747 | .irq_set_type = msm_gpio_irq_set_type, | |
748 | .irq_set_wake = msm_gpio_irq_set_wake, | |
f365be09 BA |
749 | }; |
750 | ||
bd0b9ac4 | 751 | static void msm_gpio_irq_handler(struct irq_desc *desc) |
f365be09 | 752 | { |
cdcb0ab6 | 753 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
f365be09 | 754 | const struct msm_pingroup *g; |
fded3f40 | 755 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
5663bb27 | 756 | struct irq_chip *chip = irq_desc_get_chip(desc); |
f365be09 BA |
757 | int irq_pin; |
758 | int handled = 0; | |
759 | u32 val; | |
760 | int i; | |
761 | ||
762 | chained_irq_enter(chip, desc); | |
763 | ||
764 | /* | |
1f2b2398 | 765 | * Each pin has it's own IRQ status register, so use |
f365be09 BA |
766 | * enabled_irq bitmap to limit the number of reads. |
767 | */ | |
768 | for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { | |
769 | g = &pctrl->soc->groups[i]; | |
770 | val = readl(pctrl->regs + g->intr_status_reg); | |
771 | if (val & BIT(g->intr_status_bit)) { | |
cdcb0ab6 | 772 | irq_pin = irq_find_mapping(gc->irqdomain, i); |
f365be09 BA |
773 | generic_handle_irq(irq_pin); |
774 | handled++; | |
775 | } | |
776 | } | |
777 | ||
1f2b2398 | 778 | /* No interrupts were flagged */ |
f365be09 | 779 | if (handled == 0) |
bd0b9ac4 | 780 | handle_bad_irq(desc); |
f365be09 BA |
781 | |
782 | chained_irq_exit(chip, desc); | |
783 | } | |
784 | ||
785 | static int msm_gpio_init(struct msm_pinctrl *pctrl) | |
786 | { | |
787 | struct gpio_chip *chip; | |
f365be09 | 788 | int ret; |
dcd278b8 SB |
789 | unsigned ngpio = pctrl->soc->ngpios; |
790 | ||
791 | if (WARN_ON(ngpio > MAX_NR_GPIO)) | |
792 | return -EINVAL; | |
f365be09 BA |
793 | |
794 | chip = &pctrl->chip; | |
795 | chip->base = 0; | |
dcd278b8 | 796 | chip->ngpio = ngpio; |
f365be09 | 797 | chip->label = dev_name(pctrl->dev); |
58383c78 | 798 | chip->parent = pctrl->dev; |
f365be09 BA |
799 | chip->owner = THIS_MODULE; |
800 | chip->of_node = pctrl->dev->of_node; | |
801 | ||
fded3f40 | 802 | ret = gpiochip_add_data(&pctrl->chip, pctrl); |
f365be09 BA |
803 | if (ret) { |
804 | dev_err(pctrl->dev, "Failed register gpiochip\n"); | |
805 | return ret; | |
806 | } | |
807 | ||
808 | ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); | |
809 | if (ret) { | |
810 | dev_err(pctrl->dev, "Failed to add pin range\n"); | |
c6e927a2 | 811 | gpiochip_remove(&pctrl->chip); |
f365be09 BA |
812 | return ret; |
813 | } | |
814 | ||
cdcb0ab6 LW |
815 | ret = gpiochip_irqchip_add(chip, |
816 | &msm_gpio_irq_chip, | |
817 | 0, | |
818 | handle_edge_irq, | |
819 | IRQ_TYPE_NONE); | |
820 | if (ret) { | |
821 | dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); | |
c6e927a2 | 822 | gpiochip_remove(&pctrl->chip); |
f365be09 BA |
823 | return -ENOSYS; |
824 | } | |
825 | ||
cdcb0ab6 LW |
826 | gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq, |
827 | msm_gpio_irq_handler); | |
f365be09 BA |
828 | |
829 | return 0; | |
830 | } | |
831 | ||
cf1fc187 JC |
832 | static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action, |
833 | void *data) | |
32745581 | 834 | { |
cf1fc187 JC |
835 | struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); |
836 | ||
837 | writel(0, pctrl->regs + PS_HOLD_OFFSET); | |
838 | mdelay(1000); | |
839 | return NOTIFY_DONE; | |
32745581 PG |
840 | } |
841 | ||
ad644987 SB |
842 | static struct msm_pinctrl *poweroff_pctrl; |
843 | ||
844 | static void msm_ps_hold_poweroff(void) | |
845 | { | |
846 | msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL); | |
847 | } | |
848 | ||
32745581 PG |
849 | static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) |
850 | { | |
bcd53f85 | 851 | int i; |
32745581 PG |
852 | const struct msm_function *func = pctrl->soc->functions; |
853 | ||
bcd53f85 | 854 | for (i = 0; i < pctrl->soc->nfunctions; i++) |
32745581 | 855 | if (!strcmp(func[i].name, "ps_hold")) { |
cf1fc187 JC |
856 | pctrl->restart_nb.notifier_call = msm_ps_hold_restart; |
857 | pctrl->restart_nb.priority = 128; | |
858 | if (register_restart_handler(&pctrl->restart_nb)) | |
859 | dev_err(pctrl->dev, | |
860 | "failed to setup restart handler.\n"); | |
ad644987 SB |
861 | poweroff_pctrl = pctrl; |
862 | pm_power_off = msm_ps_hold_poweroff; | |
cf1fc187 | 863 | break; |
32745581 PG |
864 | } |
865 | } | |
32745581 | 866 | |
f365be09 BA |
867 | int msm_pinctrl_probe(struct platform_device *pdev, |
868 | const struct msm_pinctrl_soc_data *soc_data) | |
869 | { | |
870 | struct msm_pinctrl *pctrl; | |
871 | struct resource *res; | |
872 | int ret; | |
873 | ||
874 | pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); | |
875 | if (!pctrl) { | |
876 | dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n"); | |
877 | return -ENOMEM; | |
878 | } | |
879 | pctrl->dev = &pdev->dev; | |
880 | pctrl->soc = soc_data; | |
881 | pctrl->chip = msm_gpio_template; | |
882 | ||
883 | spin_lock_init(&pctrl->lock); | |
884 | ||
885 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
886 | pctrl->regs = devm_ioremap_resource(&pdev->dev, res); | |
887 | if (IS_ERR(pctrl->regs)) | |
888 | return PTR_ERR(pctrl->regs); | |
889 | ||
32745581 PG |
890 | msm_pinctrl_setup_pm_reset(pctrl); |
891 | ||
f393e489 | 892 | pctrl->irq = platform_get_irq(pdev, 0); |
f365be09 BA |
893 | if (pctrl->irq < 0) { |
894 | dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); | |
895 | return pctrl->irq; | |
896 | } | |
897 | ||
898 | msm_pinctrl_desc.name = dev_name(&pdev->dev); | |
899 | msm_pinctrl_desc.pins = pctrl->soc->pins; | |
900 | msm_pinctrl_desc.npins = pctrl->soc->npins; | |
901 | pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl); | |
323de9ef | 902 | if (IS_ERR(pctrl->pctrl)) { |
f365be09 | 903 | dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); |
323de9ef | 904 | return PTR_ERR(pctrl->pctrl); |
f365be09 BA |
905 | } |
906 | ||
907 | ret = msm_gpio_init(pctrl); | |
908 | if (ret) { | |
909 | pinctrl_unregister(pctrl->pctrl); | |
910 | return ret; | |
911 | } | |
912 | ||
913 | platform_set_drvdata(pdev, pctrl); | |
914 | ||
915 | dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); | |
916 | ||
917 | return 0; | |
918 | } | |
919 | EXPORT_SYMBOL(msm_pinctrl_probe); | |
920 | ||
921 | int msm_pinctrl_remove(struct platform_device *pdev) | |
922 | { | |
923 | struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); | |
f393e489 | 924 | |
2fcea6ce | 925 | gpiochip_remove(&pctrl->chip); |
f365be09 BA |
926 | pinctrl_unregister(pctrl->pctrl); |
927 | ||
cf1fc187 JC |
928 | unregister_restart_handler(&pctrl->restart_nb); |
929 | ||
f365be09 BA |
930 | return 0; |
931 | } | |
932 | EXPORT_SYMBOL(msm_pinctrl_remove); | |
933 |