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pinctrl: samsung: Constify samsung_pin_ctrl struct
[deliverable/linux.git] / drivers / pinctrl / samsung / pinctrl-exynos.c
CommitLineData
43b169db
TA		 1/*
2 * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2012 Linaro Ltd
7 * http://www.linaro.org
8 *
9 * Author: Thomas Abraham <thomas.ab@samsung.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This file contains the Samsung Exynos specific information required by the
17 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
18 * external gpio and wakeup interrupt support.
19 */
20
21#include <linux/module.h>
22#include <linux/device.h>
23#include <linux/interrupt.h>
24#include <linux/irqdomain.h>
25#include <linux/irq.h>
de88cbb7 26#include <linux/irqchip/chained_irq.h>
43b169db
TA		 27#include <linux/of_irq.h>
28#include <linux/io.h>
29#include <linux/slab.h>
19846950 30#include <linux/spinlock.h>
43b169db
TA		 31#include <linux/err.h>
32
43b169db
TA		 33#include "pinctrl-samsung.h"
34#include "pinctrl-exynos.h"
35
2e4a4fda
TF		 36struct exynos_irq_chip {
37 struct irq_chip chip;
38
39 u32 eint_con;
40 u32 eint_mask;
41 u32 eint_pend;
42};
43
44static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip)
45{
46 return container_of(chip, struct exynos_irq_chip, chip);
47}
499147c9 48
94ce944b 49static const struct samsung_pin_bank_type bank_type_off = {
499147c9 50 .fld_width = { 4, 1, 2, 2, 2, 2, },
43fc9e7f 51 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
499147c9
TF		 52};
53
94ce944b 54static const struct samsung_pin_bank_type bank_type_alive = {
499147c9 55 .fld_width = { 4, 1, 2, 2, },
43fc9e7f 56 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
499147c9
TF		 57};
58
43b169db
TA		 59/* list of external wakeup controllers supported */
60static const struct of_device_id exynos_wkup_irq_ids[] = {
61 { .compatible = "samsung,exynos4210-wakeup-eint", },
afa538c2 62 { }
43b169db
TA		 63};
64
2e4a4fda 65static void exynos_irq_mask(struct irq_data *irqd)
43b169db 66{
2e4a4fda
TF		 67 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
68 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
595be726
TF		 69 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
70 struct samsung_pinctrl_drv_data *d = bank->drvdata;
2e4a4fda 71 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
43b169db 72 unsigned long mask;
5ae8cf79
DA		 73 unsigned long flags;
74
75 spin_lock_irqsave(&bank->slock, flags);
43b169db
TA		 76
77 mask = readl(d->virt_base + reg_mask);
5ace03fb 78 mask |= 1 << irqd->hwirq;
43b169db 79 writel(mask, d->virt_base + reg_mask);
5ae8cf79
DA		 80
81 spin_unlock_irqrestore(&bank->slock, flags);
43b169db
TA		 82}
83
2e4a4fda 84static void exynos_irq_ack(struct irq_data *irqd)
43b169db 85{
2e4a4fda
TF		 86 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
87 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
595be726
TF		 88 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
89 struct samsung_pinctrl_drv_data *d = bank->drvdata;
2e4a4fda 90 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset;
43b169db 91
5ace03fb 92 writel(1 << irqd->hwirq, d->virt_base + reg_pend);
43b169db
TA		 93}
94
2e4a4fda 95static void exynos_irq_unmask(struct irq_data *irqd)
43b169db 96{
2e4a4fda
TF		 97 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
98 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
595be726
TF		 99 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
100 struct samsung_pinctrl_drv_data *d = bank->drvdata;
2e4a4fda 101 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
43b169db 102 unsigned long mask;
5ae8cf79 103 unsigned long flags;
43b169db 104
5a68e7a7
DA		 105 /*
106 * Ack level interrupts right before unmask
107 *
108 * If we don't do this we'll get a double-interrupt. Level triggered
109 * interrupts must not fire an interrupt if the level is not
110 * _currently_ active, even if it was active while the interrupt was
111 * masked.
112 */
113 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
2e4a4fda 114 exynos_irq_ack(irqd);
5a68e7a7 115
5ae8cf79 116 spin_lock_irqsave(&bank->slock, flags);
43b169db
TA		 117
118 mask = readl(d->virt_base + reg_mask);
5ace03fb 119 mask &= ~(1 << irqd->hwirq);
43b169db 120 writel(mask, d->virt_base + reg_mask);
5ae8cf79
DA		 121
122 spin_unlock_irqrestore(&bank->slock, flags);
43b169db
TA		 123}
124
2e4a4fda 125static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
43b169db 126{
2e4a4fda
TF		 127 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
128 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
595be726
TF		 129 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
130 struct samsung_pinctrl_drv_data *d = bank->drvdata;
f6a8249f 131 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
43b169db 132 unsigned int con, trig_type;
2e4a4fda 133 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
43b169db
TA		 134
135 switch (type) {
136 case IRQ_TYPE_EDGE_RISING:
137 trig_type = EXYNOS_EINT_EDGE_RISING;
138 break;
139 case IRQ_TYPE_EDGE_FALLING:
140 trig_type = EXYNOS_EINT_EDGE_FALLING;
141 break;
142 case IRQ_TYPE_EDGE_BOTH:
143 trig_type = EXYNOS_EINT_EDGE_BOTH;
144 break;
145 case IRQ_TYPE_LEVEL_HIGH:
146 trig_type = EXYNOS_EINT_LEVEL_HIGH;
147 break;
148 case IRQ_TYPE_LEVEL_LOW:
149 trig_type = EXYNOS_EINT_LEVEL_LOW;
150 break;
151 default:
152 pr_err("unsupported external interrupt type\n");
153 return -EINVAL;
154 }
155
156 if (type & IRQ_TYPE_EDGE_BOTH)
157 __irq_set_handler_locked(irqd->irq, handle_edge_irq);
158 else
159 __irq_set_handler_locked(irqd->irq, handle_level_irq);
160
161 con = readl(d->virt_base + reg_con);
162 con &= ~(EXYNOS_EINT_CON_MASK << shift);
163 con |= trig_type << shift;
164 writel(con, d->virt_base + reg_con);
ee2f573c 165
f6a8249f
TF		 166 return 0;
167}
168
169static int exynos_irq_request_resources(struct irq_data *irqd)
170{
171 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
172 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
173 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
94ce944b 174 const struct samsung_pin_bank_type *bank_type = bank->type;
f6a8249f
TF		 175 struct samsung_pinctrl_drv_data *d = bank->drvdata;
176 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
177 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
178 unsigned long flags;
179 unsigned int mask;
180 unsigned int con;
181 int ret;
182
183 ret = gpio_lock_as_irq(&bank->gpio_chip, irqd->hwirq);
184 if (ret) {
185 dev_err(bank->gpio_chip.dev, "unable to lock pin %s-%lu IRQ\n",
186 bank->name, irqd->hwirq);
187 return ret;
188 }
189
43fc9e7f 190 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
f6a8249f 191 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
499147c9 192 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
ee2f573c 193
19846950
TF		 194 spin_lock_irqsave(&bank->slock, flags);
195
ee2f573c
TF		 196 con = readl(d->virt_base + reg_con);
197 con &= ~(mask << shift);
198 con |= EXYNOS_EINT_FUNC << shift;
199 writel(con, d->virt_base + reg_con);
200
19846950
TF		 201 spin_unlock_irqrestore(&bank->slock, flags);
202
f6a8249f
TF		 203 exynos_irq_unmask(irqd);
204
43b169db
TA		 205 return 0;
206}
207
f6a8249f
TF		 208static void exynos_irq_release_resources(struct irq_data *irqd)
209{
210 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
211 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
212 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
94ce944b 213 const struct samsung_pin_bank_type *bank_type = bank->type;
f6a8249f
TF		 214 struct samsung_pinctrl_drv_data *d = bank->drvdata;
215 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
216 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
217 unsigned long flags;
218 unsigned int mask;
219 unsigned int con;
220
221 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
222 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
223 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
224
225 exynos_irq_mask(irqd);
226
227 spin_lock_irqsave(&bank->slock, flags);
228
229 con = readl(d->virt_base + reg_con);
230 con &= ~(mask << shift);
231 con |= FUNC_INPUT << shift;
232 writel(con, d->virt_base + reg_con);
233
234 spin_unlock_irqrestore(&bank->slock, flags);
235
236 gpio_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
237}
238
43b169db
TA		 239/*
240 * irq_chip for gpio interrupts.
241 */
2e4a4fda
TF		 242static struct exynos_irq_chip exynos_gpio_irq_chip = {
243 .chip = {
244 .name = "exynos_gpio_irq_chip",
245 .irq_unmask = exynos_irq_unmask,
246 .irq_mask = exynos_irq_mask,
247 .irq_ack = exynos_irq_ack,
248 .irq_set_type = exynos_irq_set_type,
f6a8249f
TF		 249 .irq_request_resources = exynos_irq_request_resources,
250 .irq_release_resources = exynos_irq_release_resources,
2e4a4fda
TF		 251 },
252 .eint_con = EXYNOS_GPIO_ECON_OFFSET,
253 .eint_mask = EXYNOS_GPIO_EMASK_OFFSET,
254 .eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
43b169db
TA		 255};
256
43b169db
TA		 257static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
258 irq_hw_number_t hw)
259{
595be726 260 struct samsung_pin_bank *b = h->host_data;
43b169db 261
595be726 262 irq_set_chip_data(virq, b);
2e4a4fda 263 irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip.chip,
43b169db
TA		 264 handle_level_irq);
265 set_irq_flags(virq, IRQF_VALID);
266 return 0;
267}
268
43b169db
TA		 269/*
270 * irq domain callbacks for external gpio interrupt controller.
271 */
272static const struct irq_domain_ops exynos_gpio_irqd_ops = {
273 .map = exynos_gpio_irq_map,
43b169db
TA		 274 .xlate = irq_domain_xlate_twocell,
275};
276
277static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
278{
279 struct samsung_pinctrl_drv_data *d = data;
1bf00d7a 280 struct samsung_pin_bank *bank = d->pin_banks;
43b169db
TA		 281 unsigned int svc, group, pin, virq;
282
2e4a4fda 283 svc = readl(d->virt_base + EXYNOS_SVC_OFFSET);
43b169db
TA		 284 group = EXYNOS_SVC_GROUP(svc);
285 pin = svc & EXYNOS_SVC_NUM_MASK;
286
287 if (!group)
288 return IRQ_HANDLED;
289 bank += (group - 1);
290
595be726 291 virq = irq_linear_revmap(bank->irq_domain, pin);
43b169db
TA		 292 if (!virq)
293 return IRQ_NONE;
294 generic_handle_irq(virq);
295 return IRQ_HANDLED;
296}
297
7ccbc60c
TF		 298struct exynos_eint_gpio_save {
299 u32 eint_con;
300 u32 eint_fltcon0;
301 u32 eint_fltcon1;
302};
303
43b169db
TA		 304/*
305 * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
306 * @d: driver data of samsung pinctrl driver.
307 */
308static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
309{
595be726 310 struct samsung_pin_bank *bank;
43b169db 311 struct device *dev = d->dev;
7ccbc60c
TF		 312 int ret;
313 int i;
43b169db
TA		 314
315 if (!d->irq) {
316 dev_err(dev, "irq number not available\n");
317 return -EINVAL;
318 }
319
320 ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
321 0, dev_name(dev), d);
322 if (ret) {
323 dev_err(dev, "irq request failed\n");
324 return -ENXIO;
325 }
326
1bf00d7a
TF		 327 bank = d->pin_banks;
328 for (i = 0; i < d->nr_banks; ++i, ++bank) {
595be726
TF		 329 if (bank->eint_type != EINT_TYPE_GPIO)
330 continue;
331 bank->irq_domain = irq_domain_add_linear(bank->of_node,
332 bank->nr_pins, &exynos_gpio_irqd_ops, bank);
333 if (!bank->irq_domain) {
334 dev_err(dev, "gpio irq domain add failed\n");
7ccbc60c
TF		 335 ret = -ENXIO;
336 goto err_domains;
337 }
338
339 bank->soc_priv = devm_kzalloc(d->dev,
340 sizeof(struct exynos_eint_gpio_save), GFP_KERNEL);
341 if (!bank->soc_priv) {
342 irq_domain_remove(bank->irq_domain);
343 ret = -ENOMEM;
344 goto err_domains;
595be726 345 }
43b169db
TA		 346 }
347
348 return 0;
7ccbc60c
TF		 349
350err_domains:
351 for (--i, --bank; i >= 0; --i, --bank) {
352 if (bank->eint_type != EINT_TYPE_GPIO)
353 continue;
354 irq_domain_remove(bank->irq_domain);
355 }
356
357 return ret;
43b169db
TA		 358}
359
ad350cd9
TF		 360static u32 exynos_eint_wake_mask = 0xffffffff;
361
362u32 exynos_get_eint_wake_mask(void)
363{
364 return exynos_eint_wake_mask;
365}
366
367static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
368{
369 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
370 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
371
372 pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq);
373
374 if (!on)
375 exynos_eint_wake_mask |= bit;
376 else
377 exynos_eint_wake_mask &= ~bit;
378
379 return 0;
380}
381
43b169db
TA		 382/*
383 * irq_chip for wakeup interrupts
384 */
2e4a4fda
TF		 385static struct exynos_irq_chip exynos_wkup_irq_chip = {
386 .chip = {
387 .name = "exynos_wkup_irq_chip",
388 .irq_unmask = exynos_irq_unmask,
389 .irq_mask = exynos_irq_mask,
390 .irq_ack = exynos_irq_ack,
391 .irq_set_type = exynos_irq_set_type,
392 .irq_set_wake = exynos_wkup_irq_set_wake,
f6a8249f
TF		 393 .irq_request_resources = exynos_irq_request_resources,
394 .irq_release_resources = exynos_irq_release_resources,
2e4a4fda
TF		 395 },
396 .eint_con = EXYNOS_WKUP_ECON_OFFSET,
397 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
398 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
43b169db
TA		 399};
400
401/* interrupt handler for wakeup interrupts 0..15 */
402static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
403{
404 struct exynos_weint_data *eintd = irq_get_handler_data(irq);
a04b07c0 405 struct samsung_pin_bank *bank = eintd->bank;
43b169db
TA		 406 struct irq_chip *chip = irq_get_chip(irq);
407 int eint_irq;
408
409 chained_irq_enter(chip, desc);
410 chip->irq_mask(&desc->irq_data);
411
412 if (chip->irq_ack)
413 chip->irq_ack(&desc->irq_data);
414
a04b07c0 415 eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq);
43b169db
TA		 416 generic_handle_irq(eint_irq);
417 chip->irq_unmask(&desc->irq_data);
418 chained_irq_exit(chip, desc);
419}
420
a04b07c0
TF		 421static inline void exynos_irq_demux_eint(unsigned long pend,
422 struct irq_domain *domain)
43b169db
TA		 423{
424 unsigned int irq;
425
426 while (pend) {
427 irq = fls(pend) - 1;
a04b07c0 428 generic_handle_irq(irq_find_mapping(domain, irq));
43b169db
TA		 429 pend &= ~(1 << irq);
430 }
431}
432
433/* interrupt handler for wakeup interrupt 16 */
434static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
435{
436 struct irq_chip *chip = irq_get_chip(irq);
a04b07c0
TF		 437 struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq);
438 struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata;
43b169db 439 unsigned long pend;
de59049b 440 unsigned long mask;
a04b07c0 441 int i;
43b169db
TA		 442
443 chained_irq_enter(chip, desc);
a04b07c0
TF		 444
445 for (i = 0; i < eintd->nr_banks; ++i) {
446 struct samsung_pin_bank *b = eintd->banks[i];
2e4a4fda
TF		 447 pend = readl(d->virt_base + EXYNOS_WKUP_EPEND_OFFSET
448 + b->eint_offset);
449 mask = readl(d->virt_base + EXYNOS_WKUP_EMASK_OFFSET
450 + b->eint_offset);
a04b07c0
TF		 451 exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
452 }
453
43b169db
TA		 454 chained_irq_exit(chip, desc);
455}
456
457static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
458 irq_hw_number_t hw)
459{
2e4a4fda
TF		 460 irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip.chip,
461 handle_level_irq);
43b169db
TA		 462 irq_set_chip_data(virq, h->host_data);
463 set_irq_flags(virq, IRQF_VALID);
464 return 0;
465}
466
467/*
468 * irq domain callbacks for external wakeup interrupt controller.
469 */
470static const struct irq_domain_ops exynos_wkup_irqd_ops = {
471 .map = exynos_wkup_irq_map,
472 .xlate = irq_domain_xlate_twocell,
473};
474
475/*
476 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
477 * @d: driver data of samsung pinctrl driver.
478 */
479static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
480{
481 struct device *dev = d->dev;
c3ad056b
TF		 482 struct device_node *wkup_np = NULL;
483 struct device_node *np;
a04b07c0 484 struct samsung_pin_bank *bank;
43b169db 485 struct exynos_weint_data *weint_data;
a04b07c0
TF		 486 struct exynos_muxed_weint_data *muxed_data;
487 unsigned int muxed_banks = 0;
488 unsigned int i;
43b169db
TA		 489 int idx, irq;
490
c3ad056b
TF		 491 for_each_child_of_node(dev->of_node, np) {
492 if (of_match_node(exynos_wkup_irq_ids, np)) {
493 wkup_np = np;
494 break;
495 }
43b169db 496 }
c3ad056b
TF		 497 if (!wkup_np)
498 return -ENODEV;
43b169db 499
1bf00d7a
TF		 500 bank = d->pin_banks;
501 for (i = 0; i < d->nr_banks; ++i, ++bank) {
a04b07c0
TF		 502 if (bank->eint_type != EINT_TYPE_WKUP)
503 continue;
43b169db 504
a04b07c0
TF		 505 bank->irq_domain = irq_domain_add_linear(bank->of_node,
506 bank->nr_pins, &exynos_wkup_irqd_ops, bank);
507 if (!bank->irq_domain) {
508 dev_err(dev, "wkup irq domain add failed\n");
509 return -ENXIO;
510 }
43b169db 511
a04b07c0
TF		 512 if (!of_find_property(bank->of_node, "interrupts", NULL)) {
513 bank->eint_type = EINT_TYPE_WKUP_MUX;
514 ++muxed_banks;
515 continue;
516 }
43b169db 517
a04b07c0
TF		 518 weint_data = devm_kzalloc(dev, bank->nr_pins
519 * sizeof(*weint_data), GFP_KERNEL);
520 if (!weint_data) {
521 dev_err(dev, "could not allocate memory for weint_data\n");
522 return -ENOMEM;
523 }
43b169db 524
a04b07c0
TF		 525 for (idx = 0; idx < bank->nr_pins; ++idx) {
526 irq = irq_of_parse_and_map(bank->of_node, idx);
527 if (!irq) {
528 dev_err(dev, "irq number for eint-%s-%d not found\n",
529 bank->name, idx);
530 continue;
531 }
532 weint_data[idx].irq = idx;
533 weint_data[idx].bank = bank;
43b169db
TA		 534 irq_set_handler_data(irq, &weint_data[idx]);
535 irq_set_chained_handler(irq, exynos_irq_eint0_15);
43b169db
TA		 536 }
537 }
a04b07c0
TF		 538
539 if (!muxed_banks)
540 return 0;
541
542 irq = irq_of_parse_and_map(wkup_np, 0);
543 if (!irq) {
544 dev_err(dev, "irq number for muxed EINTs not found\n");
545 return 0;
546 }
547
548 muxed_data = devm_kzalloc(dev, sizeof(*muxed_data)
549 + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL);
550 if (!muxed_data) {
551 dev_err(dev, "could not allocate memory for muxed_data\n");
552 return -ENOMEM;
553 }
554
555 irq_set_chained_handler(irq, exynos_irq_demux_eint16_31);
556 irq_set_handler_data(irq, muxed_data);
557
1bf00d7a 558 bank = d->pin_banks;
a04b07c0 559 idx = 0;
1bf00d7a 560 for (i = 0; i < d->nr_banks; ++i, ++bank) {
a04b07c0
TF		 561 if (bank->eint_type != EINT_TYPE_WKUP_MUX)
562 continue;
563
564 muxed_data->banks[idx++] = bank;
565 }
566 muxed_data->nr_banks = muxed_banks;
567
43b169db
TA		 568 return 0;
569}
570
7ccbc60c
TF		 571static void exynos_pinctrl_suspend_bank(
572 struct samsung_pinctrl_drv_data *drvdata,
573 struct samsung_pin_bank *bank)
574{
575 struct exynos_eint_gpio_save *save = bank->soc_priv;
576 void __iomem *regs = drvdata->virt_base;
577
578 save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
579 + bank->eint_offset);
580 save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
581 + 2 * bank->eint_offset);
582 save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
583 + 2 * bank->eint_offset + 4);
584
585 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
586 pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
587 pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
588}
589
590static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
591{
1bf00d7a 592 struct samsung_pin_bank *bank = drvdata->pin_banks;
7ccbc60c
TF		 593 int i;
594
1bf00d7a 595 for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
7ccbc60c
TF		 596 if (bank->eint_type == EINT_TYPE_GPIO)
597 exynos_pinctrl_suspend_bank(drvdata, bank);
598}
599
600static void exynos_pinctrl_resume_bank(
601 struct samsung_pinctrl_drv_data *drvdata,
602 struct samsung_pin_bank *bank)
603{
604 struct exynos_eint_gpio_save *save = bank->soc_priv;
605 void __iomem *regs = drvdata->virt_base;
606
607 pr_debug("%s: con %#010x => %#010x\n", bank->name,
608 readl(regs + EXYNOS_GPIO_ECON_OFFSET
609 + bank->eint_offset), save->eint_con);
610 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
611 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
612 + 2 * bank->eint_offset), save->eint_fltcon0);
613 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
614 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
615 + 2 * bank->eint_offset + 4), save->eint_fltcon1);
616
617 writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
618 + bank->eint_offset);
619 writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
620 + 2 * bank->eint_offset);
621 writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
622 + 2 * bank->eint_offset + 4);
623}
624
625static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
626{
1bf00d7a 627 struct samsung_pin_bank *bank = drvdata->pin_banks;
7ccbc60c
TF		 628 int i;
629
1bf00d7a 630 for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
7ccbc60c
TF		 631 if (bank->eint_type == EINT_TYPE_GPIO)
632 exynos_pinctrl_resume_bank(drvdata, bank);
633}
634
608a26a7
MK		 635/* pin banks of s5pv210 pin-controller */
636static struct samsung_pin_bank s5pv210_pin_bank[] = {
637 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
48802925 638 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
608a26a7
MK		 639 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
640 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
641 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
642 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
48802925
MK		 643 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
644 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c),
645 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20),
646 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24),
608a26a7
MK		 647 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),
648 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),
48802925 649 EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30),
608a26a7
MK		 650 EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),
651 EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
652 EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
653 EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
654 EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
655 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
656 EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
657 EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
658 EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
659 EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
660 EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
661 EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
662 EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
663 EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"),
664 EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"),
665 EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"),
666 EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"),
667 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00),
668 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04),
669 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08),
670 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
671};
672
1bf00d7a 673const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
608a26a7
MK		 674 {
675 /* pin-controller instance 0 data */
676 .pin_banks = s5pv210_pin_bank,
677 .nr_banks = ARRAY_SIZE(s5pv210_pin_bank),
608a26a7
MK		 678 .eint_gpio_init = exynos_eint_gpio_init,
679 .eint_wkup_init = exynos_eint_wkup_init,
680 .suspend = exynos_pinctrl_suspend,
681 .resume = exynos_pinctrl_resume,
608a26a7
MK		 682 },
683};
684
d97f5b98
TF		 685/* pin banks of exynos3250 pin-controller 0 */
686static struct samsung_pin_bank exynos3250_pin_banks0[] = {
687 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
688 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
689 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
690 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
691 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
692 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
693 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
694};
695
696/* pin banks of exynos3250 pin-controller 1 */
697static struct samsung_pin_bank exynos3250_pin_banks1[] = {
698 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
699 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
700 EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
701 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
702 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
703 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
704 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),
705 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
706 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
707 EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),
708 EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),
709 EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),
710 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
711 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
712 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
713 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
714};
715
716/*
717 * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
718 * two gpio/pin-mux/pinconfig controllers.
719 */
1bf00d7a 720const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
d97f5b98
TF		 721 {
722 /* pin-controller instance 0 data */
723 .pin_banks = exynos3250_pin_banks0,
724 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0),
d97f5b98
TF		 725 .eint_gpio_init = exynos_eint_gpio_init,
726 .suspend = exynos_pinctrl_suspend,
727 .resume = exynos_pinctrl_resume,
d97f5b98
TF		 728 }, {
729 /* pin-controller instance 1 data */
730 .pin_banks = exynos3250_pin_banks1,
731 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1),
d97f5b98
TF		 732 .eint_gpio_init = exynos_eint_gpio_init,
733 .eint_wkup_init = exynos_eint_wkup_init,
734 .suspend = exynos_pinctrl_suspend,
735 .resume = exynos_pinctrl_resume,
d97f5b98
TF		 736 },
737};
738
43b169db
TA		 739/* pin banks of exynos4210 pin-controller 0 */
740static struct samsung_pin_bank exynos4210_pin_banks0[] = {
1b6056d6
TF		 741 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
742 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
743 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
744 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
745 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
746 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
747 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
748 EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
749 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
750 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
751 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
752 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
753 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
754 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
755 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
756 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
43b169db
TA		 757};
758
759/* pin banks of exynos4210 pin-controller 1 */
760static struct samsung_pin_bank exynos4210_pin_banks1[] = {
1b6056d6
TF		 761 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
762 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
763 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
764 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
765 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
766 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
767 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
768 EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
769 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
40ba6227
TF		 770 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
771 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
772 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
773 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
774 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
775 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
776 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
a04b07c0
TF		 777 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
778 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
779 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
780 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
43b169db
TA		 781};
782
783/* pin banks of exynos4210 pin-controller 2 */
784static struct samsung_pin_bank exynos4210_pin_banks2[] = {
40ba6227 785 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
43b169db
TA		 786};
787
788/*
789 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
790 * three gpio/pin-mux/pinconfig controllers.
791 */
1bf00d7a 792const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {
43b169db
TA		 793 {
794 /* pin-controller instance 0 data */
795 .pin_banks = exynos4210_pin_banks0,
796 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
43b169db 797 .eint_gpio_init = exynos_eint_gpio_init,
7ccbc60c
TF		 798 .suspend = exynos_pinctrl_suspend,
799 .resume = exynos_pinctrl_resume,
43b169db
TA		 800 }, {
801 /* pin-controller instance 1 data */
802 .pin_banks = exynos4210_pin_banks1,
803 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
43b169db
TA		 804 .eint_gpio_init = exynos_eint_gpio_init,
805 .eint_wkup_init = exynos_eint_wkup_init,
7ccbc60c
TF		 806 .suspend = exynos_pinctrl_suspend,
807 .resume = exynos_pinctrl_resume,
43b169db
TA		 808 }, {
809 /* pin-controller instance 2 data */
810 .pin_banks = exynos4210_pin_banks2,
811 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),
43b169db
TA		 812 },
813};
6edc794a
TF		 814
815/* pin banks of exynos4x12 pin-controller 0 */
816static struct samsung_pin_bank exynos4x12_pin_banks0[] = {
817 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
818 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
819 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
820 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
821 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
822 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
823 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
824 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
825 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
826 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
827 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
828 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
829 EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
830};
831
832/* pin banks of exynos4x12 pin-controller 1 */
833static struct samsung_pin_bank exynos4x12_pin_banks1[] = {
834 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
835 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
836 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
837 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
838 EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
839 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
840 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
841 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
842 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
843 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
844 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
845 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
846 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
847 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
848 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
849 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
850 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
851 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
852 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
853 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
854 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
855 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
856 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
857};
858
859/* pin banks of exynos4x12 pin-controller 2 */
860static struct samsung_pin_bank exynos4x12_pin_banks2[] = {
861 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
862};
863
864/* pin banks of exynos4x12 pin-controller 3 */
865static struct samsung_pin_bank exynos4x12_pin_banks3[] = {
866 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
867 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
868 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
869 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
870 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
871};
872
873/*
874 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
875 * four gpio/pin-mux/pinconfig controllers.
876 */
1bf00d7a 877const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {
6edc794a
TF		 878 {
879 /* pin-controller instance 0 data */
880 .pin_banks = exynos4x12_pin_banks0,
881 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0),
6edc794a 882 .eint_gpio_init = exynos_eint_gpio_init,
7ccbc60c
TF		 883 .suspend = exynos_pinctrl_suspend,
884 .resume = exynos_pinctrl_resume,
6edc794a
TF		 885 }, {
886 /* pin-controller instance 1 data */
887 .pin_banks = exynos4x12_pin_banks1,
888 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1),
6edc794a
TF		 889 .eint_gpio_init = exynos_eint_gpio_init,
890 .eint_wkup_init = exynos_eint_wkup_init,
7ccbc60c
TF		 891 .suspend = exynos_pinctrl_suspend,
892 .resume = exynos_pinctrl_resume,
6edc794a
TF		 893 }, {
894 /* pin-controller instance 2 data */
895 .pin_banks = exynos4x12_pin_banks2,
896 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2),
6edc794a 897 .eint_gpio_init = exynos_eint_gpio_init,
7ccbc60c
TF		 898 .suspend = exynos_pinctrl_suspend,
899 .resume = exynos_pinctrl_resume,
6edc794a
TF		 900 }, {
901 /* pin-controller instance 3 data */
902 .pin_banks = exynos4x12_pin_banks3,
903 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3),
6edc794a 904 .eint_gpio_init = exynos_eint_gpio_init,
7ccbc60c
TF		 905 .suspend = exynos_pinctrl_suspend,
906 .resume = exynos_pinctrl_resume,
6edc794a
TF		 907 },
908};
f67faf48
TA		 909
910/* pin banks of exynos5250 pin-controller 0 */
911static struct samsung_pin_bank exynos5250_pin_banks0[] = {
912 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
913 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
914 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
915 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
916 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
917 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
918 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
919 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
920 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
921 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
922 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
923 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
924 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
925 EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
926 EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
927 EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
928 EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
929 EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
930 EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
931 EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
932 EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
933 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
934 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
935 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
936 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
937};
938
939/* pin banks of exynos5250 pin-controller 1 */
940static struct samsung_pin_bank exynos5250_pin_banks1[] = {
941 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
942 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
943 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
944 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
945 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
946 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
947 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
948 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
949 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
950};
951
952/* pin banks of exynos5250 pin-controller 2 */
953static struct samsung_pin_bank exynos5250_pin_banks2[] = {
954 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
955 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
956 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
957 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
958 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
959};
960
961/* pin banks of exynos5250 pin-controller 3 */
962static struct samsung_pin_bank exynos5250_pin_banks3[] = {
963 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
964};
965
966/*
967 * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
968 * four gpio/pin-mux/pinconfig controllers.
969 */
1bf00d7a 970const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {
f67faf48
TA		 971 {
972 /* pin-controller instance 0 data */
973 .pin_banks = exynos5250_pin_banks0,
974 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0),
f67faf48
TA		 975 .eint_gpio_init = exynos_eint_gpio_init,
976 .eint_wkup_init = exynos_eint_wkup_init,
7ccbc60c
TF		 977 .suspend = exynos_pinctrl_suspend,
978 .resume = exynos_pinctrl_resume,
f67faf48
TA		 979 }, {
980 /* pin-controller instance 1 data */
981 .pin_banks = exynos5250_pin_banks1,
982 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1),
f67faf48 983 .eint_gpio_init = exynos_eint_gpio_init,
7ccbc60c
TF		 984 .suspend = exynos_pinctrl_suspend,
985 .resume = exynos_pinctrl_resume,
f67faf48
TA		 986 }, {
987 /* pin-controller instance 2 data */
988 .pin_banks = exynos5250_pin_banks2,
989 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2),
f67faf48 990 .eint_gpio_init = exynos_eint_gpio_init,
7ccbc60c
TF		 991 .suspend = exynos_pinctrl_suspend,
992 .resume = exynos_pinctrl_resume,
f67faf48
TA		 993 }, {
994 /* pin-controller instance 3 data */
995 .pin_banks = exynos5250_pin_banks3,
996 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3),
f67faf48 997 .eint_gpio_init = exynos_eint_gpio_init,
7ccbc60c
TF		 998 .suspend = exynos_pinctrl_suspend,
999 .resume = exynos_pinctrl_resume,
f67faf48
TA		 1000 },
1001};
983dbeb3 1002
9a8b6079
YGJ		 1003/* pin banks of exynos5260 pin-controller 0 */
1004static struct samsung_pin_bank exynos5260_pin_banks0[] = {
1005 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
1006 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
1007 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1008 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1009 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
1010 EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14),
1011 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18),
1012 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c),
1013 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
1014 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
1015 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
1016 EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
1017 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
1018 EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34),
1019 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
1020 EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c),
1021 EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
1022 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
1023 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
1024 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
1025 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
1026};
1027
1028/* pin banks of exynos5260 pin-controller 1 */
1029static struct samsung_pin_bank exynos5260_pin_banks1[] = {
1030 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
1031 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
1032 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
1033 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
1034 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
1035};
1036
1037/* pin banks of exynos5260 pin-controller 2 */
1038static struct samsung_pin_bank exynos5260_pin_banks2[] = {
1039 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1040 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1041};
1042
1043/*
1044 * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
1045 * three gpio/pin-mux/pinconfig controllers.
1046 */
1bf00d7a 1047const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
9a8b6079
YGJ		 1048 {
1049 /* pin-controller instance 0 data */
1050 .pin_banks = exynos5260_pin_banks0,
1051 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
9a8b6079
YGJ		 1052 .eint_gpio_init = exynos_eint_gpio_init,
1053 .eint_wkup_init = exynos_eint_wkup_init,
9a8b6079
YGJ		 1054 }, {
1055 /* pin-controller instance 1 data */
1056 .pin_banks = exynos5260_pin_banks1,
1057 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
9a8b6079 1058 .eint_gpio_init = exynos_eint_gpio_init,
9a8b6079
YGJ		 1059 }, {
1060 /* pin-controller instance 2 data */
1061 .pin_banks = exynos5260_pin_banks2,
1062 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2),
9a8b6079 1063 .eint_gpio_init = exynos_eint_gpio_init,
9a8b6079
YGJ		 1064 },
1065};
1066
983dbeb3
LKA		 1067/* pin banks of exynos5420 pin-controller 0 */
1068static struct samsung_pin_bank exynos5420_pin_banks0[] = {
1069 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
1070 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
1071 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
1072 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
1073 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
1074};
1075
1076/* pin banks of exynos5420 pin-controller 1 */
1077static struct samsung_pin_bank exynos5420_pin_banks1[] = {
1078 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
1079 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
1080 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
1081 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
1082 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
1083 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
1084 EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
1085 EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
1086 EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
1087 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
1088 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
1089 EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
1090 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
1091};
1092
1093/* pin banks of exynos5420 pin-controller 2 */
1094static struct samsung_pin_bank exynos5420_pin_banks2[] = {
1095 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
1096 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
1097 EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
1098 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
1099 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
1100 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
1101 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
1102 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
1103};
1104
1105/* pin banks of exynos5420 pin-controller 3 */
1106static struct samsung_pin_bank exynos5420_pin_banks3[] = {
1107 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
1108 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
1109 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1110 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1111 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
1112 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
1113 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
1114 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
1115 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
1116};
1117
1118/* pin banks of exynos5420 pin-controller 4 */
1119static struct samsung_pin_bank exynos5420_pin_banks4[] = {
1120 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
1121};
1122
1123/*
1124 * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
1125 * four gpio/pin-mux/pinconfig controllers.
1126 */
1bf00d7a 1127const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
983dbeb3
LKA		 1128 {
1129 /* pin-controller instance 0 data */
1130 .pin_banks = exynos5420_pin_banks0,
1131 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
983dbeb3
LKA		 1132 .eint_gpio_init = exynos_eint_gpio_init,
1133 .eint_wkup_init = exynos_eint_wkup_init,
983dbeb3
LKA		 1134 }, {
1135 /* pin-controller instance 1 data */
1136 .pin_banks = exynos5420_pin_banks1,
1137 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),
983dbeb3 1138 .eint_gpio_init = exynos_eint_gpio_init,
983dbeb3
LKA		 1139 }, {
1140 /* pin-controller instance 2 data */
1141 .pin_banks = exynos5420_pin_banks2,
1142 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2),
983dbeb3 1143 .eint_gpio_init = exynos_eint_gpio_init,
983dbeb3
LKA		 1144 }, {
1145 /* pin-controller instance 3 data */
1146 .pin_banks = exynos5420_pin_banks3,
1147 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3),
983dbeb3 1148 .eint_gpio_init = exynos_eint_gpio_init,
983dbeb3
LKA		 1149 }, {
1150 /* pin-controller instance 4 data */
1151 .pin_banks = exynos5420_pin_banks4,
1152 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4),
983dbeb3 1153 .eint_gpio_init = exynos_eint_gpio_init,
983dbeb3
LKA		 1154 },
1155};
Linux kernel - Deliverables
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