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pinctrl: exynos: Add initial driver data for Exynos7
[deliverable/linux.git] / drivers / pinctrl / samsung / pinctrl-exynos.c
CommitLineData
43b169db
TA		 1/*
2 * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2012 Linaro Ltd
7 * http://www.linaro.org
8 *
9 * Author: Thomas Abraham <thomas.ab@samsung.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This file contains the Samsung Exynos specific information required by the
17 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
18 * external gpio and wakeup interrupt support.
19 */
20
21#include <linux/module.h>
22#include <linux/device.h>
23#include <linux/interrupt.h>
24#include <linux/irqdomain.h>
25#include <linux/irq.h>
de88cbb7 26#include <linux/irqchip/chained_irq.h>
43b169db
TA		 27#include <linux/of_irq.h>
28#include <linux/io.h>
29#include <linux/slab.h>
19846950 30#include <linux/spinlock.h>
43b169db
TA		 31#include <linux/err.h>
32
43b169db
TA		 33#include "pinctrl-samsung.h"
34#include "pinctrl-exynos.h"
35
2e4a4fda
TF		 36struct exynos_irq_chip {
37 struct irq_chip chip;
38
39 u32 eint_con;
40 u32 eint_mask;
41 u32 eint_pend;
42};
43
44static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip)
45{
46 return container_of(chip, struct exynos_irq_chip, chip);
47}
499147c9 48
94ce944b 49static const struct samsung_pin_bank_type bank_type_off = {
499147c9 50 .fld_width = { 4, 1, 2, 2, 2, 2, },
43fc9e7f 51 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
499147c9
TF		 52};
53
94ce944b 54static const struct samsung_pin_bank_type bank_type_alive = {
499147c9 55 .fld_width = { 4, 1, 2, 2, },
43fc9e7f 56 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
499147c9
TF		 57};
58
2e4a4fda 59static void exynos_irq_mask(struct irq_data *irqd)
43b169db 60{
2e4a4fda
TF		 61 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
62 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
595be726
TF		 63 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
64 struct samsung_pinctrl_drv_data *d = bank->drvdata;
2e4a4fda 65 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
43b169db 66 unsigned long mask;
5ae8cf79
DA		 67 unsigned long flags;
68
69 spin_lock_irqsave(&bank->slock, flags);
43b169db
TA		 70
71 mask = readl(d->virt_base + reg_mask);
5ace03fb 72 mask |= 1 << irqd->hwirq;
43b169db 73 writel(mask, d->virt_base + reg_mask);
5ae8cf79
DA		 74
75 spin_unlock_irqrestore(&bank->slock, flags);
43b169db
TA		 76}
77
2e4a4fda 78static void exynos_irq_ack(struct irq_data *irqd)
43b169db 79{
2e4a4fda
TF		 80 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
81 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
595be726
TF		 82 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
83 struct samsung_pinctrl_drv_data *d = bank->drvdata;
2e4a4fda 84 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset;
43b169db 85
5ace03fb 86 writel(1 << irqd->hwirq, d->virt_base + reg_pend);
43b169db
TA		 87}
88
2e4a4fda 89static void exynos_irq_unmask(struct irq_data *irqd)
43b169db 90{
2e4a4fda
TF		 91 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
92 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
595be726
TF		 93 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
94 struct samsung_pinctrl_drv_data *d = bank->drvdata;
2e4a4fda 95 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
43b169db 96 unsigned long mask;
5ae8cf79 97 unsigned long flags;
43b169db 98
5a68e7a7
DA		 99 /*
100 * Ack level interrupts right before unmask
101 *
102 * If we don't do this we'll get a double-interrupt. Level triggered
103 * interrupts must not fire an interrupt if the level is not
104 * _currently_ active, even if it was active while the interrupt was
105 * masked.
106 */
107 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
2e4a4fda 108 exynos_irq_ack(irqd);
5a68e7a7 109
5ae8cf79 110 spin_lock_irqsave(&bank->slock, flags);
43b169db
TA		 111
112 mask = readl(d->virt_base + reg_mask);
5ace03fb 113 mask &= ~(1 << irqd->hwirq);
43b169db 114 writel(mask, d->virt_base + reg_mask);
5ae8cf79
DA		 115
116 spin_unlock_irqrestore(&bank->slock, flags);
43b169db
TA		 117}
118
2e4a4fda 119static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
43b169db 120{
2e4a4fda
TF		 121 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
122 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
595be726
TF		 123 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
124 struct samsung_pinctrl_drv_data *d = bank->drvdata;
f6a8249f 125 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
43b169db 126 unsigned int con, trig_type;
2e4a4fda 127 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
43b169db
TA		 128
129 switch (type) {
130 case IRQ_TYPE_EDGE_RISING:
131 trig_type = EXYNOS_EINT_EDGE_RISING;
132 break;
133 case IRQ_TYPE_EDGE_FALLING:
134 trig_type = EXYNOS_EINT_EDGE_FALLING;
135 break;
136 case IRQ_TYPE_EDGE_BOTH:
137 trig_type = EXYNOS_EINT_EDGE_BOTH;
138 break;
139 case IRQ_TYPE_LEVEL_HIGH:
140 trig_type = EXYNOS_EINT_LEVEL_HIGH;
141 break;
142 case IRQ_TYPE_LEVEL_LOW:
143 trig_type = EXYNOS_EINT_LEVEL_LOW;
144 break;
145 default:
146 pr_err("unsupported external interrupt type\n");
147 return -EINVAL;
148 }
149
150 if (type & IRQ_TYPE_EDGE_BOTH)
151 __irq_set_handler_locked(irqd->irq, handle_edge_irq);
152 else
153 __irq_set_handler_locked(irqd->irq, handle_level_irq);
154
155 con = readl(d->virt_base + reg_con);
156 con &= ~(EXYNOS_EINT_CON_MASK << shift);
157 con |= trig_type << shift;
158 writel(con, d->virt_base + reg_con);
ee2f573c 159
f6a8249f
TF		 160 return 0;
161}
162
163static int exynos_irq_request_resources(struct irq_data *irqd)
164{
165 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
166 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
167 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
94ce944b 168 const struct samsung_pin_bank_type *bank_type = bank->type;
f6a8249f
TF		 169 struct samsung_pinctrl_drv_data *d = bank->drvdata;
170 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
171 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
172 unsigned long flags;
173 unsigned int mask;
174 unsigned int con;
175 int ret;
176
177 ret = gpio_lock_as_irq(&bank->gpio_chip, irqd->hwirq);
178 if (ret) {
179 dev_err(bank->gpio_chip.dev, "unable to lock pin %s-%lu IRQ\n",
180 bank->name, irqd->hwirq);
181 return ret;
182 }
183
43fc9e7f 184 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
f6a8249f 185 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
499147c9 186 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
ee2f573c 187
19846950
TF		 188 spin_lock_irqsave(&bank->slock, flags);
189
ee2f573c
TF		 190 con = readl(d->virt_base + reg_con);
191 con &= ~(mask << shift);
192 con |= EXYNOS_EINT_FUNC << shift;
193 writel(con, d->virt_base + reg_con);
194
19846950
TF		 195 spin_unlock_irqrestore(&bank->slock, flags);
196
f6a8249f
TF		 197 exynos_irq_unmask(irqd);
198
43b169db
TA		 199 return 0;
200}
201
f6a8249f
TF		 202static void exynos_irq_release_resources(struct irq_data *irqd)
203{
204 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
205 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
206 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
94ce944b 207 const struct samsung_pin_bank_type *bank_type = bank->type;
f6a8249f
TF		 208 struct samsung_pinctrl_drv_data *d = bank->drvdata;
209 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
210 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
211 unsigned long flags;
212 unsigned int mask;
213 unsigned int con;
214
215 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
216 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
217 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
218
219 exynos_irq_mask(irqd);
220
221 spin_lock_irqsave(&bank->slock, flags);
222
223 con = readl(d->virt_base + reg_con);
224 con &= ~(mask << shift);
225 con |= FUNC_INPUT << shift;
226 writel(con, d->virt_base + reg_con);
227
228 spin_unlock_irqrestore(&bank->slock, flags);
229
230 gpio_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
231}
232
43b169db
TA		 233/*
234 * irq_chip for gpio interrupts.
235 */
2e4a4fda
TF		 236static struct exynos_irq_chip exynos_gpio_irq_chip = {
237 .chip = {
238 .name = "exynos_gpio_irq_chip",
239 .irq_unmask = exynos_irq_unmask,
240 .irq_mask = exynos_irq_mask,
241 .irq_ack = exynos_irq_ack,
242 .irq_set_type = exynos_irq_set_type,
f6a8249f
TF		 243 .irq_request_resources = exynos_irq_request_resources,
244 .irq_release_resources = exynos_irq_release_resources,
2e4a4fda
TF		 245 },
246 .eint_con = EXYNOS_GPIO_ECON_OFFSET,
247 .eint_mask = EXYNOS_GPIO_EMASK_OFFSET,
248 .eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
43b169db
TA		 249};
250
6f5e41bd 251static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq,
43b169db
TA		 252 irq_hw_number_t hw)
253{
595be726 254 struct samsung_pin_bank *b = h->host_data;
43b169db 255
595be726 256 irq_set_chip_data(virq, b);
0d3d30db 257 irq_set_chip_and_handler(virq, &b->irq_chip->chip,
43b169db
TA		 258 handle_level_irq);
259 set_irq_flags(virq, IRQF_VALID);
260 return 0;
261}
262
43b169db 263/*
6f5e41bd 264 * irq domain callbacks for external gpio and wakeup interrupt controllers.
43b169db 265 */
6f5e41bd
AK		 266static const struct irq_domain_ops exynos_eint_irqd_ops = {
267 .map = exynos_eint_irq_map,
43b169db
TA		 268 .xlate = irq_domain_xlate_twocell,
269};
270
271static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
272{
273 struct samsung_pinctrl_drv_data *d = data;
1bf00d7a 274 struct samsung_pin_bank *bank = d->pin_banks;
43b169db
TA		 275 unsigned int svc, group, pin, virq;
276
2e4a4fda 277 svc = readl(d->virt_base + EXYNOS_SVC_OFFSET);
43b169db
TA		 278 group = EXYNOS_SVC_GROUP(svc);
279 pin = svc & EXYNOS_SVC_NUM_MASK;
280
281 if (!group)
282 return IRQ_HANDLED;
283 bank += (group - 1);
284
595be726 285 virq = irq_linear_revmap(bank->irq_domain, pin);
43b169db
TA		 286 if (!virq)
287 return IRQ_NONE;
288 generic_handle_irq(virq);
289 return IRQ_HANDLED;
290}
291
7ccbc60c
TF		 292struct exynos_eint_gpio_save {
293 u32 eint_con;
294 u32 eint_fltcon0;
295 u32 eint_fltcon1;
296};
297
43b169db
TA		 298/*
299 * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
300 * @d: driver data of samsung pinctrl driver.
301 */
302static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
303{
595be726 304 struct samsung_pin_bank *bank;
43b169db 305 struct device *dev = d->dev;
7ccbc60c
TF		 306 int ret;
307 int i;
43b169db
TA		 308
309 if (!d->irq) {
310 dev_err(dev, "irq number not available\n");
311 return -EINVAL;
312 }
313
314 ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
315 0, dev_name(dev), d);
316 if (ret) {
317 dev_err(dev, "irq request failed\n");
318 return -ENXIO;
319 }
320
1bf00d7a
TF		 321 bank = d->pin_banks;
322 for (i = 0; i < d->nr_banks; ++i, ++bank) {
595be726
TF		 323 if (bank->eint_type != EINT_TYPE_GPIO)
324 continue;
325 bank->irq_domain = irq_domain_add_linear(bank->of_node,
6f5e41bd 326 bank->nr_pins, &exynos_eint_irqd_ops, bank);
595be726
TF		 327 if (!bank->irq_domain) {
328 dev_err(dev, "gpio irq domain add failed\n");
7ccbc60c
TF		 329 ret = -ENXIO;
330 goto err_domains;
331 }
332
333 bank->soc_priv = devm_kzalloc(d->dev,
334 sizeof(struct exynos_eint_gpio_save), GFP_KERNEL);
335 if (!bank->soc_priv) {
336 irq_domain_remove(bank->irq_domain);
337 ret = -ENOMEM;
338 goto err_domains;
595be726 339 }
0d3d30db
AK		 340
341 bank->irq_chip = &exynos_gpio_irq_chip;
43b169db
TA		 342 }
343
344 return 0;
7ccbc60c
TF		 345
346err_domains:
347 for (--i, --bank; i >= 0; --i, --bank) {
348 if (bank->eint_type != EINT_TYPE_GPIO)
349 continue;
350 irq_domain_remove(bank->irq_domain);
351 }
352
353 return ret;
43b169db
TA		 354}
355
ad350cd9
TF		 356static u32 exynos_eint_wake_mask = 0xffffffff;
357
358u32 exynos_get_eint_wake_mask(void)
359{
360 return exynos_eint_wake_mask;
361}
362
363static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
364{
365 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
366 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
367
368 pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq);
369
370 if (!on)
371 exynos_eint_wake_mask |= bit;
372 else
373 exynos_eint_wake_mask &= ~bit;
374
375 return 0;
376}
377
43b169db
TA		 378/*
379 * irq_chip for wakeup interrupts
380 */
14c255d3 381static struct exynos_irq_chip exynos4210_wkup_irq_chip __initdata = {
2e4a4fda 382 .chip = {
14c255d3 383 .name = "exynos4210_wkup_irq_chip",
2e4a4fda
TF		 384 .irq_unmask = exynos_irq_unmask,
385 .irq_mask = exynos_irq_mask,
386 .irq_ack = exynos_irq_ack,
387 .irq_set_type = exynos_irq_set_type,
388 .irq_set_wake = exynos_wkup_irq_set_wake,
f6a8249f
TF		 389 .irq_request_resources = exynos_irq_request_resources,
390 .irq_release_resources = exynos_irq_release_resources,
2e4a4fda
TF		 391 },
392 .eint_con = EXYNOS_WKUP_ECON_OFFSET,
393 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
394 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
43b169db
TA		 395};
396
14c255d3
AK		 397static struct exynos_irq_chip exynos7_wkup_irq_chip __initdata = {
398 .chip = {
399 .name = "exynos7_wkup_irq_chip",
400 .irq_unmask = exynos_irq_unmask,
401 .irq_mask = exynos_irq_mask,
402 .irq_ack = exynos_irq_ack,
403 .irq_set_type = exynos_irq_set_type,
404 .irq_set_wake = exynos_wkup_irq_set_wake,
405 .irq_request_resources = exynos_irq_request_resources,
406 .irq_release_resources = exynos_irq_release_resources,
407 },
408 .eint_con = EXYNOS7_WKUP_ECON_OFFSET,
409 .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
410 .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
411};
412
413/* list of external wakeup controllers supported */
414static const struct of_device_id exynos_wkup_irq_ids[] = {
415 { .compatible = "samsung,exynos4210-wakeup-eint",
416 .data = &exynos4210_wkup_irq_chip },
417 { .compatible = "samsung,exynos7-wakeup-eint",
418 .data = &exynos7_wkup_irq_chip },
419 { }
420};
421
43b169db
TA		 422/* interrupt handler for wakeup interrupts 0..15 */
423static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
424{
425 struct exynos_weint_data *eintd = irq_get_handler_data(irq);
a04b07c0 426 struct samsung_pin_bank *bank = eintd->bank;
43b169db
TA		 427 struct irq_chip *chip = irq_get_chip(irq);
428 int eint_irq;
429
430 chained_irq_enter(chip, desc);
431 chip->irq_mask(&desc->irq_data);
432
433 if (chip->irq_ack)
434 chip->irq_ack(&desc->irq_data);
435
a04b07c0 436 eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq);
43b169db
TA		 437 generic_handle_irq(eint_irq);
438 chip->irq_unmask(&desc->irq_data);
439 chained_irq_exit(chip, desc);
440}
441
a04b07c0
TF		 442static inline void exynos_irq_demux_eint(unsigned long pend,
443 struct irq_domain *domain)
43b169db
TA		 444{
445 unsigned int irq;
446
447 while (pend) {
448 irq = fls(pend) - 1;
a04b07c0 449 generic_handle_irq(irq_find_mapping(domain, irq));
43b169db
TA		 450 pend &= ~(1 << irq);
451 }
452}
453
454/* interrupt handler for wakeup interrupt 16 */
455static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
456{
457 struct irq_chip *chip = irq_get_chip(irq);
a04b07c0
TF		 458 struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq);
459 struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata;
43b169db 460 unsigned long pend;
de59049b 461 unsigned long mask;
a04b07c0 462 int i;
43b169db
TA		 463
464 chained_irq_enter(chip, desc);
a04b07c0
TF		 465
466 for (i = 0; i < eintd->nr_banks; ++i) {
467 struct samsung_pin_bank *b = eintd->banks[i];
0d3d30db 468 pend = readl(d->virt_base + b->irq_chip->eint_pend
2e4a4fda 469 + b->eint_offset);
0d3d30db 470 mask = readl(d->virt_base + b->irq_chip->eint_mask
2e4a4fda 471 + b->eint_offset);
a04b07c0
TF		 472 exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
473 }
474
43b169db
TA		 475 chained_irq_exit(chip, desc);
476}
477
43b169db
TA		 478/*
479 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
480 * @d: driver data of samsung pinctrl driver.
481 */
482static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
483{
484 struct device *dev = d->dev;
c3ad056b
TF		 485 struct device_node *wkup_np = NULL;
486 struct device_node *np;
a04b07c0 487 struct samsung_pin_bank *bank;
43b169db 488 struct exynos_weint_data *weint_data;
a04b07c0 489 struct exynos_muxed_weint_data *muxed_data;
14c255d3 490 struct exynos_irq_chip *irq_chip;
a04b07c0
TF		 491 unsigned int muxed_banks = 0;
492 unsigned int i;
43b169db
TA		 493 int idx, irq;
494
c3ad056b 495 for_each_child_of_node(dev->of_node, np) {
14c255d3
AK		 496 const struct of_device_id *match;
497
498 match = of_match_node(exynos_wkup_irq_ids, np);
499 if (match) {
500 irq_chip = kmemdup(match->data,
501 sizeof(*irq_chip), GFP_KERNEL);
c3ad056b
TF		 502 wkup_np = np;
503 break;
504 }
43b169db 505 }
c3ad056b
TF		 506 if (!wkup_np)
507 return -ENODEV;
43b169db 508
1bf00d7a
TF		 509 bank = d->pin_banks;
510 for (i = 0; i < d->nr_banks; ++i, ++bank) {
a04b07c0
TF		 511 if (bank->eint_type != EINT_TYPE_WKUP)
512 continue;
43b169db 513
a04b07c0 514 bank->irq_domain = irq_domain_add_linear(bank->of_node,
6f5e41bd 515 bank->nr_pins, &exynos_eint_irqd_ops, bank);
a04b07c0
TF		 516 if (!bank->irq_domain) {
517 dev_err(dev, "wkup irq domain add failed\n");
518 return -ENXIO;
519 }
43b169db 520
14c255d3 521 bank->irq_chip = irq_chip;
0d3d30db 522
a04b07c0
TF		 523 if (!of_find_property(bank->of_node, "interrupts", NULL)) {
524 bank->eint_type = EINT_TYPE_WKUP_MUX;
525 ++muxed_banks;
526 continue;
527 }
43b169db 528
a04b07c0
TF		 529 weint_data = devm_kzalloc(dev, bank->nr_pins
530 * sizeof(*weint_data), GFP_KERNEL);
531 if (!weint_data) {
532 dev_err(dev, "could not allocate memory for weint_data\n");
533 return -ENOMEM;
534 }
43b169db 535
a04b07c0
TF		 536 for (idx = 0; idx < bank->nr_pins; ++idx) {
537 irq = irq_of_parse_and_map(bank->of_node, idx);
538 if (!irq) {
539 dev_err(dev, "irq number for eint-%s-%d not found\n",
540 bank->name, idx);
541 continue;
542 }
543 weint_data[idx].irq = idx;
544 weint_data[idx].bank = bank;
43b169db
TA		 545 irq_set_handler_data(irq, &weint_data[idx]);
546 irq_set_chained_handler(irq, exynos_irq_eint0_15);
43b169db
TA		 547 }
548 }
a04b07c0
TF		 549
550 if (!muxed_banks)
551 return 0;
552
553 irq = irq_of_parse_and_map(wkup_np, 0);
554 if (!irq) {
555 dev_err(dev, "irq number for muxed EINTs not found\n");
556 return 0;
557 }
558
559 muxed_data = devm_kzalloc(dev, sizeof(*muxed_data)
560 + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL);
561 if (!muxed_data) {
562 dev_err(dev, "could not allocate memory for muxed_data\n");
563 return -ENOMEM;
564 }
565
566 irq_set_chained_handler(irq, exynos_irq_demux_eint16_31);
567 irq_set_handler_data(irq, muxed_data);
568
1bf00d7a 569 bank = d->pin_banks;
a04b07c0 570 idx = 0;
1bf00d7a 571 for (i = 0; i < d->nr_banks; ++i, ++bank) {
a04b07c0
TF		 572 if (bank->eint_type != EINT_TYPE_WKUP_MUX)
573 continue;
574
575 muxed_data->banks[idx++] = bank;
576 }
577 muxed_data->nr_banks = muxed_banks;
578
43b169db
TA		 579 return 0;
580}
581
7ccbc60c
TF		 582static void exynos_pinctrl_suspend_bank(
583 struct samsung_pinctrl_drv_data *drvdata,
584 struct samsung_pin_bank *bank)
585{
586 struct exynos_eint_gpio_save *save = bank->soc_priv;
587 void __iomem *regs = drvdata->virt_base;
588
589 save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
590 + bank->eint_offset);
591 save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
592 + 2 * bank->eint_offset);
593 save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
594 + 2 * bank->eint_offset + 4);
595
596 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
597 pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
598 pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
599}
600
601static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
602{
1bf00d7a 603 struct samsung_pin_bank *bank = drvdata->pin_banks;
7ccbc60c
TF		 604 int i;
605
1bf00d7a 606 for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
7ccbc60c
TF		 607 if (bank->eint_type == EINT_TYPE_GPIO)
608 exynos_pinctrl_suspend_bank(drvdata, bank);
609}
610
611static void exynos_pinctrl_resume_bank(
612 struct samsung_pinctrl_drv_data *drvdata,
613 struct samsung_pin_bank *bank)
614{
615 struct exynos_eint_gpio_save *save = bank->soc_priv;
616 void __iomem *regs = drvdata->virt_base;
617
618 pr_debug("%s: con %#010x => %#010x\n", bank->name,
619 readl(regs + EXYNOS_GPIO_ECON_OFFSET
620 + bank->eint_offset), save->eint_con);
621 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
622 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
623 + 2 * bank->eint_offset), save->eint_fltcon0);
624 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
625 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
626 + 2 * bank->eint_offset + 4), save->eint_fltcon1);
627
628 writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
629 + bank->eint_offset);
630 writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
631 + 2 * bank->eint_offset);
632 writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
633 + 2 * bank->eint_offset + 4);
634}
635
636static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
637{
1bf00d7a 638 struct samsung_pin_bank *bank = drvdata->pin_banks;
7ccbc60c
TF		 639 int i;
640
1bf00d7a 641 for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
7ccbc60c
TF		 642 if (bank->eint_type == EINT_TYPE_GPIO)
643 exynos_pinctrl_resume_bank(drvdata, bank);
644}
645
608a26a7 646/* pin banks of s5pv210 pin-controller */
8100cf47 647static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
608a26a7 648 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
48802925 649 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
608a26a7
MK		 650 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
651 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
652 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
653 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
48802925
MK		 654 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
655 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c),
656 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20),
657 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24),
608a26a7
MK		 658 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),
659 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),
48802925 660 EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30),
608a26a7
MK		 661 EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),
662 EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
663 EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
664 EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
665 EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
666 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
667 EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
668 EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
669 EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
670 EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
671 EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
672 EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
673 EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
674 EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"),
675 EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"),
676 EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"),
677 EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"),
678 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00),
679 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04),
680 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08),
681 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
682};
683
1bf00d7a 684const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
608a26a7
MK		 685 {
686 /* pin-controller instance 0 data */
687 .pin_banks = s5pv210_pin_bank,
688 .nr_banks = ARRAY_SIZE(s5pv210_pin_bank),
608a26a7
MK		 689 .eint_gpio_init = exynos_eint_gpio_init,
690 .eint_wkup_init = exynos_eint_wkup_init,
691 .suspend = exynos_pinctrl_suspend,
692 .resume = exynos_pinctrl_resume,
608a26a7
MK		 693 },
694};
695
d97f5b98 696/* pin banks of exynos3250 pin-controller 0 */
8100cf47 697static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = {
d97f5b98
TF		 698 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
699 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
700 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
701 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
702 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
703 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
704 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
705};
706
707/* pin banks of exynos3250 pin-controller 1 */
8100cf47 708static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = {
d97f5b98
TF		 709 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
710 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
711 EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
712 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
713 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
714 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
715 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),
716 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
717 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
718 EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),
719 EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),
720 EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),
721 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
722 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
723 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
724 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
725};
726
727/*
728 * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
729 * two gpio/pin-mux/pinconfig controllers.
730 */
1bf00d7a 731const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
d97f5b98
TF		 732 {
733 /* pin-controller instance 0 data */
734 .pin_banks = exynos3250_pin_banks0,
735 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0),
d97f5b98
TF		 736 .eint_gpio_init = exynos_eint_gpio_init,
737 .suspend = exynos_pinctrl_suspend,
738 .resume = exynos_pinctrl_resume,
d97f5b98
TF		 739 }, {
740 /* pin-controller instance 1 data */
741 .pin_banks = exynos3250_pin_banks1,
742 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1),
d97f5b98
TF		 743 .eint_gpio_init = exynos_eint_gpio_init,
744 .eint_wkup_init = exynos_eint_wkup_init,
745 .suspend = exynos_pinctrl_suspend,
746 .resume = exynos_pinctrl_resume,
d97f5b98
TF		 747 },
748};
749
43b169db 750/* pin banks of exynos4210 pin-controller 0 */
8100cf47 751static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = {
1b6056d6
TF		 752 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
753 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
754 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
755 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
756 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
757 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
758 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
759 EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
760 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
761 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
762 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
763 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
764 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
765 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
766 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
767 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
43b169db
TA		 768};
769
770/* pin banks of exynos4210 pin-controller 1 */
8100cf47 771static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = {
1b6056d6
TF		 772 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
773 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
774 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
775 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
776 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
777 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
778 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
779 EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
780 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
40ba6227
TF		 781 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
782 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
783 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
784 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
785 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
786 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
787 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
a04b07c0
TF		 788 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
789 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
790 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
791 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
43b169db
TA		 792};
793
794/* pin banks of exynos4210 pin-controller 2 */
8100cf47 795static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = {
40ba6227 796 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
43b169db
TA		 797};
798
799/*
800 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
801 * three gpio/pin-mux/pinconfig controllers.
802 */
1bf00d7a 803const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {
43b169db
TA		 804 {
805 /* pin-controller instance 0 data */
806 .pin_banks = exynos4210_pin_banks0,
807 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
43b169db 808 .eint_gpio_init = exynos_eint_gpio_init,
7ccbc60c
TF		 809 .suspend = exynos_pinctrl_suspend,
810 .resume = exynos_pinctrl_resume,
43b169db
TA		 811 }, {
812 /* pin-controller instance 1 data */
813 .pin_banks = exynos4210_pin_banks1,
814 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
43b169db
TA		 815 .eint_gpio_init = exynos_eint_gpio_init,
816 .eint_wkup_init = exynos_eint_wkup_init,
7ccbc60c
TF		 817 .suspend = exynos_pinctrl_suspend,
818 .resume = exynos_pinctrl_resume,
43b169db
TA		 819 }, {
820 /* pin-controller instance 2 data */
821 .pin_banks = exynos4210_pin_banks2,
822 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),
43b169db
TA		 823 },
824};
6edc794a
TF		 825
826/* pin banks of exynos4x12 pin-controller 0 */
8100cf47 827static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = {
6edc794a
TF		 828 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
829 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
830 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
831 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
832 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
833 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
834 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
835 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
836 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
837 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
838 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
839 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
840 EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
841};
842
843/* pin banks of exynos4x12 pin-controller 1 */
8100cf47 844static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = {
6edc794a
TF		 845 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
846 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
847 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
848 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
849 EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
850 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
851 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
852 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
853 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
854 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
855 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
856 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
857 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
858 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
859 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
860 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
861 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
862 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
863 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
864 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
865 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
866 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
867 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
868};
869
870/* pin banks of exynos4x12 pin-controller 2 */
8100cf47 871static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = {
6edc794a
TF		 872 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
873};
874
875/* pin banks of exynos4x12 pin-controller 3 */
8100cf47 876static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = {
6edc794a
TF		 877 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
878 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
879 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
880 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
881 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
882};
883
884/*
885 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
886 * four gpio/pin-mux/pinconfig controllers.
887 */
1bf00d7a 888const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {
6edc794a
TF		 889 {
890 /* pin-controller instance 0 data */
891 .pin_banks = exynos4x12_pin_banks0,
892 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0),
6edc794a 893 .eint_gpio_init = exynos_eint_gpio_init,
7ccbc60c
TF		 894 .suspend = exynos_pinctrl_suspend,
895 .resume = exynos_pinctrl_resume,
6edc794a
TF		 896 }, {
897 /* pin-controller instance 1 data */
898 .pin_banks = exynos4x12_pin_banks1,
899 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1),
6edc794a
TF		 900 .eint_gpio_init = exynos_eint_gpio_init,
901 .eint_wkup_init = exynos_eint_wkup_init,
7ccbc60c
TF		 902 .suspend = exynos_pinctrl_suspend,
903 .resume = exynos_pinctrl_resume,
6edc794a
TF		 904 }, {
905 /* pin-controller instance 2 data */
906 .pin_banks = exynos4x12_pin_banks2,
907 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2),
6edc794a 908 .eint_gpio_init = exynos_eint_gpio_init,
7ccbc60c
TF		 909 .suspend = exynos_pinctrl_suspend,
910 .resume = exynos_pinctrl_resume,
6edc794a
TF		 911 }, {
912 /* pin-controller instance 3 data */
913 .pin_banks = exynos4x12_pin_banks3,
914 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3),
6edc794a 915 .eint_gpio_init = exynos_eint_gpio_init,
7ccbc60c
TF		 916 .suspend = exynos_pinctrl_suspend,
917 .resume = exynos_pinctrl_resume,
6edc794a
TF		 918 },
919};
f67faf48
TA		 920
921/* pin banks of exynos5250 pin-controller 0 */
8100cf47 922static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = {
f67faf48
TA		 923 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
924 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
925 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
926 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
927 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
928 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
929 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
930 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
931 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
932 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
933 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
934 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
935 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
936 EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
937 EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
938 EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
939 EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
940 EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
941 EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
942 EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
943 EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
944 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
945 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
946 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
947 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
948};
949
950/* pin banks of exynos5250 pin-controller 1 */
8100cf47 951static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = {
f67faf48
TA		 952 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
953 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
954 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
955 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
956 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
957 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
958 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
959 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
960 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
961};
962
963/* pin banks of exynos5250 pin-controller 2 */
8100cf47 964static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = {
f67faf48
TA		 965 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
966 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
967 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
968 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
969 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
970};
971
972/* pin banks of exynos5250 pin-controller 3 */
8100cf47 973static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = {
f67faf48
TA		 974 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
975};
976
977/*
978 * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
979 * four gpio/pin-mux/pinconfig controllers.
980 */
1bf00d7a 981const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {
f67faf48
TA		 982 {
983 /* pin-controller instance 0 data */
984 .pin_banks = exynos5250_pin_banks0,
985 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0),
f67faf48
TA		 986 .eint_gpio_init = exynos_eint_gpio_init,
987 .eint_wkup_init = exynos_eint_wkup_init,
7ccbc60c
TF		 988 .suspend = exynos_pinctrl_suspend,
989 .resume = exynos_pinctrl_resume,
f67faf48
TA		 990 }, {
991 /* pin-controller instance 1 data */
992 .pin_banks = exynos5250_pin_banks1,
993 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1),
f67faf48 994 .eint_gpio_init = exynos_eint_gpio_init,
7ccbc60c
TF		 995 .suspend = exynos_pinctrl_suspend,
996 .resume = exynos_pinctrl_resume,
f67faf48
TA		 997 }, {
998 /* pin-controller instance 2 data */
999 .pin_banks = exynos5250_pin_banks2,
1000 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2),
f67faf48 1001 .eint_gpio_init = exynos_eint_gpio_init,
7ccbc60c
TF		 1002 .suspend = exynos_pinctrl_suspend,
1003 .resume = exynos_pinctrl_resume,
f67faf48
TA		 1004 }, {
1005 /* pin-controller instance 3 data */
1006 .pin_banks = exynos5250_pin_banks3,
1007 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3),
f67faf48 1008 .eint_gpio_init = exynos_eint_gpio_init,
7ccbc60c
TF		 1009 .suspend = exynos_pinctrl_suspend,
1010 .resume = exynos_pinctrl_resume,
f67faf48
TA		 1011 },
1012};
983dbeb3 1013
9a8b6079 1014/* pin banks of exynos5260 pin-controller 0 */
8100cf47 1015static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = {
9a8b6079
YGJ		 1016 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
1017 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
1018 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1019 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1020 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
1021 EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14),
1022 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18),
1023 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c),
1024 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
1025 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
1026 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
1027 EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
1028 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
1029 EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34),
1030 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
1031 EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c),
1032 EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
1033 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
1034 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
1035 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
1036 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
1037};
1038
1039/* pin banks of exynos5260 pin-controller 1 */
8100cf47 1040static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = {
9a8b6079
YGJ		 1041 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
1042 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
1043 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
1044 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
1045 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
1046};
1047
1048/* pin banks of exynos5260 pin-controller 2 */
8100cf47 1049static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = {
9a8b6079
YGJ		 1050 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1051 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1052};
1053
1054/*
1055 * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
1056 * three gpio/pin-mux/pinconfig controllers.
1057 */
1bf00d7a 1058const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
9a8b6079
YGJ		 1059 {
1060 /* pin-controller instance 0 data */
1061 .pin_banks = exynos5260_pin_banks0,
1062 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
9a8b6079
YGJ		 1063 .eint_gpio_init = exynos_eint_gpio_init,
1064 .eint_wkup_init = exynos_eint_wkup_init,
9a8b6079
YGJ		 1065 }, {
1066 /* pin-controller instance 1 data */
1067 .pin_banks = exynos5260_pin_banks1,
1068 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
9a8b6079 1069 .eint_gpio_init = exynos_eint_gpio_init,
9a8b6079
YGJ		 1070 }, {
1071 /* pin-controller instance 2 data */
1072 .pin_banks = exynos5260_pin_banks2,
1073 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2),
9a8b6079 1074 .eint_gpio_init = exynos_eint_gpio_init,
9a8b6079
YGJ		 1075 },
1076};
1077
983dbeb3 1078/* pin banks of exynos5420 pin-controller 0 */
8100cf47 1079static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = {
983dbeb3
LKA		 1080 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
1081 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
1082 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
1083 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
1084 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
1085};
1086
1087/* pin banks of exynos5420 pin-controller 1 */
8100cf47 1088static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = {
983dbeb3
LKA		 1089 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
1090 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
1091 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
1092 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
1093 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
1094 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
1095 EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
1096 EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
1097 EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
1098 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
1099 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
1100 EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
1101 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
1102};
1103
1104/* pin banks of exynos5420 pin-controller 2 */
8100cf47 1105static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = {
983dbeb3
LKA		 1106 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
1107 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
1108 EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
1109 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
1110 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
1111 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
1112 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
1113 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
1114};
1115
1116/* pin banks of exynos5420 pin-controller 3 */
8100cf47 1117static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = {
983dbeb3
LKA		 1118 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
1119 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
1120 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1121 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1122 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
1123 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
1124 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
1125 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
1126 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
1127};
1128
1129/* pin banks of exynos5420 pin-controller 4 */
8100cf47 1130static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = {
983dbeb3
LKA		 1131 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
1132};
1133
1134/*
1135 * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
1136 * four gpio/pin-mux/pinconfig controllers.
1137 */
1bf00d7a 1138const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
983dbeb3
LKA		 1139 {
1140 /* pin-controller instance 0 data */
1141 .pin_banks = exynos5420_pin_banks0,
1142 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
983dbeb3
LKA		 1143 .eint_gpio_init = exynos_eint_gpio_init,
1144 .eint_wkup_init = exynos_eint_wkup_init,
983dbeb3
LKA		 1145 }, {
1146 /* pin-controller instance 1 data */
1147 .pin_banks = exynos5420_pin_banks1,
1148 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),
983dbeb3 1149 .eint_gpio_init = exynos_eint_gpio_init,
983dbeb3
LKA		 1150 }, {
1151 /* pin-controller instance 2 data */
1152 .pin_banks = exynos5420_pin_banks2,
1153 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2),
983dbeb3 1154 .eint_gpio_init = exynos_eint_gpio_init,
983dbeb3
LKA		 1155 }, {
1156 /* pin-controller instance 3 data */
1157 .pin_banks = exynos5420_pin_banks3,
1158 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3),
983dbeb3 1159 .eint_gpio_init = exynos_eint_gpio_init,
983dbeb3
LKA		 1160 }, {
1161 /* pin-controller instance 4 data */
1162 .pin_banks = exynos5420_pin_banks4,
1163 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4),
983dbeb3 1164 .eint_gpio_init = exynos_eint_gpio_init,
983dbeb3
LKA		 1165 },
1166};
50cea0cf
NKC		 1167
1168/* pin banks of exynos7 pin-controller - ALIVE */
1169static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = {
1170 EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
1171 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
1172 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
1173 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
1174};
1175
1176/* pin banks of exynos7 pin-controller - BUS0 */
1177static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = {
1178 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
1179 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04),
1180 EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08),
1181 EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c),
1182 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),
1183 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
1184 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
1185 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c),
1186 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20),
1187 EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24),
1188 EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28),
1189 EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c),
1190 EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30),
1191 EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),
1192 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38),
1193};
1194
1195/* pin banks of exynos7 pin-controller - NFC */
1196static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = {
1197 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
1198};
1199
1200/* pin banks of exynos7 pin-controller - TOUCH */
1201static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = {
1202 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
1203};
1204
1205/* pin banks of exynos7 pin-controller - FF */
1206static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = {
1207 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00),
1208};
1209
1210/* pin banks of exynos7 pin-controller - ESE */
1211static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = {
1212 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00),
1213};
1214
1215/* pin banks of exynos7 pin-controller - FSYS0 */
1216static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = {
1217 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00),
1218};
1219
1220/* pin banks of exynos7 pin-controller - FSYS1 */
1221static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
1222 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00),
1223 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
1224 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08),
1225 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
1226};
1227
1228const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
1229 {
1230 /* pin-controller instance 0 Alive data */
1231 .pin_banks = exynos7_pin_banks0,
1232 .nr_banks = ARRAY_SIZE(exynos7_pin_banks0),
1233 .eint_gpio_init = exynos_eint_gpio_init,
1234 .eint_wkup_init = exynos_eint_wkup_init,
1235 }, {
1236 /* pin-controller instance 1 BUS0 data */
1237 .pin_banks = exynos7_pin_banks1,
1238 .nr_banks = ARRAY_SIZE(exynos7_pin_banks1),
1239 .eint_gpio_init = exynos_eint_gpio_init,
1240 }, {
1241 /* pin-controller instance 2 NFC data */
1242 .pin_banks = exynos7_pin_banks2,
1243 .nr_banks = ARRAY_SIZE(exynos7_pin_banks2),
1244 .eint_gpio_init = exynos_eint_gpio_init,
1245 }, {
1246 /* pin-controller instance 3 TOUCH data */
1247 .pin_banks = exynos7_pin_banks3,
1248 .nr_banks = ARRAY_SIZE(exynos7_pin_banks3),
1249 .eint_gpio_init = exynos_eint_gpio_init,
1250 }, {
1251 /* pin-controller instance 4 FF data */
1252 .pin_banks = exynos7_pin_banks4,
1253 .nr_banks = ARRAY_SIZE(exynos7_pin_banks4),
1254 .eint_gpio_init = exynos_eint_gpio_init,
1255 }, {
1256 /* pin-controller instance 5 ESE data */
1257 .pin_banks = exynos7_pin_banks5,
1258 .nr_banks = ARRAY_SIZE(exynos7_pin_banks5),
1259 .eint_gpio_init = exynos_eint_gpio_init,
1260 }, {
1261 /* pin-controller instance 6 FSYS0 data */
1262 .pin_banks = exynos7_pin_banks6,
1263 .nr_banks = ARRAY_SIZE(exynos7_pin_banks6),
1264 .eint_gpio_init = exynos_eint_gpio_init,
1265 }, {
1266 /* pin-controller instance 7 FSYS1 data */
1267 .pin_banks = exynos7_pin_banks7,
1268 .nr_banks = ARRAY_SIZE(exynos7_pin_banks7),
1269 .eint_gpio_init = exynos_eint_gpio_init,
1270 },
1271};
Linux kernel - Deliverables
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