[deliverable/linux.git] / drivers / pinctrl / sh-pfc / core.c

/*
 * SuperH Pin Function Controller support.
 *
 * Copyright (C) 2008 Magnus Damm
 * Copyright (C) 2009 - 2012 Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#define DRV_NAME "sh-pfc"

#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include "core.h"

static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev)
{
	struct resource *res;
	int k;

	if (pdev->num_resources == 0)
		return -EINVAL;

	pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
				   sizeof(*pfc->window), GFP_NOWAIT);
	if (!pfc->window)
		return -ENOMEM;

	pfc->num_windows = pdev->num_resources;

	for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) {
		WARN_ON(resource_type(res) != IORESOURCE_MEM);
		pfc->window[k].phys = res->start;
		pfc->window[k].size = resource_size(res);
		pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start,
							   resource_size(res));
		if (!pfc->window[k].virt)
			return -ENOMEM;
	}

	return 0;
}

static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
					 unsigned long address)
{
	struct sh_pfc_window *window;
	unsigned int i;

	/* scan through physical windows and convert address */
	for (i = 0; i < pfc->num_windows; i++) {
		window = pfc->window + i;

		if (address < window->phys)
			continue;

		if (address >= (window->phys + window->size))
			continue;

		return window->virt + (address - window->phys);
	}

	BUG();
	return NULL;
}

int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
{
	unsigned int offset;
	unsigned int i;

	for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
		const struct sh_pfc_pin_range *range = &pfc->ranges[i];

		if (pin <= range->end)
			return pin >= range->start
			     ? offset + pin - range->start : -1;

		offset += range->end - range->start + 1;
	}

	return -EINVAL;
}

static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
{
	if (enum_id < r->begin)
		return 0;

	if (enum_id > r->end)
		return 0;

	return 1;
}

unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
				  unsigned long reg_width)
{
	switch (reg_width) {
	case 8:
		return ioread8(mapped_reg);
	case 16:
		return ioread16(mapped_reg);
	case 32:
		return ioread32(mapped_reg);
	}

	BUG();
	return 0;
}

void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
			  unsigned long data)
{
	switch (reg_width) {
	case 8:
		iowrite8(data, mapped_reg);
		return;
	case 16:
		iowrite16(data, mapped_reg);
		return;
	case 32:
		iowrite32(data, mapped_reg);
		return;
	}

	BUG();
}

static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
				     const struct pinmux_cfg_reg *crp,
				     unsigned long in_pos,
				     void __iomem **mapped_regp,
				     unsigned long *maskp,
				     unsigned long *posp)
{
	int k;

	*mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);

	if (crp->field_width) {
		*maskp = (1 << crp->field_width) - 1;
		*posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
	} else {
		*maskp = (1 << crp->var_field_width[in_pos]) - 1;
		*posp = crp->reg_width;
		for (k = 0; k <= in_pos; k++)
			*posp -= crp->var_field_width[k];
	}
}

static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
				    const struct pinmux_cfg_reg *crp,
				    unsigned long field, unsigned long value)
{
	void __iomem *mapped_reg;
	unsigned long mask, pos, data;

	sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);

	dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, "
		"r_width = %ld, f_width = %ld\n",
		crp->reg, value, field, crp->reg_width, crp->field_width);

	mask = ~(mask << pos);
	value = value << pos;

	data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
	data &= mask;
	data |= value;

	if (pfc->info->unlock_reg)
		sh_pfc_write_raw_reg(
			sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
			~data);

	sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
}

static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
				 const struct pinmux_cfg_reg **crp, int *fieldp,
				 int *valuep)
{
	const struct pinmux_cfg_reg *config_reg;
	unsigned long r_width, f_width, curr_width, ncomb;
	int k, m, n, pos, bit_pos;

	k = 0;
	while (1) {
		config_reg = pfc->info->cfg_regs + k;

		r_width = config_reg->reg_width;
		f_width = config_reg->field_width;

		if (!r_width)
			break;

		pos = 0;
		m = 0;
		for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
			if (f_width)
				curr_width = f_width;
			else
				curr_width = config_reg->var_field_width[m];

			ncomb = 1 << curr_width;
			for (n = 0; n < ncomb; n++) {
				if (config_reg->enum_ids[pos + n] == enum_id) {
					*crp = config_reg;
					*fieldp = m;
					*valuep = n;
					return 0;
				}
			}
			pos += ncomb;
			m++;
		}
		k++;
	}

	return -EINVAL;
}

static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
			      u16 *enum_idp)
{
	const u16 *data = pfc->info->gpio_data;
	int k;

	if (pos) {
		*enum_idp = data[pos + 1];
		return pos + 1;
	}

	for (k = 0; k < pfc->info->gpio_data_size; k++) {
		if (data[k] == mark) {
			*enum_idp = data[k + 1];
			return k + 1;
		}
	}

	dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
		mark);
	return -EINVAL;
}

int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
{
	const struct pinmux_cfg_reg *cr = NULL;
	u16 enum_id;
	const struct pinmux_range *range;
	int in_range, pos, field, value;
	int ret;

	switch (pinmux_type) {
	case PINMUX_TYPE_GPIO:
	case PINMUX_TYPE_FUNCTION:
		range = NULL;
		break;

	case PINMUX_TYPE_OUTPUT:
		range = &pfc->info->output;
		break;

	case PINMUX_TYPE_INPUT:
		range = &pfc->info->input;
		break;

	default:
		return -EINVAL;
	}

	pos = 0;
	enum_id = 0;
	field = 0;
	value = 0;

	/* Iterate over all the configuration fields we need to update. */
	while (1) {
		pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
		if (pos < 0)
			return pos;

		if (!enum_id)
			break;

		/* Check if the configuration field selects a function. If it
		 * doesn't, skip the field if it's not applicable to the
		 * requested pinmux type.
		 */
		in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
		if (!in_range) {
			if (pinmux_type == PINMUX_TYPE_FUNCTION) {
				/* Functions are allowed to modify all
				 * fields.
				 */
				in_range = 1;
			} else if (pinmux_type != PINMUX_TYPE_GPIO) {
				/* Input/output types can only modify fields
				 * that correspond to their respective ranges.
				 */
				in_range = sh_pfc_enum_in_range(enum_id, range);

				/*
				 * special case pass through for fixed
				 * input-only or output-only pins without
				 * function enum register association.
				 */
				if (in_range && enum_id == range->force)
					continue;
			}
			/* GPIOs are only allowed to modify function fields. */
		}

		if (!in_range)
			continue;

		ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
		if (ret < 0)
			return ret;

		sh_pfc_write_config_reg(pfc, cr, field, value);
	}

	return 0;
}

static int sh_pfc_init_ranges(struct sh_pfc *pfc)
{
	struct sh_pfc_pin_range *range;
	unsigned int nr_ranges;
	unsigned int i;

	if (pfc->info->pins[0].pin == (u16)-1) {
		/* Pin number -1 denotes that the SoC doesn't report pin numbers
		 * in its pin arrays yet. Consider the pin numbers range as
		 * continuous and allocate a single range.
		 */
		pfc->nr_ranges = 1;
		pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
					   GFP_KERNEL);
		if (pfc->ranges == NULL)
			return -ENOMEM;

		pfc->ranges->start = 0;
		pfc->ranges->end = pfc->info->nr_pins - 1;
		pfc->nr_gpio_pins = pfc->info->nr_pins;

		return 0;
	}

	/* Count, allocate and fill the ranges. The PFC SoC data pins array must
	 * be sorted by pin numbers, and pins without a GPIO port must come
	 * last.
	 */
	for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
		if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
			nr_ranges++;
	}

	pfc->nr_ranges = nr_ranges;
	pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges,
				   GFP_KERNEL);
	if (pfc->ranges == NULL)
		return -ENOMEM;

	range = pfc->ranges;
	range->start = pfc->info->pins[0].pin;

	for (i = 1; i < pfc->info->nr_pins; ++i) {
		if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
			continue;

		range->end = pfc->info->pins[i-1].pin;
		if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
			pfc->nr_gpio_pins = range->end + 1;

		range++;
		range->start = pfc->info->pins[i].pin;
	}

	range->end = pfc->info->pins[i-1].pin;
	if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
		pfc->nr_gpio_pins = range->end + 1;

	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id sh_pfc_of_table[] = {
#ifdef CONFIG_PINCTRL_PFC_R8A73A4
	{
		.compatible = "renesas,pfc-r8a73a4",
		.data = &r8a73a4_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7740
	{
		.compatible = "renesas,pfc-r8a7740",
		.data = &r8a7740_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7778
	{
		.compatible = "renesas,pfc-r8a7778",
		.data = &r8a7778_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7779
	{
		.compatible = "renesas,pfc-r8a7779",
		.data = &r8a7779_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7790
	{
		.compatible = "renesas,pfc-r8a7790",
		.data = &r8a7790_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7372
	{
		.compatible = "renesas,pfc-sh7372",
		.data = &sh7372_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_SH73A0
	{
		.compatible = "renesas,pfc-sh73a0",
		.data = &sh73a0_pinmux_info,
	},
#endif
	{ },
};
MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
#endif

static int sh_pfc_probe(struct platform_device *pdev)
{
	const struct platform_device_id *platid = platform_get_device_id(pdev);
#ifdef CONFIG_OF
	struct device_node *np = pdev->dev.of_node;
#endif
	const struct sh_pfc_soc_info *info;
	struct sh_pfc *pfc;
	int ret;

#ifdef CONFIG_OF
	if (np)
		info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
	else
#endif
		info = platid ? (const void *)platid->driver_data : NULL;

	if (info == NULL)
		return -ENODEV;

	pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
	if (pfc == NULL)
		return -ENOMEM;

	pfc->info = info;
	pfc->dev = &pdev->dev;

	ret = sh_pfc_ioremap(pfc, pdev);
	if (unlikely(ret < 0))
		return ret;

	spin_lock_init(&pfc->lock);

	if (info->ops && info->ops->init) {
		ret = info->ops->init(pfc);
		if (ret < 0)
			return ret;
	}

	pinctrl_provide_dummies();

	ret = sh_pfc_init_ranges(pfc);
	if (ret < 0)
		return ret;

	/*
	 * Initialize pinctrl bindings first
	 */
	ret = sh_pfc_register_pinctrl(pfc);
	if (unlikely(ret != 0))
		goto error;

#ifdef CONFIG_GPIO_SH_PFC
	/*
	 * Then the GPIO chip
	 */
	ret = sh_pfc_register_gpiochip(pfc);
	if (unlikely(ret != 0)) {
		/*
		 * If the GPIO chip fails to come up we still leave the
		 * PFC state as it is, given that there are already
		 * extant users of it that have succeeded by this point.
		 */
		dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
	}
#endif

	platform_set_drvdata(pdev, pfc);

	dev_info(pfc->dev, "%s support registered\n", info->name);

	return 0;

error:
	if (info->ops && info->ops->exit)
		info->ops->exit(pfc);
	return ret;
}

static int sh_pfc_remove(struct platform_device *pdev)
{
	struct sh_pfc *pfc = platform_get_drvdata(pdev);

#ifdef CONFIG_GPIO_SH_PFC
	sh_pfc_unregister_gpiochip(pfc);
#endif
	sh_pfc_unregister_pinctrl(pfc);

	if (pfc->info->ops && pfc->info->ops->exit)
		pfc->info->ops->exit(pfc);

	return 0;
}

static const struct platform_device_id sh_pfc_id_table[] = {
#ifdef CONFIG_PINCTRL_PFC_R8A73A4
	{ "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7740
	{ "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7778
	{ "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7779
	{ "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7790
	{ "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7203
	{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7264
	{ "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7269
	{ "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7372
	{ "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH73A0
	{ "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7720
	{ "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7722
	{ "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7723
	{ "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7724
	{ "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7734
	{ "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7757
	{ "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7785
	{ "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7786
	{ "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SHX3
	{ "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
#endif
	{ "sh-pfc", 0 },
	{ },
};
MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);

static struct platform_driver sh_pfc_driver = {
	.probe		= sh_pfc_probe,
	.remove		= sh_pfc_remove,
	.id_table	= sh_pfc_id_table,
	.driver		= {
		.name	= DRV_NAME,
		.owner	= THIS_MODULE,
		.of_match_table = of_match_ptr(sh_pfc_of_table),
	},
};

static int __init sh_pfc_init(void)
{
	return platform_driver_register(&sh_pfc_driver);
}
postcore_initcall(sh_pfc_init);

static void __exit sh_pfc_exit(void)
{
	platform_driver_unregister(&sh_pfc_driver);
}
module_exit(sh_pfc_exit);

MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2967dab1	1	/*
b3c185a7	2	* SuperH Pin Function Controller support.
2967dab1 MD	3	*
2967dab1 MD	4	* Copyright (C) 2008 Magnus Damm
b3c185a7	5	* Copyright (C) 2009 - 2012 Paul Mundt
2967dab1 MD	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file "COPYING" in the main directory of this archive
	9	* for more details.
	10	*/
c6193eac LP	11
c6193eac LP	12	#define DRV_NAME "sh-pfc"
b72421d8	13
90efde22	14	#include <linux/bitops.h>
2967dab1	15	#include <linux/err.h>
90efde22	16	#include <linux/errno.h>
2967dab1	17	#include <linux/io.h>
b0e10211	18	#include <linux/ioport.h>
90efde22 LP	19	#include <linux/kernel.h>
90efde22 LP	20	#include <linux/module.h>
fe1c9a82 LP	21	#include <linux/of.h>
fe1c9a82 LP	22	#include <linux/of_device.h>
ca5481c6	23	#include <linux/pinctrl/machine.h>
c6193eac	24	#include <linux/platform_device.h>
90efde22	25	#include <linux/slab.h>
b0e10211	26
f9165132 LP	27	#include "core.h"
f9165132 LP	28
973931ae	29	static int sh_pfc_ioremap(struct sh_pfc pfc, struct platform_device pdev)
b0e10211 MD	30	{
	31	struct resource *res;
	32	int k;
	33
bee9f22b LP	34	if (pdev->num_resources == 0)
bee9f22b LP	35	return -EINVAL;
b0e10211	36
56dc04af	37	pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
1724acfd	38	sizeof(*pfc->window), GFP_NOWAIT);
b3c185a7	39	if (!pfc->window)
1724acfd	40	return -ENOMEM;
b0e10211	41
56dc04af	42	pfc->num_windows = pdev->num_resources;
973931ae	43
56dc04af	44	for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) {
b0e10211	45	WARN_ON(resource_type(res) != IORESOURCE_MEM);
b3c185a7 PM	46	pfc->window[k].phys = res->start;
b3c185a7 PM	47	pfc->window[k].size = resource_size(res);
c9fa88e2 LP	48	pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start,
	49	resource_size(res));
	50	if (!pfc->window[k].virt)
1724acfd	51	return -ENOMEM;
b0e10211 MD	52	}
	53
	54	return 0;
b0e10211 MD	55	}
b0e10211 MD	56
e51d5343 LP	57	static void __iomem sh_pfc_phys_to_virt(struct sh_pfc pfc,
e51d5343 LP	58	unsigned long address)
b0e10211	59	{
4aeacd5b	60	struct sh_pfc_window *window;
bee9f22b	61	unsigned int i;
b0e10211 MD	62
b0e10211 MD	63	/* scan through physical windows and convert address */
bee9f22b LP	64	for (i = 0; i < pfc->num_windows; i++) {
bee9f22b LP	65	window = pfc->window + i;
b0e10211 MD	66
	67	if (address < window->phys)
	68	continue;
	69
	70	if (address >= (window->phys + window->size))
	71	continue;
	72
	73	return window->virt + (address - window->phys);
	74	}
	75
bee9f22b	76	BUG();
1960d580	77	return NULL;
b0e10211	78	}
2967dab1	79
1a0039dc	80	int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
934cb02b	81	{
63d57383 LP	82	unsigned int offset;
	83	unsigned int i;
	84
acac8ed5 LP	85	for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
acac8ed5 LP	86	const struct sh_pfc_pin_range *range = &pfc->ranges[i];
63d57383 LP	87
63d57383 LP	88	if (pin <= range->end)
acac8ed5 LP	89	return pin >= range->start
acac8ed5 LP	90	? offset + pin - range->start : -1;
63d57383	91
acac8ed5	92	offset += range->end - range->start + 1;
63d57383 LP	93	}
63d57383 LP	94
b705c054	95	return -EINVAL;
934cb02b LP	96	}
934cb02b LP	97
533743dc	98	static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
2967dab1 MD	99	{
	100	if (enum_id < r->begin)
	101	return 0;
	102
	103	if (enum_id > r->end)
	104	return 0;
	105
	106	return 1;
	107	}
	108
41f1219f LP	109	unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
41f1219f LP	110	unsigned long reg_width)
3292094e MD	111	{
	112	switch (reg_width) {
	113	case 8:
b0e10211	114	return ioread8(mapped_reg);
3292094e	115	case 16:
b0e10211	116	return ioread16(mapped_reg);
3292094e	117	case 32:
b0e10211	118	return ioread32(mapped_reg);
3292094e MD	119	}
	120
	121	BUG();
	122	return 0;
	123	}
	124
41f1219f LP	125	void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
41f1219f LP	126	unsigned long data)
3292094e MD	127	{
	128	switch (reg_width) {
	129	case 8:
b0e10211	130	iowrite8(data, mapped_reg);
3292094e MD	131	return;
3292094e MD	132	case 16:
b0e10211	133	iowrite16(data, mapped_reg);
3292094e MD	134	return;
3292094e MD	135	case 32:
b0e10211	136	iowrite32(data, mapped_reg);
3292094e MD	137	return;
	138	}
	139
	140	BUG();
	141	}
	142
4aeacd5b	143	static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
cd3c1bee	144	const struct pinmux_cfg_reg *crp,
4aeacd5b LP	145	unsigned long in_pos,
	146	void __iomem **mapped_regp,
	147	unsigned long *maskp,
	148	unsigned long *posp)
2967dab1	149	{
f78a26f5 MD	150	int k;
f78a26f5 MD	151
4aeacd5b	152	*mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
2967dab1	153
f78a26f5 MD	154	if (crp->field_width) {
	155	*maskp = (1 << crp->field_width) - 1;
	156	posp = crp->reg_width - ((in_pos + 1) crp->field_width);
	157	} else {
	158	*maskp = (1 << crp->var_field_width[in_pos]) - 1;
	159	*posp = crp->reg_width;
	160	for (k = 0; k <= in_pos; k++)
	161	*posp -= crp->var_field_width[k];
	162	}
18925e11 MD	163	}
18925e11 MD	164
4aeacd5b	165	static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
cd3c1bee	166	const struct pinmux_cfg_reg *crp,
4aeacd5b	167	unsigned long field, unsigned long value)
0fc64cc0	168	{
18925e11	169	void __iomem *mapped_reg;
e499ada8	170	unsigned long mask, pos, data;
0fc64cc0	171
4aeacd5b	172	sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
2967dab1	173
9a643c9a LP	174	dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, "
	175	"r_width = %ld, f_width = %ld\n",
	176	crp->reg, value, field, crp->reg_width, crp->field_width);
0fc64cc0 MD	177
	178	mask = ~(mask << pos);
	179	value = value << pos;
2967dab1	180
4aeacd5b	181	data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
e499ada8 MD	182	data &= mask;
	183	data \|= value;
	184
19bb7fe3	185	if (pfc->info->unlock_reg)
4aeacd5b	186	sh_pfc_write_raw_reg(
19bb7fe3	187	sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
4aeacd5b	188	~data);
e499ada8	189
4aeacd5b	190	sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
2967dab1 MD	191	}
2967dab1 MD	192
533743dc	193	static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
cd3c1bee	194	const struct pinmux_cfg_reg *crp, int fieldp,
861601de	195	int *valuep)
2967dab1	196	{
cd3c1bee	197	const struct pinmux_cfg_reg *config_reg;
f78a26f5 MD	198	unsigned long r_width, f_width, curr_width, ncomb;
f78a26f5 MD	199	int k, m, n, pos, bit_pos;
2967dab1 MD	200
	201	k = 0;
	202	while (1) {
19bb7fe3	203	config_reg = pfc->info->cfg_regs + k;
2967dab1 MD	204
	205	r_width = config_reg->reg_width;
	206	f_width = config_reg->field_width;
	207
	208	if (!r_width)
	209	break;
f78a26f5 MD	210
	211	pos = 0;
	212	m = 0;
	213	for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
	214	if (f_width)
	215	curr_width = f_width;
	216	else
	217	curr_width = config_reg->var_field_width[m];
	218
	219	ncomb = 1 << curr_width;
	220	for (n = 0; n < ncomb; n++) {
	221	if (config_reg->enum_ids[pos + n] == enum_id) {
	222	*crp = config_reg;
	223	*fieldp = m;
	224	*valuep = n;
f78a26f5 MD	225	return 0;
f78a26f5 MD	226	}
2967dab1	227	}
f78a26f5 MD	228	pos += ncomb;
f78a26f5 MD	229	m++;
2967dab1 MD	230	}
	231	k++;
	232	}
	233
b705c054	234	return -EINVAL;
2967dab1 MD	235	}
2967dab1 MD	236
533743dc LP	237	static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
533743dc LP	238	u16 *enum_idp)
2967dab1	239	{
533743dc	240	const u16 *data = pfc->info->gpio_data;
2967dab1 MD	241	int k;
2967dab1 MD	242
2967dab1 MD	243	if (pos) {
	244	*enum_idp = data[pos + 1];
	245	return pos + 1;
	246	}
	247
19bb7fe3	248	for (k = 0; k < pfc->info->gpio_data_size; k++) {
a68fdca9	249	if (data[k] == mark) {
2967dab1 MD	250	*enum_idp = data[k + 1];
	251	return k + 1;
	252	}
	253	}
	254
9a643c9a LP	255	dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
9a643c9a LP	256	mark);
b705c054	257	return -EINVAL;
2967dab1 MD	258	}
2967dab1 MD	259
861601de	260	int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
2967dab1	261	{
cd3c1bee	262	const struct pinmux_cfg_reg *cr = NULL;
533743dc	263	u16 enum_id;
cd3c1bee	264	const struct pinmux_range *range;
ad4a07ff	265	int in_range, pos, field, value;
b705c054	266	int ret;
2967dab1 MD	267
2967dab1 MD	268	switch (pinmux_type) {
e3c47051	269	case PINMUX_TYPE_GPIO:
2967dab1 MD	270	case PINMUX_TYPE_FUNCTION:
	271	range = NULL;
	272	break;
	273
	274	case PINMUX_TYPE_OUTPUT:
19bb7fe3	275	range = &pfc->info->output;
2967dab1 MD	276	break;
	277
	278	case PINMUX_TYPE_INPUT:
19bb7fe3	279	range = &pfc->info->input;
2967dab1 MD	280	break;
2967dab1 MD	281
2967dab1	282	default:
b705c054	283	return -EINVAL;
2967dab1 MD	284	}
	285
	286	pos = 0;
	287	enum_id = 0;
ad4a07ff MD	288	field = 0;
ad4a07ff MD	289	value = 0;
e3c47051 LP	290
e3c47051 LP	291	/* Iterate over all the configuration fields we need to update. */
2967dab1	292	while (1) {
a68fdca9	293	pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
b705c054 LP	294	if (pos < 0)
b705c054 LP	295	return pos;
2967dab1 MD	296
	297	if (!enum_id)
	298	break;
	299
e3c47051 LP	300	/* Check if the configuration field selects a function. If it
	301	* doesn't, skip the field if it's not applicable to the
	302	* requested pinmux type.
	303	*/
19bb7fe3	304	in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
50dd3145	305	if (!in_range) {
e3c47051 LP	306	if (pinmux_type == PINMUX_TYPE_FUNCTION) {
	307	/* Functions are allowed to modify all
	308	* fields.
	309	*/
	310	in_range = 1;
	311	} else if (pinmux_type != PINMUX_TYPE_GPIO) {
	312	/* Input/output types can only modify fields
	313	* that correspond to their respective ranges.
50dd3145	314	*/
4aeacd5b	315	in_range = sh_pfc_enum_in_range(enum_id, range);
50dd3145 MD	316
	317	/*
	318	* special case pass through for fixed
	319	* input-only or output-only pins without
	320	* function enum register association.
	321	*/
	322	if (in_range && enum_id == range->force)
	323	continue;
50dd3145	324	}
e3c47051	325	/* GPIOs are only allowed to modify function fields. */
42eed42b MD	326	}
42eed42b MD	327
2967dab1 MD	328	if (!in_range)
	329	continue;
	330
b705c054 LP	331	ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
	332	if (ret < 0)
	333	return ret;
2967dab1	334
861601de	335	sh_pfc_write_config_reg(pfc, cr, field, value);
2967dab1 MD	336	}
	337
	338	return 0;
2967dab1 MD	339	}
2967dab1 MD	340
acac8ed5 LP	341	static int sh_pfc_init_ranges(struct sh_pfc *pfc)
	342	{
	343	struct sh_pfc_pin_range *range;
	344	unsigned int nr_ranges;
	345	unsigned int i;
	346
	347	if (pfc->info->pins[0].pin == (u16)-1) {
	348	/* Pin number -1 denotes that the SoC doesn't report pin numbers
	349	* in its pin arrays yet. Consider the pin numbers range as
	350	* continuous and allocate a single range.
	351	*/
	352	pfc->nr_ranges = 1;
	353	pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
	354	GFP_KERNEL);
	355	if (pfc->ranges == NULL)
	356	return -ENOMEM;
	357
	358	pfc->ranges->start = 0;
	359	pfc->ranges->end = pfc->info->nr_pins - 1;
	360	pfc->nr_gpio_pins = pfc->info->nr_pins;
	361
	362	return 0;
	363	}
	364
4f82e3ee LP	365	/* Count, allocate and fill the ranges. The PFC SoC data pins array must
	366	* be sorted by pin numbers, and pins without a GPIO port must come
	367	* last.
	368	*/
acac8ed5 LP	369	for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
	370	if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
	371	nr_ranges++;
	372	}
	373
	374	pfc->nr_ranges = nr_ranges;
	375	pfc->ranges = devm_kzalloc(pfc->dev, sizeof(pfc->ranges) nr_ranges,
	376	GFP_KERNEL);
	377	if (pfc->ranges == NULL)
	378	return -ENOMEM;
	379
	380	range = pfc->ranges;
	381	range->start = pfc->info->pins[0].pin;
	382
	383	for (i = 1; i < pfc->info->nr_pins; ++i) {
4f82e3ee LP	384	if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
	385	continue;
	386
	387	range->end = pfc->info->pins[i-1].pin;
	388	if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
	389	pfc->nr_gpio_pins = range->end + 1;
	390
	391	range++;
	392	range->start = pfc->info->pins[i].pin;
acac8ed5 LP	393	}
	394
	395	range->end = pfc->info->pins[i-1].pin;
4f82e3ee LP	396	if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
4f82e3ee LP	397	pfc->nr_gpio_pins = range->end + 1;
acac8ed5 LP	398
	399	return 0;
	400	}
	401
fe1c9a82 LP	402	#ifdef CONFIG_OF
	403	static const struct of_device_id sh_pfc_of_table[] = {
	404	#ifdef CONFIG_PINCTRL_PFC_R8A73A4
	405	{
	406	.compatible = "renesas,pfc-r8a73a4",
	407	.data = &r8a73a4_pinmux_info,
	408	},
	409	#endif
	410	#ifdef CONFIG_PINCTRL_PFC_R8A7740
	411	{
	412	.compatible = "renesas,pfc-r8a7740",
	413	.data = &r8a7740_pinmux_info,
	414	},
	415	#endif
	416	#ifdef CONFIG_PINCTRL_PFC_R8A7778
	417	{
	418	.compatible = "renesas,pfc-r8a7778",
	419	.data = &r8a7778_pinmux_info,
	420	},
	421	#endif
	422	#ifdef CONFIG_PINCTRL_PFC_R8A7779
	423	{
	424	.compatible = "renesas,pfc-r8a7779",
	425	.data = &r8a7779_pinmux_info,
	426	},
	427	#endif
	428	#ifdef CONFIG_PINCTRL_PFC_R8A7790
	429	{
	430	.compatible = "renesas,pfc-r8a7790",
	431	.data = &r8a7790_pinmux_info,
	432	},
	433	#endif
	434	#ifdef CONFIG_PINCTRL_PFC_SH7372
	435	{
	436	.compatible = "renesas,pfc-sh7372",
	437	.data = &sh7372_pinmux_info,
	438	},
	439	#endif
	440	#ifdef CONFIG_PINCTRL_PFC_SH73A0
	441	{
	442	.compatible = "renesas,pfc-sh73a0",
	443	.data = &sh73a0_pinmux_info,
	444	},
	445	#endif
	446	{ },
	447	};
	448	MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
	449	#endif
	450
c6193eac	451	static int sh_pfc_probe(struct platform_device *pdev)
2967dab1	452	{
fe1c9a82 LP	453	const struct platform_device_id *platid = platform_get_device_id(pdev);
	454	#ifdef CONFIG_OF
	455	struct device_node *np = pdev->dev.of_node;
	456	#endif
cd3c1bee	457	const struct sh_pfc_soc_info *info;
c6193eac	458	struct sh_pfc *pfc;
0fc64cc0	459	int ret;
2967dab1	460
fe1c9a82 LP	461	#ifdef CONFIG_OF
	462	if (np)
	463	info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
	464	else
	465	#endif
	466	info = platid ? (const void *)platid->driver_data : NULL;
	467
19bb7fe3	468	if (info == NULL)
c6193eac	469	return -ENODEV;
2967dab1	470
8c43fcc7	471	pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
c6193eac LP	472	if (pfc == NULL)
c6193eac LP	473	return -ENOMEM;
d4e62d00	474
19bb7fe3	475	pfc->info = info;
c6193eac LP	476	pfc->dev = &pdev->dev;
c6193eac LP	477
973931ae	478	ret = sh_pfc_ioremap(pfc, pdev);
c6193eac	479	if (unlikely(ret < 0))
b0e10211 MD	480	return ret;
b0e10211 MD	481
c6193eac	482	spin_lock_init(&pfc->lock);
69edbba0	483
0c151062 LP	484	if (info->ops && info->ops->init) {
	485	ret = info->ops->init(pfc);
	486	if (ret < 0)
	487	return ret;
	488	}
	489
ca5481c6	490	pinctrl_provide_dummies();
b0e10211	491
acac8ed5 LP	492	ret = sh_pfc_init_ranges(pfc);
	493	if (ret < 0)
	494	return ret;
	495
ca5481c6 PM	496	/*
	497	* Initialize pinctrl bindings first
	498	*/
c6193eac	499	ret = sh_pfc_register_pinctrl(pfc);
f9492fda	500	if (unlikely(ret != 0))
0c151062	501	goto error;
ca5481c6	502
6f6a4a68	503	#ifdef CONFIG_GPIO_SH_PFC
ca5481c6 PM	504	/*
	505	* Then the GPIO chip
	506	*/
c6193eac	507	ret = sh_pfc_register_gpiochip(pfc);
6f6a4a68	508	if (unlikely(ret != 0)) {
ca5481c6 PM	509	/*
	510	* If the GPIO chip fails to come up we still leave the
	511	* PFC state as it is, given that there are already
	512	* extant users of it that have succeeded by this point.
	513	*/
9a643c9a	514	dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
b3c185a7	515	}
6f6a4a68	516	#endif
b72421d8	517
c6193eac LP	518	platform_set_drvdata(pdev, pfc);
c6193eac LP	519
9a643c9a	520	dev_info(pfc->dev, "%s support registered\n", info->name);
ca5481c6	521
b3c185a7	522	return 0;
0c151062 LP	523
	524	error:
	525	if (info->ops && info->ops->exit)
	526	info->ops->exit(pfc);
	527	return ret;
b72421d8	528	}
6f6a4a68	529
c6193eac LP	530	static int sh_pfc_remove(struct platform_device *pdev)
	531	{
	532	struct sh_pfc *pfc = platform_get_drvdata(pdev);
	533
	534	#ifdef CONFIG_GPIO_SH_PFC
	535	sh_pfc_unregister_gpiochip(pfc);
	536	#endif
	537	sh_pfc_unregister_pinctrl(pfc);
	538
0c151062 LP	539	if (pfc->info->ops && pfc->info->ops->exit)
	540	pfc->info->ops->exit(pfc);
	541
c6193eac LP	542	return 0;
	543	}
	544
	545	static const struct platform_device_id sh_pfc_id_table[] = {
c98f6c21 MD	546	#ifdef CONFIG_PINCTRL_PFC_R8A73A4
	547	{ "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
	548	#endif
d5b1521a LP	549	#ifdef CONFIG_PINCTRL_PFC_R8A7740
d5b1521a LP	550	{ "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
881023d2	551	#endif
87f8c988 KM	552	#ifdef CONFIG_PINCTRL_PFC_R8A7778
	553	{ "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
	554	#endif
881023d2 LP	555	#ifdef CONFIG_PINCTRL_PFC_R8A7779
881023d2 LP	556	{ "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
6e5469a6	557	#endif
58c229e1 KM	558	#ifdef CONFIG_PINCTRL_PFC_R8A7790
	559	{ "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info },
	560	#endif
ccda552e LP	561	#ifdef CONFIG_PINCTRL_PFC_SH7203
	562	{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
	563	#endif
a8d42fc4 LP	564	#ifdef CONFIG_PINCTRL_PFC_SH7264
	565	{ "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
	566	#endif
f5e811f2 LP	567	#ifdef CONFIG_PINCTRL_PFC_SH7269
	568	{ "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
	569	#endif
6e5469a6 LP	570	#ifdef CONFIG_PINCTRL_PFC_SH7372
6e5469a6 LP	571	{ "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info },
5d5166dc LP	572	#endif
	573	#ifdef CONFIG_PINCTRL_PFC_SH73A0
	574	{ "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
74cad605 LP	575	#endif
	576	#ifdef CONFIG_PINCTRL_PFC_SH7720
	577	{ "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
f5e25ae5 LP	578	#endif
	579	#ifdef CONFIG_PINCTRL_PFC_SH7722
	580	{ "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
d05afa0a LP	581	#endif
	582	#ifdef CONFIG_PINCTRL_PFC_SH7723
	583	{ "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
0ff25bab LP	584	#endif
	585	#ifdef CONFIG_PINCTRL_PFC_SH7724
	586	{ "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
ac1ebc21 LP	587	#endif
	588	#ifdef CONFIG_PINCTRL_PFC_SH7734
	589	{ "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
0bb92677 LP	590	#endif
	591	#ifdef CONFIG_PINCTRL_PFC_SH7757
	592	{ "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
a56398e9 LP	593	#endif
	594	#ifdef CONFIG_PINCTRL_PFC_SH7785
	595	{ "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
d2a31bdd LP	596	#endif
	597	#ifdef CONFIG_PINCTRL_PFC_SH7786
	598	{ "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
d5d9a818 LP	599	#endif
	600	#ifdef CONFIG_PINCTRL_PFC_SHX3
	601	{ "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
d5b1521a	602	#endif
c6193eac LP	603	{ "sh-pfc", 0 },
	604	{ },
	605	};
	606	MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
	607
	608	static struct platform_driver sh_pfc_driver = {
	609	.probe = sh_pfc_probe,
	610	.remove = sh_pfc_remove,
	611	.id_table = sh_pfc_id_table,
	612	.driver = {
	613	.name = DRV_NAME,
	614	.owner = THIS_MODULE,
fe1c9a82	615	.of_match_table = of_match_ptr(sh_pfc_of_table),
c6193eac LP	616	},
	617	};
	618
40ee6fce LP	619	static int __init sh_pfc_init(void)
	620	{
	621	return platform_driver_register(&sh_pfc_driver);
c6193eac	622	}
40ee6fce	623	postcore_initcall(sh_pfc_init);
c6193eac LP	624
	625	static void __exit sh_pfc_exit(void)
	626	{
	627	platform_driver_unregister(&sh_pfc_driver);
	628	}
	629	module_exit(sh_pfc_exit);
	630
6f6a4a68 LP	631	MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
	632	MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
	633	MODULE_LICENSE("GPL v2");