Commit | Line | Data |
---|---|---|
2967dab1 | 1 | /* |
b3c185a7 | 2 | * SuperH Pin Function Controller support. |
2967dab1 MD |
3 | * |
4 | * Copyright (C) 2008 Magnus Damm | |
b3c185a7 | 5 | * Copyright (C) 2009 - 2012 Paul Mundt |
2967dab1 MD |
6 | * |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
c6193eac LP |
11 | |
12 | #define DRV_NAME "sh-pfc" | |
f9492fda | 13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
b72421d8 | 14 | |
90efde22 | 15 | #include <linux/bitops.h> |
2967dab1 | 16 | #include <linux/err.h> |
90efde22 | 17 | #include <linux/errno.h> |
2967dab1 | 18 | #include <linux/io.h> |
b0e10211 | 19 | #include <linux/ioport.h> |
90efde22 LP |
20 | #include <linux/kernel.h> |
21 | #include <linux/module.h> | |
ca5481c6 | 22 | #include <linux/pinctrl/machine.h> |
c6193eac | 23 | #include <linux/platform_device.h> |
90efde22 LP |
24 | #include <linux/sh_pfc.h> |
25 | #include <linux/slab.h> | |
b0e10211 | 26 | |
f9165132 LP |
27 | #include "core.h" |
28 | ||
973931ae | 29 | static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev) |
b0e10211 MD |
30 | { |
31 | struct resource *res; | |
32 | int k; | |
33 | ||
56dc04af | 34 | if (pdev->num_resources == 0) { |
973931ae | 35 | pfc->num_windows = 0; |
b0e10211 | 36 | return 0; |
973931ae | 37 | } |
b0e10211 | 38 | |
56dc04af | 39 | pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources * |
1724acfd | 40 | sizeof(*pfc->window), GFP_NOWAIT); |
b3c185a7 | 41 | if (!pfc->window) |
1724acfd | 42 | return -ENOMEM; |
b0e10211 | 43 | |
56dc04af | 44 | pfc->num_windows = pdev->num_resources; |
973931ae | 45 | |
56dc04af | 46 | for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) { |
b0e10211 | 47 | WARN_ON(resource_type(res) != IORESOURCE_MEM); |
b3c185a7 PM |
48 | pfc->window[k].phys = res->start; |
49 | pfc->window[k].size = resource_size(res); | |
c9fa88e2 LP |
50 | pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start, |
51 | resource_size(res)); | |
52 | if (!pfc->window[k].virt) | |
1724acfd | 53 | return -ENOMEM; |
b0e10211 MD |
54 | } |
55 | ||
56 | return 0; | |
b0e10211 MD |
57 | } |
58 | ||
4aeacd5b LP |
59 | static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, |
60 | unsigned long address) | |
b0e10211 | 61 | { |
4aeacd5b | 62 | struct sh_pfc_window *window; |
b0e10211 MD |
63 | int k; |
64 | ||
65 | /* scan through physical windows and convert address */ | |
973931ae | 66 | for (k = 0; k < pfc->num_windows; k++) { |
b3c185a7 | 67 | window = pfc->window + k; |
b0e10211 MD |
68 | |
69 | if (address < window->phys) | |
70 | continue; | |
71 | ||
72 | if (address >= (window->phys + window->size)) | |
73 | continue; | |
74 | ||
75 | return window->virt + (address - window->phys); | |
76 | } | |
77 | ||
78 | /* no windows defined, register must be 1:1 mapped virt:phys */ | |
79 | return (void __iomem *)address; | |
80 | } | |
2967dab1 | 81 | |
4aeacd5b | 82 | static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r) |
2967dab1 MD |
83 | { |
84 | if (enum_id < r->begin) | |
85 | return 0; | |
86 | ||
87 | if (enum_id > r->end) | |
88 | return 0; | |
89 | ||
90 | return 1; | |
91 | } | |
92 | ||
4aeacd5b LP |
93 | static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, |
94 | unsigned long reg_width) | |
3292094e MD |
95 | { |
96 | switch (reg_width) { | |
97 | case 8: | |
b0e10211 | 98 | return ioread8(mapped_reg); |
3292094e | 99 | case 16: |
b0e10211 | 100 | return ioread16(mapped_reg); |
3292094e | 101 | case 32: |
b0e10211 | 102 | return ioread32(mapped_reg); |
3292094e MD |
103 | } |
104 | ||
105 | BUG(); | |
106 | return 0; | |
107 | } | |
108 | ||
4aeacd5b LP |
109 | static void sh_pfc_write_raw_reg(void __iomem *mapped_reg, |
110 | unsigned long reg_width, unsigned long data) | |
3292094e MD |
111 | { |
112 | switch (reg_width) { | |
113 | case 8: | |
b0e10211 | 114 | iowrite8(data, mapped_reg); |
3292094e MD |
115 | return; |
116 | case 16: | |
b0e10211 | 117 | iowrite16(data, mapped_reg); |
3292094e MD |
118 | return; |
119 | case 32: | |
b0e10211 | 120 | iowrite32(data, mapped_reg); |
3292094e MD |
121 | return; |
122 | } | |
123 | ||
124 | BUG(); | |
125 | } | |
126 | ||
b3c185a7 | 127 | int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos) |
92554d97 MD |
128 | { |
129 | unsigned long pos; | |
130 | ||
131 | pos = dr->reg_width - (in_pos + 1); | |
132 | ||
133 | pr_debug("read_bit: addr = %lx, pos = %ld, " | |
134 | "r_width = %ld\n", dr->reg, pos, dr->reg_width); | |
135 | ||
4aeacd5b | 136 | return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1; |
92554d97 MD |
137 | } |
138 | ||
b3c185a7 PM |
139 | void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos, |
140 | unsigned long value) | |
3292094e MD |
141 | { |
142 | unsigned long pos; | |
143 | ||
144 | pos = dr->reg_width - (in_pos + 1); | |
145 | ||
ca6f2d7f | 146 | pr_debug("write_bit addr = %lx, value = %d, pos = %ld, " |
fd2cb0ce PM |
147 | "r_width = %ld\n", |
148 | dr->reg, !!value, pos, dr->reg_width); | |
3292094e MD |
149 | |
150 | if (value) | |
151 | set_bit(pos, &dr->reg_shadow); | |
152 | else | |
153 | clear_bit(pos, &dr->reg_shadow); | |
154 | ||
4aeacd5b | 155 | sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow); |
3292094e MD |
156 | } |
157 | ||
4aeacd5b LP |
158 | static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, |
159 | struct pinmux_cfg_reg *crp, | |
160 | unsigned long in_pos, | |
161 | void __iomem **mapped_regp, | |
162 | unsigned long *maskp, | |
163 | unsigned long *posp) | |
2967dab1 | 164 | { |
f78a26f5 MD |
165 | int k; |
166 | ||
4aeacd5b | 167 | *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg); |
2967dab1 | 168 | |
f78a26f5 MD |
169 | if (crp->field_width) { |
170 | *maskp = (1 << crp->field_width) - 1; | |
171 | *posp = crp->reg_width - ((in_pos + 1) * crp->field_width); | |
172 | } else { | |
173 | *maskp = (1 << crp->var_field_width[in_pos]) - 1; | |
174 | *posp = crp->reg_width; | |
175 | for (k = 0; k <= in_pos; k++) | |
176 | *posp -= crp->var_field_width[k]; | |
177 | } | |
18925e11 MD |
178 | } |
179 | ||
4aeacd5b LP |
180 | static int sh_pfc_read_config_reg(struct sh_pfc *pfc, |
181 | struct pinmux_cfg_reg *crp, | |
182 | unsigned long field) | |
18925e11 MD |
183 | { |
184 | void __iomem *mapped_reg; | |
185 | unsigned long mask, pos; | |
186 | ||
4aeacd5b | 187 | sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); |
2967dab1 | 188 | |
18925e11 | 189 | pr_debug("read_reg: addr = %lx, field = %ld, " |
fd2cb0ce | 190 | "r_width = %ld, f_width = %ld\n", |
18925e11 | 191 | crp->reg, field, crp->reg_width, crp->field_width); |
2967dab1 | 192 | |
4aeacd5b | 193 | return (sh_pfc_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask; |
0fc64cc0 MD |
194 | } |
195 | ||
4aeacd5b LP |
196 | static void sh_pfc_write_config_reg(struct sh_pfc *pfc, |
197 | struct pinmux_cfg_reg *crp, | |
198 | unsigned long field, unsigned long value) | |
0fc64cc0 | 199 | { |
18925e11 | 200 | void __iomem *mapped_reg; |
e499ada8 | 201 | unsigned long mask, pos, data; |
0fc64cc0 | 202 | |
4aeacd5b | 203 | sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); |
2967dab1 | 204 | |
18925e11 | 205 | pr_debug("write_reg addr = %lx, value = %ld, field = %ld, " |
fd2cb0ce | 206 | "r_width = %ld, f_width = %ld\n", |
18925e11 | 207 | crp->reg, value, field, crp->reg_width, crp->field_width); |
0fc64cc0 MD |
208 | |
209 | mask = ~(mask << pos); | |
210 | value = value << pos; | |
2967dab1 | 211 | |
4aeacd5b | 212 | data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width); |
e499ada8 MD |
213 | data &= mask; |
214 | data |= value; | |
215 | ||
19bb7fe3 | 216 | if (pfc->info->unlock_reg) |
4aeacd5b | 217 | sh_pfc_write_raw_reg( |
19bb7fe3 | 218 | sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32, |
4aeacd5b | 219 | ~data); |
e499ada8 | 220 | |
4aeacd5b | 221 | sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); |
2967dab1 MD |
222 | } |
223 | ||
4aeacd5b | 224 | static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio) |
2967dab1 | 225 | { |
19bb7fe3 | 226 | struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio]; |
2967dab1 MD |
227 | struct pinmux_data_reg *data_reg; |
228 | int k, n; | |
229 | ||
19bb7fe3 | 230 | if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data)) |
2967dab1 MD |
231 | return -1; |
232 | ||
233 | k = 0; | |
234 | while (1) { | |
19bb7fe3 | 235 | data_reg = pfc->info->data_regs + k; |
2967dab1 MD |
236 | |
237 | if (!data_reg->reg_width) | |
238 | break; | |
239 | ||
4aeacd5b | 240 | data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg); |
b0e10211 | 241 | |
2967dab1 | 242 | for (n = 0; n < data_reg->reg_width; n++) { |
18801be7 MD |
243 | if (data_reg->enum_ids[n] == gpiop->enum_id) { |
244 | gpiop->flags &= ~PINMUX_FLAG_DREG; | |
245 | gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT); | |
246 | gpiop->flags &= ~PINMUX_FLAG_DBIT; | |
247 | gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT); | |
2967dab1 | 248 | return 0; |
2967dab1 MD |
249 | } |
250 | } | |
251 | k++; | |
252 | } | |
253 | ||
18801be7 MD |
254 | BUG(); |
255 | ||
2967dab1 MD |
256 | return -1; |
257 | } | |
258 | ||
4aeacd5b | 259 | static void sh_pfc_setup_data_regs(struct sh_pfc *pfc) |
3292094e MD |
260 | { |
261 | struct pinmux_data_reg *drp; | |
262 | int k; | |
263 | ||
19bb7fe3 | 264 | for (k = pfc->info->first_gpio; k <= pfc->info->last_gpio; k++) |
4aeacd5b | 265 | sh_pfc_setup_data_reg(pfc, k); |
3292094e MD |
266 | |
267 | k = 0; | |
268 | while (1) { | |
19bb7fe3 | 269 | drp = pfc->info->data_regs + k; |
3292094e MD |
270 | |
271 | if (!drp->reg_width) | |
272 | break; | |
273 | ||
4aeacd5b LP |
274 | drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg, |
275 | drp->reg_width); | |
3292094e MD |
276 | k++; |
277 | } | |
278 | } | |
279 | ||
b3c185a7 | 280 | int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, |
18801be7 MD |
281 | struct pinmux_data_reg **drp, int *bitp) |
282 | { | |
19bb7fe3 | 283 | struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio]; |
18801be7 MD |
284 | int k, n; |
285 | ||
19bb7fe3 | 286 | if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data)) |
18801be7 MD |
287 | return -1; |
288 | ||
289 | k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT; | |
290 | n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT; | |
19bb7fe3 | 291 | *drp = pfc->info->data_regs + k; |
18801be7 MD |
292 | *bitp = n; |
293 | return 0; | |
294 | } | |
295 | ||
4aeacd5b LP |
296 | static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, |
297 | struct pinmux_cfg_reg **crp, int *fieldp, | |
298 | int *valuep, unsigned long **cntp) | |
2967dab1 MD |
299 | { |
300 | struct pinmux_cfg_reg *config_reg; | |
f78a26f5 MD |
301 | unsigned long r_width, f_width, curr_width, ncomb; |
302 | int k, m, n, pos, bit_pos; | |
2967dab1 MD |
303 | |
304 | k = 0; | |
305 | while (1) { | |
19bb7fe3 | 306 | config_reg = pfc->info->cfg_regs + k; |
2967dab1 MD |
307 | |
308 | r_width = config_reg->reg_width; | |
309 | f_width = config_reg->field_width; | |
310 | ||
311 | if (!r_width) | |
312 | break; | |
f78a26f5 MD |
313 | |
314 | pos = 0; | |
315 | m = 0; | |
316 | for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) { | |
317 | if (f_width) | |
318 | curr_width = f_width; | |
319 | else | |
320 | curr_width = config_reg->var_field_width[m]; | |
321 | ||
322 | ncomb = 1 << curr_width; | |
323 | for (n = 0; n < ncomb; n++) { | |
324 | if (config_reg->enum_ids[pos + n] == enum_id) { | |
325 | *crp = config_reg; | |
326 | *fieldp = m; | |
327 | *valuep = n; | |
328 | *cntp = &config_reg->cnt[m]; | |
329 | return 0; | |
330 | } | |
2967dab1 | 331 | } |
f78a26f5 MD |
332 | pos += ncomb; |
333 | m++; | |
2967dab1 MD |
334 | } |
335 | k++; | |
336 | } | |
337 | ||
338 | return -1; | |
339 | } | |
340 | ||
b3c185a7 PM |
341 | int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos, |
342 | pinmux_enum_t *enum_idp) | |
2967dab1 | 343 | { |
19bb7fe3 LP |
344 | pinmux_enum_t enum_id = pfc->info->gpios[gpio].enum_id; |
345 | pinmux_enum_t *data = pfc->info->gpio_data; | |
2967dab1 MD |
346 | int k; |
347 | ||
19bb7fe3 LP |
348 | if (!sh_pfc_enum_in_range(enum_id, &pfc->info->data)) { |
349 | if (!sh_pfc_enum_in_range(enum_id, &pfc->info->mark)) { | |
2967dab1 MD |
350 | pr_err("non data/mark enum_id for gpio %d\n", gpio); |
351 | return -1; | |
352 | } | |
353 | } | |
354 | ||
355 | if (pos) { | |
356 | *enum_idp = data[pos + 1]; | |
357 | return pos + 1; | |
358 | } | |
359 | ||
19bb7fe3 | 360 | for (k = 0; k < pfc->info->gpio_data_size; k++) { |
2967dab1 MD |
361 | if (data[k] == enum_id) { |
362 | *enum_idp = data[k + 1]; | |
363 | return k + 1; | |
364 | } | |
365 | } | |
366 | ||
367 | pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio); | |
368 | return -1; | |
369 | } | |
370 | ||
b3c185a7 PM |
371 | int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type, |
372 | int cfg_mode) | |
2967dab1 MD |
373 | { |
374 | struct pinmux_cfg_reg *cr = NULL; | |
375 | pinmux_enum_t enum_id; | |
376 | struct pinmux_range *range; | |
ad4a07ff | 377 | int in_range, pos, field, value; |
2967dab1 MD |
378 | unsigned long *cntp; |
379 | ||
380 | switch (pinmux_type) { | |
381 | ||
382 | case PINMUX_TYPE_FUNCTION: | |
383 | range = NULL; | |
384 | break; | |
385 | ||
386 | case PINMUX_TYPE_OUTPUT: | |
19bb7fe3 | 387 | range = &pfc->info->output; |
2967dab1 MD |
388 | break; |
389 | ||
390 | case PINMUX_TYPE_INPUT: | |
19bb7fe3 | 391 | range = &pfc->info->input; |
2967dab1 MD |
392 | break; |
393 | ||
394 | case PINMUX_TYPE_INPUT_PULLUP: | |
19bb7fe3 | 395 | range = &pfc->info->input_pu; |
2967dab1 MD |
396 | break; |
397 | ||
398 | case PINMUX_TYPE_INPUT_PULLDOWN: | |
19bb7fe3 | 399 | range = &pfc->info->input_pd; |
2967dab1 MD |
400 | break; |
401 | ||
402 | default: | |
403 | goto out_err; | |
404 | } | |
405 | ||
406 | pos = 0; | |
407 | enum_id = 0; | |
ad4a07ff MD |
408 | field = 0; |
409 | value = 0; | |
2967dab1 | 410 | while (1) { |
b3c185a7 | 411 | pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id); |
2967dab1 MD |
412 | if (pos <= 0) |
413 | goto out_err; | |
414 | ||
415 | if (!enum_id) | |
416 | break; | |
417 | ||
50dd3145 | 418 | /* first check if this is a function enum */ |
19bb7fe3 | 419 | in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function); |
50dd3145 MD |
420 | if (!in_range) { |
421 | /* not a function enum */ | |
422 | if (range) { | |
423 | /* | |
424 | * other range exists, so this pin is | |
425 | * a regular GPIO pin that now is being | |
426 | * bound to a specific direction. | |
427 | * | |
428 | * for this case we only allow function enums | |
429 | * and the enums that match the other range. | |
430 | */ | |
4aeacd5b | 431 | in_range = sh_pfc_enum_in_range(enum_id, range); |
50dd3145 MD |
432 | |
433 | /* | |
434 | * special case pass through for fixed | |
435 | * input-only or output-only pins without | |
436 | * function enum register association. | |
437 | */ | |
438 | if (in_range && enum_id == range->force) | |
439 | continue; | |
440 | } else { | |
441 | /* | |
442 | * no other range exists, so this pin | |
443 | * must then be of the function type. | |
444 | * | |
445 | * allow function type pins to select | |
446 | * any combination of function/in/out | |
447 | * in their MARK lists. | |
448 | */ | |
449 | in_range = 1; | |
450 | } | |
42eed42b MD |
451 | } |
452 | ||
2967dab1 MD |
453 | if (!in_range) |
454 | continue; | |
455 | ||
4aeacd5b LP |
456 | if (sh_pfc_get_config_reg(pfc, enum_id, &cr, |
457 | &field, &value, &cntp) != 0) | |
2967dab1 MD |
458 | goto out_err; |
459 | ||
460 | switch (cfg_mode) { | |
461 | case GPIO_CFG_DRYRUN: | |
18925e11 | 462 | if (!*cntp || |
4aeacd5b | 463 | (sh_pfc_read_config_reg(pfc, cr, field) != value)) |
2967dab1 MD |
464 | continue; |
465 | break; | |
466 | ||
467 | case GPIO_CFG_REQ: | |
4aeacd5b | 468 | sh_pfc_write_config_reg(pfc, cr, field, value); |
2967dab1 MD |
469 | *cntp = *cntp + 1; |
470 | break; | |
471 | ||
472 | case GPIO_CFG_FREE: | |
473 | *cntp = *cntp - 1; | |
474 | break; | |
475 | } | |
476 | } | |
477 | ||
478 | return 0; | |
479 | out_err: | |
480 | return -1; | |
481 | } | |
482 | ||
c6193eac | 483 | static int sh_pfc_probe(struct platform_device *pdev) |
2967dab1 | 484 | { |
19bb7fe3 | 485 | struct sh_pfc_soc_info *info; |
c6193eac | 486 | struct sh_pfc *pfc; |
0fc64cc0 | 487 | int ret; |
2967dab1 | 488 | |
06d5631f PM |
489 | /* |
490 | * Ensure that the type encoding fits | |
491 | */ | |
492 | BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1)); | |
493 | ||
19bb7fe3 LP |
494 | info = pdev->id_entry->driver_data |
495 | ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data; | |
496 | if (info == NULL) | |
c6193eac | 497 | return -ENODEV; |
2967dab1 | 498 | |
c6193eac LP |
499 | pfc = devm_kzalloc(&pdev->dev, sizeof(pfc), GFP_KERNEL); |
500 | if (pfc == NULL) | |
501 | return -ENOMEM; | |
d4e62d00 | 502 | |
19bb7fe3 | 503 | pfc->info = info; |
c6193eac LP |
504 | pfc->dev = &pdev->dev; |
505 | ||
973931ae | 506 | ret = sh_pfc_ioremap(pfc, pdev); |
c6193eac | 507 | if (unlikely(ret < 0)) |
b0e10211 MD |
508 | return ret; |
509 | ||
c6193eac | 510 | spin_lock_init(&pfc->lock); |
69edbba0 | 511 | |
ca5481c6 | 512 | pinctrl_provide_dummies(); |
4aeacd5b | 513 | sh_pfc_setup_data_regs(pfc); |
b0e10211 | 514 | |
ca5481c6 PM |
515 | /* |
516 | * Initialize pinctrl bindings first | |
517 | */ | |
c6193eac | 518 | ret = sh_pfc_register_pinctrl(pfc); |
f9492fda | 519 | if (unlikely(ret != 0)) |
c9fa88e2 | 520 | return ret; |
ca5481c6 | 521 | |
6f6a4a68 | 522 | #ifdef CONFIG_GPIO_SH_PFC |
ca5481c6 PM |
523 | /* |
524 | * Then the GPIO chip | |
525 | */ | |
c6193eac | 526 | ret = sh_pfc_register_gpiochip(pfc); |
6f6a4a68 | 527 | if (unlikely(ret != 0)) { |
ca5481c6 PM |
528 | /* |
529 | * If the GPIO chip fails to come up we still leave the | |
530 | * PFC state as it is, given that there are already | |
531 | * extant users of it that have succeeded by this point. | |
532 | */ | |
6f6a4a68 | 533 | pr_notice("failed to init GPIO chip, ignoring...\n"); |
b3c185a7 | 534 | } |
6f6a4a68 | 535 | #endif |
b72421d8 | 536 | |
c6193eac LP |
537 | platform_set_drvdata(pdev, pfc); |
538 | ||
19bb7fe3 | 539 | pr_info("%s support registered\n", info->name); |
ca5481c6 | 540 | |
b3c185a7 | 541 | return 0; |
b72421d8 | 542 | } |
6f6a4a68 | 543 | |
c6193eac LP |
544 | static int sh_pfc_remove(struct platform_device *pdev) |
545 | { | |
546 | struct sh_pfc *pfc = platform_get_drvdata(pdev); | |
547 | ||
548 | #ifdef CONFIG_GPIO_SH_PFC | |
549 | sh_pfc_unregister_gpiochip(pfc); | |
550 | #endif | |
551 | sh_pfc_unregister_pinctrl(pfc); | |
552 | ||
c6193eac LP |
553 | platform_set_drvdata(pdev, NULL); |
554 | ||
555 | return 0; | |
556 | } | |
557 | ||
558 | static const struct platform_device_id sh_pfc_id_table[] = { | |
559 | { "sh-pfc", 0 }, | |
560 | { }, | |
561 | }; | |
562 | MODULE_DEVICE_TABLE(platform, sh_pfc_id_table); | |
563 | ||
564 | static struct platform_driver sh_pfc_driver = { | |
565 | .probe = sh_pfc_probe, | |
566 | .remove = sh_pfc_remove, | |
567 | .id_table = sh_pfc_id_table, | |
568 | .driver = { | |
569 | .name = DRV_NAME, | |
570 | .owner = THIS_MODULE, | |
571 | }, | |
572 | }; | |
573 | ||
40ee6fce LP |
574 | static int __init sh_pfc_init(void) |
575 | { | |
576 | return platform_driver_register(&sh_pfc_driver); | |
c6193eac | 577 | } |
40ee6fce | 578 | postcore_initcall(sh_pfc_init); |
c6193eac LP |
579 | |
580 | static void __exit sh_pfc_exit(void) | |
581 | { | |
582 | platform_driver_unregister(&sh_pfc_driver); | |
583 | } | |
584 | module_exit(sh_pfc_exit); | |
585 | ||
6f6a4a68 LP |
586 | MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart"); |
587 | MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller"); | |
588 | MODULE_LICENSE("GPL v2"); |