Commit | Line | Data |
---|---|---|
2967dab1 | 1 | /* |
a43647b6 PG |
2 | * Pin Control and GPIO driver for SuperH Pin Function Controller. |
3 | * | |
4 | * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart | |
2967dab1 MD |
5 | * |
6 | * Copyright (C) 2008 Magnus Damm | |
b3c185a7 | 7 | * Copyright (C) 2009 - 2012 Paul Mundt |
2967dab1 MD |
8 | * |
9 | * This file is subject to the terms and conditions of the GNU General Public | |
10 | * License. See the file "COPYING" in the main directory of this archive | |
11 | * for more details. | |
12 | */ | |
c6193eac LP |
13 | |
14 | #define DRV_NAME "sh-pfc" | |
b72421d8 | 15 | |
90efde22 | 16 | #include <linux/bitops.h> |
2967dab1 | 17 | #include <linux/err.h> |
90efde22 | 18 | #include <linux/errno.h> |
2967dab1 | 19 | #include <linux/io.h> |
b0e10211 | 20 | #include <linux/ioport.h> |
90efde22 | 21 | #include <linux/kernel.h> |
a43647b6 | 22 | #include <linux/init.h> |
fe1c9a82 LP |
23 | #include <linux/of.h> |
24 | #include <linux/of_device.h> | |
ca5481c6 | 25 | #include <linux/pinctrl/machine.h> |
c6193eac | 26 | #include <linux/platform_device.h> |
90efde22 | 27 | #include <linux/slab.h> |
b0e10211 | 28 | |
f9165132 LP |
29 | #include "core.h" |
30 | ||
70c8f01a LP |
31 | static int sh_pfc_map_resources(struct sh_pfc *pfc, |
32 | struct platform_device *pdev) | |
b0e10211 | 33 | { |
c7977ec4 | 34 | unsigned int num_windows, num_irqs; |
70c8f01a LP |
35 | struct sh_pfc_window *windows; |
36 | unsigned int *irqs = NULL; | |
b0e10211 | 37 | struct resource *res; |
70c8f01a | 38 | unsigned int i; |
c7977ec4 | 39 | int irq; |
70c8f01a LP |
40 | |
41 | /* Count the MEM and IRQ resources. */ | |
c7977ec4 GU |
42 | for (num_windows = 0;; num_windows++) { |
43 | res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows); | |
44 | if (!res) | |
70c8f01a | 45 | break; |
c7977ec4 GU |
46 | } |
47 | for (num_irqs = 0;; num_irqs++) { | |
48 | irq = platform_get_irq(pdev, num_irqs); | |
49 | if (irq == -EPROBE_DEFER) | |
50 | return irq; | |
51 | if (irq < 0) | |
70c8f01a | 52 | break; |
70c8f01a | 53 | } |
b0e10211 | 54 | |
70c8f01a | 55 | if (num_windows == 0) |
bee9f22b | 56 | return -EINVAL; |
b0e10211 | 57 | |
70c8f01a LP |
58 | /* Allocate memory windows and IRQs arrays. */ |
59 | windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows), | |
60 | GFP_KERNEL); | |
61 | if (windows == NULL) | |
1724acfd | 62 | return -ENOMEM; |
b0e10211 | 63 | |
70c8f01a LP |
64 | pfc->num_windows = num_windows; |
65 | pfc->windows = windows; | |
973931ae | 66 | |
70c8f01a LP |
67 | if (num_irqs) { |
68 | irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs), | |
69 | GFP_KERNEL); | |
70 | if (irqs == NULL) | |
1724acfd | 71 | return -ENOMEM; |
70c8f01a LP |
72 | |
73 | pfc->num_irqs = num_irqs; | |
74 | pfc->irqs = irqs; | |
75 | } | |
76 | ||
77 | /* Fill them. */ | |
c7977ec4 GU |
78 | for (i = 0; i < num_windows; i++) { |
79 | res = platform_get_resource(pdev, IORESOURCE_MEM, i); | |
80 | windows->phys = res->start; | |
81 | windows->size = resource_size(res); | |
82 | windows->virt = devm_ioremap_resource(pfc->dev, res); | |
83 | if (IS_ERR(windows->virt)) | |
84 | return -ENOMEM; | |
85 | windows++; | |
b0e10211 | 86 | } |
c7977ec4 GU |
87 | for (i = 0; i < num_irqs; i++) |
88 | *irqs++ = platform_get_irq(pdev, i); | |
b0e10211 MD |
89 | |
90 | return 0; | |
b0e10211 MD |
91 | } |
92 | ||
1f34de05 | 93 | static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg) |
b0e10211 | 94 | { |
4aeacd5b | 95 | struct sh_pfc_window *window; |
1f34de05 | 96 | phys_addr_t address = reg; |
bee9f22b | 97 | unsigned int i; |
b0e10211 MD |
98 | |
99 | /* scan through physical windows and convert address */ | |
bee9f22b | 100 | for (i = 0; i < pfc->num_windows; i++) { |
5b46ac3a | 101 | window = pfc->windows + i; |
b0e10211 MD |
102 | |
103 | if (address < window->phys) | |
104 | continue; | |
105 | ||
106 | if (address >= (window->phys + window->size)) | |
107 | continue; | |
108 | ||
109 | return window->virt + (address - window->phys); | |
110 | } | |
111 | ||
bee9f22b | 112 | BUG(); |
1960d580 | 113 | return NULL; |
b0e10211 | 114 | } |
2967dab1 | 115 | |
1a0039dc | 116 | int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin) |
934cb02b | 117 | { |
63d57383 LP |
118 | unsigned int offset; |
119 | unsigned int i; | |
120 | ||
acac8ed5 LP |
121 | for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) { |
122 | const struct sh_pfc_pin_range *range = &pfc->ranges[i]; | |
63d57383 LP |
123 | |
124 | if (pin <= range->end) | |
acac8ed5 LP |
125 | return pin >= range->start |
126 | ? offset + pin - range->start : -1; | |
63d57383 | 127 | |
acac8ed5 | 128 | offset += range->end - range->start + 1; |
63d57383 LP |
129 | } |
130 | ||
b705c054 | 131 | return -EINVAL; |
934cb02b LP |
132 | } |
133 | ||
533743dc | 134 | static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r) |
2967dab1 MD |
135 | { |
136 | if (enum_id < r->begin) | |
137 | return 0; | |
138 | ||
139 | if (enum_id > r->end) | |
140 | return 0; | |
141 | ||
142 | return 1; | |
143 | } | |
144 | ||
cef28a28 | 145 | u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width) |
3292094e MD |
146 | { |
147 | switch (reg_width) { | |
148 | case 8: | |
b0e10211 | 149 | return ioread8(mapped_reg); |
3292094e | 150 | case 16: |
b0e10211 | 151 | return ioread16(mapped_reg); |
3292094e | 152 | case 32: |
b0e10211 | 153 | return ioread32(mapped_reg); |
3292094e MD |
154 | } |
155 | ||
156 | BUG(); | |
157 | return 0; | |
158 | } | |
159 | ||
cef28a28 | 160 | void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width, |
fc88936a | 161 | u32 data) |
3292094e MD |
162 | { |
163 | switch (reg_width) { | |
164 | case 8: | |
b0e10211 | 165 | iowrite8(data, mapped_reg); |
3292094e MD |
166 | return; |
167 | case 16: | |
b0e10211 | 168 | iowrite16(data, mapped_reg); |
3292094e MD |
169 | return; |
170 | case 32: | |
b0e10211 | 171 | iowrite32(data, mapped_reg); |
3292094e MD |
172 | return; |
173 | } | |
174 | ||
175 | BUG(); | |
176 | } | |
177 | ||
3caa7d8c LP |
178 | u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width) |
179 | { | |
180 | return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), width); | |
181 | } | |
182 | ||
183 | void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data) | |
184 | { | |
185 | if (pfc->info->unlock_reg) | |
186 | sh_pfc_write_raw_reg( | |
187 | sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32, | |
188 | ~data); | |
189 | ||
190 | sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), width, data); | |
191 | } | |
192 | ||
4aeacd5b | 193 | static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, |
cd3c1bee | 194 | const struct pinmux_cfg_reg *crp, |
cef28a28 | 195 | unsigned int in_pos, |
fc88936a | 196 | void __iomem **mapped_regp, u32 *maskp, |
cef28a28 | 197 | unsigned int *posp) |
2967dab1 | 198 | { |
8d72a7fc | 199 | unsigned int k; |
f78a26f5 | 200 | |
4aeacd5b | 201 | *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg); |
2967dab1 | 202 | |
f78a26f5 MD |
203 | if (crp->field_width) { |
204 | *maskp = (1 << crp->field_width) - 1; | |
205 | *posp = crp->reg_width - ((in_pos + 1) * crp->field_width); | |
206 | } else { | |
207 | *maskp = (1 << crp->var_field_width[in_pos]) - 1; | |
208 | *posp = crp->reg_width; | |
209 | for (k = 0; k <= in_pos; k++) | |
210 | *posp -= crp->var_field_width[k]; | |
211 | } | |
18925e11 MD |
212 | } |
213 | ||
4aeacd5b | 214 | static void sh_pfc_write_config_reg(struct sh_pfc *pfc, |
cd3c1bee | 215 | const struct pinmux_cfg_reg *crp, |
cef28a28 | 216 | unsigned int field, u32 value) |
0fc64cc0 | 217 | { |
18925e11 | 218 | void __iomem *mapped_reg; |
cef28a28 | 219 | unsigned int pos; |
fc88936a | 220 | u32 mask, data; |
0fc64cc0 | 221 | |
4aeacd5b | 222 | sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); |
2967dab1 | 223 | |
1f34de05 | 224 | dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, " |
dc700715 | 225 | "r_width = %u, f_width = %u\n", |
9a643c9a | 226 | crp->reg, value, field, crp->reg_width, crp->field_width); |
0fc64cc0 MD |
227 | |
228 | mask = ~(mask << pos); | |
229 | value = value << pos; | |
2967dab1 | 230 | |
4aeacd5b | 231 | data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width); |
e499ada8 MD |
232 | data &= mask; |
233 | data |= value; | |
234 | ||
19bb7fe3 | 235 | if (pfc->info->unlock_reg) |
4aeacd5b | 236 | sh_pfc_write_raw_reg( |
19bb7fe3 | 237 | sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32, |
4aeacd5b | 238 | ~data); |
e499ada8 | 239 | |
4aeacd5b | 240 | sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); |
2967dab1 MD |
241 | } |
242 | ||
533743dc | 243 | static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id, |
cef28a28 GU |
244 | const struct pinmux_cfg_reg **crp, |
245 | unsigned int *fieldp, u32 *valuep) | |
2967dab1 | 246 | { |
cef28a28 | 247 | unsigned int k = 0; |
2967dab1 | 248 | |
2967dab1 | 249 | while (1) { |
cef28a28 GU |
250 | const struct pinmux_cfg_reg *config_reg = |
251 | pfc->info->cfg_regs + k; | |
252 | unsigned int r_width = config_reg->reg_width; | |
253 | unsigned int f_width = config_reg->field_width; | |
254 | unsigned int curr_width; | |
255 | unsigned int bit_pos; | |
256 | unsigned int pos = 0; | |
257 | unsigned int m = 0; | |
2967dab1 MD |
258 | |
259 | if (!r_width) | |
260 | break; | |
f78a26f5 | 261 | |
f78a26f5 | 262 | for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) { |
cef28a28 GU |
263 | u32 ncomb; |
264 | u32 n; | |
265 | ||
f78a26f5 MD |
266 | if (f_width) |
267 | curr_width = f_width; | |
268 | else | |
269 | curr_width = config_reg->var_field_width[m]; | |
270 | ||
271 | ncomb = 1 << curr_width; | |
272 | for (n = 0; n < ncomb; n++) { | |
273 | if (config_reg->enum_ids[pos + n] == enum_id) { | |
274 | *crp = config_reg; | |
275 | *fieldp = m; | |
276 | *valuep = n; | |
f78a26f5 MD |
277 | return 0; |
278 | } | |
2967dab1 | 279 | } |
f78a26f5 MD |
280 | pos += ncomb; |
281 | m++; | |
2967dab1 MD |
282 | } |
283 | k++; | |
284 | } | |
285 | ||
b705c054 | 286 | return -EINVAL; |
2967dab1 MD |
287 | } |
288 | ||
533743dc LP |
289 | static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos, |
290 | u16 *enum_idp) | |
2967dab1 | 291 | { |
b8b47d67 | 292 | const u16 *data = pfc->info->pinmux_data; |
8d72a7fc | 293 | unsigned int k; |
2967dab1 | 294 | |
2967dab1 MD |
295 | if (pos) { |
296 | *enum_idp = data[pos + 1]; | |
297 | return pos + 1; | |
298 | } | |
299 | ||
b8b47d67 | 300 | for (k = 0; k < pfc->info->pinmux_data_size; k++) { |
a68fdca9 | 301 | if (data[k] == mark) { |
2967dab1 MD |
302 | *enum_idp = data[k + 1]; |
303 | return k + 1; | |
304 | } | |
305 | } | |
306 | ||
9a643c9a LP |
307 | dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n", |
308 | mark); | |
b705c054 | 309 | return -EINVAL; |
2967dab1 MD |
310 | } |
311 | ||
861601de | 312 | int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) |
2967dab1 | 313 | { |
cd3c1bee | 314 | const struct pinmux_range *range; |
cef28a28 | 315 | int pos = 0; |
2967dab1 MD |
316 | |
317 | switch (pinmux_type) { | |
e3c47051 | 318 | case PINMUX_TYPE_GPIO: |
2967dab1 MD |
319 | case PINMUX_TYPE_FUNCTION: |
320 | range = NULL; | |
321 | break; | |
322 | ||
323 | case PINMUX_TYPE_OUTPUT: | |
19bb7fe3 | 324 | range = &pfc->info->output; |
2967dab1 MD |
325 | break; |
326 | ||
327 | case PINMUX_TYPE_INPUT: | |
19bb7fe3 | 328 | range = &pfc->info->input; |
2967dab1 MD |
329 | break; |
330 | ||
2967dab1 | 331 | default: |
b705c054 | 332 | return -EINVAL; |
2967dab1 MD |
333 | } |
334 | ||
e3c47051 | 335 | /* Iterate over all the configuration fields we need to update. */ |
2967dab1 | 336 | while (1) { |
cef28a28 GU |
337 | const struct pinmux_cfg_reg *cr; |
338 | unsigned int field; | |
339 | u16 enum_id; | |
340 | u32 value; | |
341 | int in_range; | |
342 | int ret; | |
343 | ||
a68fdca9 | 344 | pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id); |
b705c054 LP |
345 | if (pos < 0) |
346 | return pos; | |
2967dab1 MD |
347 | |
348 | if (!enum_id) | |
349 | break; | |
350 | ||
e3c47051 LP |
351 | /* Check if the configuration field selects a function. If it |
352 | * doesn't, skip the field if it's not applicable to the | |
353 | * requested pinmux type. | |
354 | */ | |
19bb7fe3 | 355 | in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function); |
50dd3145 | 356 | if (!in_range) { |
e3c47051 LP |
357 | if (pinmux_type == PINMUX_TYPE_FUNCTION) { |
358 | /* Functions are allowed to modify all | |
359 | * fields. | |
360 | */ | |
361 | in_range = 1; | |
362 | } else if (pinmux_type != PINMUX_TYPE_GPIO) { | |
363 | /* Input/output types can only modify fields | |
364 | * that correspond to their respective ranges. | |
50dd3145 | 365 | */ |
4aeacd5b | 366 | in_range = sh_pfc_enum_in_range(enum_id, range); |
50dd3145 MD |
367 | |
368 | /* | |
369 | * special case pass through for fixed | |
370 | * input-only or output-only pins without | |
371 | * function enum register association. | |
372 | */ | |
373 | if (in_range && enum_id == range->force) | |
374 | continue; | |
50dd3145 | 375 | } |
e3c47051 | 376 | /* GPIOs are only allowed to modify function fields. */ |
42eed42b MD |
377 | } |
378 | ||
2967dab1 MD |
379 | if (!in_range) |
380 | continue; | |
381 | ||
b705c054 LP |
382 | ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value); |
383 | if (ret < 0) | |
384 | return ret; | |
2967dab1 | 385 | |
861601de | 386 | sh_pfc_write_config_reg(pfc, cr, field, value); |
2967dab1 MD |
387 | } |
388 | ||
389 | return 0; | |
2967dab1 MD |
390 | } |
391 | ||
acac8ed5 LP |
392 | static int sh_pfc_init_ranges(struct sh_pfc *pfc) |
393 | { | |
394 | struct sh_pfc_pin_range *range; | |
395 | unsigned int nr_ranges; | |
396 | unsigned int i; | |
397 | ||
398 | if (pfc->info->pins[0].pin == (u16)-1) { | |
399 | /* Pin number -1 denotes that the SoC doesn't report pin numbers | |
400 | * in its pin arrays yet. Consider the pin numbers range as | |
401 | * continuous and allocate a single range. | |
402 | */ | |
403 | pfc->nr_ranges = 1; | |
404 | pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges), | |
405 | GFP_KERNEL); | |
406 | if (pfc->ranges == NULL) | |
407 | return -ENOMEM; | |
408 | ||
409 | pfc->ranges->start = 0; | |
410 | pfc->ranges->end = pfc->info->nr_pins - 1; | |
411 | pfc->nr_gpio_pins = pfc->info->nr_pins; | |
412 | ||
413 | return 0; | |
414 | } | |
415 | ||
4f82e3ee LP |
416 | /* Count, allocate and fill the ranges. The PFC SoC data pins array must |
417 | * be sorted by pin numbers, and pins without a GPIO port must come | |
418 | * last. | |
419 | */ | |
acac8ed5 LP |
420 | for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) { |
421 | if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1) | |
422 | nr_ranges++; | |
423 | } | |
424 | ||
425 | pfc->nr_ranges = nr_ranges; | |
426 | pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges, | |
427 | GFP_KERNEL); | |
428 | if (pfc->ranges == NULL) | |
429 | return -ENOMEM; | |
430 | ||
431 | range = pfc->ranges; | |
432 | range->start = pfc->info->pins[0].pin; | |
433 | ||
434 | for (i = 1; i < pfc->info->nr_pins; ++i) { | |
4f82e3ee LP |
435 | if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1) |
436 | continue; | |
437 | ||
438 | range->end = pfc->info->pins[i-1].pin; | |
439 | if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) | |
440 | pfc->nr_gpio_pins = range->end + 1; | |
441 | ||
442 | range++; | |
443 | range->start = pfc->info->pins[i].pin; | |
acac8ed5 LP |
444 | } |
445 | ||
446 | range->end = pfc->info->pins[i-1].pin; | |
4f82e3ee LP |
447 | if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) |
448 | pfc->nr_gpio_pins = range->end + 1; | |
acac8ed5 LP |
449 | |
450 | return 0; | |
451 | } | |
452 | ||
fe1c9a82 LP |
453 | #ifdef CONFIG_OF |
454 | static const struct of_device_id sh_pfc_of_table[] = { | |
1e7d5d84 NS |
455 | #ifdef CONFIG_PINCTRL_PFC_EMEV2 |
456 | { | |
457 | .compatible = "renesas,pfc-emev2", | |
458 | .data = &emev2_pinmux_info, | |
459 | }, | |
460 | #endif | |
fe1c9a82 LP |
461 | #ifdef CONFIG_PINCTRL_PFC_R8A73A4 |
462 | { | |
463 | .compatible = "renesas,pfc-r8a73a4", | |
464 | .data = &r8a73a4_pinmux_info, | |
465 | }, | |
466 | #endif | |
467 | #ifdef CONFIG_PINCTRL_PFC_R8A7740 | |
468 | { | |
469 | .compatible = "renesas,pfc-r8a7740", | |
470 | .data = &r8a7740_pinmux_info, | |
471 | }, | |
472 | #endif | |
473 | #ifdef CONFIG_PINCTRL_PFC_R8A7778 | |
474 | { | |
475 | .compatible = "renesas,pfc-r8a7778", | |
476 | .data = &r8a7778_pinmux_info, | |
477 | }, | |
478 | #endif | |
479 | #ifdef CONFIG_PINCTRL_PFC_R8A7779 | |
480 | { | |
481 | .compatible = "renesas,pfc-r8a7779", | |
482 | .data = &r8a7779_pinmux_info, | |
483 | }, | |
484 | #endif | |
485 | #ifdef CONFIG_PINCTRL_PFC_R8A7790 | |
486 | { | |
487 | .compatible = "renesas,pfc-r8a7790", | |
488 | .data = &r8a7790_pinmux_info, | |
489 | }, | |
490 | #endif | |
50884519 HN |
491 | #ifdef CONFIG_PINCTRL_PFC_R8A7791 |
492 | { | |
493 | .compatible = "renesas,pfc-r8a7791", | |
494 | .data = &r8a7791_pinmux_info, | |
495 | }, | |
496 | #endif | |
2cf59e0c SS |
497 | #ifdef CONFIG_PINCTRL_PFC_R8A7792 |
498 | { | |
499 | .compatible = "renesas,pfc-r8a7792", | |
500 | .data = &r8a7792_pinmux_info, | |
501 | }, | |
502 | #endif | |
19e1e98f UH |
503 | #ifdef CONFIG_PINCTRL_PFC_R8A7793 |
504 | { | |
505 | .compatible = "renesas,pfc-r8a7793", | |
506 | .data = &r8a7793_pinmux_info, | |
507 | }, | |
508 | #endif | |
43c4436e HN |
509 | #ifdef CONFIG_PINCTRL_PFC_R8A7794 |
510 | { | |
511 | .compatible = "renesas,pfc-r8a7794", | |
512 | .data = &r8a7794_pinmux_info, | |
513 | }, | |
514 | #endif | |
0b0ffc96 TK |
515 | #ifdef CONFIG_PINCTRL_PFC_R8A7795 |
516 | { | |
517 | .compatible = "renesas,pfc-r8a7795", | |
518 | .data = &r8a7795_pinmux_info, | |
519 | }, | |
520 | #endif | |
f9aece73 TK |
521 | #ifdef CONFIG_PINCTRL_PFC_R8A7796 |
522 | { | |
523 | .compatible = "renesas,pfc-r8a7796", | |
524 | .data = &r8a7796_pinmux_info, | |
525 | }, | |
526 | #endif | |
fe1c9a82 LP |
527 | #ifdef CONFIG_PINCTRL_PFC_SH73A0 |
528 | { | |
529 | .compatible = "renesas,pfc-sh73a0", | |
530 | .data = &sh73a0_pinmux_info, | |
531 | }, | |
532 | #endif | |
533 | { }, | |
534 | }; | |
fe1c9a82 LP |
535 | #endif |
536 | ||
c6193eac | 537 | static int sh_pfc_probe(struct platform_device *pdev) |
2967dab1 | 538 | { |
fe1c9a82 LP |
539 | const struct platform_device_id *platid = platform_get_device_id(pdev); |
540 | #ifdef CONFIG_OF | |
541 | struct device_node *np = pdev->dev.of_node; | |
542 | #endif | |
cd3c1bee | 543 | const struct sh_pfc_soc_info *info; |
c6193eac | 544 | struct sh_pfc *pfc; |
0fc64cc0 | 545 | int ret; |
2967dab1 | 546 | |
fe1c9a82 LP |
547 | #ifdef CONFIG_OF |
548 | if (np) | |
331207af | 549 | info = of_device_get_match_data(&pdev->dev); |
fe1c9a82 LP |
550 | else |
551 | #endif | |
552 | info = platid ? (const void *)platid->driver_data : NULL; | |
553 | ||
19bb7fe3 | 554 | if (info == NULL) |
c6193eac | 555 | return -ENODEV; |
2967dab1 | 556 | |
8c43fcc7 | 557 | pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL); |
c6193eac LP |
558 | if (pfc == NULL) |
559 | return -ENOMEM; | |
d4e62d00 | 560 | |
19bb7fe3 | 561 | pfc->info = info; |
c6193eac LP |
562 | pfc->dev = &pdev->dev; |
563 | ||
70c8f01a | 564 | ret = sh_pfc_map_resources(pfc, pdev); |
c6193eac | 565 | if (unlikely(ret < 0)) |
b0e10211 MD |
566 | return ret; |
567 | ||
c6193eac | 568 | spin_lock_init(&pfc->lock); |
69edbba0 | 569 | |
0c151062 LP |
570 | if (info->ops && info->ops->init) { |
571 | ret = info->ops->init(pfc); | |
572 | if (ret < 0) | |
573 | return ret; | |
574 | } | |
575 | ||
0129801b WS |
576 | /* Enable dummy states for those platforms without pinctrl support */ |
577 | if (!of_have_populated_dt()) | |
578 | pinctrl_provide_dummies(); | |
b0e10211 | 579 | |
acac8ed5 LP |
580 | ret = sh_pfc_init_ranges(pfc); |
581 | if (ret < 0) | |
582 | return ret; | |
583 | ||
ca5481c6 PM |
584 | /* |
585 | * Initialize pinctrl bindings first | |
586 | */ | |
c6193eac | 587 | ret = sh_pfc_register_pinctrl(pfc); |
f9492fda | 588 | if (unlikely(ret != 0)) |
0a332c96 | 589 | return ret; |
ca5481c6 | 590 | |
abc60d48 | 591 | #ifdef CONFIG_PINCTRL_SH_PFC_GPIO |
ca5481c6 PM |
592 | /* |
593 | * Then the GPIO chip | |
594 | */ | |
c6193eac | 595 | ret = sh_pfc_register_gpiochip(pfc); |
6f6a4a68 | 596 | if (unlikely(ret != 0)) { |
ca5481c6 PM |
597 | /* |
598 | * If the GPIO chip fails to come up we still leave the | |
599 | * PFC state as it is, given that there are already | |
600 | * extant users of it that have succeeded by this point. | |
601 | */ | |
9a643c9a | 602 | dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n"); |
b3c185a7 | 603 | } |
6f6a4a68 | 604 | #endif |
b72421d8 | 605 | |
c6193eac LP |
606 | platform_set_drvdata(pdev, pfc); |
607 | ||
9a643c9a | 608 | dev_info(pfc->dev, "%s support registered\n", info->name); |
ca5481c6 | 609 | |
b3c185a7 | 610 | return 0; |
b72421d8 | 611 | } |
6f6a4a68 | 612 | |
c6193eac | 613 | static const struct platform_device_id sh_pfc_id_table[] = { |
ccda552e LP |
614 | #ifdef CONFIG_PINCTRL_PFC_SH7203 |
615 | { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info }, | |
616 | #endif | |
a8d42fc4 LP |
617 | #ifdef CONFIG_PINCTRL_PFC_SH7264 |
618 | { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info }, | |
619 | #endif | |
f5e811f2 LP |
620 | #ifdef CONFIG_PINCTRL_PFC_SH7269 |
621 | { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info }, | |
622 | #endif | |
74cad605 LP |
623 | #ifdef CONFIG_PINCTRL_PFC_SH7720 |
624 | { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info }, | |
f5e25ae5 LP |
625 | #endif |
626 | #ifdef CONFIG_PINCTRL_PFC_SH7722 | |
627 | { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info }, | |
d05afa0a LP |
628 | #endif |
629 | #ifdef CONFIG_PINCTRL_PFC_SH7723 | |
630 | { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info }, | |
0ff25bab LP |
631 | #endif |
632 | #ifdef CONFIG_PINCTRL_PFC_SH7724 | |
633 | { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info }, | |
ac1ebc21 LP |
634 | #endif |
635 | #ifdef CONFIG_PINCTRL_PFC_SH7734 | |
636 | { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info }, | |
0bb92677 LP |
637 | #endif |
638 | #ifdef CONFIG_PINCTRL_PFC_SH7757 | |
639 | { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info }, | |
a56398e9 LP |
640 | #endif |
641 | #ifdef CONFIG_PINCTRL_PFC_SH7785 | |
642 | { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info }, | |
d2a31bdd LP |
643 | #endif |
644 | #ifdef CONFIG_PINCTRL_PFC_SH7786 | |
645 | { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info }, | |
d5d9a818 LP |
646 | #endif |
647 | #ifdef CONFIG_PINCTRL_PFC_SHX3 | |
648 | { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info }, | |
d5b1521a | 649 | #endif |
c6193eac LP |
650 | { "sh-pfc", 0 }, |
651 | { }, | |
652 | }; | |
c6193eac LP |
653 | |
654 | static struct platform_driver sh_pfc_driver = { | |
655 | .probe = sh_pfc_probe, | |
c6193eac LP |
656 | .id_table = sh_pfc_id_table, |
657 | .driver = { | |
658 | .name = DRV_NAME, | |
fe1c9a82 | 659 | .of_match_table = of_match_ptr(sh_pfc_of_table), |
c6193eac LP |
660 | }, |
661 | }; | |
662 | ||
40ee6fce LP |
663 | static int __init sh_pfc_init(void) |
664 | { | |
665 | return platform_driver_register(&sh_pfc_driver); | |
c6193eac | 666 | } |
40ee6fce | 667 | postcore_initcall(sh_pfc_init); |