Commit | Line | Data |
---|---|---|
b3c185a7 PM |
1 | /* |
2 | * SuperH Pin Function Controller GPIO driver. | |
3 | * | |
4 | * Copyright (C) 2008 Magnus Damm | |
5 | * Copyright (C) 2009 - 2012 Paul Mundt | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
c6193eac LP |
11 | |
12 | #define pr_fmt(fmt) KBUILD_MODNAME " gpio: " fmt | |
b3c185a7 | 13 | |
1724acfd | 14 | #include <linux/device.h> |
b3c185a7 | 15 | #include <linux/gpio.h> |
90efde22 | 16 | #include <linux/init.h> |
b3c185a7 | 17 | #include <linux/module.h> |
ca5481c6 | 18 | #include <linux/pinctrl/consumer.h> |
90efde22 LP |
19 | #include <linux/slab.h> |
20 | #include <linux/spinlock.h> | |
b3c185a7 | 21 | |
f9165132 LP |
22 | #include "core.h" |
23 | ||
b3c185a7 PM |
24 | struct sh_pfc_chip { |
25 | struct sh_pfc *pfc; | |
26 | struct gpio_chip gpio_chip; | |
27 | }; | |
28 | ||
29 | static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc) | |
30 | { | |
31 | return container_of(gc, struct sh_pfc_chip, gpio_chip); | |
32 | } | |
33 | ||
34 | static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc) | |
35 | { | |
36 | return gpio_to_pfc_chip(gc)->pfc; | |
37 | } | |
38 | ||
41f1219f LP |
39 | static void gpio_get_data_reg(struct sh_pfc *pfc, unsigned int gpio, |
40 | struct pinmux_data_reg **dr, unsigned int *bit) | |
41 | { | |
42 | struct sh_pfc_pin *gpiop = sh_pfc_get_pin(pfc, gpio); | |
43 | ||
44 | *dr = pfc->info->data_regs | |
45 | + ((gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT); | |
46 | *bit = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT; | |
47 | } | |
48 | ||
49 | static void gpio_setup_data_reg(struct sh_pfc *pfc, unsigned gpio) | |
50 | { | |
51 | struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio]; | |
52 | struct pinmux_data_reg *data_reg; | |
53 | int k, n; | |
54 | ||
55 | k = 0; | |
56 | while (1) { | |
57 | data_reg = pfc->info->data_regs + k; | |
58 | ||
59 | if (!data_reg->reg_width) | |
60 | break; | |
61 | ||
62 | data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg); | |
63 | ||
64 | for (n = 0; n < data_reg->reg_width; n++) { | |
65 | if (data_reg->enum_ids[n] == gpiop->enum_id) { | |
66 | gpiop->flags &= ~PINMUX_FLAG_DREG; | |
67 | gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT); | |
68 | gpiop->flags &= ~PINMUX_FLAG_DBIT; | |
69 | gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT); | |
70 | return; | |
71 | } | |
72 | } | |
73 | k++; | |
74 | } | |
75 | ||
76 | BUG(); | |
77 | } | |
78 | ||
79 | static void gpio_setup_data_regs(struct sh_pfc *pfc) | |
80 | { | |
81 | struct pinmux_data_reg *drp; | |
82 | int k; | |
83 | ||
84 | for (k = 0; k < pfc->info->nr_pins; k++) { | |
85 | if (pfc->info->pins[k].enum_id == 0) | |
86 | continue; | |
87 | ||
88 | gpio_setup_data_reg(pfc, k); | |
89 | } | |
90 | ||
91 | k = 0; | |
92 | while (1) { | |
93 | drp = pfc->info->data_regs + k; | |
94 | ||
95 | if (!drp->reg_width) | |
96 | break; | |
97 | ||
98 | drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg, | |
99 | drp->reg_width); | |
100 | k++; | |
101 | } | |
102 | } | |
103 | ||
16883814 LP |
104 | /* ----------------------------------------------------------------------------- |
105 | * Pin GPIOs | |
106 | */ | |
b3c185a7 | 107 | |
16883814 | 108 | static int gpio_pin_request(struct gpio_chip *gc, unsigned offset) |
b3c185a7 | 109 | { |
0b73ee5d | 110 | struct sh_pfc *pfc = gpio_to_pfc(gc); |
934cb02b | 111 | struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset); |
0b73ee5d | 112 | |
63d57383 | 113 | if (pin == NULL || pin->enum_id == 0) |
0b73ee5d LP |
114 | return -EINVAL; |
115 | ||
16883814 | 116 | return pinctrl_request_gpio(offset); |
b3c185a7 PM |
117 | } |
118 | ||
16883814 | 119 | static void gpio_pin_free(struct gpio_chip *gc, unsigned offset) |
b3c185a7 | 120 | { |
16883814 | 121 | return pinctrl_free_gpio(offset); |
b3c185a7 PM |
122 | } |
123 | ||
16883814 | 124 | static void gpio_pin_set_value(struct sh_pfc *pfc, unsigned offset, int value) |
b3c185a7 | 125 | { |
0b73ee5d | 126 | struct pinmux_data_reg *dr; |
41f1219f LP |
127 | unsigned long pos; |
128 | unsigned int bit; | |
b3c185a7 | 129 | |
41f1219f LP |
130 | gpio_get_data_reg(pfc, offset, &dr, &bit); |
131 | ||
132 | pos = dr->reg_width - (bit + 1); | |
133 | ||
134 | if (value) | |
135 | set_bit(pos, &dr->reg_shadow); | |
136 | else | |
137 | clear_bit(pos, &dr->reg_shadow); | |
138 | ||
139 | sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow); | |
b3c185a7 PM |
140 | } |
141 | ||
16883814 | 142 | static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset) |
ca5481c6 PM |
143 | { |
144 | return pinctrl_gpio_direction_input(offset); | |
145 | } | |
146 | ||
16883814 | 147 | static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset, |
ca5481c6 PM |
148 | int value) |
149 | { | |
16883814 | 150 | gpio_pin_set_value(gpio_to_pfc(gc), offset, value); |
ca5481c6 PM |
151 | |
152 | return pinctrl_gpio_direction_output(offset); | |
153 | } | |
154 | ||
16883814 | 155 | static int gpio_pin_get(struct gpio_chip *gc, unsigned offset) |
b3c185a7 | 156 | { |
16883814 | 157 | struct sh_pfc *pfc = gpio_to_pfc(gc); |
0b73ee5d | 158 | struct pinmux_data_reg *dr; |
41f1219f LP |
159 | unsigned long pos; |
160 | unsigned int bit; | |
16883814 | 161 | |
41f1219f LP |
162 | gpio_get_data_reg(pfc, offset, &dr, &bit); |
163 | ||
164 | pos = dr->reg_width - (bit + 1); | |
165 | ||
166 | return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1; | |
b3c185a7 PM |
167 | } |
168 | ||
16883814 | 169 | static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value) |
b3c185a7 | 170 | { |
16883814 | 171 | gpio_pin_set_value(gpio_to_pfc(gc), offset, value); |
b3c185a7 PM |
172 | } |
173 | ||
16883814 | 174 | static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset) |
b3c185a7 PM |
175 | { |
176 | struct sh_pfc *pfc = gpio_to_pfc(gc); | |
c07f54f6 LP |
177 | int i, k; |
178 | ||
179 | for (i = 0; i < pfc->info->gpio_irq_size; i++) { | |
180 | unsigned short *gpios = pfc->info->gpio_irq[i].gpios; | |
181 | ||
182 | for (k = 0; gpios[k]; k++) { | |
183 | if (gpios[k] == offset) | |
184 | return pfc->info->gpio_irq[i].irq; | |
b3c185a7 PM |
185 | } |
186 | } | |
187 | ||
188 | return -ENOSYS; | |
189 | } | |
190 | ||
16883814 | 191 | static void gpio_pin_setup(struct sh_pfc_chip *chip) |
b3c185a7 PM |
192 | { |
193 | struct sh_pfc *pfc = chip->pfc; | |
194 | struct gpio_chip *gc = &chip->gpio_chip; | |
195 | ||
16883814 LP |
196 | gc->request = gpio_pin_request; |
197 | gc->free = gpio_pin_free; | |
198 | gc->direction_input = gpio_pin_direction_input; | |
199 | gc->get = gpio_pin_get; | |
200 | gc->direction_output = gpio_pin_direction_output; | |
201 | gc->set = gpio_pin_set; | |
202 | gc->to_irq = gpio_pin_to_irq; | |
b3c185a7 | 203 | |
19bb7fe3 | 204 | gc->label = pfc->info->name; |
16883814 | 205 | gc->dev = pfc->dev; |
b3c185a7 | 206 | gc->owner = THIS_MODULE; |
d7a7ca57 | 207 | gc->base = 0; |
63d57383 | 208 | gc->ngpio = pfc->nr_pins; |
b3c185a7 PM |
209 | } |
210 | ||
16883814 LP |
211 | /* ----------------------------------------------------------------------------- |
212 | * Function GPIOs | |
213 | */ | |
214 | ||
215 | static int gpio_function_request(struct gpio_chip *gc, unsigned offset) | |
216 | { | |
217 | struct sh_pfc *pfc = gpio_to_pfc(gc); | |
a68fdca9 | 218 | unsigned int mark = pfc->info->func_gpios[offset].enum_id; |
16883814 LP |
219 | unsigned long flags; |
220 | int ret = -EINVAL; | |
221 | ||
222 | pr_notice_once("Use of GPIO API for function requests is deprecated, convert to pinctrl\n"); | |
223 | ||
a68fdca9 | 224 | if (mark == 0) |
16883814 LP |
225 | return ret; |
226 | ||
227 | spin_lock_irqsave(&pfc->lock, flags); | |
228 | ||
a68fdca9 | 229 | if (sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_DRYRUN)) |
16883814 LP |
230 | goto done; |
231 | ||
a68fdca9 | 232 | if (sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_REQ)) |
16883814 LP |
233 | goto done; |
234 | ||
235 | ret = 0; | |
236 | ||
237 | done: | |
238 | spin_unlock_irqrestore(&pfc->lock, flags); | |
239 | return ret; | |
240 | } | |
241 | ||
242 | static void gpio_function_free(struct gpio_chip *gc, unsigned offset) | |
243 | { | |
244 | struct sh_pfc *pfc = gpio_to_pfc(gc); | |
a68fdca9 | 245 | unsigned int mark = pfc->info->func_gpios[offset].enum_id; |
16883814 LP |
246 | unsigned long flags; |
247 | ||
248 | spin_lock_irqsave(&pfc->lock, flags); | |
249 | ||
a68fdca9 | 250 | sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_FREE); |
16883814 LP |
251 | |
252 | spin_unlock_irqrestore(&pfc->lock, flags); | |
253 | } | |
254 | ||
255 | static void gpio_function_setup(struct sh_pfc_chip *chip) | |
256 | { | |
257 | struct sh_pfc *pfc = chip->pfc; | |
258 | struct gpio_chip *gc = &chip->gpio_chip; | |
259 | ||
260 | gc->request = gpio_function_request; | |
261 | gc->free = gpio_function_free; | |
262 | ||
263 | gc->label = pfc->info->name; | |
264 | gc->owner = THIS_MODULE; | |
63d57383 | 265 | gc->base = pfc->nr_pins; |
16883814 LP |
266 | gc->ngpio = pfc->info->nr_func_gpios; |
267 | } | |
268 | ||
269 | /* ----------------------------------------------------------------------------- | |
270 | * Register/unregister | |
271 | */ | |
272 | ||
273 | static struct sh_pfc_chip * | |
274 | sh_pfc_add_gpiochip(struct sh_pfc *pfc, void(*setup)(struct sh_pfc_chip *)) | |
b3c185a7 PM |
275 | { |
276 | struct sh_pfc_chip *chip; | |
277 | int ret; | |
278 | ||
1724acfd | 279 | chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL); |
b3c185a7 | 280 | if (unlikely(!chip)) |
16883814 | 281 | return ERR_PTR(-ENOMEM); |
b3c185a7 PM |
282 | |
283 | chip->pfc = pfc; | |
284 | ||
16883814 | 285 | setup(chip); |
b3c185a7 PM |
286 | |
287 | ret = gpiochip_add(&chip->gpio_chip); | |
1724acfd | 288 | if (unlikely(ret < 0)) |
16883814 LP |
289 | return ERR_PTR(ret); |
290 | ||
291 | pr_info("%s handling gpio %u -> %u\n", | |
292 | chip->gpio_chip.label, chip->gpio_chip.base, | |
293 | chip->gpio_chip.base + chip->gpio_chip.ngpio - 1); | |
294 | ||
295 | return chip; | |
296 | } | |
297 | ||
298 | int sh_pfc_register_gpiochip(struct sh_pfc *pfc) | |
299 | { | |
63d57383 LP |
300 | const struct pinmux_range *ranges; |
301 | struct pinmux_range def_range; | |
16883814 | 302 | struct sh_pfc_chip *chip; |
63d57383 LP |
303 | unsigned int nr_ranges; |
304 | unsigned int i; | |
247127f9 | 305 | int ret; |
16883814 | 306 | |
41f1219f LP |
307 | gpio_setup_data_regs(pfc); |
308 | ||
63d57383 | 309 | /* Register the real GPIOs chip. */ |
16883814 LP |
310 | chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup); |
311 | if (IS_ERR(chip)) | |
312 | return PTR_ERR(chip); | |
6f6a4a68 LP |
313 | |
314 | pfc->gpio = chip; | |
b3c185a7 | 315 | |
63d57383 LP |
316 | /* Register the GPIO to pin mappings. */ |
317 | if (pfc->info->ranges == NULL) { | |
318 | def_range.begin = 0; | |
319 | def_range.end = pfc->info->nr_pins - 1; | |
320 | ranges = &def_range; | |
321 | nr_ranges = 1; | |
322 | } else { | |
323 | ranges = pfc->info->ranges; | |
324 | nr_ranges = pfc->info->nr_ranges; | |
325 | } | |
326 | ||
327 | for (i = 0; i < nr_ranges; ++i) { | |
328 | const struct pinmux_range *range = &ranges[i]; | |
329 | ||
330 | ret = gpiochip_add_pin_range(&chip->gpio_chip, | |
331 | dev_name(pfc->dev), | |
332 | range->begin, range->begin, | |
333 | range->end - range->begin + 1); | |
334 | if (ret < 0) | |
335 | return ret; | |
336 | } | |
247127f9 | 337 | |
63d57383 | 338 | /* Register the function GPIOs chip. */ |
16883814 LP |
339 | chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup); |
340 | if (IS_ERR(chip)) | |
341 | return PTR_ERR(chip); | |
342 | ||
343 | pfc->func = chip; | |
b3c185a7 | 344 | |
b3c185a7 PM |
345 | return 0; |
346 | } | |
347 | ||
6f6a4a68 | 348 | int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc) |
b3c185a7 | 349 | { |
16883814 | 350 | int err; |
b3c185a7 PM |
351 | int ret; |
352 | ||
16883814 LP |
353 | ret = gpiochip_remove(&pfc->gpio->gpio_chip); |
354 | err = gpiochip_remove(&pfc->func->gpio_chip); | |
b3c185a7 | 355 | |
16883814 | 356 | return ret < 0 ? ret : err; |
b3c185a7 | 357 | } |