Commit | Line | Data |
---|---|---|
b3c185a7 PM |
1 | /* |
2 | * SuperH Pin Function Controller GPIO driver. | |
3 | * | |
4 | * Copyright (C) 2008 Magnus Damm | |
5 | * Copyright (C) 2009 - 2012 Paul Mundt | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
c6193eac | 11 | |
1724acfd | 12 | #include <linux/device.h> |
b3c185a7 | 13 | #include <linux/gpio.h> |
90efde22 | 14 | #include <linux/init.h> |
b3c185a7 | 15 | #include <linux/module.h> |
ca5481c6 | 16 | #include <linux/pinctrl/consumer.h> |
90efde22 LP |
17 | #include <linux/slab.h> |
18 | #include <linux/spinlock.h> | |
b3c185a7 | 19 | |
f9165132 LP |
20 | #include "core.h" |
21 | ||
51cb226b LP |
22 | struct sh_pfc_gpio_data_reg { |
23 | const struct pinmux_data_reg *info; | |
24 | unsigned long shadow; | |
25 | }; | |
26 | ||
1a0039dc LP |
27 | struct sh_pfc_gpio_pin { |
28 | u8 dbit; | |
29 | u8 dreg; | |
30 | }; | |
31 | ||
b3c185a7 | 32 | struct sh_pfc_chip { |
1a0039dc LP |
33 | struct sh_pfc *pfc; |
34 | struct gpio_chip gpio_chip; | |
e51d5343 | 35 | |
1a0039dc | 36 | struct sh_pfc_window *mem; |
51cb226b | 37 | struct sh_pfc_gpio_data_reg *regs; |
1a0039dc | 38 | struct sh_pfc_gpio_pin *pins; |
b3c185a7 PM |
39 | }; |
40 | ||
41 | static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc) | |
42 | { | |
43 | return container_of(gc, struct sh_pfc_chip, gpio_chip); | |
44 | } | |
45 | ||
46 | static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc) | |
47 | { | |
48 | return gpio_to_pfc_chip(gc)->pfc; | |
49 | } | |
50 | ||
757b055a | 51 | static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset, |
51cb226b LP |
52 | struct sh_pfc_gpio_data_reg **reg, |
53 | unsigned int *bit) | |
41f1219f | 54 | { |
757b055a | 55 | int idx = sh_pfc_get_pin_index(chip->pfc, offset); |
1a0039dc | 56 | struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx]; |
41f1219f | 57 | |
1a0039dc LP |
58 | *reg = &chip->regs[gpio_pin->dreg]; |
59 | *bit = gpio_pin->dbit; | |
41f1219f LP |
60 | } |
61 | ||
e51d5343 LP |
62 | static unsigned long gpio_read_data_reg(struct sh_pfc_chip *chip, |
63 | const struct pinmux_data_reg *dreg) | |
41f1219f | 64 | { |
e51d5343 LP |
65 | void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt; |
66 | ||
67 | return sh_pfc_read_raw_reg(mem, dreg->reg_width); | |
68 | } | |
41f1219f | 69 | |
e51d5343 LP |
70 | static void gpio_write_data_reg(struct sh_pfc_chip *chip, |
71 | const struct pinmux_data_reg *dreg, | |
72 | unsigned long value) | |
73 | { | |
74 | void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt; | |
41f1219f | 75 | |
e51d5343 LP |
76 | sh_pfc_write_raw_reg(mem, dreg->reg_width, value); |
77 | } | |
41f1219f | 78 | |
757b055a | 79 | static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx) |
e51d5343 | 80 | { |
1a0039dc | 81 | struct sh_pfc *pfc = chip->pfc; |
757b055a LP |
82 | struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx]; |
83 | const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; | |
e51d5343 LP |
84 | const struct pinmux_data_reg *dreg; |
85 | unsigned int bit; | |
86 | unsigned int i; | |
41f1219f | 87 | |
e51d5343 LP |
88 | for (i = 0, dreg = pfc->info->data_regs; dreg->reg; ++i, ++dreg) { |
89 | for (bit = 0; bit < dreg->reg_width; bit++) { | |
1a0039dc LP |
90 | if (dreg->enum_ids[bit] == pin->enum_id) { |
91 | gpio_pin->dreg = i; | |
92 | gpio_pin->dbit = bit; | |
41f1219f LP |
93 | return; |
94 | } | |
95 | } | |
41f1219f LP |
96 | } |
97 | ||
98 | BUG(); | |
99 | } | |
100 | ||
e51d5343 | 101 | static int gpio_setup_data_regs(struct sh_pfc_chip *chip) |
41f1219f | 102 | { |
e51d5343 | 103 | struct sh_pfc *pfc = chip->pfc; |
51cb226b | 104 | const struct pinmux_data_reg *dreg; |
e51d5343 | 105 | unsigned int i; |
41f1219f | 106 | |
51cb226b LP |
107 | /* Count the number of data registers, allocate memory and initialize |
108 | * them. | |
109 | */ | |
110 | for (i = 0; pfc->info->data_regs[i].reg_width; ++i) | |
111 | ; | |
112 | ||
113 | chip->regs = devm_kzalloc(pfc->dev, i * sizeof(*chip->regs), | |
114 | GFP_KERNEL); | |
115 | if (chip->regs == NULL) | |
116 | return -ENOMEM; | |
117 | ||
118 | for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) { | |
119 | chip->regs[i].info = dreg; | |
120 | chip->regs[i].shadow = gpio_read_data_reg(chip, dreg); | |
121 | } | |
41f1219f | 122 | |
e51d5343 LP |
123 | for (i = 0; i < pfc->info->nr_pins; i++) { |
124 | if (pfc->info->pins[i].enum_id == 0) | |
125 | continue; | |
126 | ||
1a0039dc | 127 | gpio_setup_data_reg(chip, i); |
41f1219f | 128 | } |
e51d5343 LP |
129 | |
130 | return 0; | |
41f1219f LP |
131 | } |
132 | ||
16883814 LP |
133 | /* ----------------------------------------------------------------------------- |
134 | * Pin GPIOs | |
135 | */ | |
b3c185a7 | 136 | |
16883814 | 137 | static int gpio_pin_request(struct gpio_chip *gc, unsigned offset) |
b3c185a7 | 138 | { |
0b73ee5d | 139 | struct sh_pfc *pfc = gpio_to_pfc(gc); |
1a0039dc | 140 | int idx = sh_pfc_get_pin_index(pfc, offset); |
0b73ee5d | 141 | |
1a0039dc | 142 | if (idx < 0 || pfc->info->pins[idx].enum_id == 0) |
0b73ee5d LP |
143 | return -EINVAL; |
144 | ||
16883814 | 145 | return pinctrl_request_gpio(offset); |
b3c185a7 PM |
146 | } |
147 | ||
16883814 | 148 | static void gpio_pin_free(struct gpio_chip *gc, unsigned offset) |
b3c185a7 | 149 | { |
16883814 | 150 | return pinctrl_free_gpio(offset); |
b3c185a7 PM |
151 | } |
152 | ||
e51d5343 LP |
153 | static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset, |
154 | int value) | |
b3c185a7 | 155 | { |
51cb226b | 156 | struct sh_pfc_gpio_data_reg *reg; |
41f1219f LP |
157 | unsigned long pos; |
158 | unsigned int bit; | |
b3c185a7 | 159 | |
51cb226b | 160 | gpio_get_data_reg(chip, offset, ®, &bit); |
41f1219f | 161 | |
51cb226b | 162 | pos = reg->info->reg_width - (bit + 1); |
41f1219f LP |
163 | |
164 | if (value) | |
51cb226b | 165 | set_bit(pos, ®->shadow); |
41f1219f | 166 | else |
51cb226b | 167 | clear_bit(pos, ®->shadow); |
41f1219f | 168 | |
51cb226b | 169 | gpio_write_data_reg(chip, reg->info, reg->shadow); |
b3c185a7 PM |
170 | } |
171 | ||
16883814 | 172 | static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset) |
ca5481c6 PM |
173 | { |
174 | return pinctrl_gpio_direction_input(offset); | |
175 | } | |
176 | ||
16883814 | 177 | static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset, |
ca5481c6 PM |
178 | int value) |
179 | { | |
e51d5343 | 180 | gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value); |
ca5481c6 PM |
181 | |
182 | return pinctrl_gpio_direction_output(offset); | |
183 | } | |
184 | ||
16883814 | 185 | static int gpio_pin_get(struct gpio_chip *gc, unsigned offset) |
b3c185a7 | 186 | { |
e51d5343 | 187 | struct sh_pfc_chip *chip = gpio_to_pfc_chip(gc); |
51cb226b | 188 | struct sh_pfc_gpio_data_reg *reg; |
41f1219f LP |
189 | unsigned long pos; |
190 | unsigned int bit; | |
16883814 | 191 | |
51cb226b | 192 | gpio_get_data_reg(chip, offset, ®, &bit); |
41f1219f | 193 | |
51cb226b | 194 | pos = reg->info->reg_width - (bit + 1); |
41f1219f | 195 | |
51cb226b | 196 | return (gpio_read_data_reg(chip, reg->info) >> pos) & 1; |
b3c185a7 PM |
197 | } |
198 | ||
16883814 | 199 | static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value) |
b3c185a7 | 200 | { |
e51d5343 | 201 | gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value); |
b3c185a7 PM |
202 | } |
203 | ||
16883814 | 204 | static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset) |
b3c185a7 PM |
205 | { |
206 | struct sh_pfc *pfc = gpio_to_pfc(gc); | |
8d72a7fc | 207 | unsigned int i, k; |
c07f54f6 LP |
208 | |
209 | for (i = 0; i < pfc->info->gpio_irq_size; i++) { | |
316b2550 | 210 | short *gpios = pfc->info->gpio_irq[i].gpios; |
c07f54f6 | 211 | |
316b2550 | 212 | for (k = 0; gpios[k] >= 0; k++) { |
c07f54f6 | 213 | if (gpios[k] == offset) |
70c8f01a | 214 | goto found; |
b3c185a7 PM |
215 | } |
216 | } | |
217 | ||
218 | return -ENOSYS; | |
70c8f01a LP |
219 | |
220 | found: | |
221 | if (pfc->num_irqs) | |
222 | return pfc->irqs[i]; | |
223 | else | |
224 | return pfc->info->gpio_irq[i].irq; | |
b3c185a7 PM |
225 | } |
226 | ||
e51d5343 | 227 | static int gpio_pin_setup(struct sh_pfc_chip *chip) |
b3c185a7 PM |
228 | { |
229 | struct sh_pfc *pfc = chip->pfc; | |
230 | struct gpio_chip *gc = &chip->gpio_chip; | |
e51d5343 LP |
231 | int ret; |
232 | ||
a1a3580c LP |
233 | chip->pins = devm_kzalloc(pfc->dev, pfc->info->nr_pins * |
234 | sizeof(*chip->pins), GFP_KERNEL); | |
1a0039dc LP |
235 | if (chip->pins == NULL) |
236 | return -ENOMEM; | |
237 | ||
e51d5343 LP |
238 | ret = gpio_setup_data_regs(chip); |
239 | if (ret < 0) | |
240 | return ret; | |
b3c185a7 | 241 | |
16883814 LP |
242 | gc->request = gpio_pin_request; |
243 | gc->free = gpio_pin_free; | |
244 | gc->direction_input = gpio_pin_direction_input; | |
245 | gc->get = gpio_pin_get; | |
246 | gc->direction_output = gpio_pin_direction_output; | |
247 | gc->set = gpio_pin_set; | |
248 | gc->to_irq = gpio_pin_to_irq; | |
b3c185a7 | 249 | |
19bb7fe3 | 250 | gc->label = pfc->info->name; |
16883814 | 251 | gc->dev = pfc->dev; |
b3c185a7 | 252 | gc->owner = THIS_MODULE; |
d7a7ca57 | 253 | gc->base = 0; |
28818fa5 | 254 | gc->ngpio = pfc->nr_gpio_pins; |
e51d5343 LP |
255 | |
256 | return 0; | |
b3c185a7 PM |
257 | } |
258 | ||
16883814 LP |
259 | /* ----------------------------------------------------------------------------- |
260 | * Function GPIOs | |
261 | */ | |
262 | ||
263 | static int gpio_function_request(struct gpio_chip *gc, unsigned offset) | |
264 | { | |
9a643c9a | 265 | static bool __print_once; |
16883814 | 266 | struct sh_pfc *pfc = gpio_to_pfc(gc); |
a68fdca9 | 267 | unsigned int mark = pfc->info->func_gpios[offset].enum_id; |
16883814 | 268 | unsigned long flags; |
b705c054 | 269 | int ret; |
16883814 | 270 | |
9a643c9a LP |
271 | if (!__print_once) { |
272 | dev_notice(pfc->dev, | |
273 | "Use of GPIO API for function requests is deprecated." | |
274 | " Convert to pinctrl\n"); | |
275 | __print_once = true; | |
276 | } | |
16883814 | 277 | |
a68fdca9 | 278 | if (mark == 0) |
b705c054 | 279 | return -EINVAL; |
16883814 LP |
280 | |
281 | spin_lock_irqsave(&pfc->lock, flags); | |
b705c054 | 282 | ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION); |
16883814 | 283 | spin_unlock_irqrestore(&pfc->lock, flags); |
b705c054 | 284 | |
16883814 LP |
285 | return ret; |
286 | } | |
287 | ||
288 | static void gpio_function_free(struct gpio_chip *gc, unsigned offset) | |
289 | { | |
16883814 LP |
290 | } |
291 | ||
e51d5343 | 292 | static int gpio_function_setup(struct sh_pfc_chip *chip) |
16883814 LP |
293 | { |
294 | struct sh_pfc *pfc = chip->pfc; | |
295 | struct gpio_chip *gc = &chip->gpio_chip; | |
296 | ||
297 | gc->request = gpio_function_request; | |
298 | gc->free = gpio_function_free; | |
299 | ||
300 | gc->label = pfc->info->name; | |
301 | gc->owner = THIS_MODULE; | |
28818fa5 | 302 | gc->base = pfc->nr_gpio_pins; |
16883814 | 303 | gc->ngpio = pfc->info->nr_func_gpios; |
e51d5343 LP |
304 | |
305 | return 0; | |
16883814 LP |
306 | } |
307 | ||
308 | /* ----------------------------------------------------------------------------- | |
309 | * Register/unregister | |
310 | */ | |
311 | ||
312 | static struct sh_pfc_chip * | |
ceef91dc LP |
313 | sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *), |
314 | struct sh_pfc_window *mem) | |
b3c185a7 PM |
315 | { |
316 | struct sh_pfc_chip *chip; | |
317 | int ret; | |
318 | ||
1724acfd | 319 | chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL); |
b3c185a7 | 320 | if (unlikely(!chip)) |
16883814 | 321 | return ERR_PTR(-ENOMEM); |
b3c185a7 | 322 | |
ceef91dc | 323 | chip->mem = mem; |
b3c185a7 PM |
324 | chip->pfc = pfc; |
325 | ||
e51d5343 LP |
326 | ret = setup(chip); |
327 | if (ret < 0) | |
328 | return ERR_PTR(ret); | |
b3c185a7 PM |
329 | |
330 | ret = gpiochip_add(&chip->gpio_chip); | |
1724acfd | 331 | if (unlikely(ret < 0)) |
16883814 LP |
332 | return ERR_PTR(ret); |
333 | ||
9a643c9a LP |
334 | dev_info(pfc->dev, "%s handling gpio %u -> %u\n", |
335 | chip->gpio_chip.label, chip->gpio_chip.base, | |
336 | chip->gpio_chip.base + chip->gpio_chip.ngpio - 1); | |
16883814 LP |
337 | |
338 | return chip; | |
339 | } | |
340 | ||
341 | int sh_pfc_register_gpiochip(struct sh_pfc *pfc) | |
342 | { | |
343 | struct sh_pfc_chip *chip; | |
63d57383 | 344 | unsigned int i; |
247127f9 | 345 | int ret; |
16883814 | 346 | |
1a4fd58f LP |
347 | if (pfc->info->data_regs == NULL) |
348 | return 0; | |
349 | ||
ceef91dc LP |
350 | /* Find the memory window that contain the GPIO registers. Boards that |
351 | * register a separate GPIO device will not supply a memory resource | |
352 | * that covers the data registers. In that case don't try to handle | |
353 | * GPIOs. | |
354 | */ | |
355 | for (i = 0; i < pfc->num_windows; ++i) { | |
5b46ac3a | 356 | struct sh_pfc_window *window = &pfc->windows[i]; |
ceef91dc LP |
357 | |
358 | if (pfc->info->data_regs[0].reg >= window->phys && | |
359 | pfc->info->data_regs[0].reg < window->phys + window->size) | |
360 | break; | |
361 | } | |
362 | ||
363 | if (i == pfc->num_windows) | |
364 | return 0; | |
365 | ||
70c8f01a LP |
366 | /* If we have IRQ resources make sure their number is correct. */ |
367 | if (pfc->num_irqs && pfc->num_irqs != pfc->info->gpio_irq_size) { | |
368 | dev_err(pfc->dev, "invalid number of IRQ resources\n"); | |
369 | return -EINVAL; | |
370 | } | |
371 | ||
63d57383 | 372 | /* Register the real GPIOs chip. */ |
5b46ac3a | 373 | chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->windows[i]); |
16883814 LP |
374 | if (IS_ERR(chip)) |
375 | return PTR_ERR(chip); | |
6f6a4a68 LP |
376 | |
377 | pfc->gpio = chip; | |
b3c185a7 | 378 | |
4f82e3ee LP |
379 | /* Register the GPIO to pin mappings. As pins with GPIO ports must come |
380 | * first in the ranges, skip the pins without GPIO ports by stopping at | |
381 | * the first range that contains such a pin. | |
382 | */ | |
acac8ed5 LP |
383 | for (i = 0; i < pfc->nr_ranges; ++i) { |
384 | const struct sh_pfc_pin_range *range = &pfc->ranges[i]; | |
63d57383 | 385 | |
4f82e3ee LP |
386 | if (range->start >= pfc->nr_gpio_pins) |
387 | break; | |
388 | ||
63d57383 LP |
389 | ret = gpiochip_add_pin_range(&chip->gpio_chip, |
390 | dev_name(pfc->dev), | |
acac8ed5 LP |
391 | range->start, range->start, |
392 | range->end - range->start + 1); | |
63d57383 LP |
393 | if (ret < 0) |
394 | return ret; | |
395 | } | |
247127f9 | 396 | |
63d57383 | 397 | /* Register the function GPIOs chip. */ |
542a564d LP |
398 | if (pfc->info->nr_func_gpios == 0) |
399 | return 0; | |
400 | ||
ceef91dc | 401 | chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL); |
16883814 LP |
402 | if (IS_ERR(chip)) |
403 | return PTR_ERR(chip); | |
404 | ||
405 | pfc->func = chip; | |
b3c185a7 | 406 | |
b3c185a7 PM |
407 | return 0; |
408 | } | |
409 | ||
6f6a4a68 | 410 | int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc) |
b3c185a7 | 411 | { |
16883814 | 412 | int err; |
b3c185a7 PM |
413 | int ret; |
414 | ||
16883814 LP |
415 | ret = gpiochip_remove(&pfc->gpio->gpio_chip); |
416 | err = gpiochip_remove(&pfc->func->gpio_chip); | |
b3c185a7 | 417 | |
16883814 | 418 | return ret < 0 ? ret : err; |
b3c185a7 | 419 | } |