Commit | Line | Data |
---|---|---|
b3c185a7 PM |
1 | /* |
2 | * SuperH Pin Function Controller GPIO driver. | |
3 | * | |
4 | * Copyright (C) 2008 Magnus Damm | |
5 | * Copyright (C) 2009 - 2012 Paul Mundt | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
c6193eac LP |
11 | |
12 | #define pr_fmt(fmt) KBUILD_MODNAME " gpio: " fmt | |
b3c185a7 | 13 | |
1724acfd | 14 | #include <linux/device.h> |
b3c185a7 | 15 | #include <linux/gpio.h> |
90efde22 | 16 | #include <linux/init.h> |
b3c185a7 | 17 | #include <linux/module.h> |
ca5481c6 | 18 | #include <linux/pinctrl/consumer.h> |
90efde22 LP |
19 | #include <linux/slab.h> |
20 | #include <linux/spinlock.h> | |
b3c185a7 | 21 | |
f9165132 LP |
22 | #include "core.h" |
23 | ||
b3c185a7 PM |
24 | struct sh_pfc_chip { |
25 | struct sh_pfc *pfc; | |
26 | struct gpio_chip gpio_chip; | |
27 | }; | |
28 | ||
29 | static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc) | |
30 | { | |
31 | return container_of(gc, struct sh_pfc_chip, gpio_chip); | |
32 | } | |
33 | ||
34 | static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc) | |
35 | { | |
36 | return gpio_to_pfc_chip(gc)->pfc; | |
37 | } | |
38 | ||
39 | static int sh_gpio_request(struct gpio_chip *gc, unsigned offset) | |
40 | { | |
2119f7c9 LP |
41 | struct sh_pfc *pfc = gpio_to_pfc(gc); |
42 | unsigned long flags; | |
43 | int ret = -EINVAL; | |
44 | ||
45 | if (offset < pfc->info->nr_pins) | |
46 | return pinctrl_request_gpio(offset); | |
47 | ||
48 | pr_notice_once("Use of GPIO API for function requests is deprecated, convert to pinctrl\n"); | |
49 | ||
50 | spin_lock_irqsave(&pfc->lock, flags); | |
51 | ||
52 | if (!sh_pfc_gpio_is_function(pfc, offset)) | |
53 | goto done; | |
54 | ||
55 | if (sh_pfc_config_gpio(pfc, offset, PINMUX_TYPE_FUNCTION, | |
56 | GPIO_CFG_DRYRUN)) | |
57 | goto done; | |
58 | ||
59 | if (sh_pfc_config_gpio(pfc, offset, PINMUX_TYPE_FUNCTION, | |
60 | GPIO_CFG_REQ)) | |
61 | goto done; | |
62 | ||
63 | ret = 0; | |
64 | ||
65 | done: | |
66 | spin_unlock_irqrestore(&pfc->lock, flags); | |
67 | return ret; | |
b3c185a7 PM |
68 | } |
69 | ||
70 | static void sh_gpio_free(struct gpio_chip *gc, unsigned offset) | |
71 | { | |
2119f7c9 LP |
72 | struct sh_pfc *pfc = gpio_to_pfc(gc); |
73 | unsigned long flags; | |
2119f7c9 LP |
74 | |
75 | if (offset < pfc->info->nr_pins) | |
76 | return pinctrl_free_gpio(offset); | |
77 | ||
78 | spin_lock_irqsave(&pfc->lock, flags); | |
79 | ||
24d6b36e | 80 | sh_pfc_config_gpio(pfc, offset, PINMUX_TYPE_FUNCTION, GPIO_CFG_FREE); |
2119f7c9 LP |
81 | |
82 | spin_unlock_irqrestore(&pfc->lock, flags); | |
b3c185a7 PM |
83 | } |
84 | ||
85 | static void sh_gpio_set_value(struct sh_pfc *pfc, unsigned gpio, int value) | |
86 | { | |
87 | struct pinmux_data_reg *dr = NULL; | |
88 | int bit = 0; | |
89 | ||
a99ebec1 | 90 | if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0) |
b3c185a7 PM |
91 | BUG(); |
92 | else | |
93 | sh_pfc_write_bit(dr, bit, value); | |
94 | } | |
95 | ||
b3c185a7 PM |
96 | static int sh_gpio_get_value(struct sh_pfc *pfc, unsigned gpio) |
97 | { | |
98 | struct pinmux_data_reg *dr = NULL; | |
99 | int bit = 0; | |
100 | ||
a99ebec1 | 101 | if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0) |
b3c185a7 PM |
102 | return -EINVAL; |
103 | ||
104 | return sh_pfc_read_bit(dr, bit); | |
105 | } | |
106 | ||
ca5481c6 PM |
107 | static int sh_gpio_direction_input(struct gpio_chip *gc, unsigned offset) |
108 | { | |
2119f7c9 LP |
109 | struct sh_pfc *pfc = gpio_to_pfc(gc); |
110 | ||
111 | if (offset >= pfc->info->nr_pins) { | |
112 | /* Function GPIOs can only be requested, never configured. */ | |
113 | return -EINVAL; | |
114 | } | |
115 | ||
ca5481c6 PM |
116 | return pinctrl_gpio_direction_input(offset); |
117 | } | |
118 | ||
119 | static int sh_gpio_direction_output(struct gpio_chip *gc, unsigned offset, | |
120 | int value) | |
121 | { | |
2119f7c9 LP |
122 | struct sh_pfc *pfc = gpio_to_pfc(gc); |
123 | ||
124 | if (offset >= pfc->info->nr_pins) { | |
125 | /* Function GPIOs can only be requested, never configured. */ | |
126 | return -EINVAL; | |
127 | } | |
128 | ||
ca5481c6 PM |
129 | sh_gpio_set_value(gpio_to_pfc(gc), offset, value); |
130 | ||
131 | return pinctrl_gpio_direction_output(offset); | |
132 | } | |
133 | ||
b3c185a7 PM |
134 | static int sh_gpio_get(struct gpio_chip *gc, unsigned offset) |
135 | { | |
136 | return sh_gpio_get_value(gpio_to_pfc(gc), offset); | |
137 | } | |
138 | ||
139 | static void sh_gpio_set(struct gpio_chip *gc, unsigned offset, int value) | |
140 | { | |
141 | sh_gpio_set_value(gpio_to_pfc(gc), offset, value); | |
142 | } | |
143 | ||
144 | static int sh_gpio_to_irq(struct gpio_chip *gc, unsigned offset) | |
145 | { | |
146 | struct sh_pfc *pfc = gpio_to_pfc(gc); | |
147 | pinmux_enum_t enum_id; | |
148 | pinmux_enum_t *enum_ids; | |
149 | int i, k, pos; | |
150 | ||
151 | pos = 0; | |
152 | enum_id = 0; | |
153 | while (1) { | |
154 | pos = sh_pfc_gpio_to_enum(pfc, offset, pos, &enum_id); | |
155 | if (pos <= 0 || !enum_id) | |
156 | break; | |
157 | ||
19bb7fe3 LP |
158 | for (i = 0; i < pfc->info->gpio_irq_size; i++) { |
159 | enum_ids = pfc->info->gpio_irq[i].enum_ids; | |
b3c185a7 PM |
160 | for (k = 0; enum_ids[k]; k++) { |
161 | if (enum_ids[k] == enum_id) | |
19bb7fe3 | 162 | return pfc->info->gpio_irq[i].irq; |
b3c185a7 PM |
163 | } |
164 | } | |
165 | } | |
166 | ||
167 | return -ENOSYS; | |
168 | } | |
169 | ||
170 | static void sh_pfc_gpio_setup(struct sh_pfc_chip *chip) | |
171 | { | |
172 | struct sh_pfc *pfc = chip->pfc; | |
173 | struct gpio_chip *gc = &chip->gpio_chip; | |
174 | ||
175 | gc->request = sh_gpio_request; | |
176 | gc->free = sh_gpio_free; | |
177 | gc->direction_input = sh_gpio_direction_input; | |
178 | gc->get = sh_gpio_get; | |
179 | gc->direction_output = sh_gpio_direction_output; | |
180 | gc->set = sh_gpio_set; | |
181 | gc->to_irq = sh_gpio_to_irq; | |
182 | ||
19bb7fe3 | 183 | gc->label = pfc->info->name; |
b3c185a7 | 184 | gc->owner = THIS_MODULE; |
d7a7ca57 | 185 | gc->base = 0; |
a373ed0a | 186 | gc->ngpio = pfc->info->nr_pins + pfc->info->nr_func_gpios; |
b3c185a7 PM |
187 | } |
188 | ||
189 | int sh_pfc_register_gpiochip(struct sh_pfc *pfc) | |
190 | { | |
191 | struct sh_pfc_chip *chip; | |
192 | int ret; | |
193 | ||
1724acfd | 194 | chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL); |
b3c185a7 PM |
195 | if (unlikely(!chip)) |
196 | return -ENOMEM; | |
197 | ||
198 | chip->pfc = pfc; | |
199 | ||
200 | sh_pfc_gpio_setup(chip); | |
201 | ||
202 | ret = gpiochip_add(&chip->gpio_chip); | |
1724acfd | 203 | if (unlikely(ret < 0)) |
6f6a4a68 | 204 | return ret; |
6f6a4a68 LP |
205 | |
206 | pfc->gpio = chip; | |
b3c185a7 | 207 | |
d7a7ca57 | 208 | pr_info("%s handling gpio 0 -> %u\n", |
a373ed0a LP |
209 | pfc->info->name, |
210 | pfc->info->nr_pins + pfc->info->nr_func_gpios - 1); | |
b3c185a7 | 211 | |
b3c185a7 PM |
212 | return 0; |
213 | } | |
214 | ||
6f6a4a68 | 215 | int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc) |
b3c185a7 | 216 | { |
6f6a4a68 | 217 | struct sh_pfc_chip *chip = pfc->gpio; |
b3c185a7 PM |
218 | int ret; |
219 | ||
220 | ret = gpiochip_remove(&chip->gpio_chip); | |
221 | if (unlikely(ret < 0)) | |
222 | return ret; | |
223 | ||
6f6a4a68 | 224 | pfc->gpio = NULL; |
b3c185a7 PM |
225 | return 0; |
226 | } |