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Merge tag 'pci-v3.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...
[deliverable/linux.git] / drivers / pinctrl / sh-pfc / pfc-r8a7790.c
CommitLineData
58c229e1
KM		 1/*
2 * R8A7790 processor support
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Magnus Damm
6 * Copyright (C) 2012 Renesas Solutions Corp.
7 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; version 2 of the
12 * License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
1627769b 23
58c229e1 24#include <linux/kernel.h>
1627769b
LP		 25#include <linux/platform_data/gpio-rcar.h>
26
58c229e1
KM		 27#include "core.h"
28#include "sh_pfc.h"
29
ed3e2604
LP		 30#define CPU_ALL_PORT(fn, sfx) \
31 PORT_GP_32(0, fn, sfx), \
32 PORT_GP_32(1, fn, sfx), \
33 PORT_GP_32(2, fn, sfx), \
34 PORT_GP_32(3, fn, sfx), \
35 PORT_GP_32(4, fn, sfx), \
36 PORT_GP_32(5, fn, sfx)
37
58c229e1
KM		 38enum {
39 PINMUX_RESERVED = 0,
40
41 PINMUX_DATA_BEGIN,
42 GP_ALL(DATA),
43 PINMUX_DATA_END,
44
58c229e1
KM		 45 PINMUX_FUNCTION_BEGIN,
46 GP_ALL(FN),
47
48 /* GPSR0 */
49 FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
50 FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
51 FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
52 FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
53 FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
54 FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
55 FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
56 FN_IP3_14_12, FN_IP3_17_15,
57
58 /* GPSR1 */
59 FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
60 FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
61 FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
62 FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
63 FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
64 FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
65 FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
66
67 /* GPSR2 */
68 FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
69 FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
70 FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
71 FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
72 FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
73 FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
74 FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
75
76 /* GPSR3 */
77 FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
78 FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
79 FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
80 FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
81 FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
82 FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
83 FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
84
85 /* GPSR4 */
86 FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
87 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
88 FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
89 FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
90 FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
91 FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
92 FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
93 FN_IP14_15_12, FN_IP14_18_16,
94
95 /* GPSR5 */
96 FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
97 FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
98 FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
99 FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
100 FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
101 FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
102 FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
103
104 /* IPSR0 */
105 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
106 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
107 FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
108 FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
109 FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
110 FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
111 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
112 FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
113 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
c4721249
SK		 114 FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
115 FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
05bcb07b 116 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1,
9f2edd41 117 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
58c229e1
KM		 118 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
119
120 /* IPSR1 */
9f2edd41 121 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
58c229e1 122 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
9f2edd41 123 FN_SCIFA1_TXD_C, FN_AVB_TXD2,
58c229e1 124 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
9f2edd41 125 FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
58c229e1
KM		 126 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
127 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
128 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
129 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
130 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
131 FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
132 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
133 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
134 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
135 FN_A0, FN_PWM3, FN_A1, FN_PWM4,
136
137 /* IPSR2 */
138 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
139 FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
140 FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
141 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
142 FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
143 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
1ddb66cd 144 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
58c229e1 145 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
1ddb66cd 146 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
58c229e1
KM		 147 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
148 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
149
150 /* IPSR3 */
151 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
152 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
153 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
154 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
155 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
156 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
157 FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
158 FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
159 FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
160 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
161 FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
162 FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
163 FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
164
165 /* IPSR4 */
166 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
167 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
168 FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
169 FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
170 FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
171 FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
172 FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
173 FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
174 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
175 FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
176 FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
177 FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
178 FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
179 FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
180 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
181
182 /* IPSR5 */
183 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
184 FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
c4721249
SK		 185 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
186 FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
58c229e1 187 FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
c4721249
SK		 188 FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
189 FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
58c229e1
KM		 190 FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
191 FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
192 FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
193 FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
194 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
195 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
196 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
197 FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
198 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
199 FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
200 FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
201 FN_SSI_WS78_B,
202
203 /* IPSR6 */
204 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
205 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
206 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
207 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
208 FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
209 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
210 FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
211 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
9f2edd41 212 FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
c4721249 213 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
9f2edd41 214 FN_I2C2_SCL_E, FN_ETH_RX_ER,
58c229e1 215 FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
9f2edd41 216 FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
58c229e1
KM		 217 FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
218 FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
9f2edd41 219 FN_HRX0_E, FN_STP_ISSYNC_0_B,
58c229e1 220 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
9f2edd41 221 FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
58c229e1 222 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
9f2edd41 223 FN_ETH_REF_CLK, FN_HCTS0_N_E,
58c229e1
KM		 224 FN_STP_IVCXO27_1_B, FN_HRX0_F,
225
226 /* IPSR7 */
9f2edd41 227 FN_ETH_MDIO, FN_HRTS0_N_E,
58c229e1 228 FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
14da999b 229 FN_HTX0_F, FN_BPFCLK_G,
9f2edd41
SK		 230 FN_ETH_TX_EN, FN_SIM0_CLK_C,
231 FN_HRTS0_N_F, FN_ETH_MAGIC,
232 FN_SIM0_RST_C, FN_ETH_TXD0,
58c229e1 233 FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
9f2edd41 234 FN_ETH_MDC, FN_STP_ISD_1_B,
58c229e1
KM		 235 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
236 FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
237 FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
238 FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
239 FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
f0681209 240 FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1,
58c229e1 241 FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
9f2edd41 242 FN_ATACS00_N, FN_AVB_RXD1,
58c229e1 243 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
58c229e1
KM		 244
245 /* IPSR8 */
246 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
9f2edd41 247 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
58c229e1
KM		 248 FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
249 FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
250 FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
251 FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
9f2edd41
SK		 252 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
253 FN_VI1_CLK, FN_AVB_RX_DV,
254 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
255 FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
256 FN_SCIFA1_RXD_D, FN_AVB_MDC,
58c229e1 257 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
9f2edd41 258 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
58c229e1 259 FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
9f2edd41 260 FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
58c229e1
KM		 261 FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
262 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
263 FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
264
265 /* IPSR9 */
266 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
267 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
268 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
269 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
270 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
c4721249
SK		 271 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
272 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
58c229e1 273 FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
c4721249
SK		 274 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
275 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
9f2edd41
SK		 276 FN_AVB_TX_EN, FN_SD1_CMD,
277 FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
278 FN_SD1_DAT0, FN_AVB_TX_CLK,
58c229e1 279 FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
9f2edd41
SK		 280 FN_SCIFB0_TXD_B, FN_SD1_DAT2,
281 FN_AVB_COL, FN_SCIFB0_CTS_N_B,
282 FN_SD1_DAT3, FN_AVB_RXD0,
58c229e1
KM		 283 FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
284 FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
c4721249 285 FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
58c229e1
KM		 286 FN_VI3_CLK_B,
287
288 /* IPSR10 */
289 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
c4721249 290 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
58c229e1
KM		 291 FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
292 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
293 FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
294 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
295 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
296 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
297 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
298 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
14da999b 299 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
58c229e1
KM		 300 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
301 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
14da999b 302 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
58c229e1
KM		 303 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
304 FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
305 FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
306 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
307 FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
308 FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
309 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
310 FN_GLO_I0_B, FN_VI3_DATA6_B,
311
312 /* IPSR11 */
313 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
314 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
315 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
316 FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
317 FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
318 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
319 FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
320 FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
321 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
322 FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
14da999b
SK		 323 FN_FMIN_E, FN_FMIN_F,
324 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
c4721249 325 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
7d2b2854 326 FN_I2C2_SDA_B, FN_MLB_DAT,
58c229e1 327 FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
14da999b 328 FN_SSI_SCK0129, FN_CAN_CLK_B,
58c229e1
KM		 329 FN_MOUT0,
330
331 /* IPSR12 */
332 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
333 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
334 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
335 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
336 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
337 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
338 FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
339 FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
340 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
341 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
342 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
343 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
344 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
345 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
346 FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
347 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
348 FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
349 FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
350 FN_CAN_DEBUGOUT4,
351
352 /* IPSR13 */
353 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
354 FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
14da999b 355 FN_SCIFB1_CTS_N, FN_BPFCLK_D,
58c229e1 356 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
14da999b 357 FN_BPFCLK_F, FN_SSI_WS6,
58c229e1
KM		 358 FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
359 FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
14da999b 360 FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
58c229e1
KM		 361 FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
362 FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
363 FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
364 FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
365 FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
366 FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
367 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
14da999b
SK		 368 FN_BPFCLK_E, FN_SSI_SDATA7_B,
369 FN_FMIN_G, FN_SSI_SDATA8,
58c229e1
KM		 370 FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
371 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
372 FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
373 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
374 FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
375
376 /* IPSR14 */
377 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
378 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
379 FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
c4721249
SK		 380 FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
381 FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
58c229e1
KM		 382 FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
383 FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
384 FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
c4721249 385 FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
bcec7475 386 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
58c229e1
KM		 387 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
388 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
389 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
390 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
391 FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
392 FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
bcec7475 393 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
58c229e1
KM		 394 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
395 FN_HRTS0_N_C,
396
397 /* IPSR15 */
1ddb66cd 398 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
58c229e1 399 FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
1ddb66cd
SK		 400 FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
401 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
c4721249 402 FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
58c229e1
KM		 403 FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
404 FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
405 FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
406 FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
407 FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
408 FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
409 FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
5de880dd 410 FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
58c229e1
KM		 411 FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
412 FN_DU2_DG6, FN_LCDOUT14,
413
414 /* IPSR16 */
415 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
416 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
417 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
5de880dd 418 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
58c229e1
KM		 419 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
420 FN_TCLK1_B,
421
422 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
423 FN_SEL_SCIF1_4,
424 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
425 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
426 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
427 FN_SEL_SCIFB1_4,
428 FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
429 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
430 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
431 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
432 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
433 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
434 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
435 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
436 FN_SEL_VI3_0, FN_SEL_VI3_1,
437 FN_SEL_VI2_0, FN_SEL_VI2_1,
438 FN_SEL_VI1_0, FN_SEL_VI1_1,
439 FN_SEL_VI0_0, FN_SEL_VI0_1,
440 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
441 FN_SEL_LBS_0, FN_SEL_LBS_1,
442 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
443 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
444 FN_SEL_SOF0_0, FN_SEL_SOF0_1,
445
446 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
447 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
448 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
449 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
450 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
451 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
452 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
1ddb66cd 453 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
58c229e1
KM		 454 FN_SEL_ADI_0, FN_SEL_ADI_1,
455 FN_SEL_SSP_0, FN_SEL_SSP_1,
456 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
457 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
458 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
459 FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
460 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
58c229e1
KM		 461 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
462 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
463
464 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
465 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
466 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
467 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
468 FN_SEL_IIC2_4,
469 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
470 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
471 FN_SEL_I2C2_4,
472 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
473 PINMUX_FUNCTION_END,
474
475 PINMUX_MARK_BEGIN,
476
477 VI1_DATA7_VI1_B7_MARK,
478
479 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
480 USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
481 DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
482
483 D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
484 D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
485 VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
486 VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
487 VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
488 SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
489 VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
490 SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
491 VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
c4721249
SK		 492 IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
493 I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
05bcb07b 494 VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK,
9f2edd41 495 D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
58c229e1
KM		 496 VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
497
9f2edd41 498 D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
58c229e1 499 VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
9f2edd41 500 SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
58c229e1 501 VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
9f2edd41 502 SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
58c229e1
KM		 503 VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
504 D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
505 VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
506 D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
507 VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
508 SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
509 VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
510 D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
511 VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
512 A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
513
514 A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
515 PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
516 TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
517 A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
518 SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
519 A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
1ddb66cd 520 VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK,
58c229e1 521 A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
1ddb66cd 522 VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK,
58c229e1
KM		 523 A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
524 VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
525
526 A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
527 VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
528 A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
529 VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
530 A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
531 MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
532 VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
533 ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
534 ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
535 A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
536 AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
537 ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
538 VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
539
540 A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
541 A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
542 VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
543 VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
544 VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
545 VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
546 VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
547 VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
548 CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
549 VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
550 VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
551 MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
552 HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
553 VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
554 VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
555
556 EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
557 VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
558 EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
c4721249
SK		 559 VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
560 INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
58c229e1 561 MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
c4721249
SK		 562 VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
563 I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
58c229e1
KM		 564 CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
565 CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
566 VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
567 INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
568 VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
569 WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
570 VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
571 IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
572 VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
573 MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
574 VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
575 SSI_WS78_B_MARK,
576
577 DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
578 VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
579 DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
580 SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
581 INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
582 DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
583 MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
584 SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
9f2edd41 585 ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
c4721249 586 TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
9f2edd41 587 I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
58c229e1 588 STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
9f2edd41 589 IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
58c229e1
KM		 590 STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
591 SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
9f2edd41 592 HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
58c229e1 593 TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
9f2edd41 594 RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
58c229e1 595 STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
9f2edd41 596 ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
58c229e1
KM		 597 STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
598
9f2edd41 599 ETH_MDIO_MARK, HRTS0_N_E_MARK,
58c229e1 600 SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
14da999b 601 HTX0_F_MARK, BPFCLK_G_MARK,
9f2edd41
SK		 602 ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
603 HRTS0_N_F_MARK, ETH_MAGIC_MARK,
604 SIM0_RST_C_MARK, ETH_TXD0_MARK,
58c229e1 605 STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
9f2edd41 606 ETH_MDC_MARK, STP_ISD_1_B_MARK,
58c229e1
KM		 607 TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
608 SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
609 GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
610 STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
611 PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
f0681209 612 PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK,
58c229e1 613 AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
9f2edd41 614 ATACS00_N_MARK, AVB_RXD1_MARK,
58c229e1 615 VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
58c229e1
KM		 616
617 VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
9f2edd41 618 VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
58c229e1
KM		 619 AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
620 AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
621 AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
622 AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
9f2edd41
SK		 623 VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
624 VI1_CLK_MARK, AVB_RX_DV_MARK,
625 VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
626 AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
627 SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
58c229e1 628 VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
9f2edd41 629 VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
58c229e1 630 AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
9f2edd41 631 AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
58c229e1
KM		 632 AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
633 SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
634 SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
635
636 SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
637 SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
638 SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
639 SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
640 SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
c4721249
SK		 641 GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
642 I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
58c229e1 643 MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
c4721249
SK		 644 GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
645 I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
9f2edd41
SK		 646 AVB_TX_EN_MARK, SD1_CMD_MARK,
647 AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
648 SD1_DAT0_MARK, AVB_TX_CLK_MARK,
58c229e1 649 SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
9f2edd41
SK		 650 SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
651 AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
652 SD1_DAT3_MARK, AVB_RXD0_MARK,
58c229e1
KM		 653 SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
654 TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
c4721249 655 IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
58c229e1
KM		 656 VI3_CLK_B_MARK,
657
658 SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
c4721249 659 GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
58c229e1
KM		 660 SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
661 VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
662 VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
663 VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
664 TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
665 SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
666 VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
667 TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
14da999b 668 SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
58c229e1
KM		 669 VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
670 TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
14da999b 671 SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
58c229e1
KM		 672 VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
673 GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
674 MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
675 HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
676 VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
677 TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
678 VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
679 GLO_I0_B_MARK, VI3_DATA6_B_MARK,
680
681 SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
682 GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
683 TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
684 SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
685 MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
686 SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
687 MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
688 SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
689 VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
690 MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
14da999b
SK		 691 FMIN_E_MARK, FMIN_F_MARK,
692 MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
c4721249 693 MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
7d2b2854 694 I2C2_SDA_B_MARK, MLB_DAT_MARK,
58c229e1 695 SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
14da999b 696 SSI_SCK0129_MARK, CAN_CLK_B_MARK,
58c229e1
KM		 697 MOUT0_MARK,
698
699 SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
700 SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
701 SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
702 SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
703 SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
704 MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
705 STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
706 CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
707 SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
708 SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
709 MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
710 SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
711 MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
712 SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
713 CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
714 IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
715 CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
716 IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
717 CAN_DEBUGOUT4_MARK,
718
719 SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
720 LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
14da999b 721 SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
58c229e1 722 DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
14da999b 723 BPFCLK_F_MARK, SSI_WS6_MARK,
58c229e1
KM		 724 SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
725 LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
14da999b 726 FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
58c229e1
KM		 727 CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
728 SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
729 CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
730 SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
731 LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
732 STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
733 TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
14da999b
SK		 734 BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
735 FMIN_G_MARK, SSI_SDATA8_MARK,
58c229e1
KM		 736 STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
737 CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
738 STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
739 SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
740 SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
741
742 AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
743 DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
744 REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
c4721249
SK		 745 MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
746 I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
58c229e1
KM		 747 DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
748 TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
749 HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
c4721249 750 LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
bcec7475 751 SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
58c229e1
KM		 752 MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
753 SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
754 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
755 SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
756 LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
757 CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
bcec7475 758 SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
58c229e1
KM		 759 MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
760 HRTS0_N_C_MARK,
761
1ddb66cd 762 SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
58c229e1 763 LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
1ddb66cd
SK		 764 TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
765 SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
c4721249 766 IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
58c229e1
KM		 767 DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
768 DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
769 LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
770 LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
771 LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
772 DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
773 SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
5de880dd 774 HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
58c229e1
KM		 775 DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
776 DU2_DG6_MARK, LCDOUT14_MARK,
777
778 MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
779 DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
780 MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
5de880dd 781 ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
58c229e1
KM		 782 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
783 TCLK1_B_MARK,
f6aaaac9
GL		 784
785 I2C3_SCL_MARK, I2C3_SDA_MARK,
58c229e1
KM		 786 PINMUX_MARK_END,
787};
788
533743dc 789static const u16 pinmux_data[] = {
58c229e1
KM		 790 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
791
792 PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7),
793 PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
794 PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS),
795 PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN),
796 PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC),
797 PINMUX_DATA(AVS1_MARK, FN_AVS1),
798 PINMUX_DATA(AVS2_MARK, FN_AVS2),
799 PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0),
800 PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2),
801
802 PINMUX_IPSR_DATA(IP0_2_0, D0),
803 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
804 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0),
805 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0),
806 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1),
807 PINMUX_IPSR_DATA(IP0_5_3, D1),
808 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
809 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0),
810 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0),
811 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1),
812 PINMUX_IPSR_DATA(IP0_8_6, D2),
813 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
814 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0),
815 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0),
816 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1),
817 PINMUX_IPSR_DATA(IP0_11_9, D3),
818 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
819 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0),
820 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0),
821 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1),
822 PINMUX_IPSR_DATA(IP0_15_12, D4),
823 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
824 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
825 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0),
826 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0),
827 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1),
828 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1),
829 PINMUX_IPSR_DATA(IP0_19_16, D5),
830 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
831 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
832 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0),
833 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0),
834 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1),
835 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1),
836 PINMUX_IPSR_DATA(IP0_22_20, D6),
c4721249 837 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
58c229e1
KM		 838 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0),
839 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0),
840 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1),
c4721249 841 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
58c229e1
KM		 842 PINMUX_IPSR_DATA(IP0_26_23, D7),
843 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1),
c4721249 844 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
58c229e1
KM		 845 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0),
846 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0),
847 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1),
c4721249 848 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
05bcb07b 849 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, TCLK1, SEL_TMU1_0),
58c229e1
KM		 850 PINMUX_IPSR_DATA(IP0_30_27, D8),
851 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
852 PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0),
58c229e1
KM		 853 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0),
854 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1),
855 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
856
857 PINMUX_IPSR_DATA(IP1_3_0, D9),
858 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
859 PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1),
58c229e1
KM		 860 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0),
861 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1),
862 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
863 PINMUX_IPSR_DATA(IP1_7_4, D10),
864 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
865 PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2),
58c229e1
KM		 866 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0),
867 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1),
868 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
869 PINMUX_IPSR_DATA(IP1_11_8, D11),
870 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
871 PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3),
58c229e1
KM		 872 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0),
873 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1),
874 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
875 PINMUX_IPSR_DATA(IP1_14_12, D12),
876 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
877 PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4),
878 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
879 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
880 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
881 PINMUX_IPSR_DATA(IP1_17_15, D13),
0a664e3d 882 PINMUX_IPSR_DATA(IP1_17_15, AVB_TXD5),
58c229e1
KM		 883 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
884 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
885 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
886 PINMUX_IPSR_DATA(IP1_21_18, D14),
887 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
888 PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6),
889 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1),
890 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
891 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
892 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
893 PINMUX_IPSR_DATA(IP1_25_22, D15),
894 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
895 PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7),
896 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1),
897 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0),
898 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
899 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
900 PINMUX_IPSR_DATA(IP1_27_26, A0),
901 PINMUX_IPSR_DATA(IP1_27_26, PWM3),
902 PINMUX_IPSR_DATA(IP1_29_28, A1),
903 PINMUX_IPSR_DATA(IP1_29_28, PWM4),
904
905 PINMUX_IPSR_DATA(IP2_2_0, A2),
906 PINMUX_IPSR_DATA(IP2_2_0, PWM5),
907 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
908 PINMUX_IPSR_DATA(IP2_5_3, A3),
909 PINMUX_IPSR_DATA(IP2_5_3, PWM6),
910 PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
911 PINMUX_IPSR_DATA(IP2_8_6, A4),
912 PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
913 PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0),
914 PINMUX_IPSR_DATA(IP2_11_9, A5),
915 PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
916 PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1),
917 PINMUX_IPSR_DATA(IP2_14_12, A6),
918 PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
919 PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2),
920 PINMUX_IPSR_DATA(IP2_17_15, A7),
921 PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
922 PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B),
923 PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3),
924 PINMUX_IPSR_DATA(IP2_21_18, A8),
925 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
926 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
927 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0),
928 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1),
929 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
1ddb66cd 930 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, RX2_B, SEL_SCIF2_1),
58c229e1
KM		 931 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
932 PINMUX_IPSR_DATA(IP2_25_22, A9),
933 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
934 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
935 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0),
936 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1),
937 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
1ddb66cd 938 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, TX2_B, SEL_SCIF2_1),
58c229e1
KM		 939 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
940 PINMUX_IPSR_DATA(IP2_28_26, A10),
941 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
942 PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC),
943 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0),
944 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1),
945 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
946
947 PINMUX_IPSR_DATA(IP3_3_0, A11),
948 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
949 PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK),
950 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0),
951 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1),
952 PINMUX_IPSR_DATA(IP3_3_0, VI2_G0),
0a664e3d 953 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
58c229e1
KM		 954 PINMUX_IPSR_DATA(IP3_7_4, A12),
955 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
956 PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD),
957 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0),
958 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1),
959 PINMUX_IPSR_DATA(IP3_7_4, VI2_G1),
0a664e3d 960 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
58c229e1
KM		 961 PINMUX_IPSR_DATA(IP3_11_8, A13),
962 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
963 PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2),
964 PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD),
965 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0),
966 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1),
967 PINMUX_IPSR_DATA(IP3_11_8, VI2_G2),
0a664e3d 968 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
58c229e1
KM		 969 PINMUX_IPSR_DATA(IP3_14_12, A14),
970 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
971 PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N),
972 PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1),
973 PINMUX_IPSR_DATA(IP3_17_15, A15),
974 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
975 PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N),
976 PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2),
977 PINMUX_IPSR_DATA(IP3_19_18, A16),
978 PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N),
979 PINMUX_IPSR_DATA(IP3_22_20, A17),
980 PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1),
981 PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N),
982 PINMUX_IPSR_DATA(IP3_25_23, A18),
983 PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1),
984 PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N),
985 PINMUX_IPSR_DATA(IP3_28_26, A19),
986 PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
987 PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N),
988 PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
989 PINMUX_IPSR_DATA(IP3_31_29, A20),
990 PINMUX_IPSR_DATA(IP3_31_29, SPCLK),
991 PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0),
992 PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1),
993 PINMUX_IPSR_DATA(IP3_31_29, VI2_G4),
994
995 PINMUX_IPSR_DATA(IP4_2_0, A21),
996 PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0),
997 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0),
998 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1),
999 PINMUX_IPSR_DATA(IP4_2_0, VI2_G5),
1000 PINMUX_IPSR_DATA(IP4_5_3, A22),
1001 PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1),
1002 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0),
1003 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1),
1004 PINMUX_IPSR_DATA(IP4_5_3, VI2_G6),
1005 PINMUX_IPSR_DATA(IP4_8_6, A23),
1006 PINMUX_IPSR_DATA(IP4_8_6, IO2),
1007 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0),
1008 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1),
1009 PINMUX_IPSR_DATA(IP4_8_6, VI2_G7),
1010 PINMUX_IPSR_DATA(IP4_11_9, A24),
1011 PINMUX_IPSR_DATA(IP4_11_9, IO3),
1012 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0),
1013 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1),
1014 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
1015 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
1016 PINMUX_IPSR_DATA(IP4_14_12, A25),
1017 PINMUX_IPSR_DATA(IP4_14_12, SSL),
1018 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0),
1019 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1),
1020 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0),
1021 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
1022 PINMUX_IPSR_DATA(IP4_17_15, CS0_N),
1023 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0),
1024 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1),
1025 PINMUX_IPSR_DATA(IP4_17_15, VI2_G3),
1026 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
1027 PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26),
1028 PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN),
1029 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0),
1030 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1),
1031 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0),
1032 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
1033 PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N),
1034 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
1035 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0),
1036 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1),
1037 PINMUX_IPSR_DATA(IP4_23_21, VI2_R0),
1038 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
1039 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
1040 PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N),
1041 PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK),
1042 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
1043 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0),
1044 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
1045 PINMUX_IPSR_DATA(IP4_26_24, VI2_R1),
1046 PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N),
1047 PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN),
1048 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
1049 PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB),
1050 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0),
1051 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1),
1052 PINMUX_IPSR_DATA(IP4_29_27, VI2_R2),
1053
1054 PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N),
1055 PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG),
1056 PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD),
1057 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0),
1058 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1),
1059 PINMUX_IPSR_DATA(IP5_2_0, VI2_R3),
0a664e3d 1060 PINMUX_IPSR_DATA(IP5_5_3, EX_CS4_N),
58c229e1
KM		 1061 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
1062 PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N),
1063 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
c4721249 1064 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
58c229e1
KM		 1065 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
1066 PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N),
c4721249 1067 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
58c229e1
KM		 1068 PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N),
1069 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0),
1070 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
1071 PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N),
1072 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0),
1073 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1),
1074 PINMUX_IPSR_DATA(IP5_9_6, VI2_R4),
c4721249 1075 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
58c229e1 1076 PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N),
c4721249 1077 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
58c229e1
KM		 1078 PINMUX_IPSR_DATA(IP5_12_10, BS_N),
1079 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0),
1080 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
1081 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0),
1082 PINMUX_IPSR_DATA(IP5_12_10, DRACK0),
1083 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2),
1084 PINMUX_IPSR_DATA(IP5_14_13, RD_N),
1085 PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0),
1086 PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
1087 PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N),
1088 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0),
1089 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1),
1090 PINMUX_IPSR_DATA(IP5_17_15, VI2_R5),
1091 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
1092 PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N),
1093 PINMUX_IPSR_DATA(IP5_20_18, WE0_N),
1094 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0),
1095 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
1096 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
1097 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
1098 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
1099 PINMUX_IPSR_DATA(IP5_23_21, WE1_N),
1100 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0),
1101 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0),
1102 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0),
1103 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1),
1104 PINMUX_IPSR_DATA(IP5_23_21, VI2_R6),
1105 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
1106 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2),
0a664e3d 1107 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, EX_WAIT0, SEL_LBS_0),
58c229e1
KM		 1108 PINMUX_IPSR_DATA(IP5_26_24, IRQ3),
1109 PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N),
1110 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0),
1111 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
1112 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
1113 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
1114 PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N),
1115 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
1116 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
1117 PINMUX_IPSR_DATA(IP5_29_27, VI2_R7),
1118 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
1119 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
1120
1121 PINMUX_IPSR_DATA(IP6_2_0, DACK0),
1122 PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
1123 PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
1124 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
1125 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
1126 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
1127 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
1128 PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
1129 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
1130 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
1131 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
1132 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
1133 PINMUX_IPSR_DATA(IP6_8_6, DACK1),
1134 PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
1135 PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
1136 PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
1137 PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
1138 PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
1139 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
1140 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
1141 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
1142 PINMUX_IPSR_DATA(IP6_13_11, DACK2),
1143 PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
1144 PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
1145 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
1146 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
1147 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
1148 PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
58c229e1
KM		 1149 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
1150 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
1151 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
c4721249
SK		 1152 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
1153 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
58c229e1 1154 PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
58c229e1
KM		 1155 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
1156 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
1157 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
c4721249
SK		 1158 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
1159 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
58c229e1 1160 PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
58c229e1
KM		 1161 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
1162 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
1163 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
1164 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
1165 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
1166 PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
58c229e1
KM		 1167 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
1168 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
1169 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
1170 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2),
1171 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
1172 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
1173 PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
58c229e1
KM		 1174 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
1175 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
1176 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
1177 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
1178 PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
58c229e1
KM		 1179 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
1180 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
1181 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
1182
1183 PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
58c229e1
KM		 1184 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
1185 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
1186 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
1187 PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
0a664e3d
SK		 1188 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
1189 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_FM_6),
58c229e1 1190 PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
58c229e1
KM		 1191 PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
1192 PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
1193 PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
58c229e1
KM		 1194 PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
1195 PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
58c229e1
KM		 1196 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
1197 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
1198 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
1199 PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
58c229e1
KM		 1200 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
1201 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
1202 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
1203 PINMUX_IPSR_DATA(IP7_18_16, PWM0),
1204 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
1205 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
1206 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
1207 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2),
1208 PINMUX_IPSR_DATA(IP7_21_19, PWM1),
1209 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
1210 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
1211 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
1212 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
1213 PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
1214 PINMUX_IPSR_DATA(IP7_24_22, PWM2),
1215 PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
1216 PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
1217 PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
1218 PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2),
f0681209 1219 PINMUX_IPSR_DATA(IP7_26_25, DU_DOTCLKIN1),
58c229e1
KM		 1220 PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
1221 PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
1222 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
1223 PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
1224 PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
58c229e1
KM		 1225 PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
1226 PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
1227 PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
58c229e1
KM		 1228
1229 PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
1230 PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
1231 PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
58c229e1
KM		 1232 PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
1233 PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
1234 PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
1235 PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
1236 PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N),
1237 PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5),
1238 PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
1239 PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N),
1240 PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6),
1241 PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
1242 PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1),
1243 PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
1244 PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
1245 PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
58c229e1
KM		 1246 PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
1247 PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
58c229e1
KM		 1248 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0),
1249 PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
58c229e1
KM		 1250 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
1251 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
1252 PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
58c229e1
KM		 1253 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
1254 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
1255 PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
58c229e1
KM		 1256 PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
1257 PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
1258 PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
58c229e1
KM		 1259 PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
1260 PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
1261 PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
1262 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
1263 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
1264 PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
58c229e1 1265 PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
0a664e3d 1266 PINMUX_IPSR_DATA(IP8_26, AVB_PHY_INT),
58c229e1
KM		 1267 PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
1268 PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
1269 PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
1270 PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
1271 PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD),
1272 PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
1273 PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
1274
1275 PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0),
1276 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
1277 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
1278 PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1),
1279 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
1280 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
1281 PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2),
1282 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
1283 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
1284 PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3),
1285 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
1286 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
1287 PINMUX_IPSR_DATA(IP9_11_8, SD0_CD),
1288 PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6),
1289 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
1290 PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
1291 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0),
1292 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
c4721249
SK		 1293 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
1294 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
58c229e1
KM		 1295 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
1296 PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
1297 PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
1298 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
1299 PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
1300 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0),
1301 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
c4721249
SK		 1302 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
1303 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
58c229e1
KM		 1304 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
1305 PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
1306 PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
58c229e1
KM		 1307 PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
1308 PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
58c229e1
KM		 1309 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
1310 PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
1311 PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
58c229e1
KM		 1312 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
1313 PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
1314 PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
58c229e1
KM		 1315 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
1316 PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
1317 PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
58c229e1
KM		 1318 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
1319 PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
1320 PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
58c229e1
KM		 1321 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
1322 PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
1323 PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
1324 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
1325 PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
1326 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0),
1327 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
c4721249
SK		 1328 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
1329 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
58c229e1
KM		 1330 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
1331 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
1332
1333 PINMUX_IPSR_DATA(IP10_3_0, SD1_WP),
1334 PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7),
1335 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
1336 PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
1337 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0),
1338 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
c4721249
SK		 1339 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
1340 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
58c229e1
KM		 1341 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1),
1342 PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
1343 PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
1344 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0),
1345 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
1346 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
1347 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
1348 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
1349 PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD),
1350 PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD),
1351 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0),
1352 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
1353 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
1354 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3),
1355 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
1356 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
1357 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
1358 PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0),
1359 PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0),
1360 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1),
1361 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
1362 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
1363 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3),
1364 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
1365 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1),
1366 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
1367 PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
1368 PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
1369 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1),
58c229e1
KM		 1370 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
1371 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
1372 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3),
1373 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
1374 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
1375 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
1376 PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
1377 PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
1378 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1),
58c229e1
KM		 1379 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
1380 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
1381 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
1382 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
1383 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
1384 PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3),
1385 PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3),
1386 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0),
1387 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
1388 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
1389 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
1390 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
1391 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
1392 PINMUX_IPSR_DATA(IP10_29_26, SD2_CD),
1393 PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4),
1394 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
1395 PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP),
1396 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0),
1397 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
1398 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
1399 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
1400 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1),
1401 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
1402
1403 PINMUX_IPSR_DATA(IP11_3_0, SD2_WP),
1404 PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5),
1405 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
1406 PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN),
1407 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0),
1408 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
1409 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
1410 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
1411 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1),
1412 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
1413 PINMUX_IPSR_DATA(IP11_4, SD3_CLK),
1414 PINMUX_IPSR_DATA(IP11_4, MMC1_CLK),
1415 PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD),
1416 PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD),
1417 PINMUX_IPSR_DATA(IP11_6_5, MTS_N),
1418 PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0),
1419 PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0),
1420 PINMUX_IPSR_DATA(IP11_8_7, STM_N),
1421 PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1),
1422 PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1),
1423 PINMUX_IPSR_DATA(IP11_10_9, MDATA),
1424 PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2),
1425 PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2),
1426 PINMUX_IPSR_DATA(IP11_12_11, SDATA),
1427 PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3),
1428 PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3),
1429 PINMUX_IPSR_DATA(IP11_14_13, SCKZ),
1430 PINMUX_IPSR_DATA(IP11_17_15, SD3_CD),
1431 PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4),
1432 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
1433 PINMUX_IPSR_DATA(IP11_17_15, VSP),
1434 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0),
1435 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
1436 PINMUX_IPSR_DATA(IP11_21_18, SD3_WP),
1437 PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5),
1438 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
1439 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0),
1440 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2),
58c229e1 1441 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4),
58c229e1 1442 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5),
58c229e1 1443 PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
c4721249
SK		 1444 PINMUX_IPSR_MODSEL_DATA(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
1445 PINMUX_IPSR_MODSEL_DATA(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
58c229e1
KM		 1446 PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
1447 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
1448 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2),
c4721249
SK		 1449 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
1450 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
58c229e1 1451 PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
58c229e1
KM		 1452 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
1453 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2),
1454 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2),
58c229e1
KM		 1455 PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
1456 PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
1457 PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
1458
1459 PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129),
1460 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
1461 PINMUX_IPSR_DATA(IP12_1_0, MOUT1),
1462 PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0),
1463 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
1464 PINMUX_IPSR_DATA(IP12_3_2, MOUT2),
1465 PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1),
1466 PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
1467 PINMUX_IPSR_DATA(IP12_5_4, MOUT5),
1468 PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2),
1469 PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
0a664e3d 1470 PINMUX_IPSR_DATA(IP12_7_6, SSI_SCK1),
58c229e1
KM		 1471 PINMUX_IPSR_DATA(IP12_7_6, MOUT6),
1472 PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34),
1473 PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0),
1474 PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
1475 PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
1476 PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
1477 PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34),
1478 PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
1479 PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
1480 PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC),
1481 PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0),
1482 PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3),
1483 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
1484 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
1485 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
1486 PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK),
1487 PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4),
1488 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0),
1489 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
1490 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
1491 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
1492 PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0),
1493 PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4),
1494 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
1495 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
1496 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
1497 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
1498 PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1),
1499 PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4),
1500 PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
1501 PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
1502 PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2),
1503 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
1504 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
1505 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1),
1506 PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
1507 PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS),
1508 PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3),
1509 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0),
1510 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
1511 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1),
1512 PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
1513 PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE),
1514 PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4),
1515
1516 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
1517 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
1518 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1),
1519 PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2),
1520 PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2),
1521 PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5),
1522 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
1523 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
1524 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3),
58c229e1
KM		 1525 PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3),
1526 PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3),
1527 PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6),
1528 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5),
58c229e1
KM		 1529 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0),
1530 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
1531 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
1532 PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4),
1533 PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4),
1534 PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7),
1535 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
1536 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3),
58c229e1
KM		 1537 PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5),
1538 PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5),
1539 PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8),
1540 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
1541 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
1542 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0),
1543 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
1544 PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6),
1545 PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6),
1546 PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9),
1547 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0),
1548 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
1549 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
1550 PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N),
1551 PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7),
1552 PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7),
1553 PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10),
1554 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
1555 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0),
1556 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
1557 PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N),
1558 PINMUX_IPSR_DATA(IP13_22_19, TCLK2),
1559 PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS),
1560 PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11),
1561 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4),
58c229e1
KM		 1562 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
1563 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6),
58c229e1
KM		 1564 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
1565 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
1566 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
1567 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
1568 PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12),
1569 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
1570 PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9),
1571 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
1572 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
1573 PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1),
1574 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
1575 PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13),
1576 PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA),
1577 PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
1578 PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14),
1579
1580 PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB),
1581 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
1582 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
1583 PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE),
1584 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
1585 PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15),
1586 PINMUX_IPSR_DATA(IP14_2_0, REMOCON),
1587 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
1588 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0),
1589 PINMUX_IPSR_DATA(IP14_5_3, SCK0),
1590 PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2),
1591 PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2),
1592 PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10),
c4721249
SK		 1593 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
1594 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
58c229e1
KM		 1595 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
1596 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0),
1597 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0),
1598 PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0),
1599 PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0),
1600 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
1601 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0),
1602 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0),
1603 PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1),
1604 PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1),
1605 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
1606 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
0a664e3d 1607 PINMUX_IPSR_DATA(IP14_15_12, CTS0_N),
58c229e1
KM		 1608 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
1609 PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3),
0a664e3d
SK		 1610 PINMUX_IPSR_DATA(IP14_15_12, LCDOUT11),
1611 PINMUX_IPSR_DATA(IP14_15_12, PWM0_B),
c4721249
SK		 1612 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
1613 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
58c229e1
KM		 1614 PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
1615 PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
bcec7475 1616 PINMUX_IPSR_DATA(IP14_18_16, RTS0_N),
58c229e1
KM		 1617 PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1),
1618 PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0),
1619 PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8),
1620 PINMUX_IPSR_DATA(IP14_18_16, PWM1_B),
1621 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
1622 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0),
1623 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0),
1624 PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
1625 PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE),
1626 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
1627 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0),
1628 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0),
1629 PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1),
1630 PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9),
1631 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
1632 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0),
1633 PINMUX_IPSR_DATA(IP14_27_25, CTS1_N),
1634 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
1635 PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT),
1636 PINMUX_IPSR_DATA(IP14_27_25, QCLK),
1637 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
1638 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0),
bcec7475 1639 PINMUX_IPSR_DATA(IP14_30_28, RTS1_N),
58c229e1
KM		 1640 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
1641 PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT),
1642 PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE),
1643 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
1644
1645 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
1646 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0),
1ddb66cd 1647 PINMUX_IPSR_DATA(IP15_2_0, SCK2),
58c229e1
KM		 1648 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
1649 PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7),
1650 PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15),
0a664e3d 1651 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
58c229e1
KM		 1652 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1653 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0),
1ddb66cd 1654 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, TX2, SEL_SCIF2_0),
58c229e1
KM		 1655 PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0),
1656 PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16),
c4721249
SK		 1657 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
1658 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
58c229e1
KM		 1659 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
1660 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0),
1ddb66cd 1661 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, RX2, SEL_SCIF2_0),
58c229e1
KM		 1662 PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1),
1663 PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17),
c4721249
SK		 1664 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
1665 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
58c229e1
KM		 1666 PINMUX_IPSR_DATA(IP15_11_9, HSCK0),
1667 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
1668 PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4),
1669 PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12),
0a664e3d 1670 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
58c229e1
KM		 1671 PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0),
1672 PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2),
1673 PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18),
1674 PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0),
1675 PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3),
1676 PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19),
1677 PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
1678 PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9),
1679 PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4),
1680 PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20),
1681 PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
1682 PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9),
1683 PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5),
1684 PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21),
1685 PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
1686 PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
1687 PINMUX_IPSR_DATA(IP15_22_20, ADICLK),
1688 PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6),
1689 PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22),
1690 PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC),
1691 PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
1692 PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2),
1693 PINMUX_IPSR_DATA(IP15_25_23, ADIDATA),
1694 PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7),
1695 PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23),
5de880dd 1696 PINMUX_IPSR_MODSEL_DATA(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
58c229e1
KM		 1697 PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
1698 PINMUX_IPSR_DATA(IP15_27_26, ADICHS0),
1699 PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5),
1700 PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13),
1701 PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
1702 PINMUX_IPSR_DATA(IP15_29_28, ADICHS1),
1703 PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6),
1704 PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14),
1705
1706 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
1707 PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT),
1708 PINMUX_IPSR_DATA(IP16_2_0, ADICHS2),
1709 PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP),
1710 PINMUX_IPSR_DATA(IP16_2_0, QPOLA),
1711 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
1712 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
1713 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
1714 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
1715 PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2),
1716 PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP),
1717 PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE),
1718 PINMUX_IPSR_DATA(IP16_5_3, QPOLB),
5de880dd 1719 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
58c229e1
KM		 1720 PINMUX_IPSR_DATA(IP16_6, USB1_PWEN),
1721 PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
1722 PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
1723 PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
f6aaaac9
GL		 1724
1725 PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
1726 PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
58c229e1
KM		 1727};
1728
f6aaaac9
GL		 1729/* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */
1730#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1731#define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200)
1732#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1733
44a45b55 1734static const struct sh_pfc_pin pinmux_pins[] = {
58c229e1 1735 PINMUX_GPIO_GP_ALL(),
f6aaaac9
GL		 1736
1737 /* Pins not associated with a GPIO port */
1738 SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15),
1739 SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15),
58c229e1
KM		 1740};
1741
fcec5b22
KM		 1742/* - AUDIO CLOCK ------------------------------------------------------------ */
1743static const unsigned int audio_clk_a_pins[] = {
1744 /* CLK A */
1745 RCAR_GP_PIN(4, 25),
1746};
1747static const unsigned int audio_clk_a_mux[] = {
1748 AUDIO_CLKA_MARK,
1749};
1750static const unsigned int audio_clk_b_pins[] = {
1751 /* CLK B */
1752 RCAR_GP_PIN(4, 26),
1753};
1754static const unsigned int audio_clk_b_mux[] = {
1755 AUDIO_CLKB_MARK,
1756};
1757static const unsigned int audio_clk_c_pins[] = {
1758 /* CLK C */
1759 RCAR_GP_PIN(5, 27),
1760};
1761static const unsigned int audio_clk_c_mux[] = {
1762 AUDIO_CLKC_MARK,
1763};
1764static const unsigned int audio_clkout_pins[] = {
1765 /* CLK OUT */
1766 RCAR_GP_PIN(5, 16),
1767};
1768static const unsigned int audio_clkout_mux[] = {
1769 AUDIO_CLKOUT_MARK,
1770};
1771static const unsigned int audio_clkout_b_pins[] = {
1772 /* CLK OUT B */
1773 RCAR_GP_PIN(0, 23),
1774};
1775static const unsigned int audio_clkout_b_mux[] = {
1776 AUDIO_CLKOUT_B_MARK,
1777};
1778static const unsigned int audio_clkout_c_pins[] = {
1779 /* CLK OUT C */
1780 RCAR_GP_PIN(5, 27),
1781};
1782static const unsigned int audio_clkout_c_mux[] = {
1783 AUDIO_CLKOUT_C_MARK,
1784};
1785static const unsigned int audio_clkout_d_pins[] = {
1786 /* CLK OUT D */
1787 RCAR_GP_PIN(5, 20),
1788};
1789static const unsigned int audio_clkout_d_mux[] = {
1790 AUDIO_CLKOUT_D_MARK,
1791};
62783b71
LP		 1792/* - DU RGB ----------------------------------------------------------------- */
1793static const unsigned int du_rgb666_pins[] = {
1794 /* R[7:2], G[7:2], B[7:2] */
1795 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1796 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1797 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1798 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
1799 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1800 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
1801};
1802static const unsigned int du_rgb666_mux[] = {
1803 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1804 DU2_DR3_MARK, DU2_DR2_MARK,
1805 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1806 DU2_DG3_MARK, DU2_DG2_MARK,
1807 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1808 DU2_DB3_MARK, DU2_DB2_MARK,
1809};
1810static const unsigned int du_rgb888_pins[] = {
1811 /* R[7:0], G[7:0], B[7:0] */
1812 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1813 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1814 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4),
1815 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7),
1816 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1),
1817 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12),
1818 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),
1819 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
1820};
1821static const unsigned int du_rgb888_mux[] = {
1822 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1823 DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK,
1824 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1825 DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK,
1826 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1827 DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK,
1828};
1829static const unsigned int du_clk_out_0_pins[] = {
1830 /* CLKOUT */
1831 RCAR_GP_PIN(5, 2),
1832};
1833static const unsigned int du_clk_out_0_mux[] = {
1834 DU0_DOTCLKOUT_MARK
1835};
1836static const unsigned int du_clk_out_1_pins[] = {
1837 /* CLKOUT */
1838 RCAR_GP_PIN(5, 3),
1839};
1840static const unsigned int du_clk_out_1_mux[] = {
1841 DU1_DOTCLKOUT_MARK
1842};
1843static const unsigned int du_sync_0_pins[] = {
1844 /* VSYNC, HSYNC, DISP */
1845 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0),
1846};
1847static const unsigned int du_sync_0_mux[] = {
1848 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
1849 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
1850};
1851static const unsigned int du_sync_1_pins[] = {
1852 /* VSYNC, HSYNC, DISP */
1853 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16),
1854};
1855static const unsigned int du_sync_1_mux[] = {
1856 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
1857 DU2_DISP_MARK
1858};
1859static const unsigned int du_cde_pins[] = {
1860 /* CDE */
1861 RCAR_GP_PIN(5, 17),
1862};
1863static const unsigned int du_cde_mux[] = {
1864 DU2_CDE_MARK,
1865};
1866/* - DU0 -------------------------------------------------------------------- */
1867static const unsigned int du0_clk_in_pins[] = {
1868 /* CLKIN */
1869 RCAR_GP_PIN(5, 26),
1870};
1871static const unsigned int du0_clk_in_mux[] = {
1872 DU_DOTCLKIN0_MARK
1873};
1874/* - DU1 -------------------------------------------------------------------- */
1875static const unsigned int du1_clk_in_pins[] = {
1876 /* CLKIN */
1877 RCAR_GP_PIN(5, 27),
1878};
1879static const unsigned int du1_clk_in_mux[] = {
1880 DU_DOTCLKIN1_MARK,
1881};
1882/* - DU2 -------------------------------------------------------------------- */
1883static const unsigned int du2_clk_in_pins[] = {
1884 /* CLKIN */
1885 RCAR_GP_PIN(5, 28),
1886};
1887static const unsigned int du2_clk_in_mux[] = {
1888 DU_DOTCLKIN2_MARK,
1889};
1627769b
LP		 1890/* - ETH -------------------------------------------------------------------- */
1891static const unsigned int eth_link_pins[] = {
1892 /* LINK */
1893 RCAR_GP_PIN(2, 22),
1894};
1895static const unsigned int eth_link_mux[] = {
1896 ETH_LINK_MARK,
1897};
1898static const unsigned int eth_magic_pins[] = {
1899 /* MAGIC */
1900 RCAR_GP_PIN(2, 27),
1901};
1902static const unsigned int eth_magic_mux[] = {
1903 ETH_MAGIC_MARK,
1904};
1905static const unsigned int eth_mdio_pins[] = {
1906 /* MDC, MDIO */
1907 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
1908};
1909static const unsigned int eth_mdio_mux[] = {
1910 ETH_MDC_MARK, ETH_MDIO_MARK,
1911};
1912static const unsigned int eth_rmii_pins[] = {
1913 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1914 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
1915 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
1916 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
1917};
1918static const unsigned int eth_rmii_mux[] = {
1919 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1920 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
1921};
fbd0ca3d
UH		 1922/* - HSCIF0 ----------------------------------------------------------------- */
1923static const unsigned int hscif0_data_pins[] = {
1924 /* RX, TX */
1925 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1926};
1927static const unsigned int hscif0_data_mux[] = {
1928 HRX0_MARK, HTX0_MARK,
1929};
1930static const unsigned int hscif0_clk_pins[] = {
1931 /* SCK */
1932 RCAR_GP_PIN(5, 7),
1933};
1934static const unsigned int hscif0_clk_mux[] = {
1935 HSCK0_MARK,
1936};
1937static const unsigned int hscif0_ctrl_pins[] = {
1938 /* RTS, CTS */
1939 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
1940};
1941static const unsigned int hscif0_ctrl_mux[] = {
1942 HRTS0_N_MARK, HCTS0_N_MARK,
1943};
1944static const unsigned int hscif0_data_b_pins[] = {
1945 /* RX, TX */
1946 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
1947};
1948static const unsigned int hscif0_data_b_mux[] = {
1949 HRX0_B_MARK, HTX0_B_MARK,
1950};
1951static const unsigned int hscif0_ctrl_b_pins[] = {
1952 /* RTS, CTS */
1953 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
1954};
1955static const unsigned int hscif0_ctrl_b_mux[] = {
1956 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
1957};
1958static const unsigned int hscif0_data_c_pins[] = {
1959 /* RX, TX */
1960 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
1961};
1962static const unsigned int hscif0_data_c_mux[] = {
1963 HRX0_C_MARK, HTX0_C_MARK,
1964};
1965static const unsigned int hscif0_ctrl_c_pins[] = {
1966 /* RTS, CTS */
1967 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
1968};
1969static const unsigned int hscif0_ctrl_c_mux[] = {
1970 HRTS0_N_C_MARK, HCTS0_N_C_MARK,
1971};
1972static const unsigned int hscif0_data_d_pins[] = {
1973 /* RX, TX */
1974 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
1975};
1976static const unsigned int hscif0_data_d_mux[] = {
1977 HRX0_D_MARK, HTX0_D_MARK,
1978};
1979static const unsigned int hscif0_ctrl_d_pins[] = {
1980 /* RTS, CTS */
1981 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
1982};
1983static const unsigned int hscif0_ctrl_d_mux[] = {
1984 HRTS0_N_D_MARK, HCTS0_N_D_MARK,
1985};
1986static const unsigned int hscif0_data_e_pins[] = {
1987 /* RX, TX */
1988 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1989};
1990static const unsigned int hscif0_data_e_mux[] = {
1991 HRX0_E_MARK, HTX0_E_MARK,
1992};
1993static const unsigned int hscif0_ctrl_e_pins[] = {
1994 /* RTS, CTS */
1995 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
1996};
1997static const unsigned int hscif0_ctrl_e_mux[] = {
1998 HRTS0_N_E_MARK, HCTS0_N_E_MARK,
1999};
2000static const unsigned int hscif0_data_f_pins[] = {
2001 /* RX, TX */
2002 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
2003};
2004static const unsigned int hscif0_data_f_mux[] = {
2005 HRX0_F_MARK, HTX0_F_MARK,
2006};
2007static const unsigned int hscif0_ctrl_f_pins[] = {
2008 /* RTS, CTS */
2009 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
2010};
2011static const unsigned int hscif0_ctrl_f_mux[] = {
2012 HRTS0_N_F_MARK, HCTS0_N_F_MARK,
2013};
2014/* - HSCIF1 ----------------------------------------------------------------- */
2015static const unsigned int hscif1_data_pins[] = {
2016 /* RX, TX */
2017 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2018};
2019static const unsigned int hscif1_data_mux[] = {
2020 HRX1_MARK, HTX1_MARK,
2021};
2022static const unsigned int hscif1_clk_pins[] = {
2023 /* SCK */
2024 RCAR_GP_PIN(4, 27),
2025};
2026static const unsigned int hscif1_clk_mux[] = {
2027 HSCK1_MARK,
2028};
2029static const unsigned int hscif1_ctrl_pins[] = {
2030 /* RTS, CTS */
2031 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2032};
2033static const unsigned int hscif1_ctrl_mux[] = {
2034 HRTS1_N_MARK, HCTS1_N_MARK,
2035};
2036static const unsigned int hscif1_data_b_pins[] = {
2037 /* RX, TX */
2038 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
2039};
2040static const unsigned int hscif1_data_b_mux[] = {
2041 HRX1_B_MARK, HTX1_B_MARK,
2042};
2043static const unsigned int hscif1_clk_b_pins[] = {
2044 /* SCK */
2045 RCAR_GP_PIN(1, 28),
2046};
2047static const unsigned int hscif1_clk_b_mux[] = {
2048 HSCK1_B_MARK,
2049};
2050static const unsigned int hscif1_ctrl_b_pins[] = {
2051 /* RTS, CTS */
2052 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2053};
2054static const unsigned int hscif1_ctrl_b_mux[] = {
2055 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2056};
70702bfc
UH		 2057/* - I2C1 ------------------------------------------------------------------- */
2058static const unsigned int i2c1_pins[] = {
2059 /* SCL, SDA */
2060 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2061};
2062static const unsigned int i2c1_mux[] = {
2063 I2C1_SCL_MARK, I2C1_SDA_MARK,
2064};
2065static const unsigned int i2c1_b_pins[] = {
2066 /* SCL, SDA */
2067 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2068};
2069static const unsigned int i2c1_b_mux[] = {
2070 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2071};
2072static const unsigned int i2c1_c_pins[] = {
2073 /* SCL, SDA */
2074 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2075};
2076static const unsigned int i2c1_c_mux[] = {
2077 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2078};
2079/* - I2C2 ------------------------------------------------------------------- */
2080static const unsigned int i2c2_pins[] = {
2081 /* SCL, SDA */
2082 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2083};
2084static const unsigned int i2c2_mux[] = {
2085 I2C2_SCL_MARK, I2C2_SDA_MARK,
2086};
2087static const unsigned int i2c2_b_pins[] = {
2088 /* SCL, SDA */
2089 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2090};
2091static const unsigned int i2c2_b_mux[] = {
2092 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2093};
2094static const unsigned int i2c2_c_pins[] = {
2095 /* SCL, SDA */
2096 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2097};
2098static const unsigned int i2c2_c_mux[] = {
2099 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2100};
2101static const unsigned int i2c2_d_pins[] = {
2102 /* SCL, SDA */
2103 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2104};
2105static const unsigned int i2c2_d_mux[] = {
2106 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2107};
2108static const unsigned int i2c2_e_pins[] = {
2109 /* SCL, SDA */
2110 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2111};
2112static const unsigned int i2c2_e_mux[] = {
2113 I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2114};
f6aaaac9
GL		 2115/* - I2C3 ------------------------------------------------------------------- */
2116static const unsigned int i2c3_pins[] = {
2117 /* SCL, SDA */
2118 PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2119};
2120static const unsigned int i2c3_mux[] = {
2121 I2C3_SCL_MARK, I2C3_SDA_MARK,
2122};
457c11d3
LP		 2123/* - INTC ------------------------------------------------------------------- */
2124static const unsigned int intc_irq0_pins[] = {
2125 /* IRQ */
2126 RCAR_GP_PIN(1, 25),
2127};
2128static const unsigned int intc_irq0_mux[] = {
2129 IRQ0_MARK,
2130};
2131static const unsigned int intc_irq1_pins[] = {
2132 /* IRQ */
2133 RCAR_GP_PIN(1, 27),
2134};
2135static const unsigned int intc_irq1_mux[] = {
2136 IRQ1_MARK,
2137};
2138static const unsigned int intc_irq2_pins[] = {
2139 /* IRQ */
2140 RCAR_GP_PIN(1, 29),
2141};
2142static const unsigned int intc_irq2_mux[] = {
2143 IRQ2_MARK,
2144};
2145static const unsigned int intc_irq3_pins[] = {
2146 /* IRQ */
2147 RCAR_GP_PIN(1, 23),
2148};
2149static const unsigned int intc_irq3_mux[] = {
2150 IRQ3_MARK,
2151};
2152/* - MMCIF0 ----------------------------------------------------------------- */
2153static const unsigned int mmc0_data1_pins[] = {
2154 /* D[0] */
2155 RCAR_GP_PIN(3, 18),
2156};
2157static const unsigned int mmc0_data1_mux[] = {
2158 MMC0_D0_MARK,
2159};
2160static const unsigned int mmc0_data4_pins[] = {
2161 /* D[0:3] */
2162 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2163 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2164};
2165static const unsigned int mmc0_data4_mux[] = {
2166 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2167};
2168static const unsigned int mmc0_data8_pins[] = {
2169 /* D[0:7] */
2170 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2171 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2172 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2173 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2174};
2175static const unsigned int mmc0_data8_mux[] = {
2176 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2177 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
2178};
2179static const unsigned int mmc0_ctrl_pins[] = {
2180 /* CLK, CMD */
2181 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2182};
2183static const unsigned int mmc0_ctrl_mux[] = {
2184 MMC0_CLK_MARK, MMC0_CMD_MARK,
2185};
2186/* - MMCIF1 ----------------------------------------------------------------- */
2187static const unsigned int mmc1_data1_pins[] = {
2188 /* D[0] */
2189 RCAR_GP_PIN(3, 26),
2190};
2191static const unsigned int mmc1_data1_mux[] = {
2192 MMC1_D0_MARK,
2193};
2194static const unsigned int mmc1_data4_pins[] = {
2195 /* D[0:3] */
2196 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2197 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2198};
2199static const unsigned int mmc1_data4_mux[] = {
2200 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2201};
2202static const unsigned int mmc1_data8_pins[] = {
2203 /* D[0:7] */
2204 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2205 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2206 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2207 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2208};
2209static const unsigned int mmc1_data8_mux[] = {
2210 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2211 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
2212};
2213static const unsigned int mmc1_ctrl_pins[] = {
2214 /* CLK, CMD */
2215 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2216};
2217static const unsigned int mmc1_ctrl_mux[] = {
2218 MMC1_CLK_MARK, MMC1_CMD_MARK,
2219};
4f47cc5e
KH		 2220/* - MSIOF0 ----------------------------------------------------------------- */
2221static const unsigned int msiof0_clk_pins[] = {
2222 /* SCK */
2223 RCAR_GP_PIN(5, 12),
2224};
2225static const unsigned int msiof0_clk_mux[] = {
2226 MSIOF0_SCK_MARK,
2227};
2228static const unsigned int msiof0_sync_pins[] = {
2229 /* SYNC */
2230 RCAR_GP_PIN(5, 13),
2231};
2232static const unsigned int msiof0_sync_mux[] = {
2233 MSIOF0_SYNC_MARK,
2234};
2235static const unsigned int msiof0_ss1_pins[] = {
2236 /* SS1 */
2237 RCAR_GP_PIN(5, 14),
2238};
2239static const unsigned int msiof0_ss1_mux[] = {
2240 MSIOF0_SS1_MARK,
2241};
2242static const unsigned int msiof0_ss2_pins[] = {
2243 /* SS2 */
2244 RCAR_GP_PIN(5, 16),
2245};
2246static const unsigned int msiof0_ss2_mux[] = {
2247 MSIOF0_SS2_MARK,
2248};
2249static const unsigned int msiof0_rx_pins[] = {
2250 /* RXD */
2251 RCAR_GP_PIN(5, 17),
2252};
2253static const unsigned int msiof0_rx_mux[] = {
2254 MSIOF0_RXD_MARK,
2255};
2256static const unsigned int msiof0_tx_pins[] = {
2257 /* TXD */
2258 RCAR_GP_PIN(5, 15),
2259};
2260static const unsigned int msiof0_tx_mux[] = {
2261 MSIOF0_TXD_MARK,
2262};
7033168d
GU		 2263
2264static const unsigned int msiof0_clk_b_pins[] = {
2265 /* SCK */
2266 RCAR_GP_PIN(1, 23),
2267};
2268static const unsigned int msiof0_clk_b_mux[] = {
2269 MSIOF0_SCK_B_MARK,
2270};
2271static const unsigned int msiof0_ss1_b_pins[] = {
2272 /* SS1 */
2273 RCAR_GP_PIN(1, 12),
2274};
2275static const unsigned int msiof0_ss1_b_mux[] = {
2276 MSIOF0_SS1_B_MARK,
2277};
2278static const unsigned int msiof0_ss2_b_pins[] = {
2279 /* SS2 */
2280 RCAR_GP_PIN(1, 10),
2281};
2282static const unsigned int msiof0_ss2_b_mux[] = {
2283 MSIOF0_SS2_B_MARK,
2284};
2285static const unsigned int msiof0_rx_b_pins[] = {
2286 /* RXD */
2287 RCAR_GP_PIN(1, 29),
2288};
2289static const unsigned int msiof0_rx_b_mux[] = {
2290 MSIOF0_RXD_B_MARK,
2291};
2292static const unsigned int msiof0_tx_b_pins[] = {
2293 /* TXD */
2294 RCAR_GP_PIN(1, 28),
2295};
2296static const unsigned int msiof0_tx_b_mux[] = {
2297 MSIOF0_TXD_B_MARK,
2298};
4f47cc5e
KH		 2299/* - MSIOF1 ----------------------------------------------------------------- */
2300static const unsigned int msiof1_clk_pins[] = {
2301 /* SCK */
2302 RCAR_GP_PIN(4, 8),
2303};
2304static const unsigned int msiof1_clk_mux[] = {
2305 MSIOF1_SCK_MARK,
2306};
2307static const unsigned int msiof1_sync_pins[] = {
2308 /* SYNC */
2309 RCAR_GP_PIN(4, 9),
2310};
2311static const unsigned int msiof1_sync_mux[] = {
2312 MSIOF1_SYNC_MARK,
2313};
2314static const unsigned int msiof1_ss1_pins[] = {
2315 /* SS1 */
2316 RCAR_GP_PIN(4, 10),
2317};
2318static const unsigned int msiof1_ss1_mux[] = {
2319 MSIOF1_SS1_MARK,
2320};
2321static const unsigned int msiof1_ss2_pins[] = {
2322 /* SS2 */
2323 RCAR_GP_PIN(4, 11),
2324};
2325static const unsigned int msiof1_ss2_mux[] = {
2326 MSIOF1_SS2_MARK,
2327};
2328static const unsigned int msiof1_rx_pins[] = {
2329 /* RXD */
2330 RCAR_GP_PIN(4, 13),
2331};
2332static const unsigned int msiof1_rx_mux[] = {
2333 MSIOF1_RXD_MARK,
2334};
2335static const unsigned int msiof1_tx_pins[] = {
2336 /* TXD */
2337 RCAR_GP_PIN(4, 12),
2338};
2339static const unsigned int msiof1_tx_mux[] = {
2340 MSIOF1_TXD_MARK,
2341};
7033168d
GU		 2342
2343static const unsigned int msiof1_clk_b_pins[] = {
2344 /* SCK */
2345 RCAR_GP_PIN(1, 16),
2346};
2347static const unsigned int msiof1_clk_b_mux[] = {
2348 MSIOF1_SCK_B_MARK,
2349};
2350static const unsigned int msiof1_ss1_b_pins[] = {
2351 /* SS1 */
2352 RCAR_GP_PIN(0, 18),
2353};
2354static const unsigned int msiof1_ss1_b_mux[] = {
2355 MSIOF1_SS1_B_MARK,
2356};
2357static const unsigned int msiof1_ss2_b_pins[] = {
2358 /* SS2 */
2359 RCAR_GP_PIN(0, 19),
2360};
2361static const unsigned int msiof1_ss2_b_mux[] = {
2362 MSIOF1_SS2_B_MARK,
2363};
2364static const unsigned int msiof1_rx_b_pins[] = {
2365 /* RXD */
2366 RCAR_GP_PIN(1, 17),
2367};
2368static const unsigned int msiof1_rx_b_mux[] = {
2369 MSIOF1_RXD_B_MARK,
2370};
2371static const unsigned int msiof1_tx_b_pins[] = {
2372 /* TXD */
2373 RCAR_GP_PIN(0, 20),
2374};
2375static const unsigned int msiof1_tx_b_mux[] = {
2376 MSIOF1_TXD_B_MARK,
2377};
4f47cc5e
KH		 2378/* - MSIOF2 ----------------------------------------------------------------- */
2379static const unsigned int msiof2_clk_pins[] = {
2380 /* SCK */
2381 RCAR_GP_PIN(0, 27),
2382};
2383static const unsigned int msiof2_clk_mux[] = {
2384 MSIOF2_SCK_MARK,
2385};
2386static const unsigned int msiof2_sync_pins[] = {
2387 /* SYNC */
2388 RCAR_GP_PIN(0, 26),
2389};
2390static const unsigned int msiof2_sync_mux[] = {
2391 MSIOF2_SYNC_MARK,
2392};
2393static const unsigned int msiof2_ss1_pins[] = {
2394 /* SS1 */
2395 RCAR_GP_PIN(0, 30),
2396};
2397static const unsigned int msiof2_ss1_mux[] = {
2398 MSIOF2_SS1_MARK,
2399};
2400static const unsigned int msiof2_ss2_pins[] = {
2401 /* SS2 */
2402 RCAR_GP_PIN(0, 31),
2403};
2404static const unsigned int msiof2_ss2_mux[] = {
2405 MSIOF2_SS2_MARK,
2406};
2407static const unsigned int msiof2_rx_pins[] = {
2408 /* RXD */
2409 RCAR_GP_PIN(0, 29),
2410};
2411static const unsigned int msiof2_rx_mux[] = {
2412 MSIOF2_RXD_MARK,
2413};
2414static const unsigned int msiof2_tx_pins[] = {
2415 /* TXD */
2416 RCAR_GP_PIN(0, 28),
2417};
2418static const unsigned int msiof2_tx_mux[] = {
2419 MSIOF2_TXD_MARK,
2420};
2421/* - MSIOF3 ----------------------------------------------------------------- */
2422static const unsigned int msiof3_clk_pins[] = {
2423 /* SCK */
2424 RCAR_GP_PIN(5, 4),
2425};
2426static const unsigned int msiof3_clk_mux[] = {
2427 MSIOF3_SCK_MARK,
2428};
2429static const unsigned int msiof3_sync_pins[] = {
2430 /* SYNC */
2431 RCAR_GP_PIN(4, 30),
2432};
2433static const unsigned int msiof3_sync_mux[] = {
2434 MSIOF3_SYNC_MARK,
2435};
2436static const unsigned int msiof3_ss1_pins[] = {
2437 /* SS1 */
2438 RCAR_GP_PIN(4, 31),
2439};
2440static const unsigned int msiof3_ss1_mux[] = {
2441 MSIOF3_SS1_MARK,
2442};
2443static const unsigned int msiof3_ss2_pins[] = {
2444 /* SS2 */
2445 RCAR_GP_PIN(4, 27),
2446};
2447static const unsigned int msiof3_ss2_mux[] = {
2448 MSIOF3_SS2_MARK,
2449};
2450static const unsigned int msiof3_rx_pins[] = {
2451 /* RXD */
2452 RCAR_GP_PIN(5, 2),
2453};
2454static const unsigned int msiof3_rx_mux[] = {
2455 MSIOF3_RXD_MARK,
2456};
2457static const unsigned int msiof3_tx_pins[] = {
2458 /* TXD */
2459 RCAR_GP_PIN(5, 3),
2460};
2461static const unsigned int msiof3_tx_mux[] = {
2462 MSIOF3_TXD_MARK,
2463};
7033168d
GU		 2464
2465static const unsigned int msiof3_clk_b_pins[] = {
2466 /* SCK */
2467 RCAR_GP_PIN(0, 0),
2468};
2469static const unsigned int msiof3_clk_b_mux[] = {
2470 MSIOF3_SCK_B_MARK,
2471};
2472static const unsigned int msiof3_sync_b_pins[] = {
2473 /* SYNC */
2474 RCAR_GP_PIN(0, 1),
2475};
2476static const unsigned int msiof3_sync_b_mux[] = {
2477 MSIOF3_SYNC_B_MARK,
2478};
2479static const unsigned int msiof3_rx_b_pins[] = {
2480 /* RXD */
2481 RCAR_GP_PIN(0, 2),
2482};
2483static const unsigned int msiof3_rx_b_mux[] = {
2484 MSIOF3_RXD_B_MARK,
2485};
2486static const unsigned int msiof3_tx_b_pins[] = {
2487 /* TXD */
2488 RCAR_GP_PIN(0, 3),
2489};
2490static const unsigned int msiof3_tx_b_mux[] = {
2491 MSIOF3_TXD_B_MARK,
2492};
202909cd
GU		 2493/* - QSPI ------------------------------------------------------------------- */
2494static const unsigned int qspi_ctrl_pins[] = {
2495 /* SPCLK, SSL */
2496 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2497};
2498static const unsigned int qspi_ctrl_mux[] = {
2499 SPCLK_MARK, SSL_MARK,
2500};
2501static const unsigned int qspi_data2_pins[] = {
2502 /* MOSI_IO0, MISO_IO1 */
2503 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2504};
2505static const unsigned int qspi_data2_mux[] = {
2506 MOSI_IO0_MARK, MISO_IO1_MARK,
2507};
2508static const unsigned int qspi_data4_pins[] = {
2509 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2510 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2511 RCAR_GP_PIN(1, 8),
2512};
2513static const unsigned int qspi_data4_mux[] = {
2514 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2515};
457c11d3
LP		 2516/* - SCIF0 ------------------------------------------------------------------ */
2517static const unsigned int scif0_data_pins[] = {
2518 /* RX, TX */
2519 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2520};
2521static const unsigned int scif0_data_mux[] = {
2522 RX0_MARK, TX0_MARK,
2523};
2524static const unsigned int scif0_clk_pins[] = {
2525 /* SCK */
2526 RCAR_GP_PIN(4, 27),
2527};
2528static const unsigned int scif0_clk_mux[] = {
2529 SCK0_MARK,
2530};
2531static const unsigned int scif0_ctrl_pins[] = {
2532 /* RTS, CTS */
2533 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2534};
2535static const unsigned int scif0_ctrl_mux[] = {
2536 RTS0_N_MARK, CTS0_N_MARK,
2537};
2538static const unsigned int scif0_data_b_pins[] = {
2539 /* RX, TX */
2540 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2541};
2542static const unsigned int scif0_data_b_mux[] = {
2543 RX0_B_MARK, TX0_B_MARK,
2544};
2545/* - SCIF1 ------------------------------------------------------------------ */
2546static const unsigned int scif1_data_pins[] = {
2547 /* RX, TX */
2548 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2549};
2550static const unsigned int scif1_data_mux[] = {
2551 RX1_MARK, TX1_MARK,
2552};
2553static const unsigned int scif1_clk_pins[] = {
2554 /* SCK */
2555 RCAR_GP_PIN(4, 20),
2556};
2557static const unsigned int scif1_clk_mux[] = {
2558 SCK1_MARK,
2559};
2560static const unsigned int scif1_ctrl_pins[] = {
2561 /* RTS, CTS */
2562 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2563};
2564static const unsigned int scif1_ctrl_mux[] = {
2565 RTS1_N_MARK, CTS1_N_MARK,
2566};
2567static const unsigned int scif1_data_b_pins[] = {
2568 /* RX, TX */
2569 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2570};
2571static const unsigned int scif1_data_b_mux[] = {
2572 RX1_B_MARK, TX1_B_MARK,
2573};
2574static const unsigned int scif1_data_c_pins[] = {
2575 /* RX, TX */
2576 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2577};
2578static const unsigned int scif1_data_c_mux[] = {
2579 RX1_C_MARK, TX1_C_MARK,
fbd0ca3d 2580};
457c11d3 2581static const unsigned int scif1_data_d_pins[] = {
fbd0ca3d 2582 /* RX, TX */
457c11d3 2583 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
fbd0ca3d 2584};
457c11d3
LP		 2585static const unsigned int scif1_data_d_mux[] = {
2586 RX1_D_MARK, TX1_D_MARK,
fbd0ca3d 2587};
457c11d3 2588static const unsigned int scif1_clk_d_pins[] = {
fbd0ca3d 2589 /* SCK */
457c11d3 2590 RCAR_GP_PIN(3, 17),
fbd0ca3d 2591};
457c11d3
LP		 2592static const unsigned int scif1_clk_d_mux[] = {
2593 SCK1_D_MARK,
fbd0ca3d 2594};
457c11d3
LP		 2595static const unsigned int scif1_data_e_pins[] = {
2596 /* RX, TX */
2597 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
fbd0ca3d 2598};
457c11d3
LP		 2599static const unsigned int scif1_data_e_mux[] = {
2600 RX1_E_MARK, TX1_E_MARK,
2601};
2602static const unsigned int scif1_clk_e_pins[] = {
2603 /* SCK */
2604 RCAR_GP_PIN(2, 20),
2605};
2606static const unsigned int scif1_clk_e_mux[] = {
2607 SCK1_E_MARK,
fbd0ca3d 2608};
2dbe7f2c
LP		 2609/* - SCIF2 ------------------------------------------------------------------ */
2610static const unsigned int scif2_data_pins[] = {
2611 /* RX, TX */
2612 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
2613};
2614static const unsigned int scif2_data_mux[] = {
2615 RX2_MARK, TX2_MARK,
2616};
2617static const unsigned int scif2_clk_pins[] = {
2618 /* SCK */
2619 RCAR_GP_PIN(5, 4),
2620};
2621static const unsigned int scif2_clk_mux[] = {
2622 SCK2_MARK,
2623};
2624static const unsigned int scif2_data_b_pins[] = {
2625 /* RX, TX */
2626 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2627};
2628static const unsigned int scif2_data_b_mux[] = {
2629 RX2_B_MARK, TX2_B_MARK,
2630};
45c6c85d
LP		 2631/* - SCIFA0 ----------------------------------------------------------------- */
2632static const unsigned int scifa0_data_pins[] = {
2633 /* RXD, TXD */
2634 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2635};
2636static const unsigned int scifa0_data_mux[] = {
2637 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2638};
2639static const unsigned int scifa0_clk_pins[] = {
2640 /* SCK */
2641 RCAR_GP_PIN(4, 27),
2642};
2643static const unsigned int scifa0_clk_mux[] = {
2644 SCIFA0_SCK_MARK,
2645};
2646static const unsigned int scifa0_ctrl_pins[] = {
2647 /* RTS, CTS */
2648 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2649};
2650static const unsigned int scifa0_ctrl_mux[] = {
2651 SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
2652};
2653static const unsigned int scifa0_data_b_pins[] = {
2654 /* RXD, TXD */
2655 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2656};
2657static const unsigned int scifa0_data_b_mux[] = {
2658 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2659};
2660static const unsigned int scifa0_clk_b_pins[] = {
2661 /* SCK */
2662 RCAR_GP_PIN(1, 19),
2663};
2664static const unsigned int scifa0_clk_b_mux[] = {
2665 SCIFA0_SCK_B_MARK,
2666};
2667static const unsigned int scifa0_ctrl_b_pins[] = {
2668 /* RTS, CTS */
2669 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
2670};
2671static const unsigned int scifa0_ctrl_b_mux[] = {
2672 SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
2673};
2674/* - SCIFA1 ----------------------------------------------------------------- */
2675static const unsigned int scifa1_data_pins[] = {
2676 /* RXD, TXD */
2677 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2678};
2679static const unsigned int scifa1_data_mux[] = {
2680 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2681};
2682static const unsigned int scifa1_clk_pins[] = {
2683 /* SCK */
2684 RCAR_GP_PIN(4, 20),
2685};
2686static const unsigned int scifa1_clk_mux[] = {
2687 SCIFA1_SCK_MARK,
2688};
2689static const unsigned int scifa1_ctrl_pins[] = {
2690 /* RTS, CTS */
2691 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2692};
2693static const unsigned int scifa1_ctrl_mux[] = {
2694 SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
2695};
2696static const unsigned int scifa1_data_b_pins[] = {
2697 /* RXD, TXD */
2698 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
2699};
2700static const unsigned int scifa1_data_b_mux[] = {
2701 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2702};
2703static const unsigned int scifa1_clk_b_pins[] = {
2704 /* SCK */
2705 RCAR_GP_PIN(0, 23),
2706};
2707static const unsigned int scifa1_clk_b_mux[] = {
2708 SCIFA1_SCK_B_MARK,
2709};
2710static const unsigned int scifa1_ctrl_b_pins[] = {
2711 /* RTS, CTS */
2712 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
2713};
2714static const unsigned int scifa1_ctrl_b_mux[] = {
2715 SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
2716};
2717static const unsigned int scifa1_data_c_pins[] = {
2718 /* RXD, TXD */
2719 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2720};
2721static const unsigned int scifa1_data_c_mux[] = {
2722 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2723};
2724static const unsigned int scifa1_clk_c_pins[] = {
2725 /* SCK */
2726 RCAR_GP_PIN(0, 8),
2727};
2728static const unsigned int scifa1_clk_c_mux[] = {
2729 SCIFA1_SCK_C_MARK,
2730};
2731static const unsigned int scifa1_ctrl_c_pins[] = {
2732 /* RTS, CTS */
2733 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2734};
2735static const unsigned int scifa1_ctrl_c_mux[] = {
2736 SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
2737};
2738static const unsigned int scifa1_data_d_pins[] = {
2739 /* RXD, TXD */
2740 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2741};
2742static const unsigned int scifa1_data_d_mux[] = {
2743 SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
2744};
2745static const unsigned int scifa1_clk_d_pins[] = {
2746 /* SCK */
2747 RCAR_GP_PIN(2, 10),
2748};
2749static const unsigned int scifa1_clk_d_mux[] = {
2750 SCIFA1_SCK_D_MARK,
2751};
2752static const unsigned int scifa1_ctrl_d_pins[] = {
2753 /* RTS, CTS */
2754 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2755};
2756static const unsigned int scifa1_ctrl_d_mux[] = {
2757 SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
2758};
2759/* - SCIFA2 ----------------------------------------------------------------- */
2760static const unsigned int scifa2_data_pins[] = {
2761 /* RXD, TXD */
2762 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2763};
2764static const unsigned int scifa2_data_mux[] = {
2765 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2766};
2767static const unsigned int scifa2_clk_pins[] = {
2768 /* SCK */
2769 RCAR_GP_PIN(5, 4),
2770};
2771static const unsigned int scifa2_clk_mux[] = {
2772 SCIFA2_SCK_MARK,
2773};
2774static const unsigned int scifa2_ctrl_pins[] = {
2775 /* RTS, CTS */
2776 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
2777};
2778static const unsigned int scifa2_ctrl_mux[] = {
2779 SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
2780};
2781static const unsigned int scifa2_data_b_pins[] = {
2782 /* RXD, TXD */
2783 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
2784};
2785static const unsigned int scifa2_data_b_mux[] = {
2786 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2787};
2788static const unsigned int scifa2_data_c_pins[] = {
2789 /* RXD, TXD */
2790 RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
2791};
2792static const unsigned int scifa2_data_c_mux[] = {
2793 SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
2794};
2795static const unsigned int scifa2_clk_c_pins[] = {
2796 /* SCK */
2797 RCAR_GP_PIN(5, 29),
2798};
2799static const unsigned int scifa2_clk_c_mux[] = {
2800 SCIFA2_SCK_C_MARK,
2801};
2802/* - SCIFB0 ----------------------------------------------------------------- */
2803static const unsigned int scifb0_data_pins[] = {
2804 /* RXD, TXD */
2805 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
2806};
2807static const unsigned int scifb0_data_mux[] = {
2808 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
2809};
2810static const unsigned int scifb0_clk_pins[] = {
2811 /* SCK */
2812 RCAR_GP_PIN(4, 8),
2813};
2814static const unsigned int scifb0_clk_mux[] = {
2815 SCIFB0_SCK_MARK,
2816};
2817static const unsigned int scifb0_ctrl_pins[] = {
2818 /* RTS, CTS */
2819 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
2820};
2821static const unsigned int scifb0_ctrl_mux[] = {
2822 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
2823};
2824static const unsigned int scifb0_data_b_pins[] = {
2825 /* RXD, TXD */
2826 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2827};
2828static const unsigned int scifb0_data_b_mux[] = {
2829 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
2830};
2831static const unsigned int scifb0_clk_b_pins[] = {
2832 /* SCK */
2833 RCAR_GP_PIN(3, 9),
2834};
2835static const unsigned int scifb0_clk_b_mux[] = {
2836 SCIFB0_SCK_B_MARK,
2837};
2838static const unsigned int scifb0_ctrl_b_pins[] = {
2839 /* RTS, CTS */
2840 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2841};
2842static const unsigned int scifb0_ctrl_b_mux[] = {
2843 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
2844};
2845static const unsigned int scifb0_data_c_pins[] = {
2846 /* RXD, TXD */
2847 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2848};
2849static const unsigned int scifb0_data_c_mux[] = {
2850 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
2851};
2852/* - SCIFB1 ----------------------------------------------------------------- */
2853static const unsigned int scifb1_data_pins[] = {
2854 /* RXD, TXD */
2855 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2856};
2857static const unsigned int scifb1_data_mux[] = {
2858 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
2859};
2860static const unsigned int scifb1_clk_pins[] = {
2861 /* SCK */
2862 RCAR_GP_PIN(4, 14),
2863};
2864static const unsigned int scifb1_clk_mux[] = {
2865 SCIFB1_SCK_MARK,
2866};
2867static const unsigned int scifb1_ctrl_pins[] = {
2868 /* RTS, CTS */
2869 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
2870};
2871static const unsigned int scifb1_ctrl_mux[] = {
2872 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
2873};
2874static const unsigned int scifb1_data_b_pins[] = {
2875 /* RXD, TXD */
2876 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2877};
2878static const unsigned int scifb1_data_b_mux[] = {
2879 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
2880};
2881static const unsigned int scifb1_clk_b_pins[] = {
2882 /* SCK */
2883 RCAR_GP_PIN(3, 1),
2884};
2885static const unsigned int scifb1_clk_b_mux[] = {
2886 SCIFB1_SCK_B_MARK,
2887};
2888static const unsigned int scifb1_ctrl_b_pins[] = {
2889 /* RTS, CTS */
2890 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
2891};
2892static const unsigned int scifb1_ctrl_b_mux[] = {
2893 SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
2894};
2895static const unsigned int scifb1_data_c_pins[] = {
2896 /* RXD, TXD */
2897 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2898};
2899static const unsigned int scifb1_data_c_mux[] = {
2900 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
2901};
2902static const unsigned int scifb1_data_d_pins[] = {
2903 /* RXD, TXD */
2904 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2905};
2906static const unsigned int scifb1_data_d_mux[] = {
2907 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
2908};
2909static const unsigned int scifb1_data_e_pins[] = {
2910 /* RXD, TXD */
2911 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2912};
2913static const unsigned int scifb1_data_e_mux[] = {
2914 SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
2915};
2916static const unsigned int scifb1_clk_e_pins[] = {
2917 /* SCK */
2918 RCAR_GP_PIN(3, 17),
2919};
2920static const unsigned int scifb1_clk_e_mux[] = {
2921 SCIFB1_SCK_E_MARK,
2922};
2923static const unsigned int scifb1_data_f_pins[] = {
2924 /* RXD, TXD */
2925 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2926};
2927static const unsigned int scifb1_data_f_mux[] = {
2928 SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
2929};
2930static const unsigned int scifb1_data_g_pins[] = {
2931 /* RXD, TXD */
2932 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2933};
2934static const unsigned int scifb1_data_g_mux[] = {
2935 SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
2936};
2937static const unsigned int scifb1_clk_g_pins[] = {
2938 /* SCK */
2939 RCAR_GP_PIN(2, 20),
2940};
2941static const unsigned int scifb1_clk_g_mux[] = {
2942 SCIFB1_SCK_G_MARK,
066f0d6e 2943};
45c6c85d
LP		 2944/* - SCIFB2 ----------------------------------------------------------------- */
2945static const unsigned int scifb2_data_pins[] = {
2946 /* RXD, TXD */
2947 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
066f0d6e 2948};
45c6c85d
LP		 2949static const unsigned int scifb2_data_mux[] = {
2950 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
066f0d6e 2951};
45c6c85d
LP		 2952static const unsigned int scifb2_clk_pins[] = {
2953 /* SCK */
2954 RCAR_GP_PIN(4, 21),
066f0d6e 2955};
45c6c85d
LP		 2956static const unsigned int scifb2_clk_mux[] = {
2957 SCIFB2_SCK_MARK,
066f0d6e 2958};
45c6c85d
LP		 2959static const unsigned int scifb2_ctrl_pins[] = {
2960 /* RTS, CTS */
2961 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
066f0d6e 2962};
45c6c85d
LP		 2963static const unsigned int scifb2_ctrl_mux[] = {
2964 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
066f0d6e 2965};
45c6c85d
LP		 2966static const unsigned int scifb2_data_b_pins[] = {
2967 /* RXD, TXD */
2968 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
066f0d6e 2969};
45c6c85d
LP		 2970static const unsigned int scifb2_data_b_mux[] = {
2971 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
066f0d6e 2972};
45c6c85d
LP		 2973static const unsigned int scifb2_clk_b_pins[] = {
2974 /* SCK */
2975 RCAR_GP_PIN(0, 31),
066f0d6e 2976};
45c6c85d
LP		 2977static const unsigned int scifb2_clk_b_mux[] = {
2978 SCIFB2_SCK_B_MARK,
066f0d6e 2979};
45c6c85d
LP		 2980static const unsigned int scifb2_ctrl_b_pins[] = {
2981 /* RTS, CTS */
2982 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
066f0d6e 2983};
45c6c85d
LP		 2984static const unsigned int scifb2_ctrl_b_mux[] = {
2985 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
066f0d6e 2986};
45c6c85d
LP		 2987static const unsigned int scifb2_data_c_pins[] = {
2988 /* RXD, TXD */
2989 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2990};
2991static const unsigned int scifb2_data_c_mux[] = {
2992 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
066f0d6e 2993};
0a6ea54f 2994/* - SDHI0 ------------------------------------------------------------------ */
066f0d6e
GL		 2995static const unsigned int sdhi0_data1_pins[] = {
2996 /* D0 */
2997 RCAR_GP_PIN(3, 2),
2998};
2999static const unsigned int sdhi0_data1_mux[] = {
3000 SD0_DAT0_MARK,
3001};
3002static const unsigned int sdhi0_data4_pins[] = {
3003 /* D[0:3] */
3004 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3005};
3006static const unsigned int sdhi0_data4_mux[] = {
3007 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
3008};
3009static const unsigned int sdhi0_ctrl_pins[] = {
3010 /* CLK, CMD */
3011 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3012};
3013static const unsigned int sdhi0_ctrl_mux[] = {
3014 SD0_CLK_MARK, SD0_CMD_MARK,
3015};
3016static const unsigned int sdhi0_cd_pins[] = {
3017 /* CD */
3018 RCAR_GP_PIN(3, 6),
3019};
3020static const unsigned int sdhi0_cd_mux[] = {
3021 SD0_CD_MARK,
3022};
3023static const unsigned int sdhi0_wp_pins[] = {
3024 /* WP */
3025 RCAR_GP_PIN(3, 7),
3026};
3027static const unsigned int sdhi0_wp_mux[] = {
3028 SD0_WP_MARK,
3029};
0a6ea54f 3030/* - SDHI1 ------------------------------------------------------------------ */
066f0d6e
GL		 3031static const unsigned int sdhi1_data1_pins[] = {
3032 /* D0 */
3033 RCAR_GP_PIN(3, 10),
3034};
3035static const unsigned int sdhi1_data1_mux[] = {
3036 SD1_DAT0_MARK,
3037};
3038static const unsigned int sdhi1_data4_pins[] = {
3039 /* D[0:3] */
3040 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3041};
3042static const unsigned int sdhi1_data4_mux[] = {
3043 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
3044};
3045static const unsigned int sdhi1_ctrl_pins[] = {
3046 /* CLK, CMD */
3047 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3048};
3049static const unsigned int sdhi1_ctrl_mux[] = {
3050 SD1_CLK_MARK, SD1_CMD_MARK,
3051};
3052static const unsigned int sdhi1_cd_pins[] = {
3053 /* CD */
3054 RCAR_GP_PIN(3, 14),
3055};
3056static const unsigned int sdhi1_cd_mux[] = {
3057 SD1_CD_MARK,
3058};
3059static const unsigned int sdhi1_wp_pins[] = {
3060 /* WP */
3061 RCAR_GP_PIN(3, 15),
3062};
3063static const unsigned int sdhi1_wp_mux[] = {
3064 SD1_WP_MARK,
3065};
0a6ea54f 3066/* - SDHI2 ------------------------------------------------------------------ */
066f0d6e
GL		 3067static const unsigned int sdhi2_data1_pins[] = {
3068 /* D0 */
3069 RCAR_GP_PIN(3, 18),
3070};
3071static const unsigned int sdhi2_data1_mux[] = {
3072 SD2_DAT0_MARK,
3073};
3074static const unsigned int sdhi2_data4_pins[] = {
3075 /* D[0:3] */
3076 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
3077};
3078static const unsigned int sdhi2_data4_mux[] = {
3079 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
3080};
3081static const unsigned int sdhi2_ctrl_pins[] = {
3082 /* CLK, CMD */
3083 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
3084};
3085static const unsigned int sdhi2_ctrl_mux[] = {
3086 SD2_CLK_MARK, SD2_CMD_MARK,
3087};
3088static const unsigned int sdhi2_cd_pins[] = {
3089 /* CD */
3090 RCAR_GP_PIN(3, 22),
3091};
3092static const unsigned int sdhi2_cd_mux[] = {
3093 SD2_CD_MARK,
3094};
3095static const unsigned int sdhi2_wp_pins[] = {
3096 /* WP */
3097 RCAR_GP_PIN(3, 23),
3098};
3099static const unsigned int sdhi2_wp_mux[] = {
3100 SD2_WP_MARK,
3101};
0a6ea54f 3102/* - SDHI3 ------------------------------------------------------------------ */
066f0d6e
GL		 3103static const unsigned int sdhi3_data1_pins[] = {
3104 /* D0 */
3105 RCAR_GP_PIN(3, 26),
3106};
3107static const unsigned int sdhi3_data1_mux[] = {
3108 SD3_DAT0_MARK,
3109};
3110static const unsigned int sdhi3_data4_pins[] = {
3111 /* D[0:3] */
3112 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
3113};
3114static const unsigned int sdhi3_data4_mux[] = {
3115 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
3116};
3117static const unsigned int sdhi3_ctrl_pins[] = {
3118 /* CLK, CMD */
3119 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
3120};
3121static const unsigned int sdhi3_ctrl_mux[] = {
3122 SD3_CLK_MARK, SD3_CMD_MARK,
3123};
3124static const unsigned int sdhi3_cd_pins[] = {
3125 /* CD */
3126 RCAR_GP_PIN(3, 30),
3127};
3128static const unsigned int sdhi3_cd_mux[] = {
3129 SD3_CD_MARK,
3130};
3131static const unsigned int sdhi3_wp_pins[] = {
3132 /* WP */
3133 RCAR_GP_PIN(3, 31),
3134};
3135static const unsigned int sdhi3_wp_mux[] = {
3136 SD3_WP_MARK,
3137};
1d7b59a0
KM		 3138/* - SSI -------------------------------------------------------------------- */
3139static const unsigned int ssi0_data_pins[] = {
3140 /* SDATA0 */
3141 RCAR_GP_PIN(4, 5),
3142};
3143static const unsigned int ssi0_data_mux[] = {
3144 SSI_SDATA0_MARK,
3145};
3146static const unsigned int ssi0129_ctrl_pins[] = {
3147 /* SCK, WS */
3148 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4),
3149};
3150static const unsigned int ssi0129_ctrl_mux[] = {
3151 SSI_SCK0129_MARK, SSI_WS0129_MARK,
3152};
3153static const unsigned int ssi1_data_pins[] = {
3154 /* SDATA1 */
3155 RCAR_GP_PIN(4, 6),
3156};
3157static const unsigned int ssi1_data_mux[] = {
3158 SSI_SDATA1_MARK,
3159};
3160static const unsigned int ssi1_ctrl_pins[] = {
3161 /* SCK, WS */
3162 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24),
3163};
3164static const unsigned int ssi1_ctrl_mux[] = {
3165 SSI_SCK1_MARK, SSI_WS1_MARK,
3166};
3167static const unsigned int ssi2_data_pins[] = {
3168 /* SDATA2 */
3169 RCAR_GP_PIN(4, 7),
3170};
3171static const unsigned int ssi2_data_mux[] = {
3172 SSI_SDATA2_MARK,
3173};
3174static const unsigned int ssi2_ctrl_pins[] = {
3175 /* SCK, WS */
3176 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17),
3177};
3178static const unsigned int ssi2_ctrl_mux[] = {
3179 SSI_SCK2_MARK, SSI_WS2_MARK,
3180};
3181static const unsigned int ssi3_data_pins[] = {
3182 /* SDATA3 */
3183 RCAR_GP_PIN(4, 10),
3184};
3185static const unsigned int ssi3_data_mux[] = {
3186 SSI_SDATA3_MARK
3187};
3188static const unsigned int ssi34_ctrl_pins[] = {
3189 /* SCK, WS */
3190 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3191};
3192static const unsigned int ssi34_ctrl_mux[] = {
3193 SSI_SCK34_MARK, SSI_WS34_MARK,
3194};
3195static const unsigned int ssi4_data_pins[] = {
3196 /* SDATA4 */
3197 RCAR_GP_PIN(4, 13),
3198};
3199static const unsigned int ssi4_data_mux[] = {
3200 SSI_SDATA4_MARK,
3201};
3202static const unsigned int ssi4_ctrl_pins[] = {
3203 /* SCK, WS */
3204 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3205};
3206static const unsigned int ssi4_ctrl_mux[] = {
3207 SSI_SCK4_MARK, SSI_WS4_MARK,
3208};
3209static const unsigned int ssi5_pins[] = {
3210 /* SDATA5, SCK, WS */
3211 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3212};
3213static const unsigned int ssi5_mux[] = {
3214 SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK,
3215};
3216static const unsigned int ssi5_b_pins[] = {
3217 /* SDATA5, SCK, WS */
3218 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3219};
3220static const unsigned int ssi5_b_mux[] = {
3221 SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK
3222};
3223static const unsigned int ssi5_c_pins[] = {
3224 /* SDATA5, SCK, WS */
3225 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3226};
3227static const unsigned int ssi5_c_mux[] = {
3228 SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK,
3229};
3230static const unsigned int ssi6_pins[] = {
3231 /* SDATA6, SCK, WS */
3232 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3233};
3234static const unsigned int ssi6_mux[] = {
3235 SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK,
3236};
3237static const unsigned int ssi6_b_pins[] = {
3238 /* SDATA6, SCK, WS */
3239 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27),
3240};
3241static const unsigned int ssi6_b_mux[] = {
3242 SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3243};
3244static const unsigned int ssi7_data_pins[] = {
3245 /* SDATA7 */
3246 RCAR_GP_PIN(4, 22),
3247};
3248static const unsigned int ssi7_data_mux[] = {
3249 SSI_SDATA7_MARK,
3250};
3251static const unsigned int ssi7_b_data_pins[] = {
3252 /* SDATA7 */
3253 RCAR_GP_PIN(4, 22),
3254};
3255static const unsigned int ssi7_b_data_mux[] = {
3256 SSI_SDATA7_B_MARK,
3257};
3258static const unsigned int ssi7_c_data_pins[] = {
3259 /* SDATA7 */
3260 RCAR_GP_PIN(1, 26),
3261};
3262static const unsigned int ssi7_c_data_mux[] = {
3263 SSI_SDATA7_C_MARK,
3264};
3265static const unsigned int ssi78_ctrl_pins[] = {
3266 /* SCK, WS */
3267 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3268};
3269static const unsigned int ssi78_ctrl_mux[] = {
3270 SSI_SCK78_MARK, SSI_WS78_MARK,
3271};
3272static const unsigned int ssi78_b_ctrl_pins[] = {
3273 /* SCK, WS */
3274 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24),
3275};
3276static const unsigned int ssi78_b_ctrl_mux[] = {
3277 SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3278};
3279static const unsigned int ssi78_c_ctrl_pins[] = {
3280 /* SCK, WS */
3281 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
3282};
3283static const unsigned int ssi78_c_ctrl_mux[] = {
3284 SSI_SCK78_C_MARK, SSI_WS78_C_MARK,
3285};
3286static const unsigned int ssi8_data_pins[] = {
3287 /* SDATA8 */
3288 RCAR_GP_PIN(4, 23),
3289};
3290static const unsigned int ssi8_data_mux[] = {
3291 SSI_SDATA8_MARK,
3292};
3293static const unsigned int ssi8_b_data_pins[] = {
3294 /* SDATA8 */
3295 RCAR_GP_PIN(4, 23),
3296};
3297static const unsigned int ssi8_b_data_mux[] = {
3298 SSI_SDATA8_B_MARK,
3299};
3300static const unsigned int ssi8_c_data_pins[] = {
3301 /* SDATA8 */
3302 RCAR_GP_PIN(1, 27),
3303};
3304static const unsigned int ssi8_c_data_mux[] = {
3305 SSI_SDATA8_C_MARK,
3306};
3307static const unsigned int ssi9_data_pins[] = {
3308 /* SDATA9 */
3309 RCAR_GP_PIN(4, 24),
3310};
3311static const unsigned int ssi9_data_mux[] = {
3312 SSI_SDATA9_MARK,
3313};
3314static const unsigned int ssi9_ctrl_pins[] = {
3315 /* SCK, WS */
3316 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3317};
3318static const unsigned int ssi9_ctrl_mux[] = {
3319 SSI_SCK9_MARK, SSI_WS9_MARK,
3320};
457c11d3
LP		 3321/* - TPU0 ------------------------------------------------------------------- */
3322static const unsigned int tpu0_to0_pins[] = {
3323 /* TO */
3324 RCAR_GP_PIN(0, 20),
3325};
3326static const unsigned int tpu0_to0_mux[] = {
3327 TPU0TO0_MARK,
3328};
3329static const unsigned int tpu0_to1_pins[] = {
3330 /* TO */
3331 RCAR_GP_PIN(0, 21),
3332};
3333static const unsigned int tpu0_to1_mux[] = {
3334 TPU0TO1_MARK,
3335};
3336static const unsigned int tpu0_to2_pins[] = {
3337 /* TO */
3338 RCAR_GP_PIN(0, 22),
3339};
3340static const unsigned int tpu0_to2_mux[] = {
3341 TPU0TO2_MARK,
3342};
3343static const unsigned int tpu0_to3_pins[] = {
3344 /* TO */
3345 RCAR_GP_PIN(0, 23),
3346};
3347static const unsigned int tpu0_to3_mux[] = {
3348 TPU0TO3_MARK,
3349};
dac896e2
SU		 3350/* - USB0 ------------------------------------------------------------------- */
3351static const unsigned int usb0_pins[] = {
3352 /* PWEN, OVC/VBUS */
3353 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3354};
3355static const unsigned int usb0_mux[] = {
3356 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
3357};
97e00faa
MD		 3358static const unsigned int usb0_ovc_vbus_pins[] = {
3359 /* OVC/VBUS */
3360 RCAR_GP_PIN(5, 19),
3361};
3362static const unsigned int usb0_ovc_vbus_mux[] = {
3363 USB0_OVC_VBUS_MARK,
3364};
dac896e2
SU		 3365/* - USB1 ------------------------------------------------------------------- */
3366static const unsigned int usb1_pins[] = {
3367 /* PWEN, OVC */
3368 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
3369};
3370static const unsigned int usb1_mux[] = {
3371 USB1_PWEN_MARK, USB1_OVC_MARK,
3372};
3373/* - USB2 ------------------------------------------------------------------- */
3374static const unsigned int usb2_pins[] = {
3375 /* PWEN, OVC */
3376 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
3377};
3378static const unsigned int usb2_mux[] = {
3379 USB2_PWEN_MARK, USB2_OVC_MARK,
3380};
64fe8abc
VB		 3381
3382union vin_data {
3383 unsigned int data24[24];
3384 unsigned int data20[20];
3385 unsigned int data16[16];
3386 unsigned int data12[12];
3387 unsigned int data10[10];
3388 unsigned int data8[8];
3389 unsigned int data4[4];
3390};
3391
3392#define VIN_DATA_PIN_GROUP(n, s) \
3393 { \
3394 .name = #n#s, \
3395 .pins = n##_pins.data##s, \
3396 .mux = n##_mux.data##s, \
3397 .nr_pins = ARRAY_SIZE(n##_pins.data##s), \
3398 }
3399
e120cacf 3400/* - VIN0 ------------------------------------------------------------------- */
64fe8abc
VB		 3401static const union vin_data vin0_data_pins = {
3402 .data24 = {
3403 /* B */
3404 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
3405 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3406 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3407 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3408 /* G */
3409 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3410 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3411 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3412 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3413 /* R */
3414 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3415 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3416 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3417 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3418 },
3419};
3420static const union vin_data vin0_data_mux = {
3421 .data24 = {
3422 /* B */
3423 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3424 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3425 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3426 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3427 /* G */
3428 VI0_G0_MARK, VI0_G1_MARK,
3429 VI0_G2_MARK, VI0_G3_MARK,
3430 VI0_G4_MARK, VI0_G5_MARK,
3431 VI0_G6_MARK, VI0_G7_MARK,
3432 /* R */
3433 VI0_R0_MARK, VI0_R1_MARK,
3434 VI0_R2_MARK, VI0_R3_MARK,
3435 VI0_R4_MARK, VI0_R5_MARK,
3436 VI0_R6_MARK, VI0_R7_MARK,
3437 },
3438};
3439static const unsigned int vin0_data18_pins[] = {
3440 /* B */
3441 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3442 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3443 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3444 /* G */
3445 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3446 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
e120cacf 3447 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
64fe8abc
VB		 3448 /* R */
3449 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3450 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
e120cacf
SU		 3451 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3452};
64fe8abc
VB		 3453static const unsigned int vin0_data18_mux[] = {
3454 /* B */
3455 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3456 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
e120cacf 3457 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
64fe8abc
VB		 3458 /* G */
3459 VI0_G2_MARK, VI0_G3_MARK,
3460 VI0_G4_MARK, VI0_G5_MARK,
3461 VI0_G6_MARK, VI0_G7_MARK,
3462 /* R */
3463 VI0_R2_MARK, VI0_R3_MARK,
3464 VI0_R4_MARK, VI0_R5_MARK,
3465 VI0_R6_MARK, VI0_R7_MARK,
e120cacf 3466};
a9e4c7bb
VB		 3467static const unsigned int vin0_sync_pins[] = {
3468 RCAR_GP_PIN(0, 12), /* HSYNC */
3469 RCAR_GP_PIN(0, 13), /* VSYNC */
e120cacf 3470};
a9e4c7bb 3471static const unsigned int vin0_sync_mux[] = {
e120cacf 3472 VI0_HSYNC_N_MARK,
e120cacf
SU		 3473 VI0_VSYNC_N_MARK,
3474};
7a57be87 3475static const unsigned int vin0_field_pins[] = {
e120cacf
SU		 3476 RCAR_GP_PIN(0, 15),
3477};
7a57be87 3478static const unsigned int vin0_field_mux[] = {
e120cacf
SU		 3479 VI0_FIELD_MARK,
3480};
7a57be87 3481static const unsigned int vin0_clkenb_pins[] = {
e120cacf
SU		 3482 RCAR_GP_PIN(0, 14),
3483};
7a57be87 3484static const unsigned int vin0_clkenb_mux[] = {
e120cacf
SU		 3485 VI0_CLKENB_MARK,
3486};
3487static const unsigned int vin0_clk_pins[] = {
3488 RCAR_GP_PIN(2, 0),
3489};
3490static const unsigned int vin0_clk_mux[] = {
3491 VI0_CLK_MARK,
3492};
3493/* - VIN1 ------------------------------------------------------------------- */
317a03a9
VB		 3494static const union vin_data vin1_data_pins = {
3495 .data24 = {
3496 /* B */
3497 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3498 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3499 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3500 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3501 /* G */
3502 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3503 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3504 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3505 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3506 /* R */
3507 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3508 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3509 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3510 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3511 },
3512};
3513static const union vin_data vin1_data_mux = {
3514 .data24 = {
3515 /* B */
3516 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
3517 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3518 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3519 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3520 /* G */
3521 VI1_G0_MARK, VI1_G1_MARK,
3522 VI1_G2_MARK, VI1_G3_MARK,
3523 VI1_G4_MARK, VI1_G5_MARK,
3524 VI1_G6_MARK, VI1_G7_MARK,
3525 /* R */
3526 VI1_R0_MARK, VI1_R1_MARK,
3527 VI1_R2_MARK, VI1_R3_MARK,
3528 VI1_R4_MARK, VI1_R5_MARK,
3529 VI1_R6_MARK, VI1_R7_MARK,
3530 },
3531};
3532static const unsigned int vin1_data18_pins[] = {
3533 /* B */
3534 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3535 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
e120cacf 3536 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
317a03a9
VB		 3537 /* G */
3538 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3539 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3540 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3541 /* R */
3542 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3543 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3544 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
e120cacf 3545};
317a03a9
VB		 3546static const unsigned int vin1_data18_mux[] = {
3547 /* B */
3548 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3549 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
e120cacf 3550 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
317a03a9
VB		 3551 /* G */
3552 VI1_G2_MARK, VI1_G3_MARK,
3553 VI1_G4_MARK, VI1_G5_MARK,
3554 VI1_G6_MARK, VI1_G7_MARK,
3555 /* R */
3556 VI1_R2_MARK, VI1_R3_MARK,
3557 VI1_R4_MARK, VI1_R5_MARK,
3558 VI1_R6_MARK, VI1_R7_MARK,
3559};
3560static const unsigned int vin1_sync_pins[] = {
3561 RCAR_GP_PIN(1, 24), /* HSYNC */
3562 RCAR_GP_PIN(1, 25), /* VSYNC */
3563};
3564static const unsigned int vin1_sync_mux[] = {
3565 VI1_HSYNC_N_MARK,
3566 VI1_VSYNC_N_MARK,
3567};
3568static const unsigned int vin1_field_pins[] = {
3569 RCAR_GP_PIN(1, 13),
3570};
3571static const unsigned int vin1_field_mux[] = {
3572 VI1_FIELD_MARK,
3573};
3574static const unsigned int vin1_clkenb_pins[] = {
3575 RCAR_GP_PIN(1, 26),
3576};
3577static const unsigned int vin1_clkenb_mux[] = {
3578 VI1_CLKENB_MARK,
e120cacf
SU		 3579};
3580static const unsigned int vin1_clk_pins[] = {
3581 RCAR_GP_PIN(2, 9),
3582};
3583static const unsigned int vin1_clk_mux[] = {
3584 VI1_CLK_MARK,
3585};
054d4259
VB		 3586/* - VIN2 ----------------------------------------------------------------- */
3587static const union vin_data vin2_data_pins = {
3588 .data24 = {
3589 /* B */
3590 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3591 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3592 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3593 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3594 /* G */
3595 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3596 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3597 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3598 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3599 /* R */
3600 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3601 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3602 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3603 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3604 },
3605};
3606static const union vin_data vin2_data_mux = {
3607 .data24 = {
3608 /* B */
3609 VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
3610 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3611 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3612 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3613 /* G */
3614 VI2_G0_MARK, VI2_G1_MARK,
3615 VI2_G2_MARK, VI2_G3_MARK,
3616 VI2_G4_MARK, VI2_G5_MARK,
3617 VI2_G6_MARK, VI2_G7_MARK,
3618 /* R */
3619 VI2_R0_MARK, VI2_R1_MARK,
3620 VI2_R2_MARK, VI2_R3_MARK,
3621 VI2_R4_MARK, VI2_R5_MARK,
3622 VI2_R6_MARK, VI2_R7_MARK,
3623 },
3624};
3625static const unsigned int vin2_data18_pins[] = {
3626 /* B */
3627 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3628 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3629 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3630 /* G */
3631 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3632 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3633 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3634 /* R */
3635 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3636 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3637 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3638};
3639static const unsigned int vin2_data18_mux[] = {
3640 /* B */
3641 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3642 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3643 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3644 /* G */
3645 VI2_G2_MARK, VI2_G3_MARK,
3646 VI2_G4_MARK, VI2_G5_MARK,
3647 VI2_G6_MARK, VI2_G7_MARK,
3648 /* R */
3649 VI2_R2_MARK, VI2_R3_MARK,
3650 VI2_R4_MARK, VI2_R5_MARK,
3651 VI2_R6_MARK, VI2_R7_MARK,
3652};
3653static const unsigned int vin2_sync_pins[] = {
3654 RCAR_GP_PIN(1, 16), /* HSYNC */
3655 RCAR_GP_PIN(1, 21), /* VSYNC */
3656};
3657static const unsigned int vin2_sync_mux[] = {
3658 VI2_HSYNC_N_MARK,
3659 VI2_VSYNC_N_MARK,
3660};
3661static const unsigned int vin2_field_pins[] = {
3662 RCAR_GP_PIN(1, 9),
3663};
3664static const unsigned int vin2_field_mux[] = {
3665 VI2_FIELD_MARK,
3666};
3667static const unsigned int vin2_clkenb_pins[] = {
3668 RCAR_GP_PIN(1, 8),
3669};
3670static const unsigned int vin2_clkenb_mux[] = {
3671 VI2_CLKENB_MARK,
3672};
3673static const unsigned int vin2_clk_pins[] = {
3674 RCAR_GP_PIN(1, 11),
3675};
3676static const unsigned int vin2_clk_mux[] = {
3677 VI2_CLK_MARK,
3678};
3679/* - VIN3 ----------------------------------------------------------------- */
3680static const unsigned int vin3_data8_pins[] = {
3681 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3682 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3683 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3684 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3685};
3686static const unsigned int vin3_data8_mux[] = {
3687 VI3_DATA0_MARK, VI3_DATA1_MARK,
3688 VI3_DATA2_MARK, VI3_DATA3_MARK,
3689 VI3_DATA4_MARK, VI3_DATA5_MARK,
3690 VI3_DATA6_MARK, VI3_DATA7_MARK,
3691};
3692static const unsigned int vin3_sync_pins[] = {
3693 RCAR_GP_PIN(1, 16), /* HSYNC */
3694 RCAR_GP_PIN(1, 17), /* VSYNC */
3695};
3696static const unsigned int vin3_sync_mux[] = {
3697 VI3_HSYNC_N_MARK,
646ae3ef 3698 VI3_VSYNC_N_MARK,
054d4259
VB		 3699};
3700static const unsigned int vin3_field_pins[] = {
3701 RCAR_GP_PIN(1, 15),
3702};
3703static const unsigned int vin3_field_mux[] = {
3704 VI3_FIELD_MARK,
3705};
3706static const unsigned int vin3_clkenb_pins[] = {
3707 RCAR_GP_PIN(1, 14),
3708};
3709static const unsigned int vin3_clkenb_mux[] = {
3710 VI3_CLKENB_MARK,
3711};
3712static const unsigned int vin3_clk_pins[] = {
3713 RCAR_GP_PIN(1, 23),
3714};
3715static const unsigned int vin3_clk_mux[] = {
3716 VI3_CLK_MARK,
3717};
066f0d6e 3718
1627769b 3719static const struct sh_pfc_pin_group pinmux_groups[] = {
fcec5b22
KM		 3720 SH_PFC_PIN_GROUP(audio_clk_a),
3721 SH_PFC_PIN_GROUP(audio_clk_b),
3722 SH_PFC_PIN_GROUP(audio_clk_c),
3723 SH_PFC_PIN_GROUP(audio_clkout),
3724 SH_PFC_PIN_GROUP(audio_clkout_b),
3725 SH_PFC_PIN_GROUP(audio_clkout_c),
3726 SH_PFC_PIN_GROUP(audio_clkout_d),
62783b71
LP		 3727 SH_PFC_PIN_GROUP(du_rgb666),
3728 SH_PFC_PIN_GROUP(du_rgb888),
3729 SH_PFC_PIN_GROUP(du_clk_out_0),
3730 SH_PFC_PIN_GROUP(du_clk_out_1),
3731 SH_PFC_PIN_GROUP(du_sync_0),
3732 SH_PFC_PIN_GROUP(du_sync_1),
3733 SH_PFC_PIN_GROUP(du_cde),
3734 SH_PFC_PIN_GROUP(du0_clk_in),
3735 SH_PFC_PIN_GROUP(du1_clk_in),
3736 SH_PFC_PIN_GROUP(du2_clk_in),
1627769b
LP		 3737 SH_PFC_PIN_GROUP(eth_link),
3738 SH_PFC_PIN_GROUP(eth_magic),
3739 SH_PFC_PIN_GROUP(eth_mdio),
3740 SH_PFC_PIN_GROUP(eth_rmii),
fbd0ca3d
UH		 3741 SH_PFC_PIN_GROUP(hscif0_data),
3742 SH_PFC_PIN_GROUP(hscif0_clk),
3743 SH_PFC_PIN_GROUP(hscif0_ctrl),
3744 SH_PFC_PIN_GROUP(hscif0_data_b),
3745 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
3746 SH_PFC_PIN_GROUP(hscif0_data_c),
3747 SH_PFC_PIN_GROUP(hscif0_ctrl_c),
3748 SH_PFC_PIN_GROUP(hscif0_data_d),
3749 SH_PFC_PIN_GROUP(hscif0_ctrl_d),
3750 SH_PFC_PIN_GROUP(hscif0_data_e),
3751 SH_PFC_PIN_GROUP(hscif0_ctrl_e),
3752 SH_PFC_PIN_GROUP(hscif0_data_f),
3753 SH_PFC_PIN_GROUP(hscif0_ctrl_f),
3754 SH_PFC_PIN_GROUP(hscif1_data),
3755 SH_PFC_PIN_GROUP(hscif1_clk),
3756 SH_PFC_PIN_GROUP(hscif1_ctrl),
3757 SH_PFC_PIN_GROUP(hscif1_data_b),
3758 SH_PFC_PIN_GROUP(hscif1_clk_b),
3759 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
70702bfc
UH		 3760 SH_PFC_PIN_GROUP(i2c1),
3761 SH_PFC_PIN_GROUP(i2c1_b),
3762 SH_PFC_PIN_GROUP(i2c1_c),
3763 SH_PFC_PIN_GROUP(i2c2),
3764 SH_PFC_PIN_GROUP(i2c2_b),
3765 SH_PFC_PIN_GROUP(i2c2_c),
3766 SH_PFC_PIN_GROUP(i2c2_d),
3767 SH_PFC_PIN_GROUP(i2c2_e),
f6aaaac9 3768 SH_PFC_PIN_GROUP(i2c3),
04e7ce78
LP		 3769 SH_PFC_PIN_GROUP(intc_irq0),
3770 SH_PFC_PIN_GROUP(intc_irq1),
3771 SH_PFC_PIN_GROUP(intc_irq2),
3772 SH_PFC_PIN_GROUP(intc_irq3),
fbd0ca3d
UH		 3773 SH_PFC_PIN_GROUP(mmc0_data1),
3774 SH_PFC_PIN_GROUP(mmc0_data4),
3775 SH_PFC_PIN_GROUP(mmc0_data8),
3776 SH_PFC_PIN_GROUP(mmc0_ctrl),
3777 SH_PFC_PIN_GROUP(mmc1_data1),
3778 SH_PFC_PIN_GROUP(mmc1_data4),
3779 SH_PFC_PIN_GROUP(mmc1_data8),
3780 SH_PFC_PIN_GROUP(mmc1_ctrl),
4f47cc5e
KH		 3781 SH_PFC_PIN_GROUP(msiof0_clk),
3782 SH_PFC_PIN_GROUP(msiof0_sync),
3783 SH_PFC_PIN_GROUP(msiof0_ss1),
3784 SH_PFC_PIN_GROUP(msiof0_ss2),
3785 SH_PFC_PIN_GROUP(msiof0_rx),
3786 SH_PFC_PIN_GROUP(msiof0_tx),
7033168d
GU		 3787 SH_PFC_PIN_GROUP(msiof0_clk_b),
3788 SH_PFC_PIN_GROUP(msiof0_ss1_b),
3789 SH_PFC_PIN_GROUP(msiof0_ss2_b),
3790 SH_PFC_PIN_GROUP(msiof0_rx_b),
3791 SH_PFC_PIN_GROUP(msiof0_tx_b),
4f47cc5e
KH		 3792 SH_PFC_PIN_GROUP(msiof1_clk),
3793 SH_PFC_PIN_GROUP(msiof1_sync),
3794 SH_PFC_PIN_GROUP(msiof1_ss1),
3795 SH_PFC_PIN_GROUP(msiof1_ss2),
3796 SH_PFC_PIN_GROUP(msiof1_rx),
3797 SH_PFC_PIN_GROUP(msiof1_tx),
7033168d
GU		 3798 SH_PFC_PIN_GROUP(msiof1_clk_b),
3799 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3800 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3801 SH_PFC_PIN_GROUP(msiof1_rx_b),
3802 SH_PFC_PIN_GROUP(msiof1_tx_b),
4f47cc5e
KH		 3803 SH_PFC_PIN_GROUP(msiof2_clk),
3804 SH_PFC_PIN_GROUP(msiof2_sync),
3805 SH_PFC_PIN_GROUP(msiof2_ss1),
3806 SH_PFC_PIN_GROUP(msiof2_ss2),
3807 SH_PFC_PIN_GROUP(msiof2_rx),
3808 SH_PFC_PIN_GROUP(msiof2_tx),
3809 SH_PFC_PIN_GROUP(msiof3_clk),
3810 SH_PFC_PIN_GROUP(msiof3_sync),
3811 SH_PFC_PIN_GROUP(msiof3_ss1),
3812 SH_PFC_PIN_GROUP(msiof3_ss2),
3813 SH_PFC_PIN_GROUP(msiof3_rx),
3814 SH_PFC_PIN_GROUP(msiof3_tx),
7033168d
GU		 3815 SH_PFC_PIN_GROUP(msiof3_clk_b),
3816 SH_PFC_PIN_GROUP(msiof3_sync_b),
3817 SH_PFC_PIN_GROUP(msiof3_rx_b),
3818 SH_PFC_PIN_GROUP(msiof3_tx_b),
202909cd
GU		 3819 SH_PFC_PIN_GROUP(qspi_ctrl),
3820 SH_PFC_PIN_GROUP(qspi_data2),
3821 SH_PFC_PIN_GROUP(qspi_data4),
45c6c85d
LP		 3822 SH_PFC_PIN_GROUP(scif0_data),
3823 SH_PFC_PIN_GROUP(scif0_clk),
3824 SH_PFC_PIN_GROUP(scif0_ctrl),
3825 SH_PFC_PIN_GROUP(scif0_data_b),
3826 SH_PFC_PIN_GROUP(scif1_data),
3827 SH_PFC_PIN_GROUP(scif1_clk),
3828 SH_PFC_PIN_GROUP(scif1_ctrl),
3829 SH_PFC_PIN_GROUP(scif1_data_b),
3830 SH_PFC_PIN_GROUP(scif1_data_c),
3831 SH_PFC_PIN_GROUP(scif1_data_d),
3832 SH_PFC_PIN_GROUP(scif1_clk_d),
3833 SH_PFC_PIN_GROUP(scif1_data_e),
3834 SH_PFC_PIN_GROUP(scif1_clk_e),
2dbe7f2c
LP		 3835 SH_PFC_PIN_GROUP(scif2_data),
3836 SH_PFC_PIN_GROUP(scif2_clk),
3837 SH_PFC_PIN_GROUP(scif2_data_b),
45c6c85d
LP		 3838 SH_PFC_PIN_GROUP(scifa0_data),
3839 SH_PFC_PIN_GROUP(scifa0_clk),
3840 SH_PFC_PIN_GROUP(scifa0_ctrl),
3841 SH_PFC_PIN_GROUP(scifa0_data_b),
3842 SH_PFC_PIN_GROUP(scifa0_clk_b),
3843 SH_PFC_PIN_GROUP(scifa0_ctrl_b),
3844 SH_PFC_PIN_GROUP(scifa1_data),
3845 SH_PFC_PIN_GROUP(scifa1_clk),
3846 SH_PFC_PIN_GROUP(scifa1_ctrl),
3847 SH_PFC_PIN_GROUP(scifa1_data_b),
3848 SH_PFC_PIN_GROUP(scifa1_clk_b),
3849 SH_PFC_PIN_GROUP(scifa1_ctrl_b),
3850 SH_PFC_PIN_GROUP(scifa1_data_c),
3851 SH_PFC_PIN_GROUP(scifa1_clk_c),
3852 SH_PFC_PIN_GROUP(scifa1_ctrl_c),
3853 SH_PFC_PIN_GROUP(scifa1_data_d),
3854 SH_PFC_PIN_GROUP(scifa1_clk_d),
3855 SH_PFC_PIN_GROUP(scifa1_ctrl_d),
3856 SH_PFC_PIN_GROUP(scifa2_data),
3857 SH_PFC_PIN_GROUP(scifa2_clk),
3858 SH_PFC_PIN_GROUP(scifa2_ctrl),
3859 SH_PFC_PIN_GROUP(scifa2_data_b),
3860 SH_PFC_PIN_GROUP(scifa2_data_c),
3861 SH_PFC_PIN_GROUP(scifa2_clk_c),
3862 SH_PFC_PIN_GROUP(scifb0_data),
3863 SH_PFC_PIN_GROUP(scifb0_clk),
3864 SH_PFC_PIN_GROUP(scifb0_ctrl),
3865 SH_PFC_PIN_GROUP(scifb0_data_b),
3866 SH_PFC_PIN_GROUP(scifb0_clk_b),
3867 SH_PFC_PIN_GROUP(scifb0_ctrl_b),
3868 SH_PFC_PIN_GROUP(scifb0_data_c),
3869 SH_PFC_PIN_GROUP(scifb1_data),
3870 SH_PFC_PIN_GROUP(scifb1_clk),
3871 SH_PFC_PIN_GROUP(scifb1_ctrl),
3872 SH_PFC_PIN_GROUP(scifb1_data_b),
3873 SH_PFC_PIN_GROUP(scifb1_clk_b),
3874 SH_PFC_PIN_GROUP(scifb1_ctrl_b),
3875 SH_PFC_PIN_GROUP(scifb1_data_c),
3876 SH_PFC_PIN_GROUP(scifb1_data_d),
3877 SH_PFC_PIN_GROUP(scifb1_data_e),
3878 SH_PFC_PIN_GROUP(scifb1_clk_e),
3879 SH_PFC_PIN_GROUP(scifb1_data_f),
3880 SH_PFC_PIN_GROUP(scifb1_data_g),
3881 SH_PFC_PIN_GROUP(scifb1_clk_g),
3882 SH_PFC_PIN_GROUP(scifb2_data),
3883 SH_PFC_PIN_GROUP(scifb2_clk),
3884 SH_PFC_PIN_GROUP(scifb2_ctrl),
3885 SH_PFC_PIN_GROUP(scifb2_data_b),
3886 SH_PFC_PIN_GROUP(scifb2_clk_b),
3887 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
3888 SH_PFC_PIN_GROUP(scifb2_data_c),
066f0d6e
GL		 3889 SH_PFC_PIN_GROUP(sdhi0_data1),
3890 SH_PFC_PIN_GROUP(sdhi0_data4),
3891 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3892 SH_PFC_PIN_GROUP(sdhi0_cd),
3893 SH_PFC_PIN_GROUP(sdhi0_wp),
3894 SH_PFC_PIN_GROUP(sdhi1_data1),
3895 SH_PFC_PIN_GROUP(sdhi1_data4),
3896 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3897 SH_PFC_PIN_GROUP(sdhi1_cd),
3898 SH_PFC_PIN_GROUP(sdhi1_wp),
3899 SH_PFC_PIN_GROUP(sdhi2_data1),
3900 SH_PFC_PIN_GROUP(sdhi2_data4),
3901 SH_PFC_PIN_GROUP(sdhi2_ctrl),
3902 SH_PFC_PIN_GROUP(sdhi2_cd),
3903 SH_PFC_PIN_GROUP(sdhi2_wp),
3904 SH_PFC_PIN_GROUP(sdhi3_data1),
3905 SH_PFC_PIN_GROUP(sdhi3_data4),
3906 SH_PFC_PIN_GROUP(sdhi3_ctrl),
3907 SH_PFC_PIN_GROUP(sdhi3_cd),
3908 SH_PFC_PIN_GROUP(sdhi3_wp),
1d7b59a0
KM		 3909 SH_PFC_PIN_GROUP(ssi0_data),
3910 SH_PFC_PIN_GROUP(ssi0129_ctrl),
3911 SH_PFC_PIN_GROUP(ssi1_data),
3912 SH_PFC_PIN_GROUP(ssi1_ctrl),
3913 SH_PFC_PIN_GROUP(ssi2_data),
3914 SH_PFC_PIN_GROUP(ssi2_ctrl),
3915 SH_PFC_PIN_GROUP(ssi3_data),
3916 SH_PFC_PIN_GROUP(ssi34_ctrl),
3917 SH_PFC_PIN_GROUP(ssi4_data),
3918 SH_PFC_PIN_GROUP(ssi4_ctrl),
3919 SH_PFC_PIN_GROUP(ssi5),
3920 SH_PFC_PIN_GROUP(ssi5_b),
3921 SH_PFC_PIN_GROUP(ssi5_c),
3922 SH_PFC_PIN_GROUP(ssi6),
3923 SH_PFC_PIN_GROUP(ssi6_b),
3924 SH_PFC_PIN_GROUP(ssi7_data),
3925 SH_PFC_PIN_GROUP(ssi7_b_data),
3926 SH_PFC_PIN_GROUP(ssi7_c_data),
3927 SH_PFC_PIN_GROUP(ssi78_ctrl),
3928 SH_PFC_PIN_GROUP(ssi78_b_ctrl),
3929 SH_PFC_PIN_GROUP(ssi78_c_ctrl),
3930 SH_PFC_PIN_GROUP(ssi8_data),
3931 SH_PFC_PIN_GROUP(ssi8_b_data),
3932 SH_PFC_PIN_GROUP(ssi8_c_data),
3933 SH_PFC_PIN_GROUP(ssi9_data),
3934 SH_PFC_PIN_GROUP(ssi9_ctrl),
fbd0ca3d
UH		 3935 SH_PFC_PIN_GROUP(tpu0_to0),
3936 SH_PFC_PIN_GROUP(tpu0_to1),
3937 SH_PFC_PIN_GROUP(tpu0_to2),
3938 SH_PFC_PIN_GROUP(tpu0_to3),
dac896e2 3939 SH_PFC_PIN_GROUP(usb0),
97e00faa 3940 SH_PFC_PIN_GROUP(usb0_ovc_vbus),
dac896e2
SU		 3941 SH_PFC_PIN_GROUP(usb1),
3942 SH_PFC_PIN_GROUP(usb2),
64fe8abc
VB		 3943 VIN_DATA_PIN_GROUP(vin0_data, 24),
3944 VIN_DATA_PIN_GROUP(vin0_data, 20),
3945 SH_PFC_PIN_GROUP(vin0_data18),
3946 VIN_DATA_PIN_GROUP(vin0_data, 16),
3947 VIN_DATA_PIN_GROUP(vin0_data, 12),
3948 VIN_DATA_PIN_GROUP(vin0_data, 10),
3949 VIN_DATA_PIN_GROUP(vin0_data, 8),
3950 VIN_DATA_PIN_GROUP(vin0_data, 4),
a9e4c7bb 3951 SH_PFC_PIN_GROUP(vin0_sync),
7a57be87
VB		 3952 SH_PFC_PIN_GROUP(vin0_field),
3953 SH_PFC_PIN_GROUP(vin0_clkenb),
e120cacf 3954 SH_PFC_PIN_GROUP(vin0_clk),
317a03a9
VB		 3955 VIN_DATA_PIN_GROUP(vin1_data, 24),
3956 VIN_DATA_PIN_GROUP(vin1_data, 20),
3957 SH_PFC_PIN_GROUP(vin1_data18),
3958 VIN_DATA_PIN_GROUP(vin1_data, 16),
3959 VIN_DATA_PIN_GROUP(vin1_data, 12),
3960 VIN_DATA_PIN_GROUP(vin1_data, 10),
3961 VIN_DATA_PIN_GROUP(vin1_data, 8),
3962 VIN_DATA_PIN_GROUP(vin1_data, 4),
3963 SH_PFC_PIN_GROUP(vin1_sync),
3964 SH_PFC_PIN_GROUP(vin1_field),
3965 SH_PFC_PIN_GROUP(vin1_clkenb),
e120cacf 3966 SH_PFC_PIN_GROUP(vin1_clk),
054d4259
VB		 3967 VIN_DATA_PIN_GROUP(vin2_data, 24),
3968 SH_PFC_PIN_GROUP(vin2_data18),
3969 VIN_DATA_PIN_GROUP(vin2_data, 16),
3970 VIN_DATA_PIN_GROUP(vin2_data, 8),
3971 VIN_DATA_PIN_GROUP(vin2_data, 4),
3972 SH_PFC_PIN_GROUP(vin2_sync),
3973 SH_PFC_PIN_GROUP(vin2_field),
3974 SH_PFC_PIN_GROUP(vin2_clkenb),
3975 SH_PFC_PIN_GROUP(vin2_clk),
3976 SH_PFC_PIN_GROUP(vin3_data8),
3977 SH_PFC_PIN_GROUP(vin3_sync),
3978 SH_PFC_PIN_GROUP(vin3_field),
3979 SH_PFC_PIN_GROUP(vin3_clkenb),
3980 SH_PFC_PIN_GROUP(vin3_clk),
1627769b
LP		 3981};
3982
fcec5b22
KM		 3983static const char * const audio_clk_groups[] = {
3984 "audio_clk_a",
3985 "audio_clk_b",
3986 "audio_clk_c",
3987 "audio_clkout",
3988 "audio_clkout_b",
3989 "audio_clkout_c",
3990 "audio_clkout_d",
3991};
3992
62783b71
LP		 3993static const char * const du_groups[] = {
3994 "du_rgb666",
3995 "du_rgb888",
3996 "du_clk_out_0",
3997 "du_clk_out_1",
3998 "du_sync_0",
3999 "du_sync_1",
4000 "du_cde",
4001};
4002
4003static const char * const du0_groups[] = {
4004 "du0_clk_in",
4005};
4006
4007static const char * const du1_groups[] = {
4008 "du1_clk_in",
4009};
4010
4011static const char * const du2_groups[] = {
4012 "du2_clk_in",
4013};
4014
1627769b
LP		 4015static const char * const eth_groups[] = {
4016 "eth_link",
4017 "eth_magic",
4018 "eth_mdio",
4019 "eth_rmii",
4020};
4021
457c11d3
LP		 4022static const char * const hscif0_groups[] = {
4023 "hscif0_data",
4024 "hscif0_clk",
4025 "hscif0_ctrl",
4026 "hscif0_data_b",
4027 "hscif0_ctrl_b",
4028 "hscif0_data_c",
4029 "hscif0_ctrl_c",
4030 "hscif0_data_d",
4031 "hscif0_ctrl_d",
4032 "hscif0_data_e",
4033 "hscif0_ctrl_e",
4034 "hscif0_data_f",
4035 "hscif0_ctrl_f",
4036};
4037
4038static const char * const hscif1_groups[] = {
4039 "hscif1_data",
4040 "hscif1_clk",
4041 "hscif1_ctrl",
4042 "hscif1_data_b",
4043 "hscif1_clk_b",
4044 "hscif1_ctrl_b",
4045};
4046
70702bfc
UH		 4047static const char * const i2c1_groups[] = {
4048 "i2c1",
4049 "i2c1_b",
4050 "i2c1_c",
4051};
4052
4053static const char * const i2c2_groups[] = {
4054 "i2c2",
4055 "i2c2_b",
4056 "i2c2_c",
4057 "i2c2_d",
4058 "i2c2_e",
4059};
4060
f6aaaac9
GL		 4061static const char * const i2c3_groups[] = {
4062 "i2c3",
4063};
4064
04e7ce78
LP		 4065static const char * const intc_groups[] = {
4066 "intc_irq0",
4067 "intc_irq1",
4068 "intc_irq2",
4069 "intc_irq3",
4070};
45c6c85d 4071
457c11d3
LP		 4072static const char * const mmc0_groups[] = {
4073 "mmc0_data1",
4074 "mmc0_data4",
4075 "mmc0_data8",
4076 "mmc0_ctrl",
4077};
4078
4079static const char * const mmc1_groups[] = {
4080 "mmc1_data1",
4081 "mmc1_data4",
4082 "mmc1_data8",
4083 "mmc1_ctrl",
4084};
4085
4f47cc5e
KH		 4086static const char * const msiof0_groups[] = {
4087 "msiof0_clk",
4088 "msiof0_sync",
4089 "msiof0_ss1",
4090 "msiof0_ss2",
4091 "msiof0_rx",
4092 "msiof0_tx",
7033168d
GU		 4093 "msiof0_clk_b",
4094 "msiof0_ss1_b",
4095 "msiof0_ss2_b",
4096 "msiof0_rx_b",
4097 "msiof0_tx_b",
4f47cc5e
KH		 4098};
4099
4100static const char * const msiof1_groups[] = {
4101 "msiof1_clk",
4102 "msiof1_sync",
4103 "msiof1_ss1",
4104 "msiof1_ss2",
4105 "msiof1_rx",
4106 "msiof1_tx",
7033168d
GU		 4107 "msiof1_clk_b",
4108 "msiof1_ss1_b",
4109 "msiof1_ss2_b",
4110 "msiof1_rx_b",
4111 "msiof1_tx_b",
4f47cc5e
KH		 4112};
4113
4114static const char * const msiof2_groups[] = {
4115 "msiof2_clk",
4116 "msiof2_sync",
4117 "msiof2_ss1",
4118 "msiof2_ss2",
4119 "msiof2_rx",
4120 "msiof2_tx",
4121};
4122
4123static const char * const msiof3_groups[] = {
4124 "msiof3_clk",
4125 "msiof3_sync",
4126 "msiof3_ss1",
4127 "msiof3_ss2",
4128 "msiof3_rx",
4129 "msiof3_tx",
7033168d
GU		 4130 "msiof3_clk_b",
4131 "msiof3_sync_b",
4132 "msiof3_rx_b",
4133 "msiof3_tx_b",
4f47cc5e
KH		 4134};
4135
202909cd
GU		 4136static const char * const qspi_groups[] = {
4137 "qspi_ctrl",
4138 "qspi_data2",
4139 "qspi_data4",
4140};
4141
45c6c85d
LP		 4142static const char * const scif0_groups[] = {
4143 "scif0_data",
4144 "scif0_clk",
4145 "scif0_ctrl",
4146 "scif0_data_b",
4147};
4148
4149static const char * const scif1_groups[] = {
4150 "scif1_data",
4151 "scif1_clk",
4152 "scif1_ctrl",
4153 "scif1_data_b",
4154 "scif1_data_c",
4155 "scif1_data_d",
4156 "scif1_clk_d",
4157 "scif1_data_e",
4158 "scif1_clk_e",
4159};
4160
2dbe7f2c
LP		 4161static const char * const scif2_groups[] = {
4162 "scif2_data",
4163 "scif2_clk",
4164 "scif2_data_b",
fbd0ca3d
UH		 4165};
4166
45c6c85d
LP		 4167static const char * const scifa0_groups[] = {
4168 "scifa0_data",
4169 "scifa0_clk",
4170 "scifa0_ctrl",
4171 "scifa0_data_b",
4172 "scifa0_clk_b",
4173 "scifa0_ctrl_b",
4174};
4175
4176static const char * const scifa1_groups[] = {
4177 "scifa1_data",
4178 "scifa1_clk",
4179 "scifa1_ctrl",
4180 "scifa1_data_b",
4181 "scifa1_clk_b",
4182 "scifa1_ctrl_b",
4183 "scifa1_data_c",
4184 "scifa1_clk_c",
4185 "scifa1_ctrl_c",
4186 "scifa1_data_d",
4187 "scifa1_clk_d",
4188 "scifa1_ctrl_d",
4189};
4190
4191static const char * const scifa2_groups[] = {
4192 "scifa2_data",
4193 "scifa2_clk",
4194 "scifa2_ctrl",
4195 "scifa2_data_b",
4196 "scifa2_data_c",
4197 "scifa2_clk_c",
4198};
4199
4200static const char * const scifb0_groups[] = {
4201 "scifb0_data",
4202 "scifb0_clk",
4203 "scifb0_ctrl",
4204 "scifb0_data_b",
4205 "scifb0_clk_b",
4206 "scifb0_ctrl_b",
4207 "scifb0_data_c",
4208};
4209
4210static const char * const scifb1_groups[] = {
4211 "scifb1_data",
4212 "scifb1_clk",
4213 "scifb1_ctrl",
4214 "scifb1_data_b",
4215 "scifb1_clk_b",
4216 "scifb1_ctrl_b",
4217 "scifb1_data_c",
4218 "scifb1_data_d",
4219 "scifb1_data_e",
4220 "scifb1_clk_e",
4221 "scifb1_data_f",
4222 "scifb1_data_g",
4223 "scifb1_clk_g",
4224};
4225
4226static const char * const scifb2_groups[] = {
4227 "scifb2_data",
4228 "scifb2_clk",
4229 "scifb2_ctrl",
4230 "scifb2_data_b",
4231 "scifb2_clk_b",
4232 "scifb2_ctrl_b",
4233 "scifb2_data_c",
4234};
4235
066f0d6e
GL		 4236static const char * const sdhi0_groups[] = {
4237 "sdhi0_data1",
4238 "sdhi0_data4",
4239 "sdhi0_ctrl",
4240 "sdhi0_cd",
4241 "sdhi0_wp",
4242};
4243
4244static const char * const sdhi1_groups[] = {
4245 "sdhi1_data1",
4246 "sdhi1_data4",
4247 "sdhi1_ctrl",
4248 "sdhi1_cd",
4249 "sdhi1_wp",
4250};
4251
4252static const char * const sdhi2_groups[] = {
4253 "sdhi2_data1",
4254 "sdhi2_data4",
4255 "sdhi2_ctrl",
4256 "sdhi2_cd",
4257 "sdhi2_wp",
4258};
4259
4260static const char * const sdhi3_groups[] = {
4261 "sdhi3_data1",
4262 "sdhi3_data4",
4263 "sdhi3_ctrl",
4264 "sdhi3_cd",
4265 "sdhi3_wp",
4266};
4267
1d7b59a0
KM		 4268static const char * const ssi_groups[] = {
4269 "ssi0_data",
4270 "ssi0129_ctrl",
4271 "ssi1_data",
4272 "ssi1_ctrl",
4273 "ssi2_data",
4274 "ssi2_ctrl",
4275 "ssi3_data",
4276 "ssi34_ctrl",
4277 "ssi4_data",
4278 "ssi4_ctrl",
4279 "ssi5",
4280 "ssi5_b",
4281 "ssi5_c",
4282 "ssi6",
4283 "ssi6_b",
4284 "ssi7_data",
4285 "ssi7_b_data",
4286 "ssi7_c_data",
4287 "ssi78_ctrl",
4288 "ssi78_b_ctrl",
4289 "ssi78_c_ctrl",
4290 "ssi8_data",
4291 "ssi8_b_data",
4292 "ssi8_c_data",
4293 "ssi9_data",
4294 "ssi9_ctrl",
4295};
4296
457c11d3
LP		 4297static const char * const tpu0_groups[] = {
4298 "tpu0_to0",
4299 "tpu0_to1",
4300 "tpu0_to2",
4301 "tpu0_to3",
4302};
4303
dac896e2
SU		 4304static const char * const usb0_groups[] = {
4305 "usb0",
97e00faa 4306 "usb0_ovc_vbus",
dac896e2
SU		 4307};
4308
4309static const char * const usb1_groups[] = {
4310 "usb1",
4311};
4312
4313static const char * const usb2_groups[] = {
4314 "usb2",
4315};
4316
e120cacf 4317static const char * const vin0_groups[] = {
64fe8abc
VB		 4318 "vin0_data24",
4319 "vin0_data20",
4320 "vin0_data18",
4321 "vin0_data16",
4322 "vin0_data12",
4323 "vin0_data10",
4324 "vin0_data8",
4325 "vin0_data4",
a9e4c7bb 4326 "vin0_sync",
7a57be87
VB		 4327 "vin0_field",
4328 "vin0_clkenb",
e120cacf
SU		 4329 "vin0_clk",
4330};
4331
4332static const char * const vin1_groups[] = {
317a03a9
VB		 4333 "vin1_data24",
4334 "vin1_data20",
4335 "vin1_data18",
4336 "vin1_data16",
4337 "vin1_data12",
4338 "vin1_data10",
4339 "vin1_data8",
4340 "vin1_data4",
4341 "vin1_sync",
4342 "vin1_field",
4343 "vin1_clkenb",
e120cacf
SU		 4344 "vin1_clk",
4345};
4346
054d4259
VB		 4347static const char * const vin2_groups[] = {
4348 "vin2_data24",
4349 "vin2_data18",
4350 "vin2_data16",
4351 "vin2_data8",
4352 "vin2_data4",
4353 "vin2_sync",
4354 "vin2_field",
4355 "vin2_clkenb",
4356 "vin2_clk",
4357};
4358
4359static const char * const vin3_groups[] = {
4360 "vin3_data8",
4361 "vin3_sync",
4362 "vin3_field",
4363 "vin3_clkenb",
4364 "vin3_clk",
4365};
4366
1627769b 4367static const struct sh_pfc_function pinmux_functions[] = {
fcec5b22 4368 SH_PFC_FUNCTION(audio_clk),
62783b71
LP		 4369 SH_PFC_FUNCTION(du),
4370 SH_PFC_FUNCTION(du0),
4371 SH_PFC_FUNCTION(du1),
4372 SH_PFC_FUNCTION(du2),
1627769b 4373 SH_PFC_FUNCTION(eth),
fbd0ca3d
UH		 4374 SH_PFC_FUNCTION(hscif0),
4375 SH_PFC_FUNCTION(hscif1),
70702bfc
UH		 4376 SH_PFC_FUNCTION(i2c1),
4377 SH_PFC_FUNCTION(i2c2),
f6aaaac9 4378 SH_PFC_FUNCTION(i2c3),
04e7ce78 4379 SH_PFC_FUNCTION(intc),
fbd0ca3d
UH		 4380 SH_PFC_FUNCTION(mmc0),
4381 SH_PFC_FUNCTION(mmc1),
4f47cc5e
KH		 4382 SH_PFC_FUNCTION(msiof0),
4383 SH_PFC_FUNCTION(msiof1),
4384 SH_PFC_FUNCTION(msiof2),
4385 SH_PFC_FUNCTION(msiof3),
202909cd 4386 SH_PFC_FUNCTION(qspi),
45c6c85d
LP		 4387 SH_PFC_FUNCTION(scif0),
4388 SH_PFC_FUNCTION(scif1),
2dbe7f2c 4389 SH_PFC_FUNCTION(scif2),
45c6c85d
LP		 4390 SH_PFC_FUNCTION(scifa0),
4391 SH_PFC_FUNCTION(scifa1),
4392 SH_PFC_FUNCTION(scifa2),
4393 SH_PFC_FUNCTION(scifb0),
4394 SH_PFC_FUNCTION(scifb1),
4395 SH_PFC_FUNCTION(scifb2),
066f0d6e
GL		 4396 SH_PFC_FUNCTION(sdhi0),
4397 SH_PFC_FUNCTION(sdhi1),
4398 SH_PFC_FUNCTION(sdhi2),
4399 SH_PFC_FUNCTION(sdhi3),
1d7b59a0 4400 SH_PFC_FUNCTION(ssi),
fbd0ca3d 4401 SH_PFC_FUNCTION(tpu0),
dac896e2
SU		 4402 SH_PFC_FUNCTION(usb0),
4403 SH_PFC_FUNCTION(usb1),
4404 SH_PFC_FUNCTION(usb2),
e120cacf
SU		 4405 SH_PFC_FUNCTION(vin0),
4406 SH_PFC_FUNCTION(vin1),
054d4259
VB		 4407 SH_PFC_FUNCTION(vin2),
4408 SH_PFC_FUNCTION(vin3),
1627769b
LP		 4409};
4410
44a45b55 4411static const struct pinmux_cfg_reg pinmux_config_regs[] = {
58c229e1
KM		 4412 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
4413 GP_0_31_FN, FN_IP3_17_15,
4414 GP_0_30_FN, FN_IP3_14_12,
4415 GP_0_29_FN, FN_IP3_11_8,
4416 GP_0_28_FN, FN_IP3_7_4,
4417 GP_0_27_FN, FN_IP3_3_0,
4418 GP_0_26_FN, FN_IP2_28_26,
4419 GP_0_25_FN, FN_IP2_25_22,
4420 GP_0_24_FN, FN_IP2_21_18,
4421 GP_0_23_FN, FN_IP2_17_15,
4422 GP_0_22_FN, FN_IP2_14_12,
4423 GP_0_21_FN, FN_IP2_11_9,
4424 GP_0_20_FN, FN_IP2_8_6,
4425 GP_0_19_FN, FN_IP2_5_3,
4426 GP_0_18_FN, FN_IP2_2_0,
4427 GP_0_17_FN, FN_IP1_29_28,
4428 GP_0_16_FN, FN_IP1_27_26,
4429 GP_0_15_FN, FN_IP1_25_22,
4430 GP_0_14_FN, FN_IP1_21_18,
4431 GP_0_13_FN, FN_IP1_17_15,
4432 GP_0_12_FN, FN_IP1_14_12,
4433 GP_0_11_FN, FN_IP1_11_8,
4434 GP_0_10_FN, FN_IP1_7_4,
4435 GP_0_9_FN, FN_IP1_3_0,
4436 GP_0_8_FN, FN_IP0_30_27,
4437 GP_0_7_FN, FN_IP0_26_23,
4438 GP_0_6_FN, FN_IP0_22_20,
4439 GP_0_5_FN, FN_IP0_19_16,
4440 GP_0_4_FN, FN_IP0_15_12,
4441 GP_0_3_FN, FN_IP0_11_9,
4442 GP_0_2_FN, FN_IP0_8_6,
4443 GP_0_1_FN, FN_IP0_5_3,
4444 GP_0_0_FN, FN_IP0_2_0 }
4445 },
4446 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
4447 0, 0,
4448 0, 0,
4449 GP_1_29_FN, FN_IP6_13_11,
4450 GP_1_28_FN, FN_IP6_10_9,
4451 GP_1_27_FN, FN_IP6_8_6,
4452 GP_1_26_FN, FN_IP6_5_3,
4453 GP_1_25_FN, FN_IP6_2_0,
4454 GP_1_24_FN, FN_IP5_29_27,
4455 GP_1_23_FN, FN_IP5_26_24,
4456 GP_1_22_FN, FN_IP5_23_21,
4457 GP_1_21_FN, FN_IP5_20_18,
4458 GP_1_20_FN, FN_IP5_17_15,
4459 GP_1_19_FN, FN_IP5_14_13,
4460 GP_1_18_FN, FN_IP5_12_10,
4461 GP_1_17_FN, FN_IP5_9_6,
4462 GP_1_16_FN, FN_IP5_5_3,
4463 GP_1_15_FN, FN_IP5_2_0,
4464 GP_1_14_FN, FN_IP4_29_27,
4465 GP_1_13_FN, FN_IP4_26_24,
4466 GP_1_12_FN, FN_IP4_23_21,
4467 GP_1_11_FN, FN_IP4_20_18,
4468 GP_1_10_FN, FN_IP4_17_15,
4469 GP_1_9_FN, FN_IP4_14_12,
4470 GP_1_8_FN, FN_IP4_11_9,
4471 GP_1_7_FN, FN_IP4_8_6,
4472 GP_1_6_FN, FN_IP4_5_3,
4473 GP_1_5_FN, FN_IP4_2_0,
4474 GP_1_4_FN, FN_IP3_31_29,
4475 GP_1_3_FN, FN_IP3_28_26,
4476 GP_1_2_FN, FN_IP3_25_23,
4477 GP_1_1_FN, FN_IP3_22_20,
4478 GP_1_0_FN, FN_IP3_19_18, }
4479 },
4480 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
4481 0, 0,
4482 0, 0,
4483 GP_2_29_FN, FN_IP7_15_13,
4484 GP_2_28_FN, FN_IP7_12_10,
4485 GP_2_27_FN, FN_IP7_9_8,
4486 GP_2_26_FN, FN_IP7_7_6,
4487 GP_2_25_FN, FN_IP7_5_3,
4488 GP_2_24_FN, FN_IP7_2_0,
4489 GP_2_23_FN, FN_IP6_31_29,
4490 GP_2_22_FN, FN_IP6_28_26,
4491 GP_2_21_FN, FN_IP6_25_23,
4492 GP_2_20_FN, FN_IP6_22_20,
4493 GP_2_19_FN, FN_IP6_19_17,
4494 GP_2_18_FN, FN_IP6_16_14,
4495 GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
4496 GP_2_16_FN, FN_IP8_27,
4497 GP_2_15_FN, FN_IP8_26,
4498 GP_2_14_FN, FN_IP8_25_24,
4499 GP_2_13_FN, FN_IP8_23_22,
4500 GP_2_12_FN, FN_IP8_21_20,
4501 GP_2_11_FN, FN_IP8_19_18,
4502 GP_2_10_FN, FN_IP8_17_16,
4503 GP_2_9_FN, FN_IP8_15_14,
4504 GP_2_8_FN, FN_IP8_13_12,
4505 GP_2_7_FN, FN_IP8_11_10,
4506 GP_2_6_FN, FN_IP8_9_8,
4507 GP_2_5_FN, FN_IP8_7_6,
4508 GP_2_4_FN, FN_IP8_5_4,
4509 GP_2_3_FN, FN_IP8_3_2,
4510 GP_2_2_FN, FN_IP8_1_0,
4511 GP_2_1_FN, FN_IP7_30_29,
4512 GP_2_0_FN, FN_IP7_28_27 }
4513 },
4514 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
4515 GP_3_31_FN, FN_IP11_21_18,
4516 GP_3_30_FN, FN_IP11_17_15,
4517 GP_3_29_FN, FN_IP11_14_13,
4518 GP_3_28_FN, FN_IP11_12_11,
4519 GP_3_27_FN, FN_IP11_10_9,
4520 GP_3_26_FN, FN_IP11_8_7,
4521 GP_3_25_FN, FN_IP11_6_5,
4522 GP_3_24_FN, FN_IP11_4,
4523 GP_3_23_FN, FN_IP11_3_0,
4524 GP_3_22_FN, FN_IP10_29_26,
4525 GP_3_21_FN, FN_IP10_25_23,
4526 GP_3_20_FN, FN_IP10_22_19,
4527 GP_3_19_FN, FN_IP10_18_15,
4528 GP_3_18_FN, FN_IP10_14_11,
4529 GP_3_17_FN, FN_IP10_10_7,
4530 GP_3_16_FN, FN_IP10_6_4,
4531 GP_3_15_FN, FN_IP10_3_0,
4532 GP_3_14_FN, FN_IP9_31_28,
4533 GP_3_13_FN, FN_IP9_27_26,
4534 GP_3_12_FN, FN_IP9_25_24,
4535 GP_3_11_FN, FN_IP9_23_22,
4536 GP_3_10_FN, FN_IP9_21_20,
4537 GP_3_9_FN, FN_IP9_19_18,
4538 GP_3_8_FN, FN_IP9_17_16,
4539 GP_3_7_FN, FN_IP9_15_12,
4540 GP_3_6_FN, FN_IP9_11_8,
4541 GP_3_5_FN, FN_IP9_7_6,
4542 GP_3_4_FN, FN_IP9_5_4,
4543 GP_3_3_FN, FN_IP9_3_2,
4544 GP_3_2_FN, FN_IP9_1_0,
4545 GP_3_1_FN, FN_IP8_30_29,
4546 GP_3_0_FN, FN_IP8_28 }
4547 },
4548 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
4549 GP_4_31_FN, FN_IP14_18_16,
4550 GP_4_30_FN, FN_IP14_15_12,
4551 GP_4_29_FN, FN_IP14_11_9,
4552 GP_4_28_FN, FN_IP14_8_6,
4553 GP_4_27_FN, FN_IP14_5_3,
4554 GP_4_26_FN, FN_IP14_2_0,
4555 GP_4_25_FN, FN_IP13_30_29,
4556 GP_4_24_FN, FN_IP13_28_26,
4557 GP_4_23_FN, FN_IP13_25_23,
4558 GP_4_22_FN, FN_IP13_22_19,
4559 GP_4_21_FN, FN_IP13_18_16,
4560 GP_4_20_FN, FN_IP13_15_13,
4561 GP_4_19_FN, FN_IP13_12_10,
4562 GP_4_18_FN, FN_IP13_9_7,
4563 GP_4_17_FN, FN_IP13_6_3,
4564 GP_4_16_FN, FN_IP13_2_0,
4565 GP_4_15_FN, FN_IP12_30_28,
4566 GP_4_14_FN, FN_IP12_27_25,
4567 GP_4_13_FN, FN_IP12_24_23,
4568 GP_4_12_FN, FN_IP12_22_20,
4569 GP_4_11_FN, FN_IP12_19_17,
4570 GP_4_10_FN, FN_IP12_16_14,
4571 GP_4_9_FN, FN_IP12_13_11,
4572 GP_4_8_FN, FN_IP12_10_8,
4573 GP_4_7_FN, FN_IP12_7_6,
4574 GP_4_6_FN, FN_IP12_5_4,
4575 GP_4_5_FN, FN_IP12_3_2,
4576 GP_4_4_FN, FN_IP12_1_0,
4577 GP_4_3_FN, FN_IP11_31_30,
4578 GP_4_2_FN, FN_IP11_29_27,
4579 GP_4_1_FN, FN_IP11_26_24,
4580 GP_4_0_FN, FN_IP11_23_22 }
4581 },
4582 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
4583 GP_5_31_FN, FN_IP7_24_22,
4584 GP_5_30_FN, FN_IP7_21_19,
4585 GP_5_29_FN, FN_IP7_18_16,
4586 GP_5_28_FN, FN_DU_DOTCLKIN2,
4587 GP_5_27_FN, FN_IP7_26_25,
4588 GP_5_26_FN, FN_DU_DOTCLKIN0,
4589 GP_5_25_FN, FN_AVS2,
4590 GP_5_24_FN, FN_AVS1,
4591 GP_5_23_FN, FN_USB2_OVC,
4592 GP_5_22_FN, FN_USB2_PWEN,
4593 GP_5_21_FN, FN_IP16_7,
4594 GP_5_20_FN, FN_IP16_6,
4595 GP_5_19_FN, FN_USB0_OVC_VBUS,
4596 GP_5_18_FN, FN_USB0_PWEN,
4597 GP_5_17_FN, FN_IP16_5_3,
4598 GP_5_16_FN, FN_IP16_2_0,
4599 GP_5_15_FN, FN_IP15_29_28,
4600 GP_5_14_FN, FN_IP15_27_26,
4601 GP_5_13_FN, FN_IP15_25_23,
4602 GP_5_12_FN, FN_IP15_22_20,
4603 GP_5_11_FN, FN_IP15_19_18,
4604 GP_5_10_FN, FN_IP15_17_16,
4605 GP_5_9_FN, FN_IP15_15_14,
4606 GP_5_8_FN, FN_IP15_13_12,
4607 GP_5_7_FN, FN_IP15_11_9,
4608 GP_5_6_FN, FN_IP15_8_6,
4609 GP_5_5_FN, FN_IP15_5_3,
4610 GP_5_4_FN, FN_IP15_2_0,
4611 GP_5_3_FN, FN_IP14_30_28,
4612 GP_5_2_FN, FN_IP14_27_25,
4613 GP_5_1_FN, FN_IP14_24_22,
4614 GP_5_0_FN, FN_IP14_21_19 }
4615 },
4616 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4617 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
4618 /* IP0_31 [1] */
4619 0, 0,
4620 /* IP0_30_27 [4] */
9f2edd41 4621 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
58c229e1
KM		 4622 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
4623 0, 0, 0, 0, 0, 0, 0, 0, 0,
4624 /* IP0_26_23 [4] */
c4721249
SK		 4625 FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
4626 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
05bcb07b 4627 FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
58c229e1 4628 /* IP0_22_20 [3] */
c4721249
SK		 4629 FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
4630 FN_I2C2_SCL_C, 0, 0,
58c229e1
KM		 4631 /* IP0_19_16 [4] */
4632 FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
4633 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
4634 0, 0, 0, 0, 0, 0, 0, 0, 0,
4635 /* IP0_15_12 [4] */
4636 FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
4637 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
4638 0, 0, 0, 0, 0, 0, 0, 0, 0,
4639 /* IP0_11_9 [3] */
4640 FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
4641 0, 0, 0,
4642 /* IP0_8_6 [3] */
4643 FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
4644 0, 0, 0,
4645 /* IP0_5_3 [3] */
4646 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
4647 0, 0, 0,
4648 /* IP0_2_0 [3] */
4649 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
4650 0, 0, 0, }
4651 },
4652 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4653 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
4654 /* IP1_31_30 [2] */
4655 0, 0, 0, 0,
4656 /* IP1_29_28 [2] */
4657 FN_A1, FN_PWM4, 0, 0,
4658 /* IP1_27_26 [2] */
4659 FN_A0, FN_PWM3, 0, 0,
4660 /* IP1_25_22 [4] */
4661 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
4662 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
4663 0, 0, 0, 0, 0, 0, 0, 0, 0,
4664 /* IP1_21_18 [4] */
4665 FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
4666 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
4667 0, 0, 0, 0, 0, 0, 0, 0, 0,
4668 /* IP1_17_15 [3] */
4669 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
4670 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
4671 0, 0, 0,
4672 /* IP1_14_12 [3] */
4673 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
4674 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
4675 0, 0,
4676 /* IP1_11_8 [4] */
9f2edd41 4677 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
58c229e1
KM		 4678 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
4679 0, 0, 0, 0, 0, 0, 0, 0, 0,
4680 /* IP1_7_4 [4] */
9f2edd41 4681 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
58c229e1
KM		 4682 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
4683 0, 0, 0, 0, 0, 0, 0, 0, 0,
4684 /* IP1_3_0 [4] */
9f2edd41 4685 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
58c229e1
KM		 4686 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
4687 0, 0, 0, 0, 0, 0, 0, 0, 0, }
4688 },
4689 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4690 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
4691 /* IP2_31_29 [3] */
4692 0, 0, 0, 0, 0, 0, 0, 0,
4693 /* IP2_28_26 [3] */
4694 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
4695 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
4696 /* IP2_25_22 [4] */
4697 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
1ddb66cd 4698 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
58c229e1
KM		 4699 0, 0, 0, 0, 0, 0, 0, 0,
4700 /* IP2_21_18 [4] */
4701 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
1ddb66cd 4702 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
58c229e1
KM		 4703 0, 0, 0, 0, 0, 0, 0, 0,
4704 /* IP2_17_15 [3] */
4705 FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
4706 0, 0, 0, 0,
4707 /* IP2_14_12 [3] */
4708 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
4709 /* IP2_11_9 [3] */
4710 FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
4711 /* IP2_8_6 [3] */
4712 FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
4713 /* IP2_5_3 [3] */
4714 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
4715 /* IP2_2_0 [3] */
4716 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, }
4717 },
4718 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
4719 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
4720 /* IP3_31_29 [3] */
4721 FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
4722 0, 0, 0,
4723 /* IP3_28_26 [3] */
4724 FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
4725 0, 0, 0, 0,
4726 /* IP3_25_23 [3] */
4727 FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
4728 /* IP3_22_20 [3] */
4729 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
4730 /* IP3_19_18 [2] */
4731 FN_A16, FN_ATAWR1_N, 0, 0,
4732 /* IP3_17_15 [3] */
4733 FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
4734 0, 0, 0, 0,
4735 /* IP3_14_12 [3] */
4736 FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
4737 0, 0, 0, 0,
4738 /* IP3_11_8 [4] */
4739 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
4740 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
4741 FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
4742 /* IP3_7_4 [4] */
4743 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
4744 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
4745 0, 0, 0, 0, 0, 0, 0, 0, 0,
4746 /* IP3_3_0 [4] */
4747 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
4748 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
4749 0, 0, 0, 0, 0, 0, 0, 0, }
4750 },
4751 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
4752 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
4753 /* IP4_31_30 [2] */
4754 0, 0, 0, 0,
4755 /* IP4_29_27 [3] */
4756 FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
4757 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
4758 /* IP4_26_24 [3] */
4759 FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
4760 FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
4761 /* IP4_23_21 [3] */
4762 FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
4763 FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
4764 /* IP4_20_18 [3] */
4765 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
4766 FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
4767 /* IP4_17_15 [3] */
4768 FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
4769 0, 0, 0,
4770 /* IP4_14_12 [3] */
4771 FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
4772 FN_VI2_FIELD_B, 0, 0,
4773 /* IP4_11_9 [3] */
4774 FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
4775 FN_VI2_CLKENB_B, 0, 0,
4776 /* IP4_8_6 [3] */
4777 FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
4778 /* IP4_5_3 [3] */
4779 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
4780 /* IP4_2_0 [3] */
4781 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
4782 }
4783 },
4784 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
4785 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
4786 /* IP5_31_30 [2] */
4787 0, 0, 0, 0,
4788 /* IP5_29_27 [3] */
4789 FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
4790 FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
4791 /* IP5_26_24 [3] */
4792 FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
4793 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
4794 FN_MSIOF0_SCK_B, 0,
4795 /* IP5_23_21 [3] */
4796 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
4797 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
4798 FN_IERX_C, 0,
4799 /* IP5_20_18 [3] */
4800 FN_WE0_N, FN_IECLK, FN_CAN_CLK,
4801 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
4802 /* IP5_17_15 [3] */
4803 FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
4804 FN_INTC_IRQ4_N, 0, 0,
4805 /* IP5_14_13 [2] */
4806 FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
4807 /* IP5_12_10 [3] */
4808 FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
4809 0, 0,
4810 /* IP5_9_6 [4] */
4811 FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
c4721249
SK		 4812 FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
4813 FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
58c229e1
KM		 4814 /* IP5_5_3 [3] */
4815 FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
c4721249
SK		 4816 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
4817 FN_INTC_EN0_N, FN_I2C1_SCL,
58c229e1
KM		 4818 /* IP5_2_0 [3] */
4819 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
4820 FN_VI2_R3, 0, 0, }
4821 },
4822 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
4823 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
4824 /* IP6_31_29 [3] */
9f2edd41 4825 FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
58c229e1
KM		 4826 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
4827 /* IP6_28_26 [3] */
9f2edd41 4828 FN_ETH_LINK, 0, FN_HTX0_E,
58c229e1
KM		 4829 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
4830 /* IP6_25_23 [3] */
9f2edd41 4831 FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
58c229e1
KM		 4832 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
4833 /* IP6_22_20 [3] */
9f2edd41 4834 FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
58c229e1
KM		 4835 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
4836 /* IP6_19_17 [3] */
9f2edd41 4837 FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
c4721249 4838 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
58c229e1 4839 /* IP6_16_14 [3] */
9f2edd41 4840 FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
c4721249
SK		 4841 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
4842 FN_I2C2_SCL_E, 0,
58c229e1
KM		 4843 /* IP6_13_11 [3] */
4844 FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
4845 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
4846 /* IP6_10_9 [2] */
4847 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
4848 /* IP6_8_6 [3] */
4849 FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
4850 FN_SSI_SDATA8_C, 0, 0, 0,
4851 /* IP6_5_3 [3] */
4852 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
4853 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
4854 /* IP6_2_0 [3] */
4855 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
4856 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
4857 },
4858 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
4859 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
4860 /* IP7_31 [1] */
4861 0, 0,
4862 /* IP7_30_29 [2] */
9f2edd41 4863 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
58c229e1 4864 /* IP7_28_27 [2] */
9f2edd41 4865 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
58c229e1 4866 /* IP7_26_25 [2] */
f0681209 4867 FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
58c229e1
KM		 4868 /* IP7_24_22 [3] */
4869 FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
4870 0, 0, 0,
4871 /* IP7_21_19 [3] */
4872 FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
4873 FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
4874 /* IP7_18_16 [3] */
4875 FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
4876 FN_GLO_SS_C, 0, 0, 0,
4877 /* IP7_15_13 [3] */
9f2edd41 4878 FN_ETH_MDC, 0, FN_STP_ISD_1_B,
58c229e1
KM		 4879 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
4880 /* IP7_12_10 [3] */
9f2edd41 4881 FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
58c229e1
KM		 4882 FN_GLO_SCLK_C, 0, 0, 0,
4883 /* IP7_9_8 [2] */
9f2edd41 4884 FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
58c229e1 4885 /* IP7_7_6 [2] */
9f2edd41 4886 FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
58c229e1 4887 /* IP7_5_3 [3] */
14da999b 4888 FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
58c229e1 4889 /* IP7_2_0 [3] */
9f2edd41 4890 FN_ETH_MDIO, 0, FN_HRTS0_N_E,
58c229e1
KM		 4891 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
4892 },
4893 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
4894 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
4895 2, 2, 2, 2, 2, 2, 2) {
4896 /* IP8_31 [1] */
4897 0, 0,
4898 /* IP8_30_29 [2] */
4899 FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
4900 /* IP8_28 [1] */
4901 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
4902 /* IP8_27 [1] */
4903 FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
4904 /* IP8_26 [1] */
4905 FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
4906 /* IP8_25_24 [2] */
4907 FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
9f2edd41 4908 FN_AVB_MAGIC, 0,
58c229e1
KM		 4909 /* IP8_23_22 [2] */
4910 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
4911 /* IP8_21_20 [2] */
9f2edd41 4912 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
58c229e1 4913 /* IP8_19_18 [2] */
9f2edd41 4914 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
58c229e1 4915 /* IP8_17_16 [2] */
9f2edd41 4916 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
58c229e1 4917 /* IP8_15_14 [2] */
9f2edd41 4918 FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
58c229e1 4919 /* IP8_13_12 [2] */
9f2edd41 4920 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
58c229e1 4921 /* IP8_11_10 [2] */
9f2edd41 4922 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
58c229e1
KM		 4923 /* IP8_9_8 [2] */
4924 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
4925 /* IP8_7_6 [2] */
4926 FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
4927 /* IP8_5_4 [2] */
4928 FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
4929 /* IP8_3_2 [2] */
4930 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
4931 /* IP8_1_0 [2] */
9f2edd41 4932 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, }
58c229e1
KM		 4933 },
4934 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
4935 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
4936 /* IP9_31_28 [4] */
4937 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
c4721249 4938 FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
58c229e1
KM		 4939 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
4940 /* IP9_27_26 [2] */
9f2edd41 4941 FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
58c229e1 4942 /* IP9_25_24 [2] */
9f2edd41 4943 FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
58c229e1 4944 /* IP9_23_22 [2] */
9f2edd41 4945 FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
58c229e1 4946 /* IP9_21_20 [2] */
9f2edd41 4947 FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
58c229e1 4948 /* IP9_19_18 [2] */
9f2edd41 4949 FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
58c229e1 4950 /* IP9_17_16 [2] */
9f2edd41 4951 FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
58c229e1
KM		 4952 /* IP9_15_12 [4] */
4953 FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
c4721249
SK		 4954 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
4955 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
58c229e1
KM		 4956 /* IP9_11_8 [4] */
4957 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
c4721249
SK		 4958 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
4959 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
58c229e1
KM		 4960 /* IP9_7_6 [2] */
4961 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
4962 /* IP9_5_4 [2] */
4963 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
4964 /* IP9_3_2 [2] */
4965 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
4966 /* IP9_1_0 [2] */
4967 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
4968 },
4969 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
4970 2, 4, 3, 4, 4, 4, 4, 3, 4) {
4971 /* IP10_31_30 [2] */
4972 0, 0, 0, 0,
4973 /* IP10_29_26 [4] */
4974 FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
4975 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
4976 FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
4977 /* IP10_25_23 [3] */
4978 FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
4979 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
4980 /* IP10_22_19 [4] */
14da999b 4981 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
58c229e1
KM		 4982 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
4983 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
4984 /* IP10_18_15 [4] */
14da999b 4985 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
58c229e1
KM		 4986 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
4987 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
4988 0, 0, 0, 0, 0, 0,
4989 /* IP10_14_11 [4] */
4990 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
4991 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
4992 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
4993 0, 0, 0, 0, 0, 0, 0,
4994 /* IP10_10_7 [4] */
4995 FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
4996 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
4997 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
4998 0, 0, 0, 0, 0, 0, 0,
4999 /* IP10_6_4 [3] */
5000 FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
5001 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
5002 FN_VI3_DATA0_B, 0,
5003 /* IP10_3_0 [4] */
5004 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
c4721249 5005 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
58c229e1
KM		 5006 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
5007 },
5008 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
17babad6 5009 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
58c229e1
KM		 5010 /* IP11_31_30 [2] */
5011 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
5012 /* IP11_29_27 [3] */
7d2b2854 5013 FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
14da999b 5014 0, 0, 0,
58c229e1 5015 /* IP11_26_24 [3] */
c4721249 5016 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
58c229e1
KM		 5017 0, 0, 0,
5018 /* IP11_23_22 [2] */
c4721249 5019 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
58c229e1
KM		 5020 /* IP11_21_18 [4] */
5021 FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
14da999b 5022 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
58c229e1
KM		 5023 /* IP11_17_15 [3] */
5024 FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
5025 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
5026 /* IP11_14_13 [2] */
5027 FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
5028 /* IP11_12_11 [2] */
5029 FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
5030 /* IP11_10_9 [2] */
5031 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
5032 /* IP11_8_7 [2] */
5033 FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
5034 /* IP11_6_5 [2] */
5035 FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
5036 /* IP11_4 [1] */
5037 FN_SD3_CLK, FN_MMC1_CLK,
5038 /* IP11_3_0 [4] */
5039 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
5040 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
5041 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
5042 },
5043 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5044 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
5045 /* IP12_31 [1] */
5046 0, 0,
5047 /* IP12_30_28 [3] */
5048 FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
5049 FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
5050 FN_CAN_DEBUGOUT4, 0, 0,
5051 /* IP12_27_25 [3] */
5052 FN_SSI_SCK5, FN_SCIFB1_SCK,
5053 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
5054 FN_CAN_DEBUGOUT3, 0, 0,
5055 /* IP12_24_23 [2] */
5056 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
5057 FN_CAN_DEBUGOUT2,
5058 /* IP12_22_20 [3] */
5059 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
5060 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
5061 /* IP12_19_17 [3] */
5062 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
5063 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
5064 /* IP12_16_14 [3] */
5065 FN_SSI_SDATA3, FN_STP_ISCLK_0,
5066 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
5067 /* IP12_13_11 [3] */
5068 FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
5069 FN_CAN_STEP0, 0, 0, 0,
5070 /* IP12_10_8 [3] */
5071 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
5072 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
5073 /* IP12_7_6 [2] */
5074 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
5075 /* IP12_5_4 [2] */
5076 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
5077 /* IP12_3_2 [2] */
5078 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
5079 /* IP12_1_0 [2] */
5080 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, }
5081 },
5082 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5083 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
5084 /* IP13_31 [1] */
5085 0, 0,
5086 /* IP13_30_29 [2] */
5087 FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
5088 /* IP13_28_26 [3] */
5089 FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
5090 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
5091 /* IP13_25_23 [3] */
5092 FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
5093 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
5094 /* IP13_22_19 [4] */
5095 FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
5096 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
14da999b 5097 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
58c229e1
KM		 5098 /* IP13_18_16 [3] */
5099 FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
5100 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
5101 /* IP13_15_13 [3] */
5102 FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
5103 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
5104 /* IP13_12_10 [3] */
14da999b 5105 FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
58c229e1
KM		 5106 FN_CAN_DEBUGOUT8, 0, 0,
5107 /* IP13_9_7 [3] */
5108 FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
5109 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
5110 /* IP13_6_3 [4] */
14da999b 5111 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
58c229e1 5112 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
14da999b 5113 FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
58c229e1
KM		 5114 /* IP13_2_0 [3] */
5115 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
5116 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
5117 },
5118 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
5119 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
5120 /* IP14_30 [1] */
5121 0, 0,
5122 /* IP14_30_28 [3] */
bcec7475 5123 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
58c229e1
KM		 5124 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
5125 FN_HRTS0_N_C, 0,
5126 /* IP14_27_25 [3] */
5127 FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
5128 FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
5129 /* IP14_24_22 [3] */
5130 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
5131 FN_LCDOUT9, 0, 0, 0,
5132 /* IP14_21_19 [3] */
5133 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
5134 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
5135 /* IP14_18_16 [3] */
bcec7475 5136 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
58c229e1
KM		 5137 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
5138 /* IP14_15_12 [4] */
5139 FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
c4721249 5140 FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
58c229e1
KM		 5141 0, 0, 0, 0, 0, 0, 0,
5142 /* IP14_11_9 [3] */
5143 FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
5144 0, 0, 0,
5145 /* IP14_8_6 [3] */
5146 FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
5147 0, 0, 0,
5148 /* IP14_5_3 [3] */
5149 FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
c4721249 5150 FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
58c229e1
KM		 5151 /* IP14_2_0 [3] */
5152 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
5153 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
5154 FN_REMOCON, 0, }
5155 },
5156 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
5157 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
5158 /* IP15_31_30 [2] */
5159 0, 0, 0, 0,
5160 /* IP15_29_28 [2] */
5161 FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
5162 /* IP15_27_26 [2] */
5163 FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
5164 /* IP15_25_23 [3] */
5165 FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
5de880dd 5166 FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
58c229e1
KM		 5167 /* IP15_22_20 [3] */
5168 FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
5169 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
5170 /* IP15_19_18 [2] */
5171 FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
5172 /* IP15_17_16 [2] */
5173 FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
5174 /* IP15_15_14 [2] */
5175 FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
5176 /* IP15_13_12 [2] */
5177 FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
5178 /* IP15_11_9 [3] */
5179 FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
5180 0, 0, 0,
5181 /* IP15_8_6 [3] */
1ddb66cd 5182 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
c4721249 5183 FN_IIC2_SDA, FN_I2C2_SDA, 0,
58c229e1 5184 /* IP15_5_3 [3] */
1ddb66cd 5185 FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16,
c4721249 5186 FN_IIC2_SCL, FN_I2C2_SCL, 0,
58c229e1 5187 /* IP15_2_0 [3] */
1ddb66cd 5188 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
58c229e1
KM		 5189 FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
5190 },
5191 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
5192 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
5193 /* IP16_31_28 [4] */
5194 0, 0, 0, 0, 0, 0, 0, 0,
5195 0, 0, 0, 0, 0, 0, 0, 0,
5196 /* IP16_27_24 [4] */
5197 0, 0, 0, 0, 0, 0, 0, 0,
5198 0, 0, 0, 0, 0, 0, 0, 0,
5199 /* IP16_23_20 [4] */
5200 0, 0, 0, 0, 0, 0, 0, 0,
5201 0, 0, 0, 0, 0, 0, 0, 0,
5202 /* IP16_19_16 [4] */
5203 0, 0, 0, 0, 0, 0, 0, 0,
5204 0, 0, 0, 0, 0, 0, 0, 0,
5205 /* IP16_15_12 [4] */
5206 0, 0, 0, 0, 0, 0, 0, 0,
5207 0, 0, 0, 0, 0, 0, 0, 0,
5208 /* IP16_11_8 [4] */
5209 0, 0, 0, 0, 0, 0, 0, 0,
5210 0, 0, 0, 0, 0, 0, 0, 0,
5211 /* IP16_7 [1] */
5212 FN_USB1_OVC, FN_TCLK1_B,
5213 /* IP16_6 [1] */
5214 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
5215 /* IP16_5_3 [3] */
5216 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
5de880dd 5217 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
58c229e1
KM		 5218 /* IP16_2_0 [3] */
5219 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
5220 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
5221 },
5222 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5223 3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
5224 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
5225 /* SEL_SCIF1 [3] */
5226 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
5227 FN_SEL_SCIF1_4, 0, 0, 0,
5228 /* SEL_SCIFB [2] */
5229 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
5230 /* SEL_SCIFB2 [2] */
5231 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
5232 /* SEL_SCIFB1 [3] */
5233 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
5234 FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
5235 FN_SEL_SCIFB1_6, 0,
5236 /* SEL_SCIFA1 [2] */
5237 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
5238 FN_SEL_SCIFA1_3,
5239 /* SEL_SCIF0 [1] */
5240 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
5241 /* SEL_SCIFA [1] */
5242 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
5243 /* SEL_SOF1 [1] */
5244 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
5245 /* SEL_SSI7 [2] */
5246 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
5247 /* SEL_SSI6 [1] */
5248 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
5249 /* SEL_SSI5 [2] */
5250 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
5251 /* SEL_VI3 [1] */
5252 FN_SEL_VI3_0, FN_SEL_VI3_1,
5253 /* SEL_VI2 [1] */
5254 FN_SEL_VI2_0, FN_SEL_VI2_1,
5255 /* SEL_VI1 [1] */
5256 FN_SEL_VI1_0, FN_SEL_VI1_1,
5257 /* SEL_VI0 [1] */
5258 FN_SEL_VI0_0, FN_SEL_VI0_1,
5259 /* SEL_TSIF1 [2] */
5260 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
5261 /* RESERVED [1] */
5262 0, 0,
5263 /* SEL_LBS [1] */
5264 FN_SEL_LBS_0, FN_SEL_LBS_1,
5265 /* SEL_TSIF0 [2] */
5266 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5267 /* SEL_SOF3 [1] */
5268 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
5269 /* SEL_SOF0 [1] */
5270 FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
5271 },
5272 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
17babad6
GL		 5273 3, 1, 1, 1, 2, 1, 2, 1, 2,
5274 1, 1, 1, 3, 3, 2, 3, 2, 2) {
7f35184b 5275 /* RESERVED [3] */
58c229e1 5276 0, 0, 0, 0, 0, 0, 0, 0,
58c229e1
KM		 5277 /* SEL_TMU1 [1] */
5278 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
5279 /* SEL_HSCIF1 [1] */
5280 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5281 /* SEL_SCIFCLK [1] */
5282 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
5283 /* SEL_CAN0 [2] */
5284 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5285 /* SEL_CANCLK [1] */
5286 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
5287 /* SEL_SCIFA2 [2] */
5288 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
5289 /* SEL_CAN1 [1] */
5290 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
7f35184b 5291 /* RESERVED [2] */
17babad6 5292 0, 0, 0, 0,
1ddb66cd
SK		 5293 /* SEL_SCIF2 [1] */
5294 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
58c229e1
KM		 5295 /* SEL_ADI [1] */
5296 FN_SEL_ADI_0, FN_SEL_ADI_1,
5297 /* SEL_SSP [1] */
5298 FN_SEL_SSP_0, FN_SEL_SSP_1,
5299 /* SEL_FM [3] */
5300 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
5301 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
5302 /* SEL_HSCIF0 [3] */
5303 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
5304 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
5305 /* SEL_GPS [2] */
5306 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
14da999b
SK		 5307 /* RESERVED [3] */
5308 0, 0, 0, 0, 0, 0, 0, 0,
58c229e1
KM		 5309 /* SEL_SIM [2] */
5310 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
5311 /* SEL_SSI8 [2] */
5312 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
5313 },
5314 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5315 1, 1, 2, 4, 4, 2, 2,
5316 4, 2, 3, 2, 3, 2) {
5317 /* SEL_IICDVFS [1] */
5318 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
5319 /* SEL_IIC0 [1] */
5320 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
7f35184b 5321 /* RESERVED [2] */
58c229e1 5322 0, 0, 0, 0,
7f35184b 5323 /* RESERVED [4] */
58c229e1
KM		 5324 0, 0, 0, 0, 0, 0, 0, 0,
5325 0, 0, 0, 0, 0, 0, 0, 0,
7f35184b 5326 /* RESERVED [4] */
58c229e1
KM		 5327 0, 0, 0, 0, 0, 0, 0, 0,
5328 0, 0, 0, 0, 0, 0, 0, 0,
7f35184b 5329 /* RESERVED [2] */
58c229e1
KM		 5330 0, 0, 0, 0,
5331 /* SEL_IEB [2] */
5332 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
7f35184b 5333 /* RESERVED [4] */
58c229e1
KM		 5334 0, 0, 0, 0, 0, 0, 0, 0,
5335 0, 0, 0, 0, 0, 0, 0, 0,
7f35184b 5336 /* RESERVED [2] */
58c229e1
KM		 5337 0, 0, 0, 0,
5338 /* SEL_IIC2 [3] */
5339 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
5340 FN_SEL_IIC2_4, 0, 0, 0,
5341 /* SEL_IIC1 [2] */
5342 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
5343 /* SEL_I2C2 [3] */
5344 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
5345 FN_SEL_I2C2_4, 0, 0, 0,
5346 /* SEL_I2C1 [2] */
5347 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
5348 },
58c229e1
KM		 5349 { },
5350};
5351
5352const struct sh_pfc_soc_info r8a7790_pinmux_info = {
5353 .name = "r8a77900_pfc",
5354 .unlock_reg = 0xe6060000, /* PMMR */
5355
58c229e1
KM		 5356 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5357
5358 .pins = pinmux_pins,
5359 .nr_pins = ARRAY_SIZE(pinmux_pins),
1627769b
LP		 5360 .groups = pinmux_groups,
5361 .nr_groups = ARRAY_SIZE(pinmux_groups),
5362 .functions = pinmux_functions,
5363 .nr_functions = ARRAY_SIZE(pinmux_functions),
58c229e1 5364
58c229e1 5365 .cfg_regs = pinmux_config_regs,
58c229e1
KM		 5366
5367 .gpio_data = pinmux_data,
5368 .gpio_data_size = ARRAY_SIZE(pinmux_data),
5369};
Linux kernel - Deliverables
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