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43c4436e HN |
1 | /* |
2 | * r8a7794 processor support - PFC hardware block. | |
3 | * | |
4 | * Copyright (C) 2014 Renesas Electronics Corporation | |
5 | * Copyright (C) 2015 Renesas Solutions Corp. | |
6 | * Copyright (C) 2015 Cogent Embedded, Inc., <source@cogentembedded.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 | |
10 | * as published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
43c4436e HN |
14 | |
15 | #include "core.h" | |
16 | #include "sh_pfc.h" | |
17 | ||
43c4436e HN |
18 | #define CPU_ALL_PORT(fn, sfx) \ |
19 | PORT_GP_32(0, fn, sfx), \ | |
20 | PORT_GP_26(1, fn, sfx), \ | |
21 | PORT_GP_32(2, fn, sfx), \ | |
22 | PORT_GP_32(3, fn, sfx), \ | |
23 | PORT_GP_32(4, fn, sfx), \ | |
24 | PORT_GP_28(5, fn, sfx), \ | |
25 | PORT_GP_26(6, fn, sfx) | |
26 | ||
27 | enum { | |
28 | PINMUX_RESERVED = 0, | |
29 | ||
30 | PINMUX_DATA_BEGIN, | |
31 | GP_ALL(DATA), | |
32 | PINMUX_DATA_END, | |
33 | ||
34 | PINMUX_FUNCTION_BEGIN, | |
35 | GP_ALL(FN), | |
36 | ||
37 | /* GPSR0 */ | |
38 | FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28, | |
39 | FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, | |
40 | FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18, | |
41 | FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27, | |
42 | FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4, | |
43 | FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14, | |
44 | FN_IP2_17_16, | |
45 | ||
46 | /* GPSR1 */ | |
47 | FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30, | |
48 | FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10, | |
49 | FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18, | |
50 | FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31, | |
51 | FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0, | |
52 | ||
53 | /* GPSR2 */ | |
54 | FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12, | |
55 | FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23, | |
56 | FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2, | |
57 | FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14, | |
58 | FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24, | |
59 | FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2, | |
60 | FN_IP6_5_4, FN_IP6_7_6, | |
61 | ||
62 | /* GPSR3 */ | |
63 | FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13, | |
64 | FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20, | |
65 | FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, | |
66 | FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18, | |
67 | FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, | |
68 | FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17, | |
69 | FN_IP8_22_20, | |
70 | ||
71 | /* GPSR4 */ | |
72 | FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3, | |
73 | FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17, | |
74 | FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0, | |
75 | FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15, | |
76 | FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27, | |
77 | FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8, | |
78 | FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16, | |
79 | ||
80 | /* GPSR5 */ | |
81 | FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0, | |
82 | FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13, | |
83 | FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24, | |
84 | FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9, | |
85 | FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21, | |
86 | FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, | |
87 | ||
88 | /* GPSR6 */ | |
89 | FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2, | |
90 | FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD, | |
91 | FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0, | |
92 | FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14, | |
93 | FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20, | |
94 | ||
95 | /* IPSR0 */ | |
96 | FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK, | |
97 | FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1, | |
98 | FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3, | |
99 | FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD, | |
100 | FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, | |
101 | FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B, | |
102 | FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4, | |
103 | FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, | |
104 | ||
105 | /* IPSR1 */ | |
106 | FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, FN_D7, FN_IRQ3, FN_TCLK1, | |
107 | FN_PWM6_B, FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, FN_D9, FN_HSCIF2_HTX, | |
108 | FN_I2C1_SDA_B, FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, | |
109 | FN_PWM5_C, FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D, | |
110 | FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, FN_D13, | |
111 | FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, FN_D14, FN_SCIFA1_RXD, | |
112 | FN_IIC0_SCL_B, FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, FN_A0, | |
113 | FN_SCIFB1_SCK, FN_PWM3_B, FN_A1, FN_SCIFB1_TXD, FN_A3, FN_SCIFB0_SCK, | |
114 | FN_A4, FN_SCIFB0_TXD, FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C, | |
115 | FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C, | |
116 | ||
117 | /* IPSR2 */ | |
118 | FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, FN_A8, FN_MSIOF1_RXD, | |
119 | FN_SCIFA0_RXD_B, FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, FN_A10, | |
120 | FN_MSIOF1_SCK, FN_IIC1_SCL_B, FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B, | |
121 | FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, FN_A13, FN_MSIOF1_SS2, | |
122 | FN_SCIFA5_TXD_B, FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N, | |
123 | FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, FN_A16, | |
124 | FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_VSP, FN_CAN_CLK_C, | |
125 | FN_TPUTO2_B, FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B, | |
126 | FN_AVB_AVTP_CAPTURE_B, FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, | |
127 | FN_CAN1_TX_B, FN_AVB_AVTP_MATCH_B, FN_A19, FN_MSIOF2_SS2, FN_PWM4, | |
128 | FN_TPUTO2, FN_MOUT0, FN_A20, FN_SPCLK, FN_MOUT1, | |
129 | ||
130 | /* IPSR3 */ | |
131 | FN_A21, FN_MOSI_IO0, FN_MOUT2, FN_A22, FN_MISO_IO1, FN_MOUT5, | |
132 | FN_ATADIR1_N, FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N, FN_A24, FN_IO3, | |
133 | FN_EX_WAIT2, FN_A25, FN_SSL, FN_ATARD1_N, FN_CS0_N, FN_VI1_DATA8, | |
134 | FN_CS1_N_A26, FN_VI1_DATA9, FN_EX_CS0_N, FN_VI1_DATA10, FN_EX_CS1_N, | |
135 | FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, FN_EX_CS2_N, FN_PWM0, | |
136 | FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD, | |
137 | FN_SDATA_B, FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, | |
138 | FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B, FN_EX_CS4_N, | |
139 | FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_RIF0_D0, FN_FMCLK, | |
140 | FN_SCIFB2_CTS_N, FN_SCKZ_B, FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, | |
141 | FN_TS_SPSYNC_B, FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B, | |
142 | FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, FN_MTS_N_B, | |
143 | FN_RD_N, FN_ATACS11_N, FN_RD_WR_N, FN_ATAG1_N, | |
144 | ||
145 | /* IPSR4 */ | |
146 | FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, FN_DU0_DR0, | |
147 | FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, FN_CC50_STATE0, | |
148 | FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, FN_CC50_STATE1, | |
149 | FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, FN_DU0_DR3, FN_LCDOUT19, | |
150 | FN_CC50_STATE3, FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, FN_DU0_DR5, | |
151 | FN_LCDOUT21, FN_CC50_STATE5, FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6, | |
152 | FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, FN_DU0_DG0, FN_LCDOUT8, | |
153 | FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, FN_CC50_STATE8, FN_DU0_DG1, FN_LCDOUT9, | |
154 | FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, FN_CC50_STATE9, FN_DU0_DG2, FN_LCDOUT10, | |
155 | FN_CC50_STATE10, FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, FN_DU0_DG4, | |
156 | FN_LCDOUT12, FN_CC50_STATE12, | |
157 | ||
158 | /* IPSR5 */ | |
159 | FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, FN_DU0_DG6, FN_LCDOUT14, | |
160 | FN_CC50_STATE14, FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, FN_DU0_DB0, | |
161 | FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C, | |
162 | FN_CC50_STATE16, FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, | |
163 | FN_CAN0_TX_C, FN_CC50_STATE17, FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18, | |
164 | FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, FN_DU0_DB4, FN_LCDOUT4, | |
165 | FN_CC50_STATE20, FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, FN_DU0_DB6, | |
166 | FN_LCDOUT6, FN_CC50_STATE22, FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23, | |
167 | FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, FN_DU0_DOTCLKOUT0, | |
168 | FN_QCLK, FN_CC50_STATE25, FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, | |
169 | FN_CC50_STATE26, FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27, | |
170 | ||
171 | /* IPSR6 */ | |
172 | FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, | |
173 | FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29, | |
174 | FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB, | |
175 | FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0, | |
176 | FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2, | |
177 | FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4, | |
178 | FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6, | |
179 | FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB, | |
180 | FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD, | |
181 | FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N, | |
182 | FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N, | |
183 | FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, | |
184 | FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK, | |
185 | FN_ADIDATA, FN_AD_DI, | |
186 | ||
187 | /* IPSR7 */ | |
188 | FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0, | |
189 | FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, | |
190 | FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3, | |
191 | FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, | |
192 | FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3, | |
193 | FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, | |
194 | FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, | |
195 | FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, | |
196 | FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0, | |
197 | FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B, | |
198 | FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B, | |
199 | FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK, | |
200 | FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD, | |
201 | ||
202 | /* IPSR8 */ | |
203 | FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC, | |
204 | FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, | |
205 | FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX, | |
206 | FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B, | |
207 | FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, | |
208 | FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7, | |
209 | FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B, | |
210 | FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, | |
211 | FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK, | |
212 | FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, | |
213 | FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD, | |
214 | FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, | |
215 | FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B, | |
216 | FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, | |
217 | FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK, | |
218 | ||
219 | /* IPSR9 */ | |
220 | FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_RIF1_D1_B, | |
221 | FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, FN_MSIOF0_SCK, FN_IRQ0, | |
222 | FN_TS_SDATA, FN_DU1_DR4, FN_RIF1_SYNC, FN_TPUTO1_C, FN_MSIOF0_SYNC, | |
223 | FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_RIF1_CLK, FN_BPFCLK_B, FN_MSIOF0_SS1, | |
224 | FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_RIF1_D0, FN_FMCLK_B, | |
225 | FN_RDS_CLK_B, FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, | |
226 | FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, FN_HSCIF1_HRX, FN_I2C4_SCL, | |
227 | FN_PWM6, FN_DU1_DG0, FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1, | |
228 | FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B, | |
229 | FN_SPEEDIN_B, FN_VSP_B, FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, | |
230 | FN_DU1_DG3, FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32, | |
231 | FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B, | |
232 | FN_CAN_STEP0, FN_CC50_STATE33, FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, | |
233 | FN_DU1_DG5, FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34, | |
234 | ||
235 | /* IPSR10 */ | |
236 | FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, FN_CAN_DEBUGOUT0, | |
237 | FN_CC50_STATE35, FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B, | |
238 | FN_CAN_DEBUGOUT1, FN_CC50_STATE36, FN_SCIF2_RXD, FN_IIC1_SCL, | |
239 | FN_DU1_DB0, FN_SSI_SDATA2_B, FN_USB0_EXTLP, FN_CAN_DEBUGOUT2, | |
240 | FN_CC50_STATE37, FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B, | |
241 | FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, FN_SCIF2_SCK, FN_IRQ1, | |
242 | FN_DU1_DB2, FN_SSI_WS9_B, FN_USB0_IDIN, FN_CAN_DEBUGOUT4, | |
243 | FN_CC50_STATE39, FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, | |
244 | FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT, | |
245 | FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C, | |
246 | FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C, FN_SCIF3_TXD, | |
247 | FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B, | |
248 | FN_CAN_DEBUGOUT7, FN_RDS_DATA_C, FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, | |
249 | FN_AUDIO_CLKC_C, FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, FN_I2C2_SDA, | |
250 | FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, FN_CAN_DEBUGOUT9, | |
251 | FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10, | |
252 | ||
253 | /* IPSR11 */ | |
254 | FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, | |
255 | FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, | |
256 | FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B, | |
257 | FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6, | |
258 | FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC, | |
259 | FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, | |
260 | FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78, | |
261 | FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78, | |
262 | FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7, | |
263 | FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N, | |
264 | FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, | |
265 | FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, | |
266 | FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, | |
267 | FN_ADICLK_B, FN_AD_CLK_B, | |
268 | ||
269 | /* IPSR12 */ | |
270 | FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B, | |
271 | FN_AD_NCS_N_B, FN_DREQ1_N_B, FN_SSI_WS34, FN_MSIOF1_SS1_B, | |
272 | FN_SCIFA1_RXD_C, FN_ADICHS1_B, FN_CAN1_RX_C, FN_DACK1_B, FN_SSI_SDATA3, | |
273 | FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, FN_CAN1_TX_C, | |
274 | FN_DREQ2_N, FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX, FN_SSI_WS4, | |
275 | FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, FN_SSI_SDATA4, FN_MLB_DAT, | |
276 | FN_IERX_B, FN_IRD_SCK, FN_SSI_SDATA8, FN_SCIF1_SCK_B, | |
277 | FN_PWM1_B, FN_IRQ9, FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, FN_SSI_SCK1, | |
278 | FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D, | |
279 | FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B, | |
280 | FN_IIC1_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, | |
281 | FN_ETH_RX_ER_B, FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA, FN_VI1_DATA1, | |
282 | FN_ATAG0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, | |
283 | FN_MDATA, FN_ATAWR0_N, FN_ETH_RXD1_B, | |
284 | ||
285 | /* IPSR13 */ | |
286 | FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, FN_SCKZ, | |
287 | FN_ATACS00_N, FN_ETH_LINK_B, FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, | |
288 | FN_SCIFA0_TXD_D, FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B, | |
289 | FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_MTS_N, | |
290 | FN_EX_WAIT1, FN_ETH_TXD1_B, FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, | |
291 | FN_VI1_DATA6, FN_ATARD0_N, FN_ETH_TX_EN_B, FN_SSI_SDATA9, | |
292 | FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, FN_ATADIR0_N, | |
293 | FN_ETH_MAGIC_B, FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, | |
294 | FN_VI1_CLKENB, FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B, | |
295 | FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD, | |
296 | FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B, FN_AUDIO_CLKC, | |
297 | FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, FN_TS_SDEN_C, | |
298 | FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D, FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, | |
299 | FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, FN_TS_SPSYNC_C, FN_RIF0_D1_B, | |
300 | FN_FMIN_E, FN_RDS_DATA_D, | |
301 | ||
302 | /* MOD_SEL */ | |
303 | FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, | |
304 | FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1, | |
305 | FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1, | |
306 | FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0, | |
307 | FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1, | |
308 | FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0, | |
309 | FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, | |
310 | FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1, | |
311 | FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0, | |
312 | FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4, | |
313 | FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, | |
314 | FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, | |
315 | FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1, | |
316 | FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1, | |
317 | ||
318 | /* MOD_SEL2 */ | |
319 | FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0, | |
320 | FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0, | |
321 | FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0, | |
322 | FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0, | |
323 | FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0, | |
324 | FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0, | |
325 | FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, | |
326 | FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, | |
327 | FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, | |
328 | FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1, | |
329 | FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, | |
330 | FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1, | |
331 | FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1, | |
332 | FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, | |
333 | FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1, | |
334 | FN_SEL_RDS_2, FN_SEL_RDS_3, | |
335 | ||
336 | /* MOD_SEL3 */ | |
337 | FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, | |
338 | FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0, | |
339 | FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, | |
340 | FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, | |
341 | FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, | |
342 | FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0, | |
343 | FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0, | |
344 | FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0, | |
345 | FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0, | |
346 | FN_SEL_SSI9_1, | |
347 | PINMUX_FUNCTION_END, | |
348 | ||
349 | PINMUX_MARK_BEGIN, | |
350 | A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK, | |
351 | ||
352 | USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK, | |
353 | ||
354 | SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK, | |
355 | SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK, | |
356 | ||
357 | SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK, | |
358 | SD1_DATA2_MARK, SD1_DATA3_MARK, | |
359 | ||
360 | /* IPSR0 */ | |
361 | SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK, | |
362 | MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK, | |
363 | SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK, | |
364 | SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK, | |
365 | MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK, | |
366 | CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK, | |
367 | CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK, | |
368 | SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK, | |
369 | SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK, | |
370 | SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK, | |
371 | ||
372 | /* IPSR1 */ | |
373 | D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK, D7_MARK, IRQ3_MARK, | |
374 | TCLK1_MARK, PWM6_B_MARK, D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK, | |
375 | D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK, D10_MARK, | |
376 | HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK, | |
377 | D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK, | |
378 | D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK, | |
379 | D13_MARK, SCIFA1_SCK_MARK, TANS1_MARK, PWM2_C_MARK, TCLK2_B_MARK, | |
380 | D14_MARK, SCIFA1_RXD_MARK, IIC0_SCL_B_MARK, D15_MARK, SCIFA1_TXD_MARK, | |
381 | IIC0_SDA_B_MARK, A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK, A1_MARK, | |
382 | SCIFB1_TXD_MARK, A3_MARK, SCIFB0_SCK_MARK, A4_MARK, SCIFB0_TXD_MARK, | |
383 | A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK, A6_MARK, | |
384 | SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK, | |
385 | ||
386 | /* IPSR2 */ | |
387 | A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK, A8_MARK, MSIOF1_RXD_MARK, | |
388 | SCIFA0_RXD_B_MARK, A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK, | |
389 | A10_MARK, MSIOF1_SCK_MARK, IIC1_SCL_B_MARK, A11_MARK, MSIOF1_SYNC_MARK, | |
390 | IIC1_SDA_B_MARK, A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK, | |
391 | A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK, A14_MARK, MSIOF2_RXD_MARK, | |
392 | HSCIF0_HRX_B_MARK, DREQ1_N_MARK, A15_MARK, MSIOF2_TXD_MARK, | |
393 | HSCIF0_HTX_B_MARK, DACK1_MARK, A16_MARK, MSIOF2_SCK_MARK, | |
394 | HSCIF0_HSCK_B_MARK, SPEEDIN_MARK, VSP_MARK, CAN_CLK_C_MARK, | |
395 | TPUTO2_B_MARK, A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, | |
396 | CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_B_MARK, A18_MARK, MSIOF2_SS1_MARK, | |
397 | SCIF4_TXD_E_MARK, CAN1_TX_B_MARK, AVB_AVTP_MATCH_B_MARK, A19_MARK, | |
398 | MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK, MOUT0_MARK, A20_MARK, | |
399 | SPCLK_MARK, MOUT1_MARK, | |
400 | ||
401 | /* IPSR3 */ | |
402 | A21_MARK, MOSI_IO0_MARK, MOUT2_MARK, A22_MARK, MISO_IO1_MARK, | |
403 | MOUT5_MARK, ATADIR1_N_MARK, A23_MARK, IO2_MARK, MOUT6_MARK, | |
404 | ATAWR1_N_MARK, A24_MARK, IO3_MARK, EX_WAIT2_MARK, A25_MARK, SSL_MARK, | |
405 | ATARD1_N_MARK, CS0_N_MARK, VI1_DATA8_MARK, CS1_N_A26_MARK, | |
406 | VI1_DATA9_MARK, EX_CS0_N_MARK, VI1_DATA10_MARK, EX_CS1_N_MARK, | |
407 | TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK, EX_CS2_N_MARK, | |
408 | PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK, RIF0_SYNC_MARK, | |
409 | TPUTO3_MARK, SCIFB2_TXD_MARK, SDATA_B_MARK, EX_CS3_N_MARK, | |
410 | SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK, RIF0_CLK_MARK, | |
411 | BPFCLK_MARK, SCIFB2_SCK_MARK, MDATA_B_MARK, EX_CS4_N_MARK, | |
412 | SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK, RIF0_D0_MARK, | |
413 | FMCLK_MARK, SCIFB2_CTS_N_MARK, SCKZ_B_MARK, EX_CS5_N_MARK, | |
414 | SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK, RIF0_D1_MARK, | |
415 | FMIN_MARK, SCIFB2_RTS_N_MARK, STM_N_B_MARK, BS_N_MARK, DRACK0_MARK, | |
416 | PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK, MTS_N_B_MARK, RD_N_MARK, | |
417 | ATACS11_N_MARK, RD_WR_N_MARK, ATAG1_N_MARK, | |
418 | ||
419 | /* IPSR4 */ | |
420 | EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK, PWMFSW0_MARK, | |
421 | DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK, | |
422 | CC50_STATE0_MARK, DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, | |
423 | I2C2_SDA_D_MARK, CC50_STATE1_MARK, DU0_DR2_MARK, LCDOUT18_MARK, | |
424 | CC50_STATE2_MARK, DU0_DR3_MARK, LCDOUT19_MARK, CC50_STATE3_MARK, | |
425 | DU0_DR4_MARK, LCDOUT20_MARK, CC50_STATE4_MARK, DU0_DR5_MARK, | |
426 | LCDOUT21_MARK, CC50_STATE5_MARK, DU0_DR6_MARK, LCDOUT22_MARK, | |
427 | CC50_STATE6_MARK, DU0_DR7_MARK, LCDOUT23_MARK, CC50_STATE7_MARK, | |
428 | DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK, | |
429 | CC50_STATE8_MARK, DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, | |
430 | I2C3_SDA_D_MARK, CC50_STATE9_MARK, DU0_DG2_MARK, LCDOUT10_MARK, | |
431 | CC50_STATE10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, CC50_STATE11_MARK, | |
432 | DU0_DG4_MARK, LCDOUT12_MARK, CC50_STATE12_MARK, | |
433 | ||
434 | /* IPSR5 */ | |
435 | DU0_DG5_MARK, LCDOUT13_MARK, CC50_STATE13_MARK, DU0_DG6_MARK, | |
436 | LCDOUT14_MARK, CC50_STATE14_MARK, DU0_DG7_MARK, LCDOUT15_MARK, | |
437 | CC50_STATE15_MARK, DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, | |
438 | I2C4_SCL_D_MARK, CAN0_RX_C_MARK, CC50_STATE16_MARK, DU0_DB1_MARK, | |
439 | LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK, CAN0_TX_C_MARK, | |
440 | CC50_STATE17_MARK, DU0_DB2_MARK, LCDOUT2_MARK, CC50_STATE18_MARK, | |
441 | DU0_DB3_MARK, LCDOUT3_MARK, CC50_STATE19_MARK, DU0_DB4_MARK, | |
442 | LCDOUT4_MARK, CC50_STATE20_MARK, DU0_DB5_MARK, LCDOUT5_MARK, | |
443 | CC50_STATE21_MARK, DU0_DB6_MARK, LCDOUT6_MARK, CC50_STATE22_MARK, | |
444 | DU0_DB7_MARK, LCDOUT7_MARK, CC50_STATE23_MARK, DU0_DOTCLKIN_MARK, | |
445 | QSTVA_QVS_MARK, CC50_STATE24_MARK, DU0_DOTCLKOUT0_MARK, | |
446 | QCLK_MARK, CC50_STATE25_MARK, DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, | |
447 | CC50_STATE26_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK, | |
448 | CC50_STATE27_MARK, | |
449 | ||
450 | /* IPSR6 */ | |
451 | DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK, | |
452 | DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK, | |
453 | DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK, | |
454 | CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, | |
455 | AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK, | |
456 | VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK, | |
457 | AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK, | |
458 | VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK, | |
459 | AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK, | |
460 | I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK, | |
461 | VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK, | |
462 | AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, | |
463 | IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, | |
464 | I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK, | |
465 | VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK, | |
466 | ADIDATA_MARK, AD_DI_MARK, | |
467 | ||
468 | /* IPSR7 */ | |
469 | ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK, | |
470 | AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK, | |
471 | MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK, | |
472 | AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, | |
473 | CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK, | |
474 | ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK, | |
475 | AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK, | |
476 | MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK, | |
477 | ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK, | |
478 | SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, | |
479 | IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK, | |
480 | VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK, | |
481 | SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, | |
482 | AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK, | |
483 | SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK, | |
484 | DREQ0_N_MARK, SCIFB1_RXD_MARK, | |
485 | ||
486 | /* IPSR8 */ | |
487 | ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK, | |
488 | AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK, | |
489 | I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK, | |
490 | HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK, | |
491 | AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK, | |
492 | SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK, | |
493 | HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK, | |
494 | AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK, | |
495 | HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK, | |
496 | I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK, | |
497 | AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK, | |
498 | SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK, | |
499 | CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, | |
500 | DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK, | |
501 | I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK, | |
502 | TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK, | |
503 | I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK, | |
504 | FMCLK_C_MARK, RDS_CLK_MARK, | |
505 | ||
506 | /* IPSR9 */ | |
507 | MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK, | |
508 | RIF1_D1_B_MARK, TS_SPSYNC_D_MARK, FMIN_C_MARK, RDS_DATA_MARK, | |
509 | MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, RIF1_SYNC_MARK, | |
510 | TPUTO1_C_MARK, MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, | |
511 | RIF1_CLK_MARK, BPFCLK_B_MARK, MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, | |
512 | TS_SDEN_MARK, DU1_DR6_MARK, RIF1_D0_MARK, FMCLK_B_MARK, RDS_CLK_B_MARK, | |
513 | MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK, | |
514 | RIF1_D1_MARK, FMIN_B_MARK, RDS_DATA_B_MARK, HSCIF1_HRX_MARK, | |
515 | I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK, HSCIF1_HTX_MARK, | |
516 | I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK, HSCIF1_HSCK_MARK, | |
517 | PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK, SPEEDIN_B_MARK, | |
518 | VSP_B_MARK, HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, | |
519 | DU1_DG3_MARK, SSI_SCK1_B_MARK, CAN_DEBUG_HW_TRIGGER_MARK, | |
520 | CC50_STATE32_MARK, HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, | |
521 | DU1_DG4_MARK, SSI_WS1_B_MARK, CAN_STEP0_MARK, CC50_STATE33_MARK, | |
522 | SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK, | |
523 | CAN_TXCLK_MARK, CC50_STATE34_MARK, | |
524 | ||
525 | /* IPSR10 */ | |
526 | SCIF1_RXD_MARK, IIC0_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK, | |
527 | CAN_DEBUGOUT0_MARK, CC50_STATE35_MARK, SCIF1_TXD_MARK, IIC0_SDA_MARK, | |
528 | DU1_DG7_MARK, SSI_WS2_B_MARK, CAN_DEBUGOUT1_MARK, CC50_STATE36_MARK, | |
529 | SCIF2_RXD_MARK, IIC1_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK, | |
530 | USB0_EXTLP_MARK, CAN_DEBUGOUT2_MARK, CC50_STATE37_MARK, SCIF2_TXD_MARK, | |
531 | IIC1_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK, USB0_OVC1_MARK, | |
532 | CAN_DEBUGOUT3_MARK, CC50_STATE38_MARK, SCIF2_SCK_MARK, IRQ1_MARK, | |
533 | DU1_DB2_MARK, SSI_WS9_B_MARK, USB0_IDIN_MARK, CAN_DEBUGOUT4_MARK, | |
534 | CC50_STATE39_MARK, SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, | |
535 | DU1_DB3_MARK, SSI_SDATA9_B_MARK, TANS2_MARK, CAN_DEBUGOUT5_MARK, | |
536 | CC50_OSCOUT_MARK, SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, | |
537 | DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK, CAN_DEBUGOUT6_MARK, | |
538 | RDS_CLK_C_MARK, SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, | |
539 | DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, CAN_DEBUGOUT7_MARK, | |
540 | RDS_DATA_C_MARK, I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, | |
541 | AUDIO_CLKC_C_MARK, SSI_SDATA4_B_MARK, CAN_DEBUGOUT8_MARK, I2C2_SDA_MARK, | |
542 | SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK, CAN_DEBUGOUT9_MARK, | |
543 | SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK, CAN_DEBUGOUT10_MARK, | |
544 | ||
545 | /* IPSR11 */ | |
546 | SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK, | |
547 | CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, | |
548 | DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK, | |
549 | SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK, | |
550 | SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK, | |
551 | DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK, | |
552 | SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, | |
553 | CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK, | |
554 | DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK, | |
555 | DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, | |
556 | AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK, | |
557 | MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK, | |
558 | PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, | |
559 | ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, | |
560 | PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK, | |
561 | ||
562 | /* IPSR12 */ | |
563 | SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK, | |
564 | AD_NCS_N_B_MARK, DREQ1_N_B_MARK, SSI_WS34_MARK, MSIOF1_SS1_B_MARK, | |
565 | SCIFA1_RXD_C_MARK, ADICHS1_B_MARK, CAN1_RX_C_MARK, DACK1_B_MARK, | |
566 | SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK, | |
567 | CAN1_TX_C_MARK, DREQ2_N_MARK, SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK, | |
568 | IRD_TX_MARK, SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK, IRD_RX_MARK, | |
569 | SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK, IRD_SCK_MARK, | |
570 | SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK, | |
571 | DACK2_MARK, ETH_MDIO_B_MARK, SSI_SCK1_MARK, SCIF1_RXD_B_MARK, | |
572 | IIC1_SCL_C_MARK, VI1_CLK_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_MARK, | |
573 | ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC1_SDA_C_MARK, | |
574 | VI1_DATA0_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK, ETH_RX_ER_B_MARK, | |
575 | SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, SDATA_MARK, | |
576 | ATAG0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, | |
577 | VI1_DATA2_MARK, MDATA_MARK, ATAWR0_N_MARK, ETH_RXD1_B_MARK, | |
578 | ||
579 | /* IPSR13 */ | |
580 | SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK, | |
581 | SCKZ_MARK, ATACS00_N_MARK, ETH_LINK_B_MARK, SSI_SDATA2_MARK, | |
582 | HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK, VI1_DATA4_MARK, STM_N_MARK, | |
583 | ATACS10_N_MARK, ETH_REFCLK_B_MARK, SSI_SCK9_MARK, SCIF2_SCK_B_MARK, | |
584 | PWM2_B_MARK, VI1_DATA5_MARK, MTS_N_MARK, EX_WAIT1_MARK, | |
585 | ETH_TXD1_B_MARK, SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, | |
586 | VI1_DATA6_MARK, ATARD0_N_MARK, ETH_TX_EN_B_MARK, SSI_SDATA9_MARK, | |
587 | SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK, ATADIR0_N_MARK, | |
588 | ETH_MAGIC_B_MARK, AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, | |
589 | VI1_CLKENB_MARK, TS_SDATA_C_MARK, RIF0_SYNC_B_MARK, ETH_TXD0_B_MARK, | |
590 | AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK, | |
591 | TS_SCK_C_MARK, RIF0_CLK_B_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK, | |
592 | AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK, | |
593 | TS_SDEN_C_MARK, RIF0_D0_B_MARK, FMCLK_E_MARK, RDS_CLK_D_MARK, | |
594 | AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK, | |
595 | TS_SPSYNC_C_MARK, RIF0_D1_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, | |
596 | PINMUX_MARK_END, | |
597 | }; | |
598 | ||
599 | static const u16 pinmux_data[] = { | |
600 | PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ | |
601 | ||
61a483ff GU |
602 | PINMUX_SINGLE(A2), |
603 | PINMUX_SINGLE(WE0_N), | |
604 | PINMUX_SINGLE(WE1_N), | |
605 | PINMUX_SINGLE(DACK0), | |
606 | PINMUX_SINGLE(USB0_PWEN), | |
607 | PINMUX_SINGLE(USB0_OVC), | |
608 | PINMUX_SINGLE(USB1_PWEN), | |
609 | PINMUX_SINGLE(USB1_OVC), | |
610 | PINMUX_SINGLE(SD0_CLK), | |
611 | PINMUX_SINGLE(SD0_CMD), | |
612 | PINMUX_SINGLE(SD0_DATA0), | |
613 | PINMUX_SINGLE(SD0_DATA1), | |
614 | PINMUX_SINGLE(SD0_DATA2), | |
615 | PINMUX_SINGLE(SD0_DATA3), | |
616 | PINMUX_SINGLE(SD0_CD), | |
617 | PINMUX_SINGLE(SD0_WP), | |
618 | PINMUX_SINGLE(SD1_CLK), | |
619 | PINMUX_SINGLE(SD1_CMD), | |
620 | PINMUX_SINGLE(SD1_DATA0), | |
621 | PINMUX_SINGLE(SD1_DATA1), | |
622 | PINMUX_SINGLE(SD1_DATA2), | |
623 | PINMUX_SINGLE(SD1_DATA3), | |
43c4436e HN |
624 | |
625 | /* IPSR0 */ | |
626 | PINMUX_IPSR_DATA(IP0_0, SD1_CD), | |
adedb87f | 627 | PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0), |
43c4436e HN |
628 | PINMUX_IPSR_DATA(IP0_9_8, SD1_WP), |
629 | PINMUX_IPSR_DATA(IP0_9_8, IRQ7), | |
adedb87f | 630 | PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0), |
43c4436e HN |
631 | PINMUX_IPSR_DATA(IP0_10, MMC_CLK), |
632 | PINMUX_IPSR_DATA(IP0_10, SD2_CLK), | |
633 | PINMUX_IPSR_DATA(IP0_11, MMC_CMD), | |
634 | PINMUX_IPSR_DATA(IP0_11, SD2_CMD), | |
635 | PINMUX_IPSR_DATA(IP0_12, MMC_D0), | |
636 | PINMUX_IPSR_DATA(IP0_12, SD2_DATA0), | |
637 | PINMUX_IPSR_DATA(IP0_13, MMC_D1), | |
638 | PINMUX_IPSR_DATA(IP0_13, SD2_DATA1), | |
639 | PINMUX_IPSR_DATA(IP0_14, MMC_D2), | |
640 | PINMUX_IPSR_DATA(IP0_14, SD2_DATA2), | |
641 | PINMUX_IPSR_DATA(IP0_15, MMC_D3), | |
642 | PINMUX_IPSR_DATA(IP0_15, SD2_DATA3), | |
643 | PINMUX_IPSR_DATA(IP0_16, MMC_D4), | |
644 | PINMUX_IPSR_DATA(IP0_16, SD2_CD), | |
645 | PINMUX_IPSR_DATA(IP0_17, MMC_D5), | |
646 | PINMUX_IPSR_DATA(IP0_17, SD2_WP), | |
647 | PINMUX_IPSR_DATA(IP0_19_18, MMC_D6), | |
adedb87f KM |
648 | PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0), |
649 | PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1), | |
650 | PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0), | |
43c4436e | 651 | PINMUX_IPSR_DATA(IP0_21_20, MMC_D7), |
adedb87f KM |
652 | PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0), |
653 | PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1), | |
654 | PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0), | |
43c4436e | 655 | PINMUX_IPSR_DATA(IP0_23_22, D0), |
adedb87f | 656 | PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1), |
43c4436e HN |
657 | PINMUX_IPSR_DATA(IP0_23_22, IRQ4), |
658 | PINMUX_IPSR_DATA(IP0_24, D1), | |
adedb87f | 659 | PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1), |
43c4436e | 660 | PINMUX_IPSR_DATA(IP0_25, D2), |
adedb87f | 661 | PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1), |
43c4436e | 662 | PINMUX_IPSR_DATA(IP0_27_26, D3), |
adedb87f KM |
663 | PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1), |
664 | PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1), | |
43c4436e | 665 | PINMUX_IPSR_DATA(IP0_29_28, D4), |
adedb87f KM |
666 | PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1), |
667 | PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1), | |
43c4436e | 668 | PINMUX_IPSR_DATA(IP0_31_30, D5), |
adedb87f KM |
669 | PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1), |
670 | PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3), | |
43c4436e HN |
671 | |
672 | /* IPSR1 */ | |
673 | PINMUX_IPSR_DATA(IP1_1_0, D6), | |
adedb87f KM |
674 | PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1), |
675 | PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3), | |
43c4436e HN |
676 | PINMUX_IPSR_DATA(IP1_3_2, D7), |
677 | PINMUX_IPSR_DATA(IP1_3_2, IRQ3), | |
adedb87f | 678 | PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0), |
43c4436e HN |
679 | PINMUX_IPSR_DATA(IP1_3_2, PWM6_B), |
680 | PINMUX_IPSR_DATA(IP1_5_4, D8), | |
681 | PINMUX_IPSR_DATA(IP1_5_4, HSCIF2_HRX), | |
adedb87f | 682 | PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1), |
43c4436e HN |
683 | PINMUX_IPSR_DATA(IP1_7_6, D9), |
684 | PINMUX_IPSR_DATA(IP1_7_6, HSCIF2_HTX), | |
adedb87f | 685 | PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1), |
43c4436e HN |
686 | PINMUX_IPSR_DATA(IP1_10_8, D10), |
687 | PINMUX_IPSR_DATA(IP1_10_8, HSCIF2_HSCK), | |
adedb87f | 688 | PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2), |
43c4436e HN |
689 | PINMUX_IPSR_DATA(IP1_10_8, IRQ6), |
690 | PINMUX_IPSR_DATA(IP1_10_8, PWM5_C), | |
691 | PINMUX_IPSR_DATA(IP1_12_11, D11), | |
692 | PINMUX_IPSR_DATA(IP1_12_11, HSCIF2_HCTS_N), | |
adedb87f KM |
693 | PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2), |
694 | PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3), | |
43c4436e HN |
695 | PINMUX_IPSR_DATA(IP1_14_13, D12), |
696 | PINMUX_IPSR_DATA(IP1_14_13, HSCIF2_HRTS_N), | |
adedb87f KM |
697 | PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2), |
698 | PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3), | |
43c4436e | 699 | PINMUX_IPSR_DATA(IP1_17_15, D13), |
adedb87f | 700 | PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0), |
43c4436e HN |
701 | PINMUX_IPSR_DATA(IP1_17_15, TANS1), |
702 | PINMUX_IPSR_DATA(IP1_17_15, PWM2_C), | |
adedb87f | 703 | PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1), |
43c4436e | 704 | PINMUX_IPSR_DATA(IP1_19_18, D14), |
adedb87f KM |
705 | PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0), |
706 | PINMUX_IPSR_MSEL(IP1_19_18, IIC0_SCL_B, SEL_IIC00_1), | |
43c4436e | 707 | PINMUX_IPSR_DATA(IP1_21_20, D15), |
adedb87f KM |
708 | PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0), |
709 | PINMUX_IPSR_MSEL(IP1_21_20, IIC0_SDA_B, SEL_IIC00_1), | |
43c4436e HN |
710 | PINMUX_IPSR_DATA(IP1_23_22, A0), |
711 | PINMUX_IPSR_DATA(IP1_23_22, SCIFB1_SCK), | |
712 | PINMUX_IPSR_DATA(IP1_23_22, PWM3_B), | |
713 | PINMUX_IPSR_DATA(IP1_24, A1), | |
714 | PINMUX_IPSR_DATA(IP1_24, SCIFB1_TXD), | |
715 | PINMUX_IPSR_DATA(IP1_26, A3), | |
716 | PINMUX_IPSR_DATA(IP1_26, SCIFB0_SCK), | |
717 | PINMUX_IPSR_DATA(IP1_27, A4), | |
718 | PINMUX_IPSR_DATA(IP1_27, SCIFB0_TXD), | |
719 | PINMUX_IPSR_DATA(IP1_29_28, A5), | |
720 | PINMUX_IPSR_DATA(IP1_29_28, SCIFB0_RXD), | |
721 | PINMUX_IPSR_DATA(IP1_29_28, PWM4_B), | |
722 | PINMUX_IPSR_DATA(IP1_29_28, TPUTO3_C), | |
723 | PINMUX_IPSR_DATA(IP1_31_30, A6), | |
724 | PINMUX_IPSR_DATA(IP1_31_30, SCIFB0_CTS_N), | |
adedb87f | 725 | PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1), |
43c4436e HN |
726 | PINMUX_IPSR_DATA(IP1_31_30, TPUTO2_C), |
727 | ||
728 | /* IPSR2 */ | |
729 | PINMUX_IPSR_DATA(IP2_1_0, A7), | |
730 | PINMUX_IPSR_DATA(IP2_1_0, SCIFB0_RTS_N), | |
adedb87f | 731 | PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1), |
43c4436e | 732 | PINMUX_IPSR_DATA(IP2_3_2, A8), |
adedb87f KM |
733 | PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0), |
734 | PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1), | |
43c4436e | 735 | PINMUX_IPSR_DATA(IP2_5_4, A9), |
adedb87f KM |
736 | PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0), |
737 | PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1), | |
43c4436e | 738 | PINMUX_IPSR_DATA(IP2_7_6, A10), |
adedb87f KM |
739 | PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0), |
740 | PINMUX_IPSR_MSEL(IP2_7_6, IIC1_SCL_B, SEL_IIC01_1), | |
43c4436e | 741 | PINMUX_IPSR_DATA(IP2_9_8, A11), |
adedb87f KM |
742 | PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0), |
743 | PINMUX_IPSR_MSEL(IP2_9_8, IIC1_SDA_B, SEL_IIC01_1), | |
43c4436e | 744 | PINMUX_IPSR_DATA(IP2_11_10, A12), |
adedb87f KM |
745 | PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0), |
746 | PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1), | |
43c4436e | 747 | PINMUX_IPSR_DATA(IP2_13_12, A13), |
adedb87f KM |
748 | PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0), |
749 | PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1), | |
43c4436e | 750 | PINMUX_IPSR_DATA(IP2_15_14, A14), |
adedb87f KM |
751 | PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0), |
752 | PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1), | |
753 | PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0), | |
43c4436e | 754 | PINMUX_IPSR_DATA(IP2_17_16, A15), |
adedb87f KM |
755 | PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0), |
756 | PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1), | |
757 | PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0), | |
43c4436e | 758 | PINMUX_IPSR_DATA(IP2_20_18, A16), |
adedb87f KM |
759 | PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0), |
760 | PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1), | |
761 | PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0), | |
762 | PINMUX_IPSR_MSEL(IP2_20_18, VSP, SEL_SPDM_0), | |
763 | PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2), | |
43c4436e HN |
764 | PINMUX_IPSR_DATA(IP2_20_18, TPUTO2_B), |
765 | PINMUX_IPSR_DATA(IP2_23_21, A17), | |
adedb87f KM |
766 | PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0), |
767 | PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4), | |
768 | PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1), | |
769 | PINMUX_IPSR_MSEL(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1), | |
43c4436e | 770 | PINMUX_IPSR_DATA(IP2_26_24, A18), |
adedb87f KM |
771 | PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0), |
772 | PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4), | |
773 | PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1), | |
774 | PINMUX_IPSR_MSEL(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1), | |
43c4436e | 775 | PINMUX_IPSR_DATA(IP2_29_27, A19), |
adedb87f | 776 | PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0), |
43c4436e HN |
777 | PINMUX_IPSR_DATA(IP2_29_27, PWM4), |
778 | PINMUX_IPSR_DATA(IP2_29_27, TPUTO2), | |
779 | PINMUX_IPSR_DATA(IP2_29_27, MOUT0), | |
780 | PINMUX_IPSR_DATA(IP2_31_30, A20), | |
781 | PINMUX_IPSR_DATA(IP2_31_30, SPCLK), | |
782 | PINMUX_IPSR_DATA(IP2_29_27, MOUT1), | |
783 | ||
784 | /* IPSR3 */ | |
785 | PINMUX_IPSR_DATA(IP3_1_0, A21), | |
786 | PINMUX_IPSR_DATA(IP3_1_0, MOSI_IO0), | |
787 | PINMUX_IPSR_DATA(IP3_1_0, MOUT2), | |
788 | PINMUX_IPSR_DATA(IP3_3_2, A22), | |
789 | PINMUX_IPSR_DATA(IP3_3_2, MISO_IO1), | |
790 | PINMUX_IPSR_DATA(IP3_3_2, MOUT5), | |
791 | PINMUX_IPSR_DATA(IP3_3_2, ATADIR1_N), | |
792 | PINMUX_IPSR_DATA(IP3_5_4, A23), | |
793 | PINMUX_IPSR_DATA(IP3_5_4, IO2), | |
794 | PINMUX_IPSR_DATA(IP3_5_4, MOUT6), | |
795 | PINMUX_IPSR_DATA(IP3_5_4, ATAWR1_N), | |
796 | PINMUX_IPSR_DATA(IP3_7_6, A24), | |
797 | PINMUX_IPSR_DATA(IP3_7_6, IO3), | |
798 | PINMUX_IPSR_DATA(IP3_7_6, EX_WAIT2), | |
799 | PINMUX_IPSR_DATA(IP3_9_8, A25), | |
800 | PINMUX_IPSR_DATA(IP3_9_8, SSL), | |
801 | PINMUX_IPSR_DATA(IP3_9_8, ATARD1_N), | |
802 | PINMUX_IPSR_DATA(IP3_10, CS0_N), | |
803 | PINMUX_IPSR_DATA(IP3_10, VI1_DATA8), | |
804 | PINMUX_IPSR_DATA(IP3_11, CS1_N_A26), | |
805 | PINMUX_IPSR_DATA(IP3_11, VI1_DATA9), | |
806 | PINMUX_IPSR_DATA(IP3_12, EX_CS0_N), | |
807 | PINMUX_IPSR_DATA(IP3_12, VI1_DATA10), | |
808 | PINMUX_IPSR_DATA(IP3_14_13, EX_CS1_N), | |
809 | PINMUX_IPSR_DATA(IP3_14_13, TPUTO3_B), | |
810 | PINMUX_IPSR_DATA(IP3_14_13, SCIFB2_RXD), | |
811 | PINMUX_IPSR_DATA(IP3_14_13, VI1_DATA11), | |
812 | PINMUX_IPSR_DATA(IP3_17_15, EX_CS2_N), | |
813 | PINMUX_IPSR_DATA(IP3_17_15, PWM0), | |
adedb87f KM |
814 | PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2), |
815 | PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1), | |
816 | PINMUX_IPSR_MSEL(IP3_17_15, RIF0_SYNC, SEL_DR0_0), | |
43c4436e HN |
817 | PINMUX_IPSR_DATA(IP3_17_15, TPUTO3), |
818 | PINMUX_IPSR_DATA(IP3_17_15, SCIFB2_TXD), | |
adedb87f | 819 | PINMUX_IPSR_MSEL(IP3_17_15, SDATA_B, SEL_FSN_1), |
43c4436e | 820 | PINMUX_IPSR_DATA(IP3_20_18, EX_CS3_N), |
adedb87f KM |
821 | PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0), |
822 | PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2), | |
823 | PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1), | |
824 | PINMUX_IPSR_MSEL(IP3_20_18, RIF0_CLK, SEL_DR0_0), | |
825 | PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0), | |
43c4436e | 826 | PINMUX_IPSR_DATA(IP3_20_18, SCIFB2_SCK), |
adedb87f | 827 | PINMUX_IPSR_MSEL(IP3_20_18, MDATA_B, SEL_FSN_1), |
43c4436e | 828 | PINMUX_IPSR_DATA(IP3_23_21, EX_CS4_N), |
adedb87f KM |
829 | PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0), |
830 | PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4), | |
831 | PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1), | |
832 | PINMUX_IPSR_MSEL(IP3_23_21, RIF0_D0, SEL_DR0_0), | |
833 | PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0), | |
43c4436e | 834 | PINMUX_IPSR_DATA(IP3_23_21, SCIFB2_CTS_N), |
adedb87f | 835 | PINMUX_IPSR_MSEL(IP3_23_21, SCKZ_B, SEL_FSN_1), |
43c4436e | 836 | PINMUX_IPSR_DATA(IP3_26_24, EX_CS5_N), |
adedb87f KM |
837 | PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0), |
838 | PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4), | |
839 | PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1), | |
840 | PINMUX_IPSR_MSEL(IP3_26_24, RIF0_D1, SEL_DR1_0), | |
841 | PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0), | |
43c4436e | 842 | PINMUX_IPSR_DATA(IP3_26_24, SCIFB2_RTS_N), |
adedb87f | 843 | PINMUX_IPSR_MSEL(IP3_26_24, STM_N_B, SEL_FSN_1), |
43c4436e HN |
844 | PINMUX_IPSR_DATA(IP3_29_27, BS_N), |
845 | PINMUX_IPSR_DATA(IP3_29_27, DRACK0), | |
846 | PINMUX_IPSR_DATA(IP3_29_27, PWM1_C), | |
847 | PINMUX_IPSR_DATA(IP3_29_27, TPUTO0_C), | |
848 | PINMUX_IPSR_DATA(IP3_29_27, ATACS01_N), | |
adedb87f | 849 | PINMUX_IPSR_MSEL(IP3_29_27, MTS_N_B, SEL_FSN_1), |
43c4436e HN |
850 | PINMUX_IPSR_DATA(IP3_30, RD_N), |
851 | PINMUX_IPSR_DATA(IP3_30, ATACS11_N), | |
852 | PINMUX_IPSR_DATA(IP3_31, RD_WR_N), | |
853 | PINMUX_IPSR_DATA(IP3_31, ATAG1_N), | |
854 | ||
855 | /* IPSR4 */ | |
856 | PINMUX_IPSR_DATA(IP4_1_0, EX_WAIT0), | |
adedb87f KM |
857 | PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1), |
858 | PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0), | |
43c4436e HN |
859 | PINMUX_IPSR_DATA(IP4_1_0, PWMFSW0), |
860 | PINMUX_IPSR_DATA(IP4_4_2, DU0_DR0), | |
861 | PINMUX_IPSR_DATA(IP4_4_2, LCDOUT16), | |
adedb87f KM |
862 | PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2), |
863 | PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3), | |
43c4436e HN |
864 | PINMUX_IPSR_DATA(IP4_4_2, CC50_STATE0), |
865 | PINMUX_IPSR_DATA(IP4_7_5, DU0_DR1), | |
866 | PINMUX_IPSR_DATA(IP4_7_5, LCDOUT17), | |
adedb87f KM |
867 | PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2), |
868 | PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3), | |
43c4436e HN |
869 | PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE1), |
870 | PINMUX_IPSR_DATA(IP4_9_8, DU0_DR2), | |
871 | PINMUX_IPSR_DATA(IP4_9_8, LCDOUT18), | |
872 | PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE2), | |
873 | PINMUX_IPSR_DATA(IP4_11_10, DU0_DR3), | |
874 | PINMUX_IPSR_DATA(IP4_11_10, LCDOUT19), | |
875 | PINMUX_IPSR_DATA(IP4_11_10, CC50_STATE3), | |
876 | PINMUX_IPSR_DATA(IP4_13_12, DU0_DR4), | |
877 | PINMUX_IPSR_DATA(IP4_13_12, LCDOUT20), | |
878 | PINMUX_IPSR_DATA(IP4_13_12, CC50_STATE4), | |
879 | PINMUX_IPSR_DATA(IP4_15_14, DU0_DR5), | |
880 | PINMUX_IPSR_DATA(IP4_15_14, LCDOUT21), | |
881 | PINMUX_IPSR_DATA(IP4_15_14, CC50_STATE5), | |
882 | PINMUX_IPSR_DATA(IP4_17_16, DU0_DR6), | |
883 | PINMUX_IPSR_DATA(IP4_17_16, LCDOUT22), | |
884 | PINMUX_IPSR_DATA(IP4_17_16, CC50_STATE6), | |
885 | PINMUX_IPSR_DATA(IP4_19_18, DU0_DR7), | |
886 | PINMUX_IPSR_DATA(IP4_19_18, LCDOUT23), | |
887 | PINMUX_IPSR_DATA(IP4_19_18, CC50_STATE7), | |
888 | PINMUX_IPSR_DATA(IP4_22_20, DU0_DG0), | |
889 | PINMUX_IPSR_DATA(IP4_22_20, LCDOUT8), | |
adedb87f KM |
890 | PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2), |
891 | PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3), | |
43c4436e HN |
892 | PINMUX_IPSR_DATA(IP4_22_20, CC50_STATE8), |
893 | PINMUX_IPSR_DATA(IP4_25_23, DU0_DG1), | |
894 | PINMUX_IPSR_DATA(IP4_25_23, LCDOUT9), | |
adedb87f KM |
895 | PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2), |
896 | PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3), | |
43c4436e HN |
897 | PINMUX_IPSR_DATA(IP4_25_23, CC50_STATE9), |
898 | PINMUX_IPSR_DATA(IP4_27_26, DU0_DG2), | |
899 | PINMUX_IPSR_DATA(IP4_27_26, LCDOUT10), | |
900 | PINMUX_IPSR_DATA(IP4_27_26, CC50_STATE10), | |
901 | PINMUX_IPSR_DATA(IP4_29_28, DU0_DG3), | |
902 | PINMUX_IPSR_DATA(IP4_29_28, LCDOUT11), | |
903 | PINMUX_IPSR_DATA(IP4_29_28, CC50_STATE11), | |
904 | PINMUX_IPSR_DATA(IP4_31_30, DU0_DG4), | |
905 | PINMUX_IPSR_DATA(IP4_31_30, LCDOUT12), | |
906 | PINMUX_IPSR_DATA(IP4_31_30, CC50_STATE12), | |
907 | ||
908 | /* IPSR5 */ | |
909 | PINMUX_IPSR_DATA(IP5_1_0, DU0_DG5), | |
910 | PINMUX_IPSR_DATA(IP5_1_0, LCDOUT13), | |
911 | PINMUX_IPSR_DATA(IP5_1_0, CC50_STATE13), | |
912 | PINMUX_IPSR_DATA(IP5_3_2, DU0_DG6), | |
913 | PINMUX_IPSR_DATA(IP5_3_2, LCDOUT14), | |
914 | PINMUX_IPSR_DATA(IP5_3_2, CC50_STATE14), | |
915 | PINMUX_IPSR_DATA(IP5_5_4, DU0_DG7), | |
916 | PINMUX_IPSR_DATA(IP5_5_4, LCDOUT15), | |
917 | PINMUX_IPSR_DATA(IP5_5_4, CC50_STATE15), | |
918 | PINMUX_IPSR_DATA(IP5_8_6, DU0_DB0), | |
919 | PINMUX_IPSR_DATA(IP5_8_6, LCDOUT0), | |
adedb87f KM |
920 | PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2), |
921 | PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3), | |
922 | PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2), | |
43c4436e HN |
923 | PINMUX_IPSR_DATA(IP5_8_6, CC50_STATE16), |
924 | PINMUX_IPSR_DATA(IP5_11_9, DU0_DB1), | |
925 | PINMUX_IPSR_DATA(IP5_11_9, LCDOUT1), | |
adedb87f KM |
926 | PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), |
927 | PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3), | |
928 | PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2), | |
43c4436e HN |
929 | PINMUX_IPSR_DATA(IP5_11_9, CC50_STATE17), |
930 | PINMUX_IPSR_DATA(IP5_13_12, DU0_DB2), | |
931 | PINMUX_IPSR_DATA(IP5_13_12, LCDOUT2), | |
932 | PINMUX_IPSR_DATA(IP5_13_12, CC50_STATE18), | |
933 | PINMUX_IPSR_DATA(IP5_15_14, DU0_DB3), | |
934 | PINMUX_IPSR_DATA(IP5_15_14, LCDOUT3), | |
935 | PINMUX_IPSR_DATA(IP5_15_14, CC50_STATE19), | |
936 | PINMUX_IPSR_DATA(IP5_17_16, DU0_DB4), | |
937 | PINMUX_IPSR_DATA(IP5_17_16, LCDOUT4), | |
938 | PINMUX_IPSR_DATA(IP5_17_16, CC50_STATE20), | |
939 | PINMUX_IPSR_DATA(IP5_19_18, DU0_DB5), | |
940 | PINMUX_IPSR_DATA(IP5_19_18, LCDOUT5), | |
941 | PINMUX_IPSR_DATA(IP5_19_18, CC50_STATE21), | |
942 | PINMUX_IPSR_DATA(IP5_21_20, DU0_DB6), | |
943 | PINMUX_IPSR_DATA(IP5_21_20, LCDOUT6), | |
944 | PINMUX_IPSR_DATA(IP5_21_20, CC50_STATE22), | |
945 | PINMUX_IPSR_DATA(IP5_23_22, DU0_DB7), | |
946 | PINMUX_IPSR_DATA(IP5_23_22, LCDOUT7), | |
947 | PINMUX_IPSR_DATA(IP5_23_22, CC50_STATE23), | |
948 | PINMUX_IPSR_DATA(IP5_25_24, DU0_DOTCLKIN), | |
949 | PINMUX_IPSR_DATA(IP5_25_24, QSTVA_QVS), | |
950 | PINMUX_IPSR_DATA(IP5_25_24, CC50_STATE24), | |
951 | PINMUX_IPSR_DATA(IP5_27_26, DU0_DOTCLKOUT0), | |
952 | PINMUX_IPSR_DATA(IP5_27_26, QCLK), | |
953 | PINMUX_IPSR_DATA(IP5_27_26, CC50_STATE25), | |
954 | PINMUX_IPSR_DATA(IP5_29_28, DU0_DOTCLKOUT1), | |
955 | PINMUX_IPSR_DATA(IP5_29_28, QSTVB_QVE), | |
956 | PINMUX_IPSR_DATA(IP5_29_28, CC50_STATE26), | |
957 | PINMUX_IPSR_DATA(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC), | |
958 | PINMUX_IPSR_DATA(IP5_31_30, QSTH_QHS), | |
959 | PINMUX_IPSR_DATA(IP5_31_30, CC50_STATE27), | |
960 | ||
961 | /* IPSR6 */ | |
962 | PINMUX_IPSR_DATA(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC), | |
963 | PINMUX_IPSR_DATA(IP6_1_0, QSTB_QHE), | |
964 | PINMUX_IPSR_DATA(IP6_1_0, CC50_STATE28), | |
965 | PINMUX_IPSR_DATA(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE), | |
966 | PINMUX_IPSR_DATA(IP6_3_2, QCPV_QDE), | |
967 | PINMUX_IPSR_DATA(IP6_3_2, CC50_STATE29), | |
968 | PINMUX_IPSR_DATA(IP6_5_4, DU0_DISP), | |
969 | PINMUX_IPSR_DATA(IP6_5_4, QPOLA), | |
970 | PINMUX_IPSR_DATA(IP6_5_4, CC50_STATE30), | |
971 | PINMUX_IPSR_DATA(IP6_7_6, DU0_CDE), | |
972 | PINMUX_IPSR_DATA(IP6_7_6, QPOLB), | |
973 | PINMUX_IPSR_DATA(IP6_7_6, CC50_STATE31), | |
974 | PINMUX_IPSR_DATA(IP6_8, VI0_CLK), | |
975 | PINMUX_IPSR_DATA(IP6_8, AVB_RX_CLK), | |
976 | PINMUX_IPSR_DATA(IP6_9, VI0_DATA0_VI0_B0), | |
977 | PINMUX_IPSR_DATA(IP6_9, AVB_RX_DV), | |
978 | PINMUX_IPSR_DATA(IP6_10, VI0_DATA1_VI0_B1), | |
979 | PINMUX_IPSR_DATA(IP6_10, AVB_RXD0), | |
980 | PINMUX_IPSR_DATA(IP6_11, VI0_DATA2_VI0_B2), | |
981 | PINMUX_IPSR_DATA(IP6_11, AVB_RXD1), | |
982 | PINMUX_IPSR_DATA(IP6_12, VI0_DATA3_VI0_B3), | |
983 | PINMUX_IPSR_DATA(IP6_12, AVB_RXD2), | |
984 | PINMUX_IPSR_DATA(IP6_13, VI0_DATA4_VI0_B4), | |
985 | PINMUX_IPSR_DATA(IP6_13, AVB_RXD3), | |
986 | PINMUX_IPSR_DATA(IP6_14, VI0_DATA5_VI0_B5), | |
987 | PINMUX_IPSR_DATA(IP6_14, AVB_RXD4), | |
988 | PINMUX_IPSR_DATA(IP6_15, VI0_DATA6_VI0_B6), | |
989 | PINMUX_IPSR_DATA(IP6_15, AVB_RXD5), | |
990 | PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7), | |
991 | PINMUX_IPSR_DATA(IP6_16, AVB_RXD6), | |
992 | PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB), | |
adedb87f KM |
993 | PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0), |
994 | PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2), | |
995 | PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2), | |
43c4436e HN |
996 | PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7), |
997 | PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD), | |
adedb87f KM |
998 | PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0), |
999 | PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2), | |
1000 | PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2), | |
43c4436e HN |
1001 | PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER), |
1002 | PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N), | |
adedb87f KM |
1003 | PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1), |
1004 | PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2), | |
1005 | PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2), | |
43c4436e HN |
1006 | PINMUX_IPSR_DATA(IP6_25_23, AVB_COL), |
1007 | PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N), | |
adedb87f KM |
1008 | PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1), |
1009 | PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2), | |
1010 | PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1), | |
43c4436e | 1011 | PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN), |
adedb87f | 1012 | PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0), |
43c4436e | 1013 | PINMUX_IPSR_DATA(IP6_31_29, VI0_G0), |
adedb87f KM |
1014 | PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1), |
1015 | PINMUX_IPSR_MSEL(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3), | |
43c4436e | 1016 | PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK), |
adedb87f KM |
1017 | PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0), |
1018 | PINMUX_IPSR_MSEL(IP6_31_29, AD_DI, SEL_ADI_0), | |
43c4436e HN |
1019 | |
1020 | /* IPSR7 */ | |
adedb87f | 1021 | PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0), |
43c4436e | 1022 | PINMUX_IPSR_DATA(IP7_2_0, VI0_G1), |
adedb87f KM |
1023 | PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1), |
1024 | PINMUX_IPSR_MSEL(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3), | |
43c4436e | 1025 | PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0), |
adedb87f KM |
1026 | PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0), |
1027 | PINMUX_IPSR_MSEL(IP7_2_0, AD_DO, SEL_ADI_0), | |
1028 | PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0), | |
43c4436e | 1029 | PINMUX_IPSR_DATA(IP7_5_3, VI0_G2), |
adedb87f KM |
1030 | PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1), |
1031 | PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1), | |
43c4436e | 1032 | PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1), |
adedb87f KM |
1033 | PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0), |
1034 | PINMUX_IPSR_MSEL(IP7_5_3, AD_CLK, SEL_ADI_0), | |
1035 | PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0), | |
43c4436e | 1036 | PINMUX_IPSR_DATA(IP7_8_6, VI0_G3), |
adedb87f KM |
1037 | PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1), |
1038 | PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1), | |
43c4436e | 1039 | PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2), |
adedb87f KM |
1040 | PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0), |
1041 | PINMUX_IPSR_MSEL(IP7_8_6, AD_NCS_N, SEL_ADI_0), | |
1042 | PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0), | |
43c4436e | 1043 | PINMUX_IPSR_DATA(IP7_11_9, VI0_G4), |
adedb87f KM |
1044 | PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1), |
1045 | PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3), | |
43c4436e | 1046 | PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3), |
adedb87f KM |
1047 | PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0), |
1048 | PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0), | |
43c4436e | 1049 | PINMUX_IPSR_DATA(IP7_14_12, VI0_G5), |
adedb87f KM |
1050 | PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1), |
1051 | PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3), | |
43c4436e | 1052 | PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4), |
adedb87f KM |
1053 | PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0), |
1054 | PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0), | |
43c4436e | 1055 | PINMUX_IPSR_DATA(IP7_17_15, VI0_G6), |
adedb87f | 1056 | PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2), |
43c4436e | 1057 | PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5), |
adedb87f KM |
1058 | PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1), |
1059 | PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0), | |
43c4436e | 1060 | PINMUX_IPSR_DATA(IP7_20_18, VI0_G7), |
adedb87f KM |
1061 | PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2), |
1062 | PINMUX_IPSR_MSEL(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3), | |
43c4436e | 1063 | PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6), |
adedb87f KM |
1064 | PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1), |
1065 | PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0), | |
43c4436e | 1066 | PINMUX_IPSR_DATA(IP7_23_21, VI0_R0), |
adedb87f KM |
1067 | PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2), |
1068 | PINMUX_IPSR_MSEL(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3), | |
43c4436e | 1069 | PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7), |
adedb87f KM |
1070 | PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1), |
1071 | PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0), | |
43c4436e | 1072 | PINMUX_IPSR_DATA(IP7_26_24, VI0_R1), |
adedb87f | 1073 | PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1), |
43c4436e | 1074 | PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER), |
adedb87f KM |
1075 | PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1), |
1076 | PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0), | |
43c4436e | 1077 | PINMUX_IPSR_DATA(IP7_29_27, VI0_R2), |
adedb87f KM |
1078 | PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1), |
1079 | PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4), | |
43c4436e | 1080 | PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK), |
adedb87f | 1081 | PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1), |
43c4436e HN |
1082 | PINMUX_IPSR_DATA(IP7_31, DREQ0_N), |
1083 | PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD), | |
1084 | ||
1085 | /* IPSR8 */ | |
adedb87f | 1086 | PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0), |
43c4436e | 1087 | PINMUX_IPSR_DATA(IP8_2_0, VI0_R3), |
adedb87f KM |
1088 | PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1), |
1089 | PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4), | |
43c4436e | 1090 | PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC), |
adedb87f KM |
1091 | PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1), |
1092 | PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0), | |
43c4436e | 1093 | PINMUX_IPSR_DATA(IP8_5_3, VI0_R4), |
adedb87f KM |
1094 | PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2), |
1095 | PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1), | |
43c4436e | 1096 | PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO), |
adedb87f KM |
1097 | PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1), |
1098 | PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0), | |
43c4436e | 1099 | PINMUX_IPSR_DATA(IP8_8_6, VI0_R5), |
adedb87f KM |
1100 | PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2), |
1101 | PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1), | |
43c4436e | 1102 | PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK), |
adedb87f | 1103 | PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1), |
43c4436e HN |
1104 | PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N), |
1105 | PINMUX_IPSR_DATA(IP8_11_9, VI0_R6), | |
adedb87f KM |
1106 | PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3), |
1107 | PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4), | |
43c4436e | 1108 | PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC), |
adedb87f | 1109 | PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1), |
43c4436e HN |
1110 | PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N), |
1111 | PINMUX_IPSR_DATA(IP8_14_12, VI0_R7), | |
adedb87f KM |
1112 | PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3), |
1113 | PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4), | |
43c4436e | 1114 | PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT), |
adedb87f KM |
1115 | PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1), |
1116 | PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0), | |
1117 | PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1), | |
43c4436e | 1118 | PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS), |
adedb87f KM |
1119 | PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1), |
1120 | PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0), | |
1121 | PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2), | |
43c4436e | 1122 | PINMUX_IPSR_DATA(IP8_19_17, PWM5), |
adedb87f | 1123 | PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1), |
43c4436e | 1124 | PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK), |
adedb87f | 1125 | PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3), |
43c4436e | 1126 | PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B), |
adedb87f KM |
1127 | PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0), |
1128 | PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2), | |
43c4436e | 1129 | PINMUX_IPSR_DATA(IP8_22_20, TPUTO0), |
adedb87f | 1130 | PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0), |
43c4436e | 1131 | PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE), |
adedb87f KM |
1132 | PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3), |
1133 | PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0), | |
1134 | PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0), | |
43c4436e HN |
1135 | PINMUX_IPSR_DATA(IP8_25_23, PWM5_B), |
1136 | PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0), | |
adedb87f KM |
1137 | PINMUX_IPSR_MSEL(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1), |
1138 | PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), | |
43c4436e | 1139 | PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B), |
adedb87f KM |
1140 | PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0), |
1141 | PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0), | |
43c4436e HN |
1142 | PINMUX_IPSR_DATA(IP8_28_26, IRQ5), |
1143 | PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1), | |
adedb87f KM |
1144 | PINMUX_IPSR_MSEL(IP8_28_26, RIF1_CLK_B, SEL_DR2_1), |
1145 | PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), | |
1146 | PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2), | |
43c4436e | 1147 | PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD), |
adedb87f KM |
1148 | PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0), |
1149 | PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2), | |
43c4436e | 1150 | PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2), |
adedb87f KM |
1151 | PINMUX_IPSR_MSEL(IP8_31_29, RIF1_D0_B, SEL_DR2_1), |
1152 | PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), | |
1153 | PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2), | |
1154 | PINMUX_IPSR_MSEL(IP8_31_29, RDS_CLK, SEL_RDS_0), | |
43c4436e HN |
1155 | |
1156 | /* IPSR9 */ | |
1157 | PINMUX_IPSR_DATA(IP9_2_0, MSIOF0_TXD), | |
adedb87f KM |
1158 | PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0), |
1159 | PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2), | |
43c4436e | 1160 | PINMUX_IPSR_DATA(IP9_2_0, DU1_DR3), |
adedb87f KM |
1161 | PINMUX_IPSR_MSEL(IP9_2_0, RIF1_D1_B, SEL_DR3_1), |
1162 | PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3), | |
1163 | PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2), | |
1164 | PINMUX_IPSR_MSEL(IP9_2_0, RDS_DATA, SEL_RDS_0), | |
43c4436e HN |
1165 | PINMUX_IPSR_DATA(IP9_5_3, MSIOF0_SCK), |
1166 | PINMUX_IPSR_DATA(IP9_5_3, IRQ0), | |
adedb87f | 1167 | PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0), |
43c4436e | 1168 | PINMUX_IPSR_DATA(IP9_5_3, DU1_DR4), |
adedb87f | 1169 | PINMUX_IPSR_MSEL(IP9_5_3, RIF1_SYNC, SEL_DR2_0), |
43c4436e HN |
1170 | PINMUX_IPSR_DATA(IP9_5_3, TPUTO1_C), |
1171 | PINMUX_IPSR_DATA(IP9_8_6, MSIOF0_SYNC), | |
1172 | PINMUX_IPSR_DATA(IP9_8_6, PWM1), | |
adedb87f | 1173 | PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0), |
43c4436e | 1174 | PINMUX_IPSR_DATA(IP9_8_6, DU1_DR5), |
adedb87f KM |
1175 | PINMUX_IPSR_MSEL(IP9_8_6, RIF1_CLK, SEL_DR2_0), |
1176 | PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1), | |
43c4436e | 1177 | PINMUX_IPSR_DATA(IP9_11_9, MSIOF0_SS1), |
adedb87f KM |
1178 | PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0), |
1179 | PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0), | |
43c4436e | 1180 | PINMUX_IPSR_DATA(IP9_11_9, DU1_DR6), |
adedb87f KM |
1181 | PINMUX_IPSR_MSEL(IP9_11_9, RIF1_D0, SEL_DR2_0), |
1182 | PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1), | |
1183 | PINMUX_IPSR_MSEL(IP9_11_9, RDS_CLK_B, SEL_RDS_1), | |
43c4436e | 1184 | PINMUX_IPSR_DATA(IP9_14_12, MSIOF0_SS2), |
adedb87f KM |
1185 | PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0), |
1186 | PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0), | |
43c4436e | 1187 | PINMUX_IPSR_DATA(IP9_14_12, DU1_DR7), |
adedb87f KM |
1188 | PINMUX_IPSR_MSEL(IP9_14_12, RIF1_D1, SEL_DR3_0), |
1189 | PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1), | |
1190 | PINMUX_IPSR_MSEL(IP9_14_12, RDS_DATA_B, SEL_RDS_1), | |
1191 | PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0), | |
1192 | PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0), | |
43c4436e HN |
1193 | PINMUX_IPSR_DATA(IP9_16_15, PWM6), |
1194 | PINMUX_IPSR_DATA(IP9_16_15, DU1_DG0), | |
adedb87f KM |
1195 | PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0), |
1196 | PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0), | |
43c4436e HN |
1197 | PINMUX_IPSR_DATA(IP9_18_17, TPUTO1), |
1198 | PINMUX_IPSR_DATA(IP9_18_17, DU1_DG1), | |
1199 | PINMUX_IPSR_DATA(IP9_21_19, HSCIF1_HSCK), | |
1200 | PINMUX_IPSR_DATA(IP9_21_19, PWM2), | |
adedb87f | 1201 | PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0), |
43c4436e | 1202 | PINMUX_IPSR_DATA(IP9_21_19, DU1_DG2), |
adedb87f KM |
1203 | PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1), |
1204 | PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1), | |
1205 | PINMUX_IPSR_MSEL(IP9_21_19, VSP_B, SEL_SPDM_1), | |
1206 | PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0), | |
1207 | PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0), | |
1208 | PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0), | |
43c4436e | 1209 | PINMUX_IPSR_DATA(IP9_24_22, DU1_DG3), |
adedb87f | 1210 | PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1), |
43c4436e HN |
1211 | PINMUX_IPSR_DATA(IP9_24_22, CAN_DEBUG_HW_TRIGGER), |
1212 | PINMUX_IPSR_DATA(IP9_24_22, CC50_STATE32), | |
adedb87f KM |
1213 | PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0), |
1214 | PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0), | |
1215 | PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0), | |
43c4436e | 1216 | PINMUX_IPSR_DATA(IP9_27_25, DU1_DG4), |
adedb87f | 1217 | PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1), |
43c4436e HN |
1218 | PINMUX_IPSR_DATA(IP9_27_25, CAN_STEP0), |
1219 | PINMUX_IPSR_DATA(IP9_27_25, CC50_STATE33), | |
adedb87f | 1220 | PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0), |
43c4436e | 1221 | PINMUX_IPSR_DATA(IP9_30_28, PWM3), |
adedb87f | 1222 | PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0), |
43c4436e | 1223 | PINMUX_IPSR_DATA(IP9_30_28, DU1_DG5), |
adedb87f | 1224 | PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1), |
43c4436e HN |
1225 | PINMUX_IPSR_DATA(IP9_30_28, CAN_TXCLK), |
1226 | PINMUX_IPSR_DATA(IP9_30_28, CC50_STATE34), | |
1227 | ||
1228 | /* IPSR10 */ | |
adedb87f KM |
1229 | PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0), |
1230 | PINMUX_IPSR_MSEL(IP10_2_0, IIC0_SCL, SEL_IIC00_0), | |
43c4436e | 1231 | PINMUX_IPSR_DATA(IP10_2_0, DU1_DG6), |
adedb87f | 1232 | PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1), |
43c4436e HN |
1233 | PINMUX_IPSR_DATA(IP10_2_0, CAN_DEBUGOUT0), |
1234 | PINMUX_IPSR_DATA(IP10_2_0, CC50_STATE35), | |
adedb87f KM |
1235 | PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0), |
1236 | PINMUX_IPSR_MSEL(IP10_5_3, IIC0_SDA, SEL_IIC00_0), | |
43c4436e | 1237 | PINMUX_IPSR_DATA(IP10_5_3, DU1_DG7), |
adedb87f | 1238 | PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1), |
43c4436e HN |
1239 | PINMUX_IPSR_DATA(IP10_5_3, CAN_DEBUGOUT1), |
1240 | PINMUX_IPSR_DATA(IP10_5_3, CC50_STATE36), | |
adedb87f KM |
1241 | PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0), |
1242 | PINMUX_IPSR_MSEL(IP10_8_6, IIC1_SCL, SEL_IIC01_0), | |
43c4436e | 1243 | PINMUX_IPSR_DATA(IP10_8_6, DU1_DB0), |
adedb87f | 1244 | PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1), |
43c4436e HN |
1245 | PINMUX_IPSR_DATA(IP10_8_6, USB0_EXTLP), |
1246 | PINMUX_IPSR_DATA(IP10_8_6, CAN_DEBUGOUT2), | |
1247 | PINMUX_IPSR_DATA(IP10_8_6, CC50_STATE37), | |
adedb87f KM |
1248 | PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0), |
1249 | PINMUX_IPSR_MSEL(IP10_11_9, IIC1_SDA, SEL_IIC01_0), | |
43c4436e | 1250 | PINMUX_IPSR_DATA(IP10_11_9, DU1_DB1), |
adedb87f | 1251 | PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1), |
43c4436e HN |
1252 | PINMUX_IPSR_DATA(IP10_11_9, USB0_OVC1), |
1253 | PINMUX_IPSR_DATA(IP10_11_9, CAN_DEBUGOUT3), | |
1254 | PINMUX_IPSR_DATA(IP10_11_9, CC50_STATE38), | |
adedb87f | 1255 | PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0), |
43c4436e HN |
1256 | PINMUX_IPSR_DATA(IP10_14_12, IRQ1), |
1257 | PINMUX_IPSR_DATA(IP10_14_12, DU1_DB2), | |
adedb87f | 1258 | PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1), |
43c4436e HN |
1259 | PINMUX_IPSR_DATA(IP10_14_12, USB0_IDIN), |
1260 | PINMUX_IPSR_DATA(IP10_14_12, CAN_DEBUGOUT4), | |
1261 | PINMUX_IPSR_DATA(IP10_14_12, CC50_STATE39), | |
adedb87f | 1262 | PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0), |
43c4436e | 1263 | PINMUX_IPSR_DATA(IP10_17_15, IRQ2), |
adedb87f | 1264 | PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3), |
43c4436e | 1265 | PINMUX_IPSR_DATA(IP10_17_15, DU1_DB3), |
adedb87f | 1266 | PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1), |
43c4436e HN |
1267 | PINMUX_IPSR_DATA(IP10_17_15, TANS2), |
1268 | PINMUX_IPSR_DATA(IP10_17_15, CAN_DEBUGOUT5), | |
1269 | PINMUX_IPSR_DATA(IP10_17_15, CC50_OSCOUT), | |
adedb87f KM |
1270 | PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0), |
1271 | PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4), | |
1272 | PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3), | |
43c4436e | 1273 | PINMUX_IPSR_DATA(IP10_20_18, DU1_DB4), |
adedb87f KM |
1274 | PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2), |
1275 | PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1), | |
43c4436e | 1276 | PINMUX_IPSR_DATA(IP10_20_18, CAN_DEBUGOUT6), |
adedb87f KM |
1277 | PINMUX_IPSR_MSEL(IP10_20_18, RDS_CLK_C, SEL_RDS_2), |
1278 | PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0), | |
1279 | PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4), | |
1280 | PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3), | |
43c4436e | 1281 | PINMUX_IPSR_DATA(IP10_23_21, DU1_DB5), |
adedb87f KM |
1282 | PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2), |
1283 | PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1), | |
43c4436e | 1284 | PINMUX_IPSR_DATA(IP10_23_21, CAN_DEBUGOUT7), |
adedb87f KM |
1285 | PINMUX_IPSR_MSEL(IP10_23_21, RDS_DATA_C, SEL_RDS_2), |
1286 | PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0), | |
1287 | PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0), | |
43c4436e | 1288 | PINMUX_IPSR_DATA(IP10_26_24, DU1_DB6), |
adedb87f KM |
1289 | PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2), |
1290 | PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1), | |
43c4436e | 1291 | PINMUX_IPSR_DATA(IP10_26_24, CAN_DEBUGOUT8), |
adedb87f KM |
1292 | PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0), |
1293 | PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0), | |
43c4436e | 1294 | PINMUX_IPSR_DATA(IP10_29_27, DU1_DB7), |
adedb87f | 1295 | PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2), |
43c4436e | 1296 | PINMUX_IPSR_DATA(IP10_29_27, CAN_DEBUGOUT9), |
adedb87f KM |
1297 | PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0), |
1298 | PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0), | |
43c4436e HN |
1299 | PINMUX_IPSR_DATA(IP10_31_30, DU1_DOTCLKIN), |
1300 | PINMUX_IPSR_DATA(IP10_31_30, CAN_DEBUGOUT10), | |
1301 | ||
1302 | /* IPSR11 */ | |
adedb87f KM |
1303 | PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0), |
1304 | PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0), | |
1305 | PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2), | |
43c4436e HN |
1306 | PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0), |
1307 | PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11), | |
adedb87f KM |
1308 | PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0), |
1309 | PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0), | |
1310 | PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2), | |
43c4436e HN |
1311 | PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1), |
1312 | PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12), | |
adedb87f KM |
1313 | PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0), |
1314 | PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1), | |
43c4436e HN |
1315 | PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC), |
1316 | PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13), | |
adedb87f KM |
1317 | PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0), |
1318 | PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1), | |
1319 | PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2), | |
43c4436e HN |
1320 | PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC), |
1321 | PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14), | |
adedb87f KM |
1322 | PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0), |
1323 | PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1), | |
1324 | PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2), | |
43c4436e HN |
1325 | PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE), |
1326 | PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15), | |
adedb87f KM |
1327 | PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0), |
1328 | PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1), | |
1329 | PINMUX_IPSR_MSEL(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2), | |
43c4436e | 1330 | PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP), |
adedb87f KM |
1331 | PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0), |
1332 | PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1), | |
1333 | PINMUX_IPSR_MSEL(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2), | |
43c4436e | 1334 | PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE), |
adedb87f KM |
1335 | PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0), |
1336 | PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1), | |
43c4436e | 1337 | PINMUX_IPSR_DATA(IP11_20_18, IRQ8), |
adedb87f KM |
1338 | PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3), |
1339 | PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3), | |
43c4436e HN |
1340 | PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N), |
1341 | PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129), | |
adedb87f KM |
1342 | PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1), |
1343 | PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3), | |
1344 | PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1), | |
1345 | PINMUX_IPSR_MSEL(IP11_23_21, AD_DI_B, SEL_ADI_1), | |
43c4436e HN |
1346 | PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N), |
1347 | PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129), | |
adedb87f KM |
1348 | PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1), |
1349 | PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3), | |
1350 | PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), | |
1351 | PINMUX_IPSR_MSEL(IP11_26_24, AD_DO_B, SEL_ADI_1), | |
43c4436e | 1352 | PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0), |
adedb87f | 1353 | PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1), |
43c4436e | 1354 | PINMUX_IPSR_DATA(IP11_29_27, PWM0_B), |
adedb87f KM |
1355 | PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1), |
1356 | PINMUX_IPSR_MSEL(IP11_29_27, AD_CLK_B, SEL_ADI_1), | |
43c4436e HN |
1357 | |
1358 | /* IPSR12 */ | |
1359 | PINMUX_IPSR_DATA(IP12_2_0, SSI_SCK34), | |
adedb87f KM |
1360 | PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1), |
1361 | PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2), | |
1362 | PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1), | |
1363 | PINMUX_IPSR_MSEL(IP12_2_0, AD_NCS_N_B, SEL_ADI_1), | |
1364 | PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1), | |
43c4436e | 1365 | PINMUX_IPSR_DATA(IP12_5_3, SSI_WS34), |
adedb87f KM |
1366 | PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1), |
1367 | PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2), | |
1368 | PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1), | |
1369 | PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2), | |
1370 | PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1), | |
43c4436e | 1371 | PINMUX_IPSR_DATA(IP12_8_6, SSI_SDATA3), |
adedb87f KM |
1372 | PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1), |
1373 | PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2), | |
1374 | PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1), | |
1375 | PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2), | |
43c4436e | 1376 | PINMUX_IPSR_DATA(IP12_8_6, DREQ2_N), |
adedb87f | 1377 | PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0), |
43c4436e | 1378 | PINMUX_IPSR_DATA(IP12_10_9, MLB_CLK), |
adedb87f | 1379 | PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1), |
43c4436e | 1380 | PINMUX_IPSR_DATA(IP12_10_9, IRD_TX), |
adedb87f | 1381 | PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0), |
43c4436e | 1382 | PINMUX_IPSR_DATA(IP12_12_11, MLB_SIG), |
adedb87f | 1383 | PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1), |
43c4436e | 1384 | PINMUX_IPSR_DATA(IP12_12_11, IRD_RX), |
adedb87f | 1385 | PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0), |
43c4436e | 1386 | PINMUX_IPSR_DATA(IP12_14_13, MLB_DAT), |
adedb87f | 1387 | PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1), |
43c4436e | 1388 | PINMUX_IPSR_DATA(IP12_14_13, IRD_SCK), |
adedb87f KM |
1389 | PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0), |
1390 | PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1), | |
43c4436e HN |
1391 | PINMUX_IPSR_DATA(IP12_17_15, PWM1_B), |
1392 | PINMUX_IPSR_DATA(IP12_17_15, IRQ9), | |
adedb87f | 1393 | PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0), |
43c4436e | 1394 | PINMUX_IPSR_DATA(IP12_17_15, DACK2), |
adedb87f KM |
1395 | PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1), |
1396 | PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0), | |
1397 | PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1), | |
1398 | PINMUX_IPSR_MSEL(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2), | |
43c4436e | 1399 | PINMUX_IPSR_DATA(IP12_20_18, VI1_CLK), |
adedb87f KM |
1400 | PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3), |
1401 | PINMUX_IPSR_MSEL(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0), | |
1402 | PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1), | |
1403 | PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0), | |
1404 | PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1), | |
1405 | PINMUX_IPSR_MSEL(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2), | |
43c4436e | 1406 | PINMUX_IPSR_DATA(IP12_23_21, VI1_DATA0), |
adedb87f KM |
1407 | PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3), |
1408 | PINMUX_IPSR_MSEL(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0), | |
1409 | PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1), | |
1410 | PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0), | |
1411 | PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1), | |
43c4436e | 1412 | PINMUX_IPSR_DATA(IP12_26_24, VI1_DATA1), |
adedb87f | 1413 | PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0), |
43c4436e | 1414 | PINMUX_IPSR_DATA(IP12_26_24, ATAG0_N), |
adedb87f KM |
1415 | PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1), |
1416 | PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0), | |
1417 | PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1), | |
43c4436e | 1418 | PINMUX_IPSR_DATA(IP12_29_27, VI1_DATA2), |
adedb87f | 1419 | PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0), |
43c4436e | 1420 | PINMUX_IPSR_DATA(IP12_29_27, ATAWR0_N), |
adedb87f | 1421 | PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1), |
43c4436e HN |
1422 | |
1423 | /* IPSR13 */ | |
adedb87f KM |
1424 | PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0), |
1425 | PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1), | |
1426 | PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3), | |
43c4436e | 1427 | PINMUX_IPSR_DATA(IP13_2_0, VI1_DATA3), |
adedb87f | 1428 | PINMUX_IPSR_MSEL(IP13_2_0, SCKZ, SEL_FSN_0), |
43c4436e | 1429 | PINMUX_IPSR_DATA(IP13_2_0, ATACS00_N), |
adedb87f KM |
1430 | PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1), |
1431 | PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0), | |
1432 | PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1), | |
1433 | PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3), | |
43c4436e | 1434 | PINMUX_IPSR_DATA(IP13_5_3, VI1_DATA4), |
adedb87f | 1435 | PINMUX_IPSR_MSEL(IP13_5_3, STM_N, SEL_FSN_0), |
43c4436e | 1436 | PINMUX_IPSR_DATA(IP13_5_3, ATACS10_N), |
adedb87f KM |
1437 | PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1), |
1438 | PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0), | |
1439 | PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1), | |
43c4436e HN |
1440 | PINMUX_IPSR_DATA(IP13_8_6, PWM2_B), |
1441 | PINMUX_IPSR_DATA(IP13_8_6, VI1_DATA5), | |
adedb87f | 1442 | PINMUX_IPSR_MSEL(IP13_8_6, MTS_N, SEL_FSN_0), |
43c4436e | 1443 | PINMUX_IPSR_DATA(IP13_8_6, EX_WAIT1), |
adedb87f KM |
1444 | PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1), |
1445 | PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0), | |
1446 | PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1), | |
1447 | PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4), | |
43c4436e HN |
1448 | PINMUX_IPSR_DATA(IP13_11_9, VI1_DATA6), |
1449 | PINMUX_IPSR_DATA(IP13_11_9, ATARD0_N), | |
adedb87f KM |
1450 | PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1), |
1451 | PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0), | |
1452 | PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1), | |
1453 | PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4), | |
43c4436e HN |
1454 | PINMUX_IPSR_DATA(IP13_14_12, VI1_DATA7), |
1455 | PINMUX_IPSR_DATA(IP13_14_12, ATADIR0_N), | |
adedb87f KM |
1456 | PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1), |
1457 | PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0), | |
1458 | PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1), | |
1459 | PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3), | |
43c4436e | 1460 | PINMUX_IPSR_DATA(IP13_17_15, VI1_CLKENB), |
adedb87f KM |
1461 | PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2), |
1462 | PINMUX_IPSR_MSEL(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1), | |
1463 | PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1), | |
1464 | PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0), | |
1465 | PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1), | |
1466 | PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3), | |
43c4436e | 1467 | PINMUX_IPSR_DATA(IP13_20_18, VI1_FIELD), |
adedb87f KM |
1468 | PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2), |
1469 | PINMUX_IPSR_MSEL(IP13_20_18, RIF0_CLK_B, SEL_DR0_1), | |
1470 | PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4), | |
1471 | PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1), | |
1472 | PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0), | |
1473 | PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1), | |
1474 | PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3), | |
43c4436e | 1475 | PINMUX_IPSR_DATA(IP13_23_21, VI1_HSYNC_N), |
adedb87f KM |
1476 | PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2), |
1477 | PINMUX_IPSR_MSEL(IP13_23_21, RIF0_D0_B, SEL_DR0_1), | |
1478 | PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4), | |
1479 | PINMUX_IPSR_MSEL(IP13_23_21, RDS_CLK_D, SEL_RDS_3), | |
1480 | PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0), | |
1481 | PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1), | |
1482 | PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3), | |
43c4436e | 1483 | PINMUX_IPSR_DATA(IP13_26_24, VI1_VSYNC_N), |
adedb87f KM |
1484 | PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2), |
1485 | PINMUX_IPSR_MSEL(IP13_26_24, RIF0_D1_B, SEL_DR1_1), | |
1486 | PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4), | |
1487 | PINMUX_IPSR_MSEL(IP13_26_24, RDS_DATA_D, SEL_RDS_3), | |
43c4436e HN |
1488 | }; |
1489 | ||
1490 | static const struct sh_pfc_pin pinmux_pins[] = { | |
1491 | PINMUX_GPIO_GP_ALL(), | |
1492 | }; | |
1493 | ||
1494 | /* - ETH -------------------------------------------------------------------- */ | |
1495 | static const unsigned int eth_link_pins[] = { | |
1496 | /* LINK */ | |
1497 | RCAR_GP_PIN(3, 18), | |
1498 | }; | |
1499 | static const unsigned int eth_link_mux[] = { | |
1500 | ETH_LINK_MARK, | |
1501 | }; | |
1502 | static const unsigned int eth_magic_pins[] = { | |
1503 | /* MAGIC */ | |
1504 | RCAR_GP_PIN(3, 22), | |
1505 | }; | |
1506 | static const unsigned int eth_magic_mux[] = { | |
1507 | ETH_MAGIC_MARK, | |
1508 | }; | |
1509 | static const unsigned int eth_mdio_pins[] = { | |
1510 | /* MDC, MDIO */ | |
1511 | RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13), | |
1512 | }; | |
1513 | static const unsigned int eth_mdio_mux[] = { | |
1514 | ETH_MDC_MARK, ETH_MDIO_MARK, | |
1515 | }; | |
1516 | static const unsigned int eth_rmii_pins[] = { | |
1517 | /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ | |
1518 | RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15), | |
1519 | RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20), | |
1520 | RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19), | |
1521 | }; | |
1522 | static const unsigned int eth_rmii_mux[] = { | |
1523 | ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, | |
1524 | ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, | |
1525 | }; | |
1526 | static const unsigned int eth_link_b_pins[] = { | |
1527 | /* LINK */ | |
1528 | RCAR_GP_PIN(5, 15), | |
1529 | }; | |
1530 | static const unsigned int eth_link_b_mux[] = { | |
1531 | ETH_LINK_B_MARK, | |
1532 | }; | |
1533 | static const unsigned int eth_magic_b_pins[] = { | |
1534 | /* MAGIC */ | |
1535 | RCAR_GP_PIN(5, 19), | |
1536 | }; | |
1537 | static const unsigned int eth_magic_b_mux[] = { | |
1538 | ETH_MAGIC_B_MARK, | |
1539 | }; | |
1540 | static const unsigned int eth_mdio_b_pins[] = { | |
1541 | /* MDC, MDIO */ | |
1542 | RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10), | |
1543 | }; | |
1544 | static const unsigned int eth_mdio_b_mux[] = { | |
1545 | ETH_MDC_B_MARK, ETH_MDIO_B_MARK, | |
1546 | }; | |
1547 | static const unsigned int eth_rmii_b_pins[] = { | |
1548 | /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ | |
1549 | RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12), | |
1550 | RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17), | |
1551 | RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16), | |
1552 | }; | |
1553 | static const unsigned int eth_rmii_b_mux[] = { | |
1554 | ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK, | |
1555 | ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK, | |
1556 | }; | |
1557 | /* - HSCIF0 ----------------------------------------------------------------- */ | |
1558 | static const unsigned int hscif0_data_pins[] = { | |
1559 | /* RX, TX */ | |
1560 | RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), | |
1561 | }; | |
1562 | static const unsigned int hscif0_data_mux[] = { | |
1563 | HSCIF0_HRX_MARK, HSCIF0_HTX_MARK, | |
1564 | }; | |
1565 | static const unsigned int hscif0_clk_pins[] = { | |
1566 | /* SCK */ | |
1567 | RCAR_GP_PIN(3, 29), | |
1568 | }; | |
1569 | static const unsigned int hscif0_clk_mux[] = { | |
1570 | HSCIF0_HSCK_MARK, | |
1571 | }; | |
1572 | static const unsigned int hscif0_ctrl_pins[] = { | |
1573 | /* RTS, CTS */ | |
1574 | RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27), | |
1575 | }; | |
1576 | static const unsigned int hscif0_ctrl_mux[] = { | |
1577 | HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK, | |
1578 | }; | |
1579 | static const unsigned int hscif0_data_b_pins[] = { | |
1580 | /* RX, TX */ | |
1581 | RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31), | |
1582 | }; | |
1583 | static const unsigned int hscif0_data_b_mux[] = { | |
1584 | HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK, | |
1585 | }; | |
1586 | static const unsigned int hscif0_clk_b_pins[] = { | |
1587 | /* SCK */ | |
1588 | RCAR_GP_PIN(1, 0), | |
1589 | }; | |
1590 | static const unsigned int hscif0_clk_b_mux[] = { | |
1591 | HSCIF0_HSCK_B_MARK, | |
1592 | }; | |
1593 | /* - HSCIF1 ----------------------------------------------------------------- */ | |
1594 | static const unsigned int hscif1_data_pins[] = { | |
1595 | /* RX, TX */ | |
1596 | RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), | |
1597 | }; | |
1598 | static const unsigned int hscif1_data_mux[] = { | |
1599 | HSCIF1_HRX_MARK, HSCIF1_HTX_MARK, | |
1600 | }; | |
1601 | static const unsigned int hscif1_clk_pins[] = { | |
1602 | /* SCK */ | |
1603 | RCAR_GP_PIN(4, 10), | |
1604 | }; | |
1605 | static const unsigned int hscif1_clk_mux[] = { | |
1606 | HSCIF1_HSCK_MARK, | |
1607 | }; | |
1608 | static const unsigned int hscif1_ctrl_pins[] = { | |
1609 | /* RTS, CTS */ | |
1610 | RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), | |
1611 | }; | |
1612 | static const unsigned int hscif1_ctrl_mux[] = { | |
1613 | HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK, | |
1614 | }; | |
1615 | static const unsigned int hscif1_data_b_pins[] = { | |
1616 | /* RX, TX */ | |
1617 | RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), | |
1618 | }; | |
1619 | static const unsigned int hscif1_data_b_mux[] = { | |
1620 | HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK, | |
1621 | }; | |
1622 | static const unsigned int hscif1_ctrl_b_pins[] = { | |
1623 | /* RTS, CTS */ | |
1624 | RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), | |
1625 | }; | |
1626 | static const unsigned int hscif1_ctrl_b_mux[] = { | |
1627 | HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK, | |
1628 | }; | |
1629 | /* - HSCIF2 ----------------------------------------------------------------- */ | |
1630 | static const unsigned int hscif2_data_pins[] = { | |
1631 | /* RX, TX */ | |
1632 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), | |
1633 | }; | |
1634 | static const unsigned int hscif2_data_mux[] = { | |
1635 | HSCIF2_HRX_MARK, HSCIF2_HTX_MARK, | |
1636 | }; | |
1637 | static const unsigned int hscif2_clk_pins[] = { | |
1638 | /* SCK */ | |
1639 | RCAR_GP_PIN(0, 10), | |
1640 | }; | |
1641 | static const unsigned int hscif2_clk_mux[] = { | |
1642 | HSCIF2_HSCK_MARK, | |
1643 | }; | |
1644 | static const unsigned int hscif2_ctrl_pins[] = { | |
1645 | /* RTS, CTS */ | |
1646 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), | |
1647 | }; | |
1648 | static const unsigned int hscif2_ctrl_mux[] = { | |
1649 | HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK, | |
1650 | }; | |
1651 | /* - I2C0 ------------------------------------------------------------------- */ | |
1652 | static const unsigned int i2c0_pins[] = { | |
1653 | /* SCL, SDA */ | |
1654 | RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), | |
1655 | }; | |
1656 | static const unsigned int i2c0_mux[] = { | |
1657 | I2C0_SCL_MARK, I2C0_SDA_MARK, | |
1658 | }; | |
1659 | static const unsigned int i2c0_b_pins[] = { | |
1660 | /* SCL, SDA */ | |
1661 | RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), | |
1662 | }; | |
1663 | static const unsigned int i2c0_b_mux[] = { | |
1664 | I2C0_SCL_B_MARK, I2C0_SDA_B_MARK, | |
1665 | }; | |
1666 | static const unsigned int i2c0_c_pins[] = { | |
1667 | /* SCL, SDA */ | |
1668 | RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), | |
1669 | }; | |
1670 | static const unsigned int i2c0_c_mux[] = { | |
1671 | I2C0_SCL_C_MARK, I2C0_SDA_C_MARK, | |
1672 | }; | |
1673 | static const unsigned int i2c0_d_pins[] = { | |
1674 | /* SCL, SDA */ | |
1675 | RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), | |
1676 | }; | |
1677 | static const unsigned int i2c0_d_mux[] = { | |
1678 | I2C0_SCL_D_MARK, I2C0_SDA_D_MARK, | |
1679 | }; | |
1680 | static const unsigned int i2c0_e_pins[] = { | |
1681 | /* SCL, SDA */ | |
1682 | RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), | |
1683 | }; | |
1684 | static const unsigned int i2c0_e_mux[] = { | |
1685 | I2C0_SCL_E_MARK, I2C0_SDA_E_MARK, | |
1686 | }; | |
1687 | /* - I2C1 ------------------------------------------------------------------- */ | |
1688 | static const unsigned int i2c1_pins[] = { | |
1689 | /* SCL, SDA */ | |
1690 | RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), | |
1691 | }; | |
1692 | static const unsigned int i2c1_mux[] = { | |
1693 | I2C1_SCL_MARK, I2C1_SDA_MARK, | |
1694 | }; | |
1695 | static const unsigned int i2c1_b_pins[] = { | |
1696 | /* SCL, SDA */ | |
1697 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), | |
1698 | }; | |
1699 | static const unsigned int i2c1_b_mux[] = { | |
1700 | I2C1_SCL_B_MARK, I2C1_SDA_B_MARK, | |
1701 | }; | |
1702 | static const unsigned int i2c1_c_pins[] = { | |
1703 | /* SCL, SDA */ | |
1704 | RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), | |
1705 | }; | |
1706 | static const unsigned int i2c1_c_mux[] = { | |
1707 | I2C1_SCL_C_MARK, I2C1_SDA_C_MARK, | |
1708 | }; | |
1709 | static const unsigned int i2c1_d_pins[] = { | |
1710 | /* SCL, SDA */ | |
1711 | RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), | |
1712 | }; | |
1713 | static const unsigned int i2c1_d_mux[] = { | |
1714 | I2C1_SCL_D_MARK, I2C1_SDA_D_MARK, | |
1715 | }; | |
1716 | static const unsigned int i2c1_e_pins[] = { | |
1717 | /* SCL, SDA */ | |
1718 | RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), | |
1719 | }; | |
1720 | static const unsigned int i2c1_e_mux[] = { | |
1721 | I2C1_SCL_E_MARK, I2C1_SDA_E_MARK, | |
1722 | }; | |
1723 | /* - I2C2 ------------------------------------------------------------------- */ | |
1724 | static const unsigned int i2c2_pins[] = { | |
1725 | /* SCL, SDA */ | |
1726 | RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), | |
1727 | }; | |
1728 | static const unsigned int i2c2_mux[] = { | |
1729 | I2C2_SCL_MARK, I2C2_SDA_MARK, | |
1730 | }; | |
1731 | static const unsigned int i2c2_b_pins[] = { | |
1732 | /* SCL, SDA */ | |
1733 | RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), | |
1734 | }; | |
1735 | static const unsigned int i2c2_b_mux[] = { | |
1736 | I2C2_SCL_B_MARK, I2C2_SDA_B_MARK, | |
1737 | }; | |
1738 | static const unsigned int i2c2_c_pins[] = { | |
1739 | /* SCL, SDA */ | |
1740 | RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), | |
1741 | }; | |
1742 | static const unsigned int i2c2_c_mux[] = { | |
1743 | I2C2_SCL_C_MARK, I2C2_SDA_C_MARK, | |
1744 | }; | |
1745 | static const unsigned int i2c2_d_pins[] = { | |
1746 | /* SCL, SDA */ | |
1747 | RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), | |
1748 | }; | |
1749 | static const unsigned int i2c2_d_mux[] = { | |
1750 | I2C2_SCL_D_MARK, I2C2_SDA_D_MARK, | |
1751 | }; | |
1752 | static const unsigned int i2c2_e_pins[] = { | |
1753 | /* SCL, SDA */ | |
1754 | RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), | |
1755 | }; | |
1756 | static const unsigned int i2c2_e_mux[] = { | |
1757 | I2C2_SCL_E_MARK, I2C2_SDA_E_MARK, | |
1758 | }; | |
1759 | /* - I2C3 ------------------------------------------------------------------- */ | |
1760 | static const unsigned int i2c3_pins[] = { | |
1761 | /* SCL, SDA */ | |
1762 | RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), | |
1763 | }; | |
1764 | static const unsigned int i2c3_mux[] = { | |
1765 | I2C3_SCL_MARK, I2C3_SDA_MARK, | |
1766 | }; | |
1767 | static const unsigned int i2c3_b_pins[] = { | |
1768 | /* SCL, SDA */ | |
1769 | RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), | |
1770 | }; | |
1771 | static const unsigned int i2c3_b_mux[] = { | |
1772 | I2C3_SCL_B_MARK, I2C3_SDA_B_MARK, | |
1773 | }; | |
1774 | static const unsigned int i2c3_c_pins[] = { | |
1775 | /* SCL, SDA */ | |
1776 | RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), | |
1777 | }; | |
1778 | static const unsigned int i2c3_c_mux[] = { | |
1779 | I2C3_SCL_C_MARK, I2C3_SDA_C_MARK, | |
1780 | }; | |
1781 | static const unsigned int i2c3_d_pins[] = { | |
1782 | /* SCL, SDA */ | |
1783 | RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), | |
1784 | }; | |
1785 | static const unsigned int i2c3_d_mux[] = { | |
1786 | I2C3_SCL_D_MARK, I2C3_SDA_D_MARK, | |
1787 | }; | |
1788 | static const unsigned int i2c3_e_pins[] = { | |
1789 | /* SCL, SDA */ | |
1790 | RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), | |
1791 | }; | |
1792 | static const unsigned int i2c3_e_mux[] = { | |
1793 | I2C3_SCL_E_MARK, I2C3_SDA_E_MARK, | |
1794 | }; | |
1795 | /* - I2C4 ------------------------------------------------------------------- */ | |
1796 | static const unsigned int i2c4_pins[] = { | |
1797 | /* SCL, SDA */ | |
1798 | RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), | |
1799 | }; | |
1800 | static const unsigned int i2c4_mux[] = { | |
1801 | I2C4_SCL_MARK, I2C4_SDA_MARK, | |
1802 | }; | |
1803 | static const unsigned int i2c4_b_pins[] = { | |
1804 | /* SCL, SDA */ | |
1805 | RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), | |
1806 | }; | |
1807 | static const unsigned int i2c4_b_mux[] = { | |
1808 | I2C4_SCL_B_MARK, I2C4_SDA_B_MARK, | |
1809 | }; | |
1810 | static const unsigned int i2c4_c_pins[] = { | |
1811 | /* SCL, SDA */ | |
1812 | RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), | |
1813 | }; | |
1814 | static const unsigned int i2c4_c_mux[] = { | |
1815 | I2C4_SCL_C_MARK, I2C4_SDA_C_MARK, | |
1816 | }; | |
1817 | static const unsigned int i2c4_d_pins[] = { | |
1818 | /* SCL, SDA */ | |
1819 | RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), | |
1820 | }; | |
1821 | static const unsigned int i2c4_d_mux[] = { | |
1822 | I2C4_SCL_D_MARK, I2C4_SDA_D_MARK, | |
1823 | }; | |
1824 | static const unsigned int i2c4_e_pins[] = { | |
1825 | /* SCL, SDA */ | |
1826 | RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), | |
1827 | }; | |
1828 | static const unsigned int i2c4_e_mux[] = { | |
1829 | I2C4_SCL_E_MARK, I2C4_SDA_E_MARK, | |
1830 | }; | |
1831 | /* - INTC ------------------------------------------------------------------- */ | |
1832 | static const unsigned int intc_irq0_pins[] = { | |
1833 | /* IRQ0 */ | |
1834 | RCAR_GP_PIN(4, 4), | |
1835 | }; | |
1836 | static const unsigned int intc_irq0_mux[] = { | |
1837 | IRQ0_MARK, | |
1838 | }; | |
1839 | static const unsigned int intc_irq1_pins[] = { | |
1840 | /* IRQ1 */ | |
1841 | RCAR_GP_PIN(4, 18), | |
1842 | }; | |
1843 | static const unsigned int intc_irq1_mux[] = { | |
1844 | IRQ1_MARK, | |
1845 | }; | |
1846 | static const unsigned int intc_irq2_pins[] = { | |
1847 | /* IRQ2 */ | |
1848 | RCAR_GP_PIN(4, 19), | |
1849 | }; | |
1850 | static const unsigned int intc_irq2_mux[] = { | |
1851 | IRQ2_MARK, | |
1852 | }; | |
1853 | static const unsigned int intc_irq3_pins[] = { | |
1854 | /* IRQ3 */ | |
1855 | RCAR_GP_PIN(0, 7), | |
1856 | }; | |
1857 | static const unsigned int intc_irq3_mux[] = { | |
1858 | IRQ3_MARK, | |
1859 | }; | |
1860 | static const unsigned int intc_irq4_pins[] = { | |
1861 | /* IRQ4 */ | |
1862 | RCAR_GP_PIN(0, 0), | |
1863 | }; | |
1864 | static const unsigned int intc_irq4_mux[] = { | |
1865 | IRQ4_MARK, | |
1866 | }; | |
1867 | static const unsigned int intc_irq5_pins[] = { | |
1868 | /* IRQ5 */ | |
1869 | RCAR_GP_PIN(4, 1), | |
1870 | }; | |
1871 | static const unsigned int intc_irq5_mux[] = { | |
1872 | IRQ5_MARK, | |
1873 | }; | |
1874 | static const unsigned int intc_irq6_pins[] = { | |
1875 | /* IRQ6 */ | |
1876 | RCAR_GP_PIN(0, 10), | |
1877 | }; | |
1878 | static const unsigned int intc_irq6_mux[] = { | |
1879 | IRQ6_MARK, | |
1880 | }; | |
1881 | static const unsigned int intc_irq7_pins[] = { | |
1882 | /* IRQ7 */ | |
1883 | RCAR_GP_PIN(6, 15), | |
1884 | }; | |
1885 | static const unsigned int intc_irq7_mux[] = { | |
1886 | IRQ7_MARK, | |
1887 | }; | |
1888 | static const unsigned int intc_irq8_pins[] = { | |
1889 | /* IRQ8 */ | |
1890 | RCAR_GP_PIN(5, 0), | |
1891 | }; | |
1892 | static const unsigned int intc_irq8_mux[] = { | |
1893 | IRQ8_MARK, | |
1894 | }; | |
1895 | static const unsigned int intc_irq9_pins[] = { | |
1896 | /* IRQ9 */ | |
1897 | RCAR_GP_PIN(5, 10), | |
1898 | }; | |
1899 | static const unsigned int intc_irq9_mux[] = { | |
1900 | IRQ9_MARK, | |
1901 | }; | |
f1f74b64 SU |
1902 | /* - MMCIF ------------------------------------------------------------------ */ |
1903 | static const unsigned int mmc_data1_pins[] = { | |
1904 | /* D[0] */ | |
1905 | RCAR_GP_PIN(6, 18), | |
1906 | }; | |
1907 | static const unsigned int mmc_data1_mux[] = { | |
1908 | MMC_D0_MARK, | |
1909 | }; | |
1910 | static const unsigned int mmc_data4_pins[] = { | |
1911 | /* D[0:3] */ | |
1912 | RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), | |
1913 | RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), | |
1914 | }; | |
1915 | static const unsigned int mmc_data4_mux[] = { | |
1916 | MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, | |
1917 | }; | |
1918 | static const unsigned int mmc_data8_pins[] = { | |
1919 | /* D[0:7] */ | |
1920 | RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), | |
1921 | RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), | |
1922 | RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), | |
1923 | RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), | |
1924 | }; | |
1925 | static const unsigned int mmc_data8_mux[] = { | |
1926 | MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, | |
1927 | MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK, | |
1928 | }; | |
1929 | static const unsigned int mmc_ctrl_pins[] = { | |
1930 | /* CLK, CMD */ | |
1931 | RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), | |
1932 | }; | |
1933 | static const unsigned int mmc_ctrl_mux[] = { | |
1934 | MMC_CLK_MARK, MMC_CMD_MARK, | |
1935 | }; | |
43c4436e HN |
1936 | /* - MSIOF0 ----------------------------------------------------------------- */ |
1937 | static const unsigned int msiof0_clk_pins[] = { | |
1938 | /* SCK */ | |
1939 | RCAR_GP_PIN(4, 4), | |
1940 | }; | |
1941 | static const unsigned int msiof0_clk_mux[] = { | |
1942 | MSIOF0_SCK_MARK, | |
1943 | }; | |
1944 | static const unsigned int msiof0_sync_pins[] = { | |
1945 | /* SYNC */ | |
1946 | RCAR_GP_PIN(4, 5), | |
1947 | }; | |
1948 | static const unsigned int msiof0_sync_mux[] = { | |
1949 | MSIOF0_SYNC_MARK, | |
1950 | }; | |
1951 | static const unsigned int msiof0_ss1_pins[] = { | |
1952 | /* SS1 */ | |
1953 | RCAR_GP_PIN(4, 6), | |
1954 | }; | |
1955 | static const unsigned int msiof0_ss1_mux[] = { | |
1956 | MSIOF0_SS1_MARK, | |
1957 | }; | |
1958 | static const unsigned int msiof0_ss2_pins[] = { | |
1959 | /* SS2 */ | |
1960 | RCAR_GP_PIN(4, 7), | |
1961 | }; | |
1962 | static const unsigned int msiof0_ss2_mux[] = { | |
1963 | MSIOF0_SS2_MARK, | |
1964 | }; | |
1965 | static const unsigned int msiof0_rx_pins[] = { | |
1966 | /* RXD */ | |
1967 | RCAR_GP_PIN(4, 2), | |
1968 | }; | |
1969 | static const unsigned int msiof0_rx_mux[] = { | |
1970 | MSIOF0_RXD_MARK, | |
1971 | }; | |
1972 | static const unsigned int msiof0_tx_pins[] = { | |
1973 | /* TXD */ | |
1974 | RCAR_GP_PIN(4, 3), | |
1975 | }; | |
1976 | static const unsigned int msiof0_tx_mux[] = { | |
1977 | MSIOF0_TXD_MARK, | |
1978 | }; | |
1979 | /* - MSIOF1 ----------------------------------------------------------------- */ | |
1980 | static const unsigned int msiof1_clk_pins[] = { | |
1981 | /* SCK */ | |
1982 | RCAR_GP_PIN(0, 26), | |
1983 | }; | |
1984 | static const unsigned int msiof1_clk_mux[] = { | |
1985 | MSIOF1_SCK_MARK, | |
1986 | }; | |
1987 | static const unsigned int msiof1_sync_pins[] = { | |
1988 | /* SYNC */ | |
1989 | RCAR_GP_PIN(0, 27), | |
1990 | }; | |
1991 | static const unsigned int msiof1_sync_mux[] = { | |
1992 | MSIOF1_SYNC_MARK, | |
1993 | }; | |
1994 | static const unsigned int msiof1_ss1_pins[] = { | |
1995 | /* SS1 */ | |
1996 | RCAR_GP_PIN(0, 28), | |
1997 | }; | |
1998 | static const unsigned int msiof1_ss1_mux[] = { | |
1999 | MSIOF1_SS1_MARK, | |
2000 | }; | |
2001 | static const unsigned int msiof1_ss2_pins[] = { | |
2002 | /* SS2 */ | |
2003 | RCAR_GP_PIN(0, 29), | |
2004 | }; | |
2005 | static const unsigned int msiof1_ss2_mux[] = { | |
2006 | MSIOF1_SS2_MARK, | |
2007 | }; | |
2008 | static const unsigned int msiof1_rx_pins[] = { | |
2009 | /* RXD */ | |
2010 | RCAR_GP_PIN(0, 24), | |
2011 | }; | |
2012 | static const unsigned int msiof1_rx_mux[] = { | |
2013 | MSIOF1_RXD_MARK, | |
2014 | }; | |
2015 | static const unsigned int msiof1_tx_pins[] = { | |
2016 | /* TXD */ | |
2017 | RCAR_GP_PIN(0, 25), | |
2018 | }; | |
2019 | static const unsigned int msiof1_tx_mux[] = { | |
2020 | MSIOF1_TXD_MARK, | |
2021 | }; | |
2022 | static const unsigned int msiof1_clk_b_pins[] = { | |
2023 | /* SCK */ | |
2024 | RCAR_GP_PIN(5, 3), | |
2025 | }; | |
2026 | static const unsigned int msiof1_clk_b_mux[] = { | |
2027 | MSIOF1_SCK_B_MARK, | |
2028 | }; | |
2029 | static const unsigned int msiof1_sync_b_pins[] = { | |
2030 | /* SYNC */ | |
2031 | RCAR_GP_PIN(5, 4), | |
2032 | }; | |
2033 | static const unsigned int msiof1_sync_b_mux[] = { | |
2034 | MSIOF1_SYNC_B_MARK, | |
2035 | }; | |
2036 | static const unsigned int msiof1_ss1_b_pins[] = { | |
2037 | /* SS1 */ | |
2038 | RCAR_GP_PIN(5, 5), | |
2039 | }; | |
2040 | static const unsigned int msiof1_ss1_b_mux[] = { | |
2041 | MSIOF1_SS1_B_MARK, | |
2042 | }; | |
2043 | static const unsigned int msiof1_ss2_b_pins[] = { | |
2044 | /* SS2 */ | |
2045 | RCAR_GP_PIN(5, 6), | |
2046 | }; | |
2047 | static const unsigned int msiof1_ss2_b_mux[] = { | |
2048 | MSIOF1_SS2_B_MARK, | |
2049 | }; | |
2050 | static const unsigned int msiof1_rx_b_pins[] = { | |
2051 | /* RXD */ | |
2052 | RCAR_GP_PIN(5, 1), | |
2053 | }; | |
2054 | static const unsigned int msiof1_rx_b_mux[] = { | |
2055 | MSIOF1_RXD_B_MARK, | |
2056 | }; | |
2057 | static const unsigned int msiof1_tx_b_pins[] = { | |
2058 | /* TXD */ | |
2059 | RCAR_GP_PIN(5, 2), | |
2060 | }; | |
2061 | static const unsigned int msiof1_tx_b_mux[] = { | |
2062 | MSIOF1_TXD_B_MARK, | |
2063 | }; | |
2064 | /* - MSIOF2 ----------------------------------------------------------------- */ | |
2065 | static const unsigned int msiof2_clk_pins[] = { | |
2066 | /* SCK */ | |
2067 | RCAR_GP_PIN(1, 0), | |
2068 | }; | |
2069 | static const unsigned int msiof2_clk_mux[] = { | |
2070 | MSIOF2_SCK_MARK, | |
2071 | }; | |
2072 | static const unsigned int msiof2_sync_pins[] = { | |
2073 | /* SYNC */ | |
2074 | RCAR_GP_PIN(1, 1), | |
2075 | }; | |
2076 | static const unsigned int msiof2_sync_mux[] = { | |
2077 | MSIOF2_SYNC_MARK, | |
2078 | }; | |
2079 | static const unsigned int msiof2_ss1_pins[] = { | |
2080 | /* SS1 */ | |
2081 | RCAR_GP_PIN(1, 2), | |
2082 | }; | |
2083 | static const unsigned int msiof2_ss1_mux[] = { | |
2084 | MSIOF2_SS1_MARK, | |
2085 | }; | |
2086 | static const unsigned int msiof2_ss2_pins[] = { | |
2087 | /* SS2 */ | |
2088 | RCAR_GP_PIN(1, 3), | |
2089 | }; | |
2090 | static const unsigned int msiof2_ss2_mux[] = { | |
2091 | MSIOF2_SS2_MARK, | |
2092 | }; | |
2093 | static const unsigned int msiof2_rx_pins[] = { | |
2094 | /* RXD */ | |
2095 | RCAR_GP_PIN(0, 30), | |
2096 | }; | |
2097 | static const unsigned int msiof2_rx_mux[] = { | |
2098 | MSIOF2_RXD_MARK, | |
2099 | }; | |
2100 | static const unsigned int msiof2_tx_pins[] = { | |
2101 | /* TXD */ | |
2102 | RCAR_GP_PIN(0, 31), | |
2103 | }; | |
2104 | static const unsigned int msiof2_tx_mux[] = { | |
2105 | MSIOF2_TXD_MARK, | |
2106 | }; | |
2107 | static const unsigned int msiof2_clk_b_pins[] = { | |
2108 | /* SCK */ | |
2109 | RCAR_GP_PIN(3, 15), | |
2110 | }; | |
2111 | static const unsigned int msiof2_clk_b_mux[] = { | |
2112 | MSIOF2_SCK_B_MARK, | |
2113 | }; | |
2114 | static const unsigned int msiof2_sync_b_pins[] = { | |
2115 | /* SYNC */ | |
2116 | RCAR_GP_PIN(3, 16), | |
2117 | }; | |
2118 | static const unsigned int msiof2_sync_b_mux[] = { | |
2119 | MSIOF2_SYNC_B_MARK, | |
2120 | }; | |
2121 | static const unsigned int msiof2_ss1_b_pins[] = { | |
2122 | /* SS1 */ | |
2123 | RCAR_GP_PIN(3, 17), | |
2124 | }; | |
2125 | static const unsigned int msiof2_ss1_b_mux[] = { | |
2126 | MSIOF2_SS1_B_MARK, | |
2127 | }; | |
2128 | static const unsigned int msiof2_ss2_b_pins[] = { | |
2129 | /* SS2 */ | |
2130 | RCAR_GP_PIN(3, 18), | |
2131 | }; | |
2132 | static const unsigned int msiof2_ss2_b_mux[] = { | |
2133 | MSIOF2_SS2_B_MARK, | |
2134 | }; | |
2135 | static const unsigned int msiof2_rx_b_pins[] = { | |
2136 | /* RXD */ | |
2137 | RCAR_GP_PIN(3, 13), | |
2138 | }; | |
2139 | static const unsigned int msiof2_rx_b_mux[] = { | |
2140 | MSIOF2_RXD_B_MARK, | |
2141 | }; | |
2142 | static const unsigned int msiof2_tx_b_pins[] = { | |
2143 | /* TXD */ | |
2144 | RCAR_GP_PIN(3, 14), | |
2145 | }; | |
2146 | static const unsigned int msiof2_tx_b_mux[] = { | |
2147 | MSIOF2_TXD_B_MARK, | |
2148 | }; | |
2149 | /* - QSPI ------------------------------------------------------------------- */ | |
2150 | static const unsigned int qspi_ctrl_pins[] = { | |
2151 | /* SPCLK, SSL */ | |
2152 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), | |
2153 | }; | |
2154 | static const unsigned int qspi_ctrl_mux[] = { | |
2155 | SPCLK_MARK, SSL_MARK, | |
2156 | }; | |
2157 | static const unsigned int qspi_data2_pins[] = { | |
2158 | /* MOSI_IO0, MISO_IO1 */ | |
2159 | RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), | |
2160 | }; | |
2161 | static const unsigned int qspi_data2_mux[] = { | |
2162 | MOSI_IO0_MARK, MISO_IO1_MARK, | |
2163 | }; | |
2164 | static const unsigned int qspi_data4_pins[] = { | |
2165 | /* MOSI_IO0, MISO_IO1, IO2, IO3 */ | |
2166 | RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | |
2167 | RCAR_GP_PIN(1, 8), | |
2168 | }; | |
2169 | static const unsigned int qspi_data4_mux[] = { | |
2170 | MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, | |
2171 | }; | |
2172 | /* - SCIF0 ------------------------------------------------------------------ */ | |
2173 | static const unsigned int scif0_data_pins[] = { | |
2174 | /* RX, TX */ | |
2175 | RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), | |
2176 | }; | |
2177 | static const unsigned int scif0_data_mux[] = { | |
2178 | SCIF0_RXD_MARK, SCIF0_TXD_MARK, | |
2179 | }; | |
43c4436e HN |
2180 | static const unsigned int scif0_data_b_pins[] = { |
2181 | /* RX, TX */ | |
2182 | RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), | |
2183 | }; | |
2184 | static const unsigned int scif0_data_b_mux[] = { | |
2185 | SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK, | |
2186 | }; | |
43c4436e HN |
2187 | static const unsigned int scif0_data_c_pins[] = { |
2188 | /* RX, TX */ | |
2189 | RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), | |
2190 | }; | |
2191 | static const unsigned int scif0_data_c_mux[] = { | |
2192 | SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK, | |
2193 | }; | |
2194 | static const unsigned int scif0_data_d_pins[] = { | |
2195 | /* RX, TX */ | |
2196 | RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), | |
2197 | }; | |
2198 | static const unsigned int scif0_data_d_mux[] = { | |
2199 | SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK, | |
2200 | }; | |
2201 | /* - SCIF1 ------------------------------------------------------------------ */ | |
2202 | static const unsigned int scif1_data_pins[] = { | |
2203 | /* RX, TX */ | |
2204 | RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), | |
2205 | }; | |
2206 | static const unsigned int scif1_data_mux[] = { | |
2207 | SCIF1_RXD_MARK, SCIF1_TXD_MARK, | |
2208 | }; | |
2209 | static const unsigned int scif1_clk_pins[] = { | |
2210 | /* SCK */ | |
2211 | RCAR_GP_PIN(4, 13), | |
2212 | }; | |
2213 | static const unsigned int scif1_clk_mux[] = { | |
2214 | SCIF1_SCK_MARK, | |
2215 | }; | |
2216 | static const unsigned int scif1_data_b_pins[] = { | |
2217 | /* RX, TX */ | |
2218 | RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12), | |
2219 | }; | |
2220 | static const unsigned int scif1_data_b_mux[] = { | |
2221 | SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK, | |
2222 | }; | |
2223 | static const unsigned int scif1_clk_b_pins[] = { | |
2224 | /* SCK */ | |
2225 | RCAR_GP_PIN(5, 10), | |
2226 | }; | |
2227 | static const unsigned int scif1_clk_b_mux[] = { | |
2228 | SCIF1_SCK_B_MARK, | |
2229 | }; | |
2230 | static const unsigned int scif1_data_c_pins[] = { | |
2231 | /* RX, TX */ | |
2232 | RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), | |
2233 | }; | |
2234 | static const unsigned int scif1_data_c_mux[] = { | |
2235 | SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK, | |
2236 | }; | |
2237 | static const unsigned int scif1_clk_c_pins[] = { | |
2238 | /* SCK */ | |
2239 | RCAR_GP_PIN(0, 10), | |
2240 | }; | |
2241 | static const unsigned int scif1_clk_c_mux[] = { | |
2242 | SCIF1_SCK_C_MARK, | |
2243 | }; | |
2244 | /* - SCIF2 ------------------------------------------------------------------ */ | |
2245 | static const unsigned int scif2_data_pins[] = { | |
2246 | /* RX, TX */ | |
2247 | RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), | |
2248 | }; | |
2249 | static const unsigned int scif2_data_mux[] = { | |
2250 | SCIF2_RXD_MARK, SCIF2_TXD_MARK, | |
2251 | }; | |
2252 | static const unsigned int scif2_clk_pins[] = { | |
2253 | /* SCK */ | |
2254 | RCAR_GP_PIN(4, 18), | |
2255 | }; | |
2256 | static const unsigned int scif2_clk_mux[] = { | |
2257 | SCIF2_SCK_MARK, | |
2258 | }; | |
2259 | static const unsigned int scif2_data_b_pins[] = { | |
2260 | /* RX, TX */ | |
2261 | RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), | |
2262 | }; | |
2263 | static const unsigned int scif2_data_b_mux[] = { | |
2264 | SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK, | |
2265 | }; | |
2266 | static const unsigned int scif2_clk_b_pins[] = { | |
2267 | /* SCK */ | |
2268 | RCAR_GP_PIN(5, 17), | |
2269 | }; | |
2270 | static const unsigned int scif2_clk_b_mux[] = { | |
2271 | SCIF2_SCK_B_MARK, | |
2272 | }; | |
2273 | static const unsigned int scif2_data_c_pins[] = { | |
2274 | /* RX, TX */ | |
2275 | RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), | |
2276 | }; | |
2277 | static const unsigned int scif2_data_c_mux[] = { | |
2278 | SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK, | |
2279 | }; | |
2280 | static const unsigned int scif2_clk_c_pins[] = { | |
2281 | /* SCK */ | |
2282 | RCAR_GP_PIN(3, 19), | |
2283 | }; | |
2284 | static const unsigned int scif2_clk_c_mux[] = { | |
2285 | SCIF2_SCK_C_MARK, | |
2286 | }; | |
2287 | /* - SCIF3 ------------------------------------------------------------------ */ | |
2288 | static const unsigned int scif3_data_pins[] = { | |
2289 | /* RX, TX */ | |
2290 | RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), | |
2291 | }; | |
2292 | static const unsigned int scif3_data_mux[] = { | |
2293 | SCIF3_RXD_MARK, SCIF3_TXD_MARK, | |
2294 | }; | |
2295 | static const unsigned int scif3_clk_pins[] = { | |
2296 | /* SCK */ | |
2297 | RCAR_GP_PIN(4, 19), | |
2298 | }; | |
2299 | static const unsigned int scif3_clk_mux[] = { | |
2300 | SCIF3_SCK_MARK, | |
2301 | }; | |
2302 | static const unsigned int scif3_data_b_pins[] = { | |
2303 | /* RX, TX */ | |
2304 | RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), | |
2305 | }; | |
2306 | static const unsigned int scif3_data_b_mux[] = { | |
2307 | SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK, | |
2308 | }; | |
2309 | static const unsigned int scif3_clk_b_pins[] = { | |
2310 | /* SCK */ | |
2311 | RCAR_GP_PIN(3, 22), | |
2312 | }; | |
2313 | static const unsigned int scif3_clk_b_mux[] = { | |
2314 | SCIF3_SCK_B_MARK, | |
2315 | }; | |
2316 | /* - SCIF4 ------------------------------------------------------------------ */ | |
2317 | static const unsigned int scif4_data_pins[] = { | |
2318 | /* RX, TX */ | |
2319 | RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), | |
2320 | }; | |
2321 | static const unsigned int scif4_data_mux[] = { | |
2322 | SCIF4_RXD_MARK, SCIF4_TXD_MARK, | |
2323 | }; | |
2324 | static const unsigned int scif4_data_b_pins[] = { | |
2325 | /* RX, TX */ | |
2326 | RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), | |
2327 | }; | |
2328 | static const unsigned int scif4_data_b_mux[] = { | |
2329 | SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK, | |
2330 | }; | |
2331 | static const unsigned int scif4_data_c_pins[] = { | |
2332 | /* RX, TX */ | |
2333 | RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), | |
2334 | }; | |
2335 | static const unsigned int scif4_data_c_mux[] = { | |
2336 | SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK, | |
2337 | }; | |
2338 | static const unsigned int scif4_data_d_pins[] = { | |
2339 | /* RX, TX */ | |
2340 | RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), | |
2341 | }; | |
2342 | static const unsigned int scif4_data_d_mux[] = { | |
2343 | SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK, | |
2344 | }; | |
2345 | static const unsigned int scif4_data_e_pins[] = { | |
2346 | /* RX, TX */ | |
2347 | RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), | |
2348 | }; | |
2349 | static const unsigned int scif4_data_e_mux[] = { | |
2350 | SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK, | |
2351 | }; | |
2352 | /* - SCIF5 ------------------------------------------------------------------ */ | |
2353 | static const unsigned int scif5_data_pins[] = { | |
2354 | /* RX, TX */ | |
2355 | RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), | |
2356 | }; | |
2357 | static const unsigned int scif5_data_mux[] = { | |
2358 | SCIF5_RXD_MARK, SCIF5_TXD_MARK, | |
2359 | }; | |
2360 | static const unsigned int scif5_data_b_pins[] = { | |
2361 | /* RX, TX */ | |
2362 | RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), | |
2363 | }; | |
2364 | static const unsigned int scif5_data_b_mux[] = { | |
2365 | SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK, | |
2366 | }; | |
2367 | static const unsigned int scif5_data_c_pins[] = { | |
2368 | /* RX, TX */ | |
2369 | RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11), | |
2370 | }; | |
2371 | static const unsigned int scif5_data_c_mux[] = { | |
2372 | SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK, | |
2373 | }; | |
2374 | static const unsigned int scif5_data_d_pins[] = { | |
2375 | /* RX, TX */ | |
2376 | RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), | |
2377 | }; | |
2378 | static const unsigned int scif5_data_d_mux[] = { | |
2379 | SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK, | |
2380 | }; | |
2381 | /* - SCIFA0 ----------------------------------------------------------------- */ | |
2382 | static const unsigned int scifa0_data_pins[] = { | |
2383 | /* RXD, TXD */ | |
2384 | RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), | |
2385 | }; | |
2386 | static const unsigned int scifa0_data_mux[] = { | |
2387 | SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, | |
2388 | }; | |
2389 | static const unsigned int scifa0_data_b_pins[] = { | |
2390 | /* RXD, TXD */ | |
2391 | RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), | |
2392 | }; | |
2393 | static const unsigned int scifa0_data_b_mux[] = { | |
2394 | SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK | |
2395 | }; | |
2396 | static const unsigned int scifa0_data_c_pins[] = { | |
2397 | /* RXD, TXD */ | |
2398 | RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), | |
2399 | }; | |
2400 | static const unsigned int scifa0_data_c_mux[] = { | |
2401 | SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK | |
2402 | }; | |
2403 | static const unsigned int scifa0_data_d_pins[] = { | |
2404 | /* RXD, TXD */ | |
2405 | RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), | |
2406 | }; | |
2407 | static const unsigned int scifa0_data_d_mux[] = { | |
2408 | SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK | |
2409 | }; | |
2410 | /* - SCIFA1 ----------------------------------------------------------------- */ | |
2411 | static const unsigned int scifa1_data_pins[] = { | |
2412 | /* RXD, TXD */ | |
2413 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | |
2414 | }; | |
2415 | static const unsigned int scifa1_data_mux[] = { | |
2416 | SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, | |
2417 | }; | |
2418 | static const unsigned int scifa1_clk_pins[] = { | |
2419 | /* SCK */ | |
2420 | RCAR_GP_PIN(0, 13), | |
2421 | }; | |
2422 | static const unsigned int scifa1_clk_mux[] = { | |
2423 | SCIFA1_SCK_MARK, | |
2424 | }; | |
2425 | static const unsigned int scifa1_data_b_pins[] = { | |
2426 | /* RXD, TXD */ | |
2427 | RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), | |
2428 | }; | |
2429 | static const unsigned int scifa1_data_b_mux[] = { | |
2430 | SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, | |
2431 | }; | |
2432 | static const unsigned int scifa1_clk_b_pins[] = { | |
2433 | /* SCK */ | |
2434 | RCAR_GP_PIN(4, 27), | |
2435 | }; | |
2436 | static const unsigned int scifa1_clk_b_mux[] = { | |
2437 | SCIFA1_SCK_B_MARK, | |
2438 | }; | |
2439 | static const unsigned int scifa1_data_c_pins[] = { | |
2440 | /* RXD, TXD */ | |
2441 | RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), | |
2442 | }; | |
2443 | static const unsigned int scifa1_data_c_mux[] = { | |
2444 | SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, | |
2445 | }; | |
2446 | static const unsigned int scifa1_clk_c_pins[] = { | |
2447 | /* SCK */ | |
2448 | RCAR_GP_PIN(5, 4), | |
2449 | }; | |
2450 | static const unsigned int scifa1_clk_c_mux[] = { | |
2451 | SCIFA1_SCK_C_MARK, | |
2452 | }; | |
2453 | /* - SCIFA2 ----------------------------------------------------------------- */ | |
2454 | static const unsigned int scifa2_data_pins[] = { | |
2455 | /* RXD, TXD */ | |
2456 | RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), | |
2457 | }; | |
2458 | static const unsigned int scifa2_data_mux[] = { | |
2459 | SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, | |
2460 | }; | |
2461 | static const unsigned int scifa2_clk_pins[] = { | |
2462 | /* SCK */ | |
2463 | RCAR_GP_PIN(1, 15), | |
2464 | }; | |
2465 | static const unsigned int scifa2_clk_mux[] = { | |
2466 | SCIFA2_SCK_MARK, | |
2467 | }; | |
2468 | static const unsigned int scifa2_data_b_pins[] = { | |
2469 | /* RXD, TXD */ | |
2470 | RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0), | |
2471 | }; | |
2472 | static const unsigned int scifa2_data_b_mux[] = { | |
2473 | SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, | |
2474 | }; | |
2475 | static const unsigned int scifa2_clk_b_pins[] = { | |
2476 | /* SCK */ | |
2477 | RCAR_GP_PIN(4, 30), | |
2478 | }; | |
2479 | static const unsigned int scifa2_clk_b_mux[] = { | |
2480 | SCIFA2_SCK_B_MARK, | |
2481 | }; | |
2482 | /* - SCIFA3 ----------------------------------------------------------------- */ | |
2483 | static const unsigned int scifa3_data_pins[] = { | |
2484 | /* RXD, TXD */ | |
2485 | RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), | |
2486 | }; | |
2487 | static const unsigned int scifa3_data_mux[] = { | |
2488 | SCIFA3_RXD_MARK, SCIFA3_TXD_MARK, | |
2489 | }; | |
2490 | static const unsigned int scifa3_clk_pins[] = { | |
2491 | /* SCK */ | |
2492 | RCAR_GP_PIN(4, 24), | |
2493 | }; | |
2494 | static const unsigned int scifa3_clk_mux[] = { | |
2495 | SCIFA3_SCK_MARK, | |
2496 | }; | |
2497 | static const unsigned int scifa3_data_b_pins[] = { | |
2498 | /* RXD, TXD */ | |
2499 | RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), | |
2500 | }; | |
2501 | static const unsigned int scifa3_data_b_mux[] = { | |
2502 | SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK, | |
2503 | }; | |
2504 | static const unsigned int scifa3_clk_b_pins[] = { | |
2505 | /* SCK */ | |
2506 | RCAR_GP_PIN(0, 0), | |
2507 | }; | |
2508 | static const unsigned int scifa3_clk_b_mux[] = { | |
2509 | SCIFA3_SCK_B_MARK, | |
2510 | }; | |
2511 | /* - SCIFA4 ----------------------------------------------------------------- */ | |
2512 | static const unsigned int scifa4_data_pins[] = { | |
2513 | /* RXD, TXD */ | |
2514 | RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12), | |
2515 | }; | |
2516 | static const unsigned int scifa4_data_mux[] = { | |
2517 | SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, | |
2518 | }; | |
2519 | static const unsigned int scifa4_data_b_pins[] = { | |
2520 | /* RXD, TXD */ | |
2521 | RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23), | |
2522 | }; | |
2523 | static const unsigned int scifa4_data_b_mux[] = { | |
2524 | SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK, | |
2525 | }; | |
2526 | static const unsigned int scifa4_data_c_pins[] = { | |
2527 | /* RXD, TXD */ | |
2528 | RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), | |
2529 | }; | |
2530 | static const unsigned int scifa4_data_c_mux[] = { | |
2531 | SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK, | |
2532 | }; | |
2533 | static const unsigned int scifa4_data_d_pins[] = { | |
2534 | /* RXD, TXD */ | |
2535 | RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), | |
2536 | }; | |
2537 | static const unsigned int scifa4_data_d_mux[] = { | |
2538 | SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK, | |
2539 | }; | |
2540 | /* - SCIFA5 ----------------------------------------------------------------- */ | |
2541 | static const unsigned int scifa5_data_pins[] = { | |
2542 | /* RXD, TXD */ | |
2543 | RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), | |
2544 | }; | |
2545 | static const unsigned int scifa5_data_mux[] = { | |
2546 | SCIFA5_RXD_MARK, SCIFA5_TXD_MARK, | |
2547 | }; | |
2548 | static const unsigned int scifa5_data_b_pins[] = { | |
2549 | /* RXD, TXD */ | |
2550 | RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29), | |
2551 | }; | |
2552 | static const unsigned int scifa5_data_b_mux[] = { | |
2553 | SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK, | |
2554 | }; | |
2555 | static const unsigned int scifa5_data_c_pins[] = { | |
2556 | /* RXD, TXD */ | |
2557 | RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), | |
2558 | }; | |
2559 | static const unsigned int scifa5_data_c_mux[] = { | |
2560 | SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK, | |
2561 | }; | |
2562 | static const unsigned int scifa5_data_d_pins[] = { | |
2563 | /* RXD, TXD */ | |
2564 | RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), | |
2565 | }; | |
2566 | static const unsigned int scifa5_data_d_mux[] = { | |
2567 | SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK, | |
2568 | }; | |
2569 | /* - SCIFB0 ----------------------------------------------------------------- */ | |
2570 | static const unsigned int scifb0_data_pins[] = { | |
2571 | /* RXD, TXD */ | |
2572 | RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20), | |
2573 | }; | |
2574 | static const unsigned int scifb0_data_mux[] = { | |
2575 | SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, | |
2576 | }; | |
2577 | static const unsigned int scifb0_clk_pins[] = { | |
2578 | /* SCK */ | |
2579 | RCAR_GP_PIN(0, 19), | |
2580 | }; | |
2581 | static const unsigned int scifb0_clk_mux[] = { | |
2582 | SCIFB0_SCK_MARK, | |
2583 | }; | |
2584 | static const unsigned int scifb0_ctrl_pins[] = { | |
2585 | /* RTS, CTS */ | |
2586 | RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), | |
2587 | }; | |
2588 | static const unsigned int scifb0_ctrl_mux[] = { | |
2589 | SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, | |
2590 | }; | |
2591 | /* - SCIFB1 ----------------------------------------------------------------- */ | |
2592 | static const unsigned int scifb1_data_pins[] = { | |
2593 | /* RXD, TXD */ | |
2594 | RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17), | |
2595 | }; | |
2596 | static const unsigned int scifb1_data_mux[] = { | |
2597 | SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, | |
2598 | }; | |
2599 | static const unsigned int scifb1_clk_pins[] = { | |
2600 | /* SCK */ | |
2601 | RCAR_GP_PIN(0, 16), | |
2602 | }; | |
2603 | static const unsigned int scifb1_clk_mux[] = { | |
2604 | SCIFB1_SCK_MARK, | |
2605 | }; | |
2606 | /* - SCIFB2 ----------------------------------------------------------------- */ | |
2607 | static const unsigned int scifb2_data_pins[] = { | |
2608 | /* RXD, TXD */ | |
2609 | RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), | |
2610 | }; | |
2611 | static const unsigned int scifb2_data_mux[] = { | |
2612 | SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, | |
2613 | }; | |
2614 | static const unsigned int scifb2_clk_pins[] = { | |
2615 | /* SCK */ | |
2616 | RCAR_GP_PIN(1, 15), | |
2617 | }; | |
2618 | static const unsigned int scifb2_clk_mux[] = { | |
2619 | SCIFB2_SCK_MARK, | |
2620 | }; | |
2621 | static const unsigned int scifb2_ctrl_pins[] = { | |
2622 | /* RTS, CTS */ | |
2623 | RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), | |
2624 | }; | |
2625 | static const unsigned int scifb2_ctrl_mux[] = { | |
2626 | SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, | |
2627 | }; | |
ed66700c GU |
2628 | /* - SCIF Clock ------------------------------------------------------------- */ |
2629 | static const unsigned int scif_clk_pins[] = { | |
2630 | /* SCIF_CLK */ | |
2631 | RCAR_GP_PIN(1, 23), | |
2632 | }; | |
2633 | static const unsigned int scif_clk_mux[] = { | |
2634 | SCIF_CLK_MARK, | |
2635 | }; | |
2636 | static const unsigned int scif_clk_b_pins[] = { | |
2637 | /* SCIF_CLK */ | |
2638 | RCAR_GP_PIN(3, 29), | |
2639 | }; | |
2640 | static const unsigned int scif_clk_b_mux[] = { | |
2641 | SCIF_CLK_B_MARK, | |
2642 | }; | |
7ac91bda SU |
2643 | /* - SDHI0 ------------------------------------------------------------------ */ |
2644 | static const unsigned int sdhi0_data1_pins[] = { | |
2645 | /* D0 */ | |
2646 | RCAR_GP_PIN(6, 2), | |
2647 | }; | |
2648 | static const unsigned int sdhi0_data1_mux[] = { | |
2649 | SD0_DATA0_MARK, | |
2650 | }; | |
2651 | static const unsigned int sdhi0_data4_pins[] = { | |
2652 | /* D[0:3] */ | |
2653 | RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), | |
2654 | RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), | |
2655 | }; | |
2656 | static const unsigned int sdhi0_data4_mux[] = { | |
2657 | SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK, | |
2658 | }; | |
2659 | static const unsigned int sdhi0_ctrl_pins[] = { | |
2660 | /* CLK, CMD */ | |
2661 | RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), | |
2662 | }; | |
2663 | static const unsigned int sdhi0_ctrl_mux[] = { | |
2664 | SD0_CLK_MARK, SD0_CMD_MARK, | |
2665 | }; | |
2666 | static const unsigned int sdhi0_cd_pins[] = { | |
2667 | /* CD */ | |
2668 | RCAR_GP_PIN(6, 6), | |
2669 | }; | |
2670 | static const unsigned int sdhi0_cd_mux[] = { | |
2671 | SD0_CD_MARK, | |
2672 | }; | |
2673 | static const unsigned int sdhi0_wp_pins[] = { | |
2674 | /* WP */ | |
2675 | RCAR_GP_PIN(6, 7), | |
2676 | }; | |
2677 | static const unsigned int sdhi0_wp_mux[] = { | |
2678 | SD0_WP_MARK, | |
2679 | }; | |
2680 | /* - SDHI1 ------------------------------------------------------------------ */ | |
2681 | static const unsigned int sdhi1_data1_pins[] = { | |
2682 | /* D0 */ | |
2683 | RCAR_GP_PIN(6, 10), | |
2684 | }; | |
2685 | static const unsigned int sdhi1_data1_mux[] = { | |
2686 | SD1_DATA0_MARK, | |
2687 | }; | |
2688 | static const unsigned int sdhi1_data4_pins[] = { | |
2689 | /* D[0:3] */ | |
2690 | RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), | |
2691 | RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), | |
2692 | }; | |
2693 | static const unsigned int sdhi1_data4_mux[] = { | |
2694 | SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK, | |
2695 | }; | |
2696 | static const unsigned int sdhi1_ctrl_pins[] = { | |
2697 | /* CLK, CMD */ | |
2698 | RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), | |
2699 | }; | |
2700 | static const unsigned int sdhi1_ctrl_mux[] = { | |
2701 | SD1_CLK_MARK, SD1_CMD_MARK, | |
2702 | }; | |
2703 | static const unsigned int sdhi1_cd_pins[] = { | |
2704 | /* CD */ | |
2705 | RCAR_GP_PIN(6, 14), | |
2706 | }; | |
2707 | static const unsigned int sdhi1_cd_mux[] = { | |
2708 | SD1_CD_MARK, | |
2709 | }; | |
2710 | static const unsigned int sdhi1_wp_pins[] = { | |
2711 | /* WP */ | |
2712 | RCAR_GP_PIN(6, 15), | |
2713 | }; | |
2714 | static const unsigned int sdhi1_wp_mux[] = { | |
2715 | SD1_WP_MARK, | |
2716 | }; | |
2717 | /* - SDHI2 ------------------------------------------------------------------ */ | |
2718 | static const unsigned int sdhi2_data1_pins[] = { | |
2719 | /* D0 */ | |
2720 | RCAR_GP_PIN(6, 18), | |
2721 | }; | |
2722 | static const unsigned int sdhi2_data1_mux[] = { | |
2723 | SD2_DATA0_MARK, | |
2724 | }; | |
2725 | static const unsigned int sdhi2_data4_pins[] = { | |
2726 | /* D[0:3] */ | |
2727 | RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), | |
2728 | RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), | |
2729 | }; | |
2730 | static const unsigned int sdhi2_data4_mux[] = { | |
2731 | SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK, | |
2732 | }; | |
2733 | static const unsigned int sdhi2_ctrl_pins[] = { | |
2734 | /* CLK, CMD */ | |
2735 | RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), | |
2736 | }; | |
2737 | static const unsigned int sdhi2_ctrl_mux[] = { | |
2738 | SD2_CLK_MARK, SD2_CMD_MARK, | |
2739 | }; | |
2740 | static const unsigned int sdhi2_cd_pins[] = { | |
2741 | /* CD */ | |
2742 | RCAR_GP_PIN(6, 22), | |
2743 | }; | |
2744 | static const unsigned int sdhi2_cd_mux[] = { | |
2745 | SD2_CD_MARK, | |
2746 | }; | |
2747 | static const unsigned int sdhi2_wp_pins[] = { | |
2748 | /* WP */ | |
2749 | RCAR_GP_PIN(6, 23), | |
2750 | }; | |
2751 | static const unsigned int sdhi2_wp_mux[] = { | |
2752 | SD2_WP_MARK, | |
2753 | }; | |
580a7ee9 SU |
2754 | /* - USB0 ------------------------------------------------------------------- */ |
2755 | static const unsigned int usb0_pins[] = { | |
2756 | RCAR_GP_PIN(5, 24), /* PWEN */ | |
2757 | RCAR_GP_PIN(5, 25), /* OVC */ | |
2758 | }; | |
2759 | static const unsigned int usb0_mux[] = { | |
2760 | USB0_PWEN_MARK, | |
2761 | USB0_OVC_MARK, | |
2762 | }; | |
2763 | /* - USB1 ------------------------------------------------------------------- */ | |
2764 | static const unsigned int usb1_pins[] = { | |
2765 | RCAR_GP_PIN(5, 26), /* PWEN */ | |
2766 | RCAR_GP_PIN(5, 27), /* OVC */ | |
2767 | }; | |
2768 | static const unsigned int usb1_mux[] = { | |
2769 | USB1_PWEN_MARK, | |
2770 | USB1_OVC_MARK, | |
2771 | }; | |
0f7711aa KM |
2772 | /* - VIN0 ------------------------------------------------------------------- */ |
2773 | static const union vin_data vin0_data_pins = { | |
2774 | .data24 = { | |
2775 | /* B */ | |
2776 | RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), | |
2777 | RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), | |
2778 | RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), | |
2779 | RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), | |
2780 | /* G */ | |
2781 | RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), | |
2782 | RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), | |
2783 | RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), | |
2784 | RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), | |
2785 | /* R */ | |
2786 | RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), | |
2787 | RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), | |
2788 | RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), | |
2789 | RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), | |
2790 | }, | |
2791 | }; | |
2792 | static const union vin_data vin0_data_mux = { | |
2793 | .data24 = { | |
2794 | /* B */ | |
2795 | VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, | |
2796 | VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, | |
2797 | VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, | |
2798 | VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, | |
2799 | /* G */ | |
2800 | VI0_G0_MARK, VI0_G1_MARK, | |
2801 | VI0_G2_MARK, VI0_G3_MARK, | |
2802 | VI0_G4_MARK, VI0_G5_MARK, | |
2803 | VI0_G6_MARK, VI0_G7_MARK, | |
2804 | /* R */ | |
2805 | VI0_R0_MARK, VI0_R1_MARK, | |
2806 | VI0_R2_MARK, VI0_R3_MARK, | |
2807 | VI0_R4_MARK, VI0_R5_MARK, | |
2808 | VI0_R6_MARK, VI0_R7_MARK, | |
2809 | }, | |
2810 | }; | |
2811 | static const unsigned int vin0_data18_pins[] = { | |
2812 | /* B */ | |
2813 | RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), | |
2814 | RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), | |
2815 | RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), | |
2816 | /* G */ | |
2817 | RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), | |
2818 | RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), | |
2819 | RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), | |
2820 | /* R */ | |
2821 | RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), | |
2822 | RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), | |
2823 | RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), | |
2824 | }; | |
2825 | static const unsigned int vin0_data18_mux[] = { | |
2826 | /* B */ | |
2827 | VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, | |
2828 | VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, | |
2829 | VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, | |
2830 | /* G */ | |
2831 | VI0_G2_MARK, VI0_G3_MARK, | |
2832 | VI0_G4_MARK, VI0_G5_MARK, | |
2833 | VI0_G6_MARK, VI0_G7_MARK, | |
2834 | /* R */ | |
2835 | VI0_R2_MARK, VI0_R3_MARK, | |
2836 | VI0_R4_MARK, VI0_R5_MARK, | |
2837 | VI0_R6_MARK, VI0_R7_MARK, | |
2838 | }; | |
2839 | static const unsigned int vin0_sync_pins[] = { | |
2840 | RCAR_GP_PIN(3, 11), /* HSYNC */ | |
2841 | RCAR_GP_PIN(3, 12), /* VSYNC */ | |
2842 | }; | |
2843 | static const unsigned int vin0_sync_mux[] = { | |
2844 | VI0_HSYNC_N_MARK, | |
2845 | VI0_VSYNC_N_MARK, | |
2846 | }; | |
2847 | static const unsigned int vin0_field_pins[] = { | |
2848 | RCAR_GP_PIN(3, 10), | |
2849 | }; | |
2850 | static const unsigned int vin0_field_mux[] = { | |
2851 | VI0_FIELD_MARK, | |
2852 | }; | |
2853 | static const unsigned int vin0_clkenb_pins[] = { | |
2854 | RCAR_GP_PIN(3, 9), | |
2855 | }; | |
2856 | static const unsigned int vin0_clkenb_mux[] = { | |
2857 | VI0_CLKENB_MARK, | |
2858 | }; | |
2859 | static const unsigned int vin0_clk_pins[] = { | |
2860 | RCAR_GP_PIN(3, 0), | |
2861 | }; | |
2862 | static const unsigned int vin0_clk_mux[] = { | |
2863 | VI0_CLK_MARK, | |
2864 | }; | |
2865 | /* - VIN1 ------------------------------------------------------------------- */ | |
2866 | static const union vin_data vin1_data_pins = { | |
2867 | .data12 = { | |
2868 | RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), | |
2869 | RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), | |
2870 | RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), | |
2871 | RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), | |
2872 | RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), | |
2873 | RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), | |
2874 | }, | |
2875 | }; | |
2876 | static const union vin_data vin1_data_mux = { | |
2877 | .data12 = { | |
2878 | VI1_DATA0_MARK, VI1_DATA1_MARK, | |
2879 | VI1_DATA2_MARK, VI1_DATA3_MARK, | |
2880 | VI1_DATA4_MARK, VI1_DATA5_MARK, | |
2881 | VI1_DATA6_MARK, VI1_DATA7_MARK, | |
2882 | VI1_DATA8_MARK, VI1_DATA9_MARK, | |
2883 | VI1_DATA10_MARK, VI1_DATA11_MARK, | |
2884 | }, | |
2885 | }; | |
2886 | static const unsigned int vin1_sync_pins[] = { | |
2887 | RCAR_GP_PIN(5, 22), /* HSYNC */ | |
2888 | RCAR_GP_PIN(5, 23), /* VSYNC */ | |
2889 | }; | |
2890 | static const unsigned int vin1_sync_mux[] = { | |
2891 | VI1_HSYNC_N_MARK, | |
2892 | VI1_VSYNC_N_MARK, | |
2893 | }; | |
2894 | static const unsigned int vin1_field_pins[] = { | |
2895 | RCAR_GP_PIN(5, 21), | |
2896 | }; | |
2897 | static const unsigned int vin1_field_mux[] = { | |
2898 | VI1_FIELD_MARK, | |
2899 | }; | |
2900 | static const unsigned int vin1_clkenb_pins[] = { | |
2901 | RCAR_GP_PIN(5, 20), | |
2902 | }; | |
2903 | static const unsigned int vin1_clkenb_mux[] = { | |
2904 | VI1_CLKENB_MARK, | |
2905 | }; | |
2906 | static const unsigned int vin1_clk_pins[] = { | |
2907 | RCAR_GP_PIN(5, 11), | |
2908 | }; | |
2909 | static const unsigned int vin1_clk_mux[] = { | |
2910 | VI1_CLK_MARK, | |
2911 | }; | |
43c4436e HN |
2912 | |
2913 | static const struct sh_pfc_pin_group pinmux_groups[] = { | |
2914 | SH_PFC_PIN_GROUP(eth_link), | |
2915 | SH_PFC_PIN_GROUP(eth_magic), | |
2916 | SH_PFC_PIN_GROUP(eth_mdio), | |
2917 | SH_PFC_PIN_GROUP(eth_rmii), | |
2918 | SH_PFC_PIN_GROUP(eth_link_b), | |
2919 | SH_PFC_PIN_GROUP(eth_magic_b), | |
2920 | SH_PFC_PIN_GROUP(eth_mdio_b), | |
2921 | SH_PFC_PIN_GROUP(eth_rmii_b), | |
2922 | SH_PFC_PIN_GROUP(hscif0_data), | |
2923 | SH_PFC_PIN_GROUP(hscif0_clk), | |
2924 | SH_PFC_PIN_GROUP(hscif0_ctrl), | |
2925 | SH_PFC_PIN_GROUP(hscif0_data_b), | |
2926 | SH_PFC_PIN_GROUP(hscif0_clk_b), | |
2927 | SH_PFC_PIN_GROUP(hscif1_data), | |
2928 | SH_PFC_PIN_GROUP(hscif1_clk), | |
2929 | SH_PFC_PIN_GROUP(hscif1_ctrl), | |
2930 | SH_PFC_PIN_GROUP(hscif1_data_b), | |
2931 | SH_PFC_PIN_GROUP(hscif1_ctrl_b), | |
2932 | SH_PFC_PIN_GROUP(hscif2_data), | |
2933 | SH_PFC_PIN_GROUP(hscif2_clk), | |
2934 | SH_PFC_PIN_GROUP(hscif2_ctrl), | |
2935 | SH_PFC_PIN_GROUP(i2c0), | |
2936 | SH_PFC_PIN_GROUP(i2c0_b), | |
2937 | SH_PFC_PIN_GROUP(i2c0_c), | |
2938 | SH_PFC_PIN_GROUP(i2c0_d), | |
2939 | SH_PFC_PIN_GROUP(i2c0_e), | |
2940 | SH_PFC_PIN_GROUP(i2c1), | |
2941 | SH_PFC_PIN_GROUP(i2c1_b), | |
2942 | SH_PFC_PIN_GROUP(i2c1_c), | |
2943 | SH_PFC_PIN_GROUP(i2c1_d), | |
2944 | SH_PFC_PIN_GROUP(i2c1_e), | |
2945 | SH_PFC_PIN_GROUP(i2c2), | |
2946 | SH_PFC_PIN_GROUP(i2c2_b), | |
2947 | SH_PFC_PIN_GROUP(i2c2_c), | |
2948 | SH_PFC_PIN_GROUP(i2c2_d), | |
2949 | SH_PFC_PIN_GROUP(i2c2_e), | |
2950 | SH_PFC_PIN_GROUP(i2c3), | |
2951 | SH_PFC_PIN_GROUP(i2c3_b), | |
2952 | SH_PFC_PIN_GROUP(i2c3_c), | |
2953 | SH_PFC_PIN_GROUP(i2c3_d), | |
2954 | SH_PFC_PIN_GROUP(i2c3_e), | |
2955 | SH_PFC_PIN_GROUP(i2c4), | |
2956 | SH_PFC_PIN_GROUP(i2c4_b), | |
2957 | SH_PFC_PIN_GROUP(i2c4_c), | |
2958 | SH_PFC_PIN_GROUP(i2c4_d), | |
2959 | SH_PFC_PIN_GROUP(i2c4_e), | |
2960 | SH_PFC_PIN_GROUP(intc_irq0), | |
2961 | SH_PFC_PIN_GROUP(intc_irq1), | |
2962 | SH_PFC_PIN_GROUP(intc_irq2), | |
2963 | SH_PFC_PIN_GROUP(intc_irq3), | |
2964 | SH_PFC_PIN_GROUP(intc_irq4), | |
2965 | SH_PFC_PIN_GROUP(intc_irq5), | |
2966 | SH_PFC_PIN_GROUP(intc_irq6), | |
2967 | SH_PFC_PIN_GROUP(intc_irq7), | |
2968 | SH_PFC_PIN_GROUP(intc_irq8), | |
2969 | SH_PFC_PIN_GROUP(intc_irq9), | |
f1f74b64 SU |
2970 | SH_PFC_PIN_GROUP(mmc_data1), |
2971 | SH_PFC_PIN_GROUP(mmc_data4), | |
2972 | SH_PFC_PIN_GROUP(mmc_data8), | |
2973 | SH_PFC_PIN_GROUP(mmc_ctrl), | |
43c4436e HN |
2974 | SH_PFC_PIN_GROUP(msiof0_clk), |
2975 | SH_PFC_PIN_GROUP(msiof0_sync), | |
2976 | SH_PFC_PIN_GROUP(msiof0_ss1), | |
2977 | SH_PFC_PIN_GROUP(msiof0_ss2), | |
2978 | SH_PFC_PIN_GROUP(msiof0_rx), | |
2979 | SH_PFC_PIN_GROUP(msiof0_tx), | |
2980 | SH_PFC_PIN_GROUP(msiof1_clk), | |
2981 | SH_PFC_PIN_GROUP(msiof1_sync), | |
2982 | SH_PFC_PIN_GROUP(msiof1_ss1), | |
2983 | SH_PFC_PIN_GROUP(msiof1_ss2), | |
2984 | SH_PFC_PIN_GROUP(msiof1_rx), | |
2985 | SH_PFC_PIN_GROUP(msiof1_tx), | |
2986 | SH_PFC_PIN_GROUP(msiof1_clk_b), | |
2987 | SH_PFC_PIN_GROUP(msiof1_sync_b), | |
2988 | SH_PFC_PIN_GROUP(msiof1_ss1_b), | |
2989 | SH_PFC_PIN_GROUP(msiof1_ss2_b), | |
2990 | SH_PFC_PIN_GROUP(msiof1_rx_b), | |
2991 | SH_PFC_PIN_GROUP(msiof1_tx_b), | |
2992 | SH_PFC_PIN_GROUP(msiof2_clk), | |
2993 | SH_PFC_PIN_GROUP(msiof2_sync), | |
2994 | SH_PFC_PIN_GROUP(msiof2_ss1), | |
2995 | SH_PFC_PIN_GROUP(msiof2_ss2), | |
2996 | SH_PFC_PIN_GROUP(msiof2_rx), | |
2997 | SH_PFC_PIN_GROUP(msiof2_tx), | |
2998 | SH_PFC_PIN_GROUP(msiof2_clk_b), | |
2999 | SH_PFC_PIN_GROUP(msiof2_sync_b), | |
3000 | SH_PFC_PIN_GROUP(msiof2_ss1_b), | |
3001 | SH_PFC_PIN_GROUP(msiof2_ss2_b), | |
3002 | SH_PFC_PIN_GROUP(msiof2_rx_b), | |
3003 | SH_PFC_PIN_GROUP(msiof2_tx_b), | |
3004 | SH_PFC_PIN_GROUP(qspi_ctrl), | |
3005 | SH_PFC_PIN_GROUP(qspi_data2), | |
3006 | SH_PFC_PIN_GROUP(qspi_data4), | |
3007 | SH_PFC_PIN_GROUP(scif0_data), | |
43c4436e | 3008 | SH_PFC_PIN_GROUP(scif0_data_b), |
43c4436e HN |
3009 | SH_PFC_PIN_GROUP(scif0_data_c), |
3010 | SH_PFC_PIN_GROUP(scif0_data_d), | |
3011 | SH_PFC_PIN_GROUP(scif1_data), | |
3012 | SH_PFC_PIN_GROUP(scif1_clk), | |
3013 | SH_PFC_PIN_GROUP(scif1_data_b), | |
3014 | SH_PFC_PIN_GROUP(scif1_clk_b), | |
3015 | SH_PFC_PIN_GROUP(scif1_data_c), | |
3016 | SH_PFC_PIN_GROUP(scif1_clk_c), | |
3017 | SH_PFC_PIN_GROUP(scif2_data), | |
3018 | SH_PFC_PIN_GROUP(scif2_clk), | |
3019 | SH_PFC_PIN_GROUP(scif2_data_b), | |
3020 | SH_PFC_PIN_GROUP(scif2_clk_b), | |
3021 | SH_PFC_PIN_GROUP(scif2_data_c), | |
3022 | SH_PFC_PIN_GROUP(scif2_clk_c), | |
3023 | SH_PFC_PIN_GROUP(scif3_data), | |
3024 | SH_PFC_PIN_GROUP(scif3_clk), | |
3025 | SH_PFC_PIN_GROUP(scif3_data_b), | |
3026 | SH_PFC_PIN_GROUP(scif3_clk_b), | |
3027 | SH_PFC_PIN_GROUP(scif4_data), | |
3028 | SH_PFC_PIN_GROUP(scif4_data_b), | |
3029 | SH_PFC_PIN_GROUP(scif4_data_c), | |
3030 | SH_PFC_PIN_GROUP(scif4_data_d), | |
3031 | SH_PFC_PIN_GROUP(scif4_data_e), | |
3032 | SH_PFC_PIN_GROUP(scif5_data), | |
3033 | SH_PFC_PIN_GROUP(scif5_data_b), | |
3034 | SH_PFC_PIN_GROUP(scif5_data_c), | |
3035 | SH_PFC_PIN_GROUP(scif5_data_d), | |
3036 | SH_PFC_PIN_GROUP(scifa0_data), | |
3037 | SH_PFC_PIN_GROUP(scifa0_data_b), | |
3038 | SH_PFC_PIN_GROUP(scifa0_data_c), | |
3039 | SH_PFC_PIN_GROUP(scifa0_data_d), | |
3040 | SH_PFC_PIN_GROUP(scifa1_data), | |
3041 | SH_PFC_PIN_GROUP(scifa1_clk), | |
3042 | SH_PFC_PIN_GROUP(scifa1_data_b), | |
3043 | SH_PFC_PIN_GROUP(scifa1_clk_b), | |
3044 | SH_PFC_PIN_GROUP(scifa1_data_c), | |
3045 | SH_PFC_PIN_GROUP(scifa1_clk_c), | |
3046 | SH_PFC_PIN_GROUP(scifa2_data), | |
3047 | SH_PFC_PIN_GROUP(scifa2_clk), | |
3048 | SH_PFC_PIN_GROUP(scifa2_data_b), | |
3049 | SH_PFC_PIN_GROUP(scifa2_clk_b), | |
3050 | SH_PFC_PIN_GROUP(scifa3_data), | |
3051 | SH_PFC_PIN_GROUP(scifa3_clk), | |
3052 | SH_PFC_PIN_GROUP(scifa3_data_b), | |
3053 | SH_PFC_PIN_GROUP(scifa3_clk_b), | |
3054 | SH_PFC_PIN_GROUP(scifa4_data), | |
3055 | SH_PFC_PIN_GROUP(scifa4_data_b), | |
3056 | SH_PFC_PIN_GROUP(scifa4_data_c), | |
3057 | SH_PFC_PIN_GROUP(scifa4_data_d), | |
3058 | SH_PFC_PIN_GROUP(scifa5_data), | |
3059 | SH_PFC_PIN_GROUP(scifa5_data_b), | |
3060 | SH_PFC_PIN_GROUP(scifa5_data_c), | |
3061 | SH_PFC_PIN_GROUP(scifa5_data_d), | |
3062 | SH_PFC_PIN_GROUP(scifb0_data), | |
3063 | SH_PFC_PIN_GROUP(scifb0_clk), | |
3064 | SH_PFC_PIN_GROUP(scifb0_ctrl), | |
3065 | SH_PFC_PIN_GROUP(scifb1_data), | |
3066 | SH_PFC_PIN_GROUP(scifb1_clk), | |
3067 | SH_PFC_PIN_GROUP(scifb2_data), | |
3068 | SH_PFC_PIN_GROUP(scifb2_clk), | |
3069 | SH_PFC_PIN_GROUP(scifb2_ctrl), | |
ed66700c GU |
3070 | SH_PFC_PIN_GROUP(scif_clk), |
3071 | SH_PFC_PIN_GROUP(scif_clk_b), | |
7ac91bda SU |
3072 | SH_PFC_PIN_GROUP(sdhi0_data1), |
3073 | SH_PFC_PIN_GROUP(sdhi0_data4), | |
3074 | SH_PFC_PIN_GROUP(sdhi0_ctrl), | |
3075 | SH_PFC_PIN_GROUP(sdhi0_cd), | |
3076 | SH_PFC_PIN_GROUP(sdhi0_wp), | |
3077 | SH_PFC_PIN_GROUP(sdhi1_data1), | |
3078 | SH_PFC_PIN_GROUP(sdhi1_data4), | |
3079 | SH_PFC_PIN_GROUP(sdhi1_ctrl), | |
3080 | SH_PFC_PIN_GROUP(sdhi1_cd), | |
3081 | SH_PFC_PIN_GROUP(sdhi1_wp), | |
3082 | SH_PFC_PIN_GROUP(sdhi2_data1), | |
3083 | SH_PFC_PIN_GROUP(sdhi2_data4), | |
3084 | SH_PFC_PIN_GROUP(sdhi2_ctrl), | |
3085 | SH_PFC_PIN_GROUP(sdhi2_cd), | |
3086 | SH_PFC_PIN_GROUP(sdhi2_wp), | |
580a7ee9 SU |
3087 | SH_PFC_PIN_GROUP(usb0), |
3088 | SH_PFC_PIN_GROUP(usb1), | |
0f7711aa KM |
3089 | VIN_DATA_PIN_GROUP(vin0_data, 24), |
3090 | VIN_DATA_PIN_GROUP(vin0_data, 20), | |
3091 | SH_PFC_PIN_GROUP(vin0_data18), | |
3092 | VIN_DATA_PIN_GROUP(vin0_data, 16), | |
3093 | VIN_DATA_PIN_GROUP(vin0_data, 12), | |
3094 | VIN_DATA_PIN_GROUP(vin0_data, 10), | |
3095 | VIN_DATA_PIN_GROUP(vin0_data, 8), | |
3096 | SH_PFC_PIN_GROUP(vin0_sync), | |
3097 | SH_PFC_PIN_GROUP(vin0_field), | |
3098 | SH_PFC_PIN_GROUP(vin0_clkenb), | |
3099 | SH_PFC_PIN_GROUP(vin0_clk), | |
3100 | VIN_DATA_PIN_GROUP(vin1_data, 12), | |
3101 | VIN_DATA_PIN_GROUP(vin1_data, 10), | |
3102 | VIN_DATA_PIN_GROUP(vin1_data, 8), | |
3103 | SH_PFC_PIN_GROUP(vin1_sync), | |
3104 | SH_PFC_PIN_GROUP(vin1_field), | |
3105 | SH_PFC_PIN_GROUP(vin1_clkenb), | |
3106 | SH_PFC_PIN_GROUP(vin1_clk), | |
43c4436e HN |
3107 | }; |
3108 | ||
3109 | static const char * const eth_groups[] = { | |
3110 | "eth_link", | |
3111 | "eth_magic", | |
3112 | "eth_mdio", | |
3113 | "eth_rmii", | |
3114 | "eth_link_b", | |
3115 | "eth_magic_b", | |
3116 | "eth_mdio_b", | |
3117 | "eth_rmii_b", | |
3118 | }; | |
3119 | ||
3120 | static const char * const hscif0_groups[] = { | |
3121 | "hscif0_data", | |
3122 | "hscif0_clk", | |
3123 | "hscif0_ctrl", | |
3124 | "hscif0_data_b", | |
3125 | "hscif0_clk_b", | |
3126 | }; | |
3127 | ||
3128 | static const char * const hscif1_groups[] = { | |
3129 | "hscif1_data", | |
3130 | "hscif1_clk", | |
3131 | "hscif1_ctrl", | |
3132 | "hscif1_data_b", | |
3133 | "hscif1_ctrl_b", | |
3134 | }; | |
3135 | ||
3136 | static const char * const hscif2_groups[] = { | |
3137 | "hscif2_data", | |
3138 | "hscif2_clk", | |
3139 | "hscif2_ctrl", | |
3140 | }; | |
3141 | ||
3142 | static const char * const i2c0_groups[] = { | |
3143 | "i2c0", | |
3144 | "i2c0_b", | |
3145 | "i2c0_c", | |
3146 | "i2c0_d", | |
3147 | "i2c0_e", | |
3148 | }; | |
3149 | ||
3150 | static const char * const i2c1_groups[] = { | |
3151 | "i2c1", | |
3152 | "i2c1_b", | |
3153 | "i2c1_c", | |
3154 | "i2c1_d", | |
3155 | "i2c1_e", | |
3156 | }; | |
3157 | ||
3158 | static const char * const i2c2_groups[] = { | |
3159 | "i2c2", | |
3160 | "i2c2_b", | |
3161 | "i2c2_c", | |
3162 | "i2c2_d", | |
3163 | "i2c2_e", | |
3164 | }; | |
3165 | ||
3166 | static const char * const i2c3_groups[] = { | |
3167 | "i2c3", | |
3168 | "i2c3_b", | |
3169 | "i2c3_c", | |
3170 | "i2c3_d", | |
3171 | "i2c3_e", | |
3172 | }; | |
3173 | ||
3174 | static const char * const i2c4_groups[] = { | |
3175 | "i2c4", | |
3176 | "i2c4_b", | |
3177 | "i2c4_c", | |
3178 | "i2c4_d", | |
3179 | "i2c4_e", | |
3180 | }; | |
3181 | ||
3182 | static const char * const intc_groups[] = { | |
3183 | "intc_irq0", | |
3184 | "intc_irq1", | |
3185 | "intc_irq2", | |
3186 | "intc_irq3", | |
3187 | "intc_irq4", | |
3188 | "intc_irq5", | |
3189 | "intc_irq6", | |
3190 | "intc_irq7", | |
3191 | "intc_irq8", | |
3192 | "intc_irq9", | |
3193 | }; | |
3194 | ||
f1f74b64 SU |
3195 | static const char * const mmc_groups[] = { |
3196 | "mmc_data1", | |
3197 | "mmc_data4", | |
3198 | "mmc_data8", | |
3199 | "mmc_ctrl", | |
3200 | }; | |
3201 | ||
43c4436e HN |
3202 | static const char * const msiof0_groups[] = { |
3203 | "msiof0_clk", | |
3204 | "msiof0_sync", | |
3205 | "msiof0_ss1", | |
3206 | "msiof0_ss2", | |
3207 | "msiof0_rx", | |
3208 | "msiof0_tx", | |
3209 | }; | |
3210 | ||
3211 | static const char * const msiof1_groups[] = { | |
3212 | "msiof1_clk", | |
3213 | "msiof1_sync", | |
3214 | "msiof1_ss1", | |
3215 | "msiof1_ss2", | |
3216 | "msiof1_rx", | |
3217 | "msiof1_tx", | |
3218 | "msiof1_clk_b", | |
3219 | "msiof1_sync_b", | |
3220 | "msiof1_ss1_b", | |
3221 | "msiof1_ss2_b", | |
3222 | "msiof1_rx_b", | |
3223 | "msiof1_tx_b", | |
3224 | }; | |
3225 | ||
3226 | static const char * const msiof2_groups[] = { | |
3227 | "msiof2_clk", | |
3228 | "msiof2_sync", | |
3229 | "msiof2_ss1", | |
3230 | "msiof2_ss2", | |
3231 | "msiof2_rx", | |
3232 | "msiof2_tx", | |
3233 | "msiof2_clk_b", | |
3234 | "msiof2_sync_b", | |
3235 | "msiof2_ss1_b", | |
3236 | "msiof2_ss2_b", | |
3237 | "msiof2_rx_b", | |
3238 | "msiof2_tx_b", | |
3239 | }; | |
3240 | ||
3241 | static const char * const qspi_groups[] = { | |
3242 | "qspi_ctrl", | |
3243 | "qspi_data2", | |
3244 | "qspi_data4", | |
3245 | }; | |
3246 | ||
3247 | static const char * const scif0_groups[] = { | |
3248 | "scif0_data", | |
43c4436e | 3249 | "scif0_data_b", |
43c4436e HN |
3250 | "scif0_data_c", |
3251 | "scif0_data_d", | |
3252 | }; | |
3253 | ||
3254 | static const char * const scif1_groups[] = { | |
3255 | "scif1_data", | |
3256 | "scif1_clk", | |
3257 | "scif1_data_b", | |
3258 | "scif1_clk_b", | |
3259 | "scif1_data_c", | |
3260 | "scif1_clk_c", | |
3261 | }; | |
3262 | ||
3263 | static const char * const scif2_groups[] = { | |
3264 | "scif2_data", | |
3265 | "scif2_clk", | |
3266 | "scif2_data_b", | |
3267 | "scif2_clk_b", | |
3268 | "scif2_data_c", | |
3269 | "scif2_clk_c", | |
3270 | }; | |
3271 | ||
3272 | static const char * const scif3_groups[] = { | |
3273 | "scif3_data", | |
3274 | "scif3_clk", | |
3275 | "scif3_data_b", | |
3276 | "scif3_clk_b", | |
3277 | }; | |
3278 | ||
3279 | static const char * const scif4_groups[] = { | |
3280 | "scif4_data", | |
3281 | "scif4_data_b", | |
3282 | "scif4_data_c", | |
3283 | "scif4_data_d", | |
3284 | "scif4_data_e", | |
3285 | }; | |
3286 | ||
3287 | static const char * const scif5_groups[] = { | |
3288 | "scif5_data", | |
3289 | "scif5_data_b", | |
3290 | "scif5_data_c", | |
3291 | "scif5_data_d", | |
3292 | }; | |
3293 | ||
3294 | static const char * const scifa0_groups[] = { | |
3295 | "scifa0_data", | |
3296 | "scifa0_data_b", | |
3297 | "scifa0_data_c", | |
3298 | "scifa0_data_d", | |
3299 | }; | |
3300 | ||
3301 | static const char * const scifa1_groups[] = { | |
3302 | "scifa1_data", | |
3303 | "scifa1_clk", | |
3304 | "scifa1_data_b", | |
3305 | "scifa1_clk_b", | |
3306 | "scifa1_data_c", | |
3307 | "scifa1_clk_c", | |
3308 | }; | |
3309 | ||
3310 | static const char * const scifa2_groups[] = { | |
3311 | "scifa2_data", | |
3312 | "scifa2_clk", | |
3313 | "scifa2_data_b", | |
3314 | "scifa2_clk_b", | |
3315 | }; | |
3316 | ||
3317 | static const char * const scifa3_groups[] = { | |
3318 | "scifa3_data", | |
3319 | "scifa3_clk", | |
3320 | "scifa3_data_b", | |
3321 | "scifa3_clk_b", | |
3322 | }; | |
3323 | ||
3324 | static const char * const scifa4_groups[] = { | |
3325 | "scifa4_data", | |
3326 | "scifa4_data_b", | |
3327 | "scifa4_data_c", | |
3328 | "scifa4_data_d", | |
3329 | }; | |
3330 | ||
3331 | static const char * const scifa5_groups[] = { | |
3332 | "scifa5_data", | |
3333 | "scifa5_data_b", | |
3334 | "scifa5_data_c", | |
3335 | "scifa5_data_d", | |
3336 | }; | |
3337 | ||
3338 | static const char * const scifb0_groups[] = { | |
3339 | "scifb0_data", | |
3340 | "scifb0_clk", | |
3341 | "scifb0_ctrl", | |
3342 | }; | |
3343 | ||
3344 | static const char * const scifb1_groups[] = { | |
3345 | "scifb1_data", | |
3346 | "scifb1_clk", | |
3347 | }; | |
3348 | ||
3349 | static const char * const scifb2_groups[] = { | |
3350 | "scifb2_data", | |
3351 | "scifb2_clk", | |
3352 | "scifb2_ctrl", | |
3353 | }; | |
3354 | ||
ed66700c GU |
3355 | static const char * const scif_clk_groups[] = { |
3356 | "scif_clk", | |
3357 | "scif_clk_b", | |
3358 | }; | |
3359 | ||
7ac91bda SU |
3360 | static const char * const sdhi0_groups[] = { |
3361 | "sdhi0_data1", | |
3362 | "sdhi0_data4", | |
3363 | "sdhi0_ctrl", | |
3364 | "sdhi0_cd", | |
3365 | "sdhi0_wp", | |
3366 | }; | |
3367 | ||
3368 | static const char * const sdhi1_groups[] = { | |
3369 | "sdhi1_data1", | |
3370 | "sdhi1_data4", | |
3371 | "sdhi1_ctrl", | |
3372 | "sdhi1_cd", | |
3373 | "sdhi1_wp", | |
3374 | }; | |
3375 | ||
3376 | static const char * const sdhi2_groups[] = { | |
3377 | "sdhi2_data1", | |
3378 | "sdhi2_data4", | |
3379 | "sdhi2_ctrl", | |
3380 | "sdhi2_cd", | |
3381 | "sdhi2_wp", | |
3382 | }; | |
3383 | ||
580a7ee9 SU |
3384 | static const char * const usb0_groups[] = { |
3385 | "usb0", | |
3386 | }; | |
3387 | ||
3388 | static const char * const usb1_groups[] = { | |
3389 | "usb1", | |
3390 | }; | |
3391 | ||
0f7711aa KM |
3392 | static const char * const vin0_groups[] = { |
3393 | "vin0_data24", | |
3394 | "vin0_data20", | |
3395 | "vin0_data18", | |
3396 | "vin0_data16", | |
3397 | "vin0_data12", | |
3398 | "vin0_data10", | |
3399 | "vin0_data8", | |
3400 | "vin0_sync", | |
3401 | "vin0_field", | |
3402 | "vin0_clkenb", | |
3403 | "vin0_clk", | |
3404 | }; | |
3405 | ||
3406 | static const char * const vin1_groups[] = { | |
3407 | "vin1_data12", | |
3408 | "vin1_data10", | |
3409 | "vin1_data8", | |
3410 | "vin1_sync", | |
3411 | "vin1_field", | |
3412 | "vin1_clkenb", | |
3413 | "vin1_clk", | |
3414 | }; | |
3415 | ||
43c4436e HN |
3416 | static const struct sh_pfc_function pinmux_functions[] = { |
3417 | SH_PFC_FUNCTION(eth), | |
3418 | SH_PFC_FUNCTION(hscif0), | |
3419 | SH_PFC_FUNCTION(hscif1), | |
3420 | SH_PFC_FUNCTION(hscif2), | |
3421 | SH_PFC_FUNCTION(i2c0), | |
3422 | SH_PFC_FUNCTION(i2c1), | |
3423 | SH_PFC_FUNCTION(i2c2), | |
3424 | SH_PFC_FUNCTION(i2c3), | |
3425 | SH_PFC_FUNCTION(i2c4), | |
3426 | SH_PFC_FUNCTION(intc), | |
f1f74b64 | 3427 | SH_PFC_FUNCTION(mmc), |
43c4436e HN |
3428 | SH_PFC_FUNCTION(msiof0), |
3429 | SH_PFC_FUNCTION(msiof1), | |
3430 | SH_PFC_FUNCTION(msiof2), | |
3431 | SH_PFC_FUNCTION(qspi), | |
3432 | SH_PFC_FUNCTION(scif0), | |
3433 | SH_PFC_FUNCTION(scif1), | |
3434 | SH_PFC_FUNCTION(scif2), | |
3435 | SH_PFC_FUNCTION(scif3), | |
3436 | SH_PFC_FUNCTION(scif4), | |
3437 | SH_PFC_FUNCTION(scif5), | |
3438 | SH_PFC_FUNCTION(scifa0), | |
3439 | SH_PFC_FUNCTION(scifa1), | |
3440 | SH_PFC_FUNCTION(scifa2), | |
3441 | SH_PFC_FUNCTION(scifa3), | |
3442 | SH_PFC_FUNCTION(scifa4), | |
3443 | SH_PFC_FUNCTION(scifa5), | |
3444 | SH_PFC_FUNCTION(scifb0), | |
3445 | SH_PFC_FUNCTION(scifb1), | |
3446 | SH_PFC_FUNCTION(scifb2), | |
ed66700c | 3447 | SH_PFC_FUNCTION(scif_clk), |
7ac91bda SU |
3448 | SH_PFC_FUNCTION(sdhi0), |
3449 | SH_PFC_FUNCTION(sdhi1), | |
3450 | SH_PFC_FUNCTION(sdhi2), | |
580a7ee9 SU |
3451 | SH_PFC_FUNCTION(usb0), |
3452 | SH_PFC_FUNCTION(usb1), | |
0f7711aa KM |
3453 | SH_PFC_FUNCTION(vin0), |
3454 | SH_PFC_FUNCTION(vin1), | |
43c4436e HN |
3455 | }; |
3456 | ||
3457 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { | |
3458 | { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { | |
3459 | GP_0_31_FN, FN_IP2_17_16, | |
3460 | GP_0_30_FN, FN_IP2_15_14, | |
3461 | GP_0_29_FN, FN_IP2_13_12, | |
3462 | GP_0_28_FN, FN_IP2_11_10, | |
3463 | GP_0_27_FN, FN_IP2_9_8, | |
3464 | GP_0_26_FN, FN_IP2_7_6, | |
3465 | GP_0_25_FN, FN_IP2_5_4, | |
3466 | GP_0_24_FN, FN_IP2_3_2, | |
3467 | GP_0_23_FN, FN_IP2_1_0, | |
3468 | GP_0_22_FN, FN_IP1_31_30, | |
3469 | GP_0_21_FN, FN_IP1_29_28, | |
3470 | GP_0_20_FN, FN_IP1_27, | |
3471 | GP_0_19_FN, FN_IP1_26, | |
3472 | GP_0_18_FN, FN_A2, | |
3473 | GP_0_17_FN, FN_IP1_24, | |
3474 | GP_0_16_FN, FN_IP1_23_22, | |
3475 | GP_0_15_FN, FN_IP1_21_20, | |
3476 | GP_0_14_FN, FN_IP1_19_18, | |
3477 | GP_0_13_FN, FN_IP1_17_15, | |
3478 | GP_0_12_FN, FN_IP1_14_13, | |
3479 | GP_0_11_FN, FN_IP1_12_11, | |
3480 | GP_0_10_FN, FN_IP1_10_8, | |
3481 | GP_0_9_FN, FN_IP1_7_6, | |
3482 | GP_0_8_FN, FN_IP1_5_4, | |
3483 | GP_0_7_FN, FN_IP1_3_2, | |
3484 | GP_0_6_FN, FN_IP1_1_0, | |
3485 | GP_0_5_FN, FN_IP0_31_30, | |
3486 | GP_0_4_FN, FN_IP0_29_28, | |
3487 | GP_0_3_FN, FN_IP0_27_26, | |
3488 | GP_0_2_FN, FN_IP0_25, | |
3489 | GP_0_1_FN, FN_IP0_24, | |
3490 | GP_0_0_FN, FN_IP0_23_22, } | |
3491 | }, | |
3492 | { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { | |
3493 | 0, 0, | |
3494 | 0, 0, | |
3495 | 0, 0, | |
3496 | 0, 0, | |
3497 | 0, 0, | |
3498 | 0, 0, | |
3499 | GP_1_25_FN, FN_DACK0, | |
3500 | GP_1_24_FN, FN_IP7_31, | |
3501 | GP_1_23_FN, FN_IP4_1_0, | |
3502 | GP_1_22_FN, FN_WE1_N, | |
3503 | GP_1_21_FN, FN_WE0_N, | |
3504 | GP_1_20_FN, FN_IP3_31, | |
3505 | GP_1_19_FN, FN_IP3_30, | |
3506 | GP_1_18_FN, FN_IP3_29_27, | |
3507 | GP_1_17_FN, FN_IP3_26_24, | |
3508 | GP_1_16_FN, FN_IP3_23_21, | |
3509 | GP_1_15_FN, FN_IP3_20_18, | |
3510 | GP_1_14_FN, FN_IP3_17_15, | |
3511 | GP_1_13_FN, FN_IP3_14_13, | |
3512 | GP_1_12_FN, FN_IP3_12, | |
3513 | GP_1_11_FN, FN_IP3_11, | |
3514 | GP_1_10_FN, FN_IP3_10, | |
3515 | GP_1_9_FN, FN_IP3_9_8, | |
3516 | GP_1_8_FN, FN_IP3_7_6, | |
3517 | GP_1_7_FN, FN_IP3_5_4, | |
3518 | GP_1_6_FN, FN_IP3_3_2, | |
3519 | GP_1_5_FN, FN_IP3_1_0, | |
3520 | GP_1_4_FN, FN_IP2_31_30, | |
3521 | GP_1_3_FN, FN_IP2_29_27, | |
3522 | GP_1_2_FN, FN_IP2_26_24, | |
3523 | GP_1_1_FN, FN_IP2_23_21, | |
3524 | GP_1_0_FN, FN_IP2_20_18, } | |
3525 | }, | |
3526 | { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { | |
3527 | GP_2_31_FN, FN_IP6_7_6, | |
3528 | GP_2_30_FN, FN_IP6_5_4, | |
3529 | GP_2_29_FN, FN_IP6_3_2, | |
3530 | GP_2_28_FN, FN_IP6_1_0, | |
3531 | GP_2_27_FN, FN_IP5_31_30, | |
3532 | GP_2_26_FN, FN_IP5_29_28, | |
3533 | GP_2_25_FN, FN_IP5_27_26, | |
3534 | GP_2_24_FN, FN_IP5_25_24, | |
3535 | GP_2_23_FN, FN_IP5_23_22, | |
3536 | GP_2_22_FN, FN_IP5_21_20, | |
3537 | GP_2_21_FN, FN_IP5_19_18, | |
3538 | GP_2_20_FN, FN_IP5_17_16, | |
3539 | GP_2_19_FN, FN_IP5_15_14, | |
3540 | GP_2_18_FN, FN_IP5_13_12, | |
3541 | GP_2_17_FN, FN_IP5_11_9, | |
3542 | GP_2_16_FN, FN_IP5_8_6, | |
3543 | GP_2_15_FN, FN_IP5_5_4, | |
3544 | GP_2_14_FN, FN_IP5_3_2, | |
3545 | GP_2_13_FN, FN_IP5_1_0, | |
3546 | GP_2_12_FN, FN_IP4_31_30, | |
3547 | GP_2_11_FN, FN_IP4_29_28, | |
3548 | GP_2_10_FN, FN_IP4_27_26, | |
3549 | GP_2_9_FN, FN_IP4_25_23, | |
3550 | GP_2_8_FN, FN_IP4_22_20, | |
3551 | GP_2_7_FN, FN_IP4_19_18, | |
3552 | GP_2_6_FN, FN_IP4_17_16, | |
3553 | GP_2_5_FN, FN_IP4_15_14, | |
3554 | GP_2_4_FN, FN_IP4_13_12, | |
3555 | GP_2_3_FN, FN_IP4_11_10, | |
3556 | GP_2_2_FN, FN_IP4_9_8, | |
3557 | GP_2_1_FN, FN_IP4_7_5, | |
3558 | GP_2_0_FN, FN_IP4_4_2 } | |
3559 | }, | |
3560 | { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { | |
3561 | GP_3_31_FN, FN_IP8_22_20, | |
3562 | GP_3_30_FN, FN_IP8_19_17, | |
3563 | GP_3_29_FN, FN_IP8_16_15, | |
3564 | GP_3_28_FN, FN_IP8_14_12, | |
3565 | GP_3_27_FN, FN_IP8_11_9, | |
3566 | GP_3_26_FN, FN_IP8_8_6, | |
3567 | GP_3_25_FN, FN_IP8_5_3, | |
3568 | GP_3_24_FN, FN_IP8_2_0, | |
3569 | GP_3_23_FN, FN_IP7_29_27, | |
3570 | GP_3_22_FN, FN_IP7_26_24, | |
3571 | GP_3_21_FN, FN_IP7_23_21, | |
3572 | GP_3_20_FN, FN_IP7_20_18, | |
3573 | GP_3_19_FN, FN_IP7_17_15, | |
3574 | GP_3_18_FN, FN_IP7_14_12, | |
3575 | GP_3_17_FN, FN_IP7_11_9, | |
3576 | GP_3_16_FN, FN_IP7_8_6, | |
3577 | GP_3_15_FN, FN_IP7_5_3, | |
3578 | GP_3_14_FN, FN_IP7_2_0, | |
3579 | GP_3_13_FN, FN_IP6_31_29, | |
3580 | GP_3_12_FN, FN_IP6_28_26, | |
3581 | GP_3_11_FN, FN_IP6_25_23, | |
3582 | GP_3_10_FN, FN_IP6_22_20, | |
3583 | GP_3_9_FN, FN_IP6_19_17, | |
3584 | GP_3_8_FN, FN_IP6_16, | |
3585 | GP_3_7_FN, FN_IP6_15, | |
3586 | GP_3_6_FN, FN_IP6_14, | |
3587 | GP_3_5_FN, FN_IP6_13, | |
3588 | GP_3_4_FN, FN_IP6_12, | |
3589 | GP_3_3_FN, FN_IP6_11, | |
3590 | GP_3_2_FN, FN_IP6_10, | |
3591 | GP_3_1_FN, FN_IP6_9, | |
3592 | GP_3_0_FN, FN_IP6_8 } | |
3593 | }, | |
3594 | { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { | |
3595 | GP_4_31_FN, FN_IP11_17_16, | |
3596 | GP_4_30_FN, FN_IP11_15_14, | |
3597 | GP_4_29_FN, FN_IP11_13_11, | |
3598 | GP_4_28_FN, FN_IP11_10_8, | |
3599 | GP_4_27_FN, FN_IP11_7_6, | |
3600 | GP_4_26_FN, FN_IP11_5_3, | |
3601 | GP_4_25_FN, FN_IP11_2_0, | |
3602 | GP_4_24_FN, FN_IP10_31_30, | |
3603 | GP_4_23_FN, FN_IP10_29_27, | |
3604 | GP_4_22_FN, FN_IP10_26_24, | |
3605 | GP_4_21_FN, FN_IP10_23_21, | |
3606 | GP_4_20_FN, FN_IP10_20_18, | |
3607 | GP_4_19_FN, FN_IP10_17_15, | |
3608 | GP_4_18_FN, FN_IP10_14_12, | |
3609 | GP_4_17_FN, FN_IP10_11_9, | |
3610 | GP_4_16_FN, FN_IP10_8_6, | |
3611 | GP_4_15_FN, FN_IP10_5_3, | |
3612 | GP_4_14_FN, FN_IP10_2_0, | |
3613 | GP_4_13_FN, FN_IP9_30_28, | |
3614 | GP_4_12_FN, FN_IP9_27_25, | |
3615 | GP_4_11_FN, FN_IP9_24_22, | |
3616 | GP_4_10_FN, FN_IP9_21_19, | |
3617 | GP_4_9_FN, FN_IP9_18_17, | |
3618 | GP_4_8_FN, FN_IP9_16_15, | |
3619 | GP_4_7_FN, FN_IP9_14_12, | |
3620 | GP_4_6_FN, FN_IP9_11_9, | |
3621 | GP_4_5_FN, FN_IP9_8_6, | |
3622 | GP_4_4_FN, FN_IP9_5_3, | |
3623 | GP_4_3_FN, FN_IP9_2_0, | |
3624 | GP_4_2_FN, FN_IP8_31_29, | |
3625 | GP_4_1_FN, FN_IP8_28_26, | |
3626 | GP_4_0_FN, FN_IP8_25_23 } | |
3627 | }, | |
3628 | { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { | |
3629 | 0, 0, | |
3630 | 0, 0, | |
3631 | 0, 0, | |
3632 | 0, 0, | |
3633 | GP_5_27_FN, FN_USB1_OVC, | |
3634 | GP_5_26_FN, FN_USB1_PWEN, | |
3635 | GP_5_25_FN, FN_USB0_OVC, | |
3636 | GP_5_24_FN, FN_USB0_PWEN, | |
3637 | GP_5_23_FN, FN_IP13_26_24, | |
3638 | GP_5_22_FN, FN_IP13_23_21, | |
3639 | GP_5_21_FN, FN_IP13_20_18, | |
3640 | GP_5_20_FN, FN_IP13_17_15, | |
3641 | GP_5_19_FN, FN_IP13_14_12, | |
3642 | GP_5_18_FN, FN_IP13_11_9, | |
3643 | GP_5_17_FN, FN_IP13_8_6, | |
3644 | GP_5_16_FN, FN_IP13_5_3, | |
3645 | GP_5_15_FN, FN_IP13_2_0, | |
3646 | GP_5_14_FN, FN_IP12_29_27, | |
3647 | GP_5_13_FN, FN_IP12_26_24, | |
3648 | GP_5_12_FN, FN_IP12_23_21, | |
3649 | GP_5_11_FN, FN_IP12_20_18, | |
3650 | GP_5_10_FN, FN_IP12_17_15, | |
3651 | GP_5_9_FN, FN_IP12_14_13, | |
3652 | GP_5_8_FN, FN_IP12_12_11, | |
3653 | GP_5_7_FN, FN_IP12_10_9, | |
3654 | GP_5_6_FN, FN_IP12_8_6, | |
3655 | GP_5_5_FN, FN_IP12_5_3, | |
3656 | GP_5_4_FN, FN_IP12_2_0, | |
3657 | GP_5_3_FN, FN_IP11_29_27, | |
3658 | GP_5_2_FN, FN_IP11_26_24, | |
3659 | GP_5_1_FN, FN_IP11_23_21, | |
3660 | GP_5_0_FN, FN_IP11_20_18 } | |
3661 | }, | |
3662 | { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { | |
3663 | 0, 0, | |
3664 | 0, 0, | |
3665 | 0, 0, | |
3666 | 0, 0, | |
3667 | 0, 0, | |
3668 | 0, 0, | |
3669 | GP_6_25_FN, FN_IP0_21_20, | |
3670 | GP_6_24_FN, FN_IP0_19_18, | |
3671 | GP_6_23_FN, FN_IP0_17, | |
3672 | GP_6_22_FN, FN_IP0_16, | |
3673 | GP_6_21_FN, FN_IP0_15, | |
3674 | GP_6_20_FN, FN_IP0_14, | |
3675 | GP_6_19_FN, FN_IP0_13, | |
3676 | GP_6_18_FN, FN_IP0_12, | |
3677 | GP_6_17_FN, FN_IP0_11, | |
3678 | GP_6_16_FN, FN_IP0_10, | |
3679 | GP_6_15_FN, FN_IP0_9_8, | |
3680 | GP_6_14_FN, FN_IP0_0, | |
3681 | GP_6_13_FN, FN_SD1_DATA3, | |
3682 | GP_6_12_FN, FN_SD1_DATA2, | |
3683 | GP_6_11_FN, FN_SD1_DATA1, | |
3684 | GP_6_10_FN, FN_SD1_DATA0, | |
3685 | GP_6_9_FN, FN_SD1_CMD, | |
3686 | GP_6_8_FN, FN_SD1_CLK, | |
3687 | GP_6_7_FN, FN_SD0_WP, | |
3688 | GP_6_6_FN, FN_SD0_CD, | |
3689 | GP_6_5_FN, FN_SD0_DATA3, | |
3690 | GP_6_4_FN, FN_SD0_DATA2, | |
3691 | GP_6_3_FN, FN_SD0_DATA1, | |
3692 | GP_6_2_FN, FN_SD0_DATA0, | |
3693 | GP_6_1_FN, FN_SD0_CMD, | |
3694 | GP_6_0_FN, FN_SD0_CLK } | |
3695 | }, | |
3696 | { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, | |
3697 | 2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, | |
3698 | 2, 1, 1, 1, 1, 1, 1, 1, 1) { | |
3699 | /* IP0_31_30 [2] */ | |
3700 | FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0, | |
3701 | /* IP0_29_28 [2] */ | |
3702 | FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0, | |
3703 | /* IP0_27_26 [2] */ | |
3704 | FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0, | |
3705 | /* IP0_25 [1] */ | |
3706 | FN_D2, FN_SCIFA3_TXD_B, | |
3707 | /* IP0_24 [1] */ | |
3708 | FN_D1, FN_SCIFA3_RXD_B, | |
3709 | /* IP0_23_22 [2] */ | |
3710 | FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0, | |
3711 | /* IP0_21_20 [2] */ | |
3712 | FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX, | |
3713 | /* IP0_19_18 [2] */ | |
3714 | FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX, | |
3715 | /* IP0_17 [1] */ | |
3716 | FN_MMC_D5, FN_SD2_WP, | |
3717 | /* IP0_16 [1] */ | |
3718 | FN_MMC_D4, FN_SD2_CD, | |
3719 | /* IP0_15 [1] */ | |
3720 | FN_MMC_D3, FN_SD2_DATA3, | |
3721 | /* IP0_14 [1] */ | |
3722 | FN_MMC_D2, FN_SD2_DATA2, | |
3723 | /* IP0_13 [1] */ | |
3724 | FN_MMC_D1, FN_SD2_DATA1, | |
3725 | /* IP0_12 [1] */ | |
3726 | FN_MMC_D0, FN_SD2_DATA0, | |
3727 | /* IP0_11 [1] */ | |
3728 | FN_MMC_CMD, FN_SD2_CMD, | |
3729 | /* IP0_10 [1] */ | |
3730 | FN_MMC_CLK, FN_SD2_CLK, | |
3731 | /* IP0_9_8 [2] */ | |
3732 | FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0, | |
3733 | /* IP0_7 [1] */ | |
3734 | 0, 0, | |
3735 | /* IP0_6 [1] */ | |
3736 | 0, 0, | |
3737 | /* IP0_5 [1] */ | |
3738 | 0, 0, | |
3739 | /* IP0_4 [1] */ | |
3740 | 0, 0, | |
3741 | /* IP0_3 [1] */ | |
3742 | 0, 0, | |
3743 | /* IP0_2 [1] */ | |
3744 | 0, 0, | |
3745 | /* IP0_1 [1] */ | |
3746 | 0, 0, | |
3747 | /* IP0_0 [1] */ | |
3748 | FN_SD1_CD, FN_CAN0_RX, } | |
3749 | }, | |
3750 | { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, | |
3751 | 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2, | |
3752 | 2, 2) { | |
3753 | /* IP1_31_30 [2] */ | |
3754 | FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C, | |
3755 | /* IP1_29_28 [2] */ | |
3756 | FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C, | |
3757 | /* IP1_27 [1] */ | |
3758 | FN_A4, FN_SCIFB0_TXD, | |
3759 | /* IP1_26 [1] */ | |
3760 | FN_A3, FN_SCIFB0_SCK, | |
3761 | /* IP1_25 [1] */ | |
3762 | 0, 0, | |
3763 | /* IP1_24 [1] */ | |
3764 | FN_A1, FN_SCIFB1_TXD, | |
3765 | /* IP1_23_22 [2] */ | |
3766 | FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0, | |
3767 | /* IP1_21_20 [2] */ | |
3768 | FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, 0, | |
3769 | /* IP1_19_18 [2] */ | |
3770 | FN_D14, FN_SCIFA1_RXD, FN_IIC0_SCL_B, 0, | |
3771 | /* IP1_17_15 [3] */ | |
3772 | FN_D13, FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, | |
3773 | 0, 0, 0, | |
3774 | /* IP1_14_13 [2] */ | |
3775 | FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, | |
3776 | /* IP1_12_11 [2] */ | |
3777 | FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D, | |
3778 | /* IP1_10_8 [3] */ | |
3779 | FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C, | |
3780 | 0, 0, 0, | |
3781 | /* IP1_7_6 [2] */ | |
3782 | FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0, | |
3783 | /* IP1_5_4 [2] */ | |
3784 | FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0, | |
3785 | /* IP1_3_2 [2] */ | |
3786 | FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B, | |
3787 | /* IP1_1_0 [2] */ | |
3788 | FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, } | |
3789 | }, | |
3790 | { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, | |
3791 | 2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) { | |
3792 | /* IP2_31_30 [2] */ | |
3793 | FN_A20, FN_SPCLK, FN_MOUT1, 0, | |
3794 | /* IP2_29_27 [3] */ | |
3795 | FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2, | |
3796 | FN_MOUT0, 0, 0, 0, | |
3797 | /* IP2_26_24 [3] */ | |
3798 | FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B, | |
3799 | FN_AVB_AVTP_MATCH_B, 0, 0, 0, | |
3800 | /* IP2_23_21 [3] */ | |
3801 | FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B, | |
3802 | FN_AVB_AVTP_CAPTURE_B, 0, 0, 0, | |
3803 | /* IP2_20_18 [3] */ | |
3804 | FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, | |
3805 | FN_VSP, FN_CAN_CLK_C, FN_TPUTO2_B, 0, | |
3806 | /* IP2_17_16 [2] */ | |
3807 | FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, | |
3808 | /* IP2_15_14 [2] */ | |
3809 | FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N, | |
3810 | /* IP2_13_12 [2] */ | |
3811 | FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0, | |
3812 | /* IP2_11_10 [2] */ | |
3813 | FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0, | |
3814 | /* IP2_9_8 [2] */ | |
3815 | FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B, 0, | |
3816 | /* IP2_7_6 [2] */ | |
3817 | FN_A10, FN_MSIOF1_SCK, FN_IIC1_SCL_B, 0, | |
3818 | /* IP2_5_4 [2] */ | |
3819 | FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0, | |
3820 | /* IP2_3_2 [2] */ | |
3821 | FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0, | |
3822 | /* IP2_1_0 [2] */ | |
3823 | FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, } | |
3824 | }, | |
3825 | { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, | |
3826 | 1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) { | |
3827 | /* IP3_31 [1] */ | |
3828 | FN_RD_WR_N, FN_ATAG1_N, | |
3829 | /* IP3_30 [1] */ | |
3830 | FN_RD_N, FN_ATACS11_N, | |
3831 | /* IP3_29_27 [3] */ | |
3832 | FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, | |
3833 | FN_MTS_N_B, 0, 0, | |
3834 | /* IP3_26_24 [3] */ | |
3835 | FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, | |
3836 | FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B, | |
3837 | /* IP3_23_21 [3] */ | |
3838 | FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, | |
3839 | FN_RIF0_D0, FN_FMCLK, FN_SCIFB2_CTS_N, FN_SCKZ_B, | |
3840 | /* IP3_20_18 [3] */ | |
3841 | FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, | |
3842 | FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B, | |
3843 | /* IP3_17_15 [3] */ | |
3844 | FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, | |
3845 | FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD, FN_SDATA_B, | |
3846 | /* IP3_14_13 [2] */ | |
3847 | FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, | |
3848 | /* IP3_12 [1] */ | |
3849 | FN_EX_CS0_N, FN_VI1_DATA10, | |
3850 | /* IP3_11 [1] */ | |
3851 | FN_CS1_N_A26, FN_VI1_DATA9, | |
3852 | /* IP3_10 [1] */ | |
3853 | FN_CS0_N, FN_VI1_DATA8, | |
3854 | /* IP3_9_8 [2] */ | |
3855 | FN_A25, FN_SSL, FN_ATARD1_N, 0, | |
3856 | /* IP3_7_6 [2] */ | |
3857 | FN_A24, FN_IO3, FN_EX_WAIT2, 0, | |
3858 | /* IP3_5_4 [2] */ | |
3859 | FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N, | |
3860 | /* IP3_3_2 [2] */ | |
3861 | FN_A22, FN_MISO_IO1, FN_MOUT5, FN_ATADIR1_N, | |
3862 | /* IP3_1_0 [2] */ | |
3863 | FN_A21, FN_MOSI_IO0, FN_MOUT2, 0, } | |
3864 | }, | |
3865 | { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, | |
3866 | 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) { | |
3867 | /* IP4_31_30 [2] */ | |
3868 | FN_DU0_DG4, FN_LCDOUT12, FN_CC50_STATE12, 0, | |
3869 | /* IP4_29_28 [2] */ | |
3870 | FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, 0, | |
3871 | /* IP4_27_26 [2] */ | |
3872 | FN_DU0_DG2, FN_LCDOUT10, FN_CC50_STATE10, 0, | |
3873 | /* IP4_25_23 [3] */ | |
3874 | FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, | |
3875 | FN_CC50_STATE9, 0, 0, 0, | |
3876 | /* IP4_22_20 [3] */ | |
3877 | FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, | |
3878 | FN_CC50_STATE8, 0, 0, 0, | |
3879 | /* IP4_19_18 [2] */ | |
3880 | FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, 0, | |
3881 | /* IP4_17_16 [2] */ | |
3882 | FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6, 0, | |
3883 | /* IP4_15_14 [2] */ | |
3884 | FN_DU0_DR5, FN_LCDOUT21, FN_CC50_STATE5, 0, | |
3885 | /* IP4_13_12 [2] */ | |
3886 | FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, 0, | |
3887 | /* IP4_11_10 [2] */ | |
3888 | FN_DU0_DR3, FN_LCDOUT19, FN_CC50_STATE3, 0, | |
3889 | /* IP4_9_8 [2] */ | |
3890 | FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, 0, | |
3891 | /* IP4_7_5 [3] */ | |
3892 | FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, | |
3893 | FN_CC50_STATE1, 0, 0, 0, | |
3894 | /* IP4_4_2 [3] */ | |
3895 | FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, | |
3896 | FN_CC50_STATE0, 0, 0, 0, | |
3897 | /* IP4_1_0 [2] */ | |
3898 | FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, } | |
3899 | }, | |
3900 | { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, | |
3901 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) { | |
3902 | /* IP5_31_30 [2] */ | |
3903 | FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27, 0, | |
3904 | /* IP5_29_28 [2] */ | |
3905 | FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_CC50_STATE26, 0, | |
3906 | /* IP5_27_26 [2] */ | |
3907 | FN_DU0_DOTCLKOUT0, FN_QCLK, FN_CC50_STATE25, 0, | |
3908 | /* IP5_25_24 [2] */ | |
3909 | FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, 0, | |
3910 | /* IP5_23_22 [2] */ | |
3911 | FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23, 0, | |
3912 | /* IP5_21_20 [2] */ | |
3913 | FN_DU0_DB6, FN_LCDOUT6, FN_CC50_STATE22, 0, | |
3914 | /* IP5_19_18 [2] */ | |
3915 | FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, 0, | |
3916 | /* IP5_17_16 [2] */ | |
3917 | FN_DU0_DB4, FN_LCDOUT4, FN_CC50_STATE20, 0, | |
3918 | /* IP5_15_14 [2] */ | |
3919 | FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, 0, | |
3920 | /* IP5_13_12 [2] */ | |
3921 | FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18, 0, | |
3922 | /* IP5_11_9 [3] */ | |
3923 | FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, | |
3924 | FN_CAN0_TX_C, FN_CC50_STATE17, 0, 0, | |
3925 | /* IP5_8_6 [3] */ | |
3926 | FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, | |
3927 | FN_CAN0_RX_C, FN_CC50_STATE16, 0, 0, | |
3928 | /* IP5_5_4 [2] */ | |
3929 | FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, 0, | |
3930 | /* IP5_3_2 [2] */ | |
3931 | FN_DU0_DG6, FN_LCDOUT14, FN_CC50_STATE14, 0, | |
3932 | /* IP5_1_0 [2] */ | |
3933 | FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, 0, } | |
3934 | }, | |
3935 | { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, | |
3936 | 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, | |
3937 | 2, 2) { | |
3938 | /* IP6_31_29 [3] */ | |
3939 | FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, | |
3940 | FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0, | |
3941 | /* IP6_28_26 [3] */ | |
3942 | FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, | |
3943 | FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0, | |
3944 | /* IP6_25_23 [3] */ | |
3945 | FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, | |
3946 | FN_AVB_COL, 0, 0, 0, | |
3947 | /* IP6_22_20 [3] */ | |
3948 | FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, | |
3949 | FN_AVB_RX_ER, 0, 0, 0, | |
3950 | /* IP6_19_17 [3] */ | |
3951 | FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, | |
3952 | FN_AVB_RXD7, 0, 0, 0, | |
3953 | /* IP6_16 [1] */ | |
3954 | FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, | |
3955 | /* IP6_15 [1] */ | |
3956 | FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5, | |
3957 | /* IP6_14 [1] */ | |
3958 | FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, | |
3959 | /* IP6_13 [1] */ | |
3960 | FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3, | |
3961 | /* IP6_12 [1] */ | |
3962 | FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, | |
3963 | /* IP6_11 [1] */ | |
3964 | FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1, | |
3965 | /* IP6_10 [1] */ | |
3966 | FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, | |
3967 | /* IP6_9 [1] */ | |
3968 | FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV, | |
3969 | /* IP6_8 [1] */ | |
3970 | FN_VI0_CLK, FN_AVB_RX_CLK, | |
3971 | /* IP6_7_6 [2] */ | |
3972 | FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0, | |
3973 | /* IP6_5_4 [2] */ | |
3974 | FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0, | |
3975 | /* IP6_3_2 [2] */ | |
3976 | FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29, | |
3977 | /* IP6_1_0 [2] */ | |
3978 | FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, } | |
3979 | }, | |
3980 | { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, | |
3981 | 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { | |
3982 | /* IP7_31 [1] */ | |
3983 | FN_DREQ0_N, FN_SCIFB1_RXD, | |
3984 | /* IP7_30 [1] */ | |
3985 | 0, 0, | |
3986 | /* IP7_29_27 [3] */ | |
3987 | FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, | |
3988 | FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0, | |
3989 | /* IP7_26_24 [3] */ | |
3990 | FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, | |
3991 | FN_SSI_SCK6_B, 0, 0, 0, | |
3992 | /* IP7_23_21 [3] */ | |
3993 | FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D, | |
3994 | FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0, | |
3995 | /* IP7_20_18 [3] */ | |
3996 | FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D, | |
3997 | FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0, | |
3998 | /* IP7_17_15 [3] */ | |
3999 | FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, | |
4000 | FN_SSI_SCK5_B, 0, 0, 0, | |
4001 | /* IP7_14_12 [3] */ | |
4002 | FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, | |
4003 | FN_AVB_TXD4, FN_ADICHS2, 0, 0, | |
4004 | /* IP7_11_9 [3] */ | |
4005 | FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, | |
4006 | FN_AVB_TXD3, FN_ADICHS1, 0, 0, | |
4007 | /* IP7_8_6 [3] */ | |
4008 | FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, | |
4009 | FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0, | |
4010 | /* IP7_5_3 [3] */ | |
4011 | FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, | |
4012 | FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0, | |
4013 | /* IP7_2_0 [3] */ | |
4014 | FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, | |
4015 | FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, } | |
4016 | }, | |
4017 | { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, | |
4018 | 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) { | |
4019 | /* IP8_31_29 [3] */ | |
4020 | FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, | |
4021 | FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK, | |
4022 | /* IP8_28_26 [3] */ | |
4023 | FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, | |
4024 | FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0, | |
4025 | /* IP8_25_23 [3] */ | |
4026 | FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, | |
4027 | FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0, | |
4028 | /* IP8_22_20 [3] */ | |
4029 | FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, | |
4030 | FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0, | |
4031 | /* IP8_19_17 [3] */ | |
4032 | FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, | |
4033 | FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0, | |
4034 | /* IP8_16_15 [2] */ | |
4035 | FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, | |
4036 | /* IP8_14_12 [3] */ | |
4037 | FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E, | |
4038 | FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0, | |
4039 | /* IP8_11_9 [3] */ | |
4040 | FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, | |
4041 | FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0, | |
4042 | /* IP8_8_6 [3] */ | |
4043 | FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, | |
4044 | FN_AVB_LINK, FN_SSI_WS78_B, 0, 0, | |
4045 | /* IP8_5_3 [3] */ | |
4046 | FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, | |
4047 | FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0, | |
4048 | /* IP8_2_0 [3] */ | |
4049 | FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, | |
4050 | FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, } | |
4051 | }, | |
4052 | { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, | |
4053 | 1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3, 3) { | |
4054 | /* IP9_31 [1] */ | |
4055 | 0, 0, | |
4056 | /* IP9_30_28 [3] */ | |
4057 | FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, | |
4058 | FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34, 0, | |
4059 | /* IP9_27_25 [3] */ | |
4060 | FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, | |
4061 | FN_SSI_WS1_B, FN_CAN_STEP0, FN_CC50_STATE33, 0, | |
4062 | /* IP9_24_22 [3] */ | |
4063 | FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, | |
4064 | FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32, 0, | |
4065 | /* IP9_21_19 [3] */ | |
4066 | FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, | |
4067 | FN_REMOCON_B, FN_SPEEDIN_B, FN_VSP_B, 0, | |
4068 | /* IP9_18_17 [2] */ | |
4069 | FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1, | |
4070 | /* IP9_16_15 [2] */ | |
4071 | FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0, | |
4072 | /* IP9_14_12 [3] */ | |
4073 | FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, | |
4074 | FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, 0, | |
4075 | /* IP9_11_9 [3] */ | |
4076 | FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, | |
4077 | FN_RIF1_D0, FN_FMCLK_B, FN_RDS_CLK_B, 0, | |
4078 | /* IP9_8_6 [3] */ | |
4079 | FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, | |
4080 | FN_RIF1_CLK, FN_BPFCLK_B, 0, 0, | |
4081 | /* IP9_5_3 [3] */ | |
4082 | FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, | |
4083 | FN_RIF1_SYNC, FN_TPUTO1_C, 0, 0, | |
4084 | /* IP9_2_0 [3] */ | |
4085 | FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, | |
4086 | FN_RIF1_D1_B, FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, } | |
4087 | }, | |
4088 | { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, | |
4089 | 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { | |
4090 | /* IP10_31_30 [2] */ | |
4091 | FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10, | |
4092 | /* IP10_29_27 [3] */ | |
4093 | FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, | |
4094 | FN_CAN_DEBUGOUT9, 0, 0, 0, | |
4095 | /* IP10_26_24 [3] */ | |
4096 | FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C, | |
4097 | FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, 0, 0, | |
4098 | /* IP10_23_21 [3] */ | |
4099 | FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, | |
4100 | FN_AUDIO_CLKB_C, FN_SSI_WS4_B, FN_CAN_DEBUGOUT7, FN_RDS_DATA_C, | |
4101 | /* IP10_20_18 [3] */ | |
4102 | FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, | |
4103 | FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C, | |
4104 | /* IP10_17_15 [3] */ | |
4105 | FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, | |
4106 | FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT, | |
4107 | /* IP10_14_12 [3] */ | |
4108 | FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B, | |
4109 | FN_USB0_IDIN, FN_CAN_DEBUGOUT4, FN_CC50_STATE39, 0, | |
4110 | /* IP10_11_9 [3] */ | |
4111 | FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B, | |
4112 | FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, 0, | |
4113 | /* IP10_8_6 [3] */ | |
4114 | FN_SCIF2_RXD, FN_IIC1_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B, | |
4115 | FN_USB0_EXTLP, FN_CAN_DEBUGOUT2, FN_CC50_STATE37, 0, | |
4116 | /* IP10_5_3 [3] */ | |
4117 | FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B, | |
4118 | FN_CAN_DEBUGOUT1, FN_CC50_STATE36, 0, 0, | |
4119 | /* IP10_2_0 [3] */ | |
4120 | FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, | |
4121 | FN_CAN_DEBUGOUT0, FN_CC50_STATE35, 0, 0, } | |
4122 | }, | |
4123 | { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, | |
4124 | 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) { | |
4125 | /* IP11_31_30 [2] */ | |
4126 | 0, 0, 0, 0, | |
4127 | /* IP11_29_27 [3] */ | |
4128 | FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B, | |
4129 | FN_AD_CLK_B, 0, 0, 0, | |
4130 | /* IP11_26_24 [3] */ | |
4131 | FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B, | |
4132 | FN_AD_DO_B, 0, 0, 0, | |
4133 | /* IP11_23_21 [3] */ | |
4134 | FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, | |
4135 | FN_AD_DI_B, FN_PCMWE_N, 0, 0, | |
4136 | /* IP11_20_18 [3] */ | |
4137 | FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, | |
4138 | FN_CAN_CLK_D, FN_PCMOE_N, 0, 0, | |
4139 | /* IP11_17_16 [2] */ | |
4140 | FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, | |
4141 | /* IP11_15_14 [2] */ | |
4142 | FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, | |
4143 | /* IP11_13_11 [3] */ | |
4144 | FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, | |
4145 | FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0, | |
4146 | /* IP11_10_8 [3] */ | |
4147 | FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, | |
4148 | FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0, | |
4149 | /* IP11_7_6 [2] */ | |
4150 | FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, | |
4151 | FN_CAN_DEBUGOUT13, | |
4152 | /* IP11_5_3 [3] */ | |
4153 | FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1, | |
4154 | FN_CAN_DEBUGOUT12, 0, 0, 0, | |
4155 | /* IP11_2_0 [3] */ | |
4156 | FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, | |
4157 | FN_CAN_DEBUGOUT11, 0, 0, 0, } | |
4158 | }, | |
4159 | { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, | |
4160 | 2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) { | |
4161 | /* IP12_31_30 [2] */ | |
4162 | 0, 0, 0, 0, | |
4163 | /* IP12_29_27 [3] */ | |
4164 | FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_MDATA, | |
4165 | FN_ATAWR0_N, FN_ETH_RXD1_B, 0, 0, | |
4166 | /* IP12_26_24 [3] */ | |
4167 | FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_SDATA, | |
4168 | FN_ATAG0_N, FN_ETH_RXD0_B, 0, 0, | |
4169 | /* IP12_23_21 [3] */ | |
4170 | FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC1_SDA_C, FN_VI1_DATA0, | |
4171 | FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, FN_ETH_RX_ER_B, 0, | |
4172 | /* IP12_20_18 [3] */ | |
4173 | FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK, | |
4174 | FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, 0, | |
4175 | /* IP12_17_15 [3] */ | |
4176 | FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, | |
4177 | FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0, | |
4178 | /* IP12_14_13 [2] */ | |
4179 | FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, FN_IRD_SCK, | |
4180 | /* IP12_12_11 [2] */ | |
4181 | FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, | |
4182 | /* IP12_10_9 [2] */ | |
4183 | FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX, | |
4184 | /* IP12_8_6 [3] */ | |
4185 | FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, | |
4186 | FN_CAN1_TX_C, FN_DREQ2_N, 0, 0, | |
4187 | /* IP12_5_3 [3] */ | |
4188 | FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B, | |
4189 | FN_CAN1_RX_C, FN_DACK1_B, 0, 0, | |
4190 | /* IP12_2_0 [3] */ | |
4191 | FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B, | |
4192 | FN_AD_NCS_N_B, FN_DREQ1_N_B, 0, 0, } | |
4193 | }, | |
4194 | { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, | |
4195 | 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) { | |
4196 | /* IP13_31 [1] */ | |
4197 | 0, 0, | |
4198 | /* IP13_30 [1] */ | |
4199 | 0, 0, | |
4200 | /* IP13_29 [1] */ | |
4201 | 0, 0, | |
4202 | /* IP13_28 [1] */ | |
4203 | 0, 0, | |
4204 | /* IP13_27 [1] */ | |
4205 | 0, 0, | |
4206 | /* IP13_26_24 [3] */ | |
4207 | FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, | |
4208 | FN_TS_SPSYNC_C, FN_RIF0_D1_B, FN_FMIN_E, FN_RDS_DATA_D, | |
4209 | /* IP13_23_21 [3] */ | |
4210 | FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, | |
4211 | FN_TS_SDEN_C, FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D, | |
4212 | /* IP13_20_18 [3] */ | |
4213 | FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD, | |
4214 | FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B, | |
4215 | /* IP13_17_15 [3] */ | |
4216 | FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB, | |
4217 | FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B, 0, | |
4218 | /* IP13_14_12 [3] */ | |
4219 | FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, | |
4220 | FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0, | |
4221 | /* IP13_11_9 [3] */ | |
4222 | FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, | |
4223 | FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0, | |
4224 | /* IP13_8_6 [3] */ | |
4225 | FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, | |
4226 | FN_MTS_N, FN_EX_WAIT1, FN_ETH_TXD1_B, 0, | |
4227 | /* IP13_5_3 [2] */ | |
4228 | FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, | |
4229 | FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B, 0, | |
4230 | /* IP13_2_0 [3] */ | |
4231 | FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, | |
4232 | FN_SCKZ, FN_ATACS00_N, FN_ETH_LINK_B, 0, } | |
4233 | }, | |
4234 | { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, | |
4235 | 2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, | |
4236 | 2, 1) { | |
4237 | /* SEL_ADG [2] */ | |
4238 | FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, | |
4239 | /* SEL_ADI [1] */ | |
4240 | FN_SEL_ADI_0, FN_SEL_ADI_1, | |
4241 | /* SEL_CAN [2] */ | |
4242 | FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3, | |
4243 | /* SEL_DARC [3] */ | |
4244 | FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3, | |
4245 | FN_SEL_DARC_4, 0, 0, 0, | |
4246 | /* SEL_DR0 [1] */ | |
4247 | FN_SEL_DR0_0, FN_SEL_DR0_1, | |
4248 | /* SEL_DR1 [1] */ | |
4249 | FN_SEL_DR1_0, FN_SEL_DR1_1, | |
4250 | /* SEL_DR2 [1] */ | |
4251 | FN_SEL_DR2_0, FN_SEL_DR2_1, | |
4252 | /* SEL_DR3 [1] */ | |
4253 | FN_SEL_DR3_0, FN_SEL_DR3_1, | |
4254 | /* SEL_ETH [1] */ | |
4255 | FN_SEL_ETH_0, FN_SEL_ETH_1, | |
4256 | /* SLE_FSN [1] */ | |
4257 | FN_SEL_FSN_0, FN_SEL_FSN_1, | |
4258 | /* SEL_IC200 [3] */ | |
4259 | FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, | |
4260 | FN_SEL_I2C00_4, 0, 0, 0, | |
4261 | /* SEL_I2C01 [3] */ | |
4262 | FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, | |
4263 | FN_SEL_I2C01_4, 0, 0, 0, | |
4264 | /* SEL_I2C02 [3] */ | |
4265 | FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, | |
4266 | FN_SEL_I2C02_4, 0, 0, 0, | |
4267 | /* SEL_I2C03 [3] */ | |
4268 | FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, | |
4269 | FN_SEL_I2C03_4, 0, 0, 0, | |
4270 | /* SEL_I2C04 [3] */ | |
4271 | FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, | |
4272 | FN_SEL_I2C04_4, 0, 0, 0, | |
4273 | /* SEL_IIC00 [2] */ | |
4274 | FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3, | |
4275 | /* SEL_AVB [1] */ | |
4276 | FN_SEL_AVB_0, FN_SEL_AVB_1, } | |
4277 | }, | |
4278 | { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, | |
4279 | 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, | |
4280 | 2, 2, 2, 1, 1, 2) { | |
4281 | /* SEL_IEB [2] */ | |
4282 | FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, | |
4283 | /* SEL_IIC0 [2] */ | |
4284 | FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, | |
4285 | /* SEL_LBS [1] */ | |
4286 | FN_SEL_LBS_0, FN_SEL_LBS_1, | |
4287 | /* SEL_MSI1 [1] */ | |
4288 | FN_SEL_MSI1_0, FN_SEL_MSI1_1, | |
4289 | /* SEL_MSI2 [1] */ | |
4290 | FN_SEL_MSI2_0, FN_SEL_MSI2_1, | |
4291 | /* SEL_RAD [1] */ | |
4292 | FN_SEL_RAD_0, FN_SEL_RAD_1, | |
4293 | /* SEL_RCN [1] */ | |
4294 | FN_SEL_RCN_0, FN_SEL_RCN_1, | |
4295 | /* SEL_RSP [1] */ | |
4296 | FN_SEL_RSP_0, FN_SEL_RSP_1, | |
4297 | /* SEL_SCIFA0 [2] */ | |
4298 | FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, | |
4299 | FN_SEL_SCIFA0_3, | |
4300 | /* SEL_SCIFA1 [2] */ | |
4301 | FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0, | |
4302 | /* SEL_SCIFA2 [1] */ | |
4303 | FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, | |
4304 | /* SEL_SCIFA3 [1] */ | |
4305 | FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, | |
4306 | /* SEL_SCIFA4 [2] */ | |
4307 | FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, | |
4308 | FN_SEL_SCIFA4_3, | |
4309 | /* SEL_SCIFA5 [2] */ | |
4310 | FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, | |
4311 | FN_SEL_SCIFA5_3, | |
4312 | /* SEL_SPDM [1] */ | |
4313 | FN_SEL_SPDM_0, FN_SEL_SPDM_1, | |
4314 | /* SEL_TMU [1] */ | |
4315 | FN_SEL_TMU_0, FN_SEL_TMU_1, | |
4316 | /* SEL_TSIF0 [2] */ | |
4317 | FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, | |
4318 | /* SEL_CAN0 [2] */ | |
4319 | FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, | |
4320 | /* SEL_CAN1 [2] */ | |
4321 | FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, | |
4322 | /* SEL_HSCIF0 [1] */ | |
4323 | FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, | |
4324 | /* SEL_HSCIF1 [1] */ | |
4325 | FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, | |
4326 | /* SEL_RDS [2] */ | |
4327 | FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, } | |
4328 | }, | |
4329 | { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, | |
4330 | 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, | |
4331 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { | |
4332 | /* SEL_SCIF0 [2] */ | |
4333 | FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, | |
4334 | /* SEL_SCIF1 [2] */ | |
4335 | FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0, | |
4336 | /* SEL_SCIF2 [2] */ | |
4337 | FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0, | |
4338 | /* SEL_SCIF3 [1] */ | |
4339 | FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, | |
4340 | /* SEL_SCIF4 [3] */ | |
4341 | FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, | |
4342 | FN_SEL_SCIF4_4, 0, 0, 0, | |
4343 | /* SEL_SCIF5 [2] */ | |
4344 | FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, | |
4345 | /* SEL_SSI1 [1] */ | |
4346 | FN_SEL_SSI1_0, FN_SEL_SSI1_1, | |
4347 | /* SEL_SSI2 [1] */ | |
4348 | FN_SEL_SSI2_0, FN_SEL_SSI2_1, | |
4349 | /* SEL_SSI4 [1] */ | |
4350 | FN_SEL_SSI4_0, FN_SEL_SSI4_1, | |
4351 | /* SEL_SSI5 [1] */ | |
4352 | FN_SEL_SSI5_0, FN_SEL_SSI5_1, | |
4353 | /* SEL_SSI6 [1] */ | |
4354 | FN_SEL_SSI6_0, FN_SEL_SSI6_1, | |
4355 | /* SEL_SSI7 [1] */ | |
4356 | FN_SEL_SSI7_0, FN_SEL_SSI7_1, | |
4357 | /* SEL_SSI8 [1] */ | |
4358 | FN_SEL_SSI8_0, FN_SEL_SSI8_1, | |
4359 | /* SEL_SSI9 [1] */ | |
4360 | FN_SEL_SSI9_0, FN_SEL_SSI9_1, | |
4361 | /* RESERVED [1] */ | |
4362 | 0, 0, | |
4363 | /* RESERVED [1] */ | |
4364 | 0, 0, | |
4365 | /* RESERVED [1] */ | |
4366 | 0, 0, | |
4367 | /* RESERVED [1] */ | |
4368 | 0, 0, | |
4369 | /* RESERVED [1] */ | |
4370 | 0, 0, | |
4371 | /* RESERVED [1] */ | |
4372 | 0, 0, | |
4373 | /* RESERVED [1] */ | |
4374 | 0, 0, | |
4375 | /* RESERVED [1] */ | |
4376 | 0, 0, | |
4377 | /* RESERVED [1] */ | |
4378 | 0, 0, | |
4379 | /* RESERVED [1] */ | |
4380 | 0, 0, | |
4381 | /* RESERVED [1] */ | |
4382 | 0, 0, | |
4383 | /* RESERVED [1] */ | |
4384 | 0, 0, } | |
4385 | }, | |
4386 | { }, | |
4387 | }; | |
4388 | ||
4389 | const struct sh_pfc_soc_info r8a7794_pinmux_info = { | |
4390 | .name = "r8a77940_pfc", | |
4391 | .unlock_reg = 0xe6060000, /* PMMR */ | |
4392 | ||
4393 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, | |
4394 | ||
4395 | .pins = pinmux_pins, | |
4396 | .nr_pins = ARRAY_SIZE(pinmux_pins), | |
4397 | .groups = pinmux_groups, | |
4398 | .nr_groups = ARRAY_SIZE(pinmux_groups), | |
4399 | .functions = pinmux_functions, | |
4400 | .nr_functions = ARRAY_SIZE(pinmux_functions), | |
4401 | ||
4402 | .cfg_regs = pinmux_config_regs, | |
4403 | ||
b8b47d67 GU |
4404 | .pinmux_data = pinmux_data, |
4405 | .pinmux_data_size = ARRAY_SIZE(pinmux_data), | |
43c4436e | 4406 | }; |