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fae43399 MD |
1 | /* |
2 | * SuperH Pin Function Controller Support | |
3 | * | |
4 | * Copyright (c) 2008 Magnus Damm | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | ||
11 | #ifndef __SH_PFC_H | |
12 | #define __SH_PFC_H | |
13 | ||
bf9f0674 | 14 | #include <linux/bug.h> |
5b9eaa56 | 15 | #include <linux/pinctrl/pinconf-generic.h> |
72c7afa1 | 16 | #include <linux/stringify.h> |
fae43399 | 17 | |
06d5631f PM |
18 | enum { |
19 | PINMUX_TYPE_NONE, | |
06d5631f PM |
20 | PINMUX_TYPE_FUNCTION, |
21 | PINMUX_TYPE_GPIO, | |
22 | PINMUX_TYPE_OUTPUT, | |
23 | PINMUX_TYPE_INPUT, | |
06d5631f | 24 | }; |
fae43399 | 25 | |
c58d9c1b LP |
26 | #define SH_PFC_PIN_CFG_INPUT (1 << 0) |
27 | #define SH_PFC_PIN_CFG_OUTPUT (1 << 1) | |
28 | #define SH_PFC_PIN_CFG_PULL_UP (1 << 2) | |
29 | #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) | |
5b9eaa56 | 30 | #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4) |
4f82e3ee | 31 | #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31) |
c58d9c1b | 32 | |
a3db40a6 | 33 | struct sh_pfc_pin { |
9689896c | 34 | u16 pin; |
533743dc | 35 | u16 enum_id; |
72c7afa1 | 36 | const char *name; |
c58d9c1b | 37 | unsigned int configs; |
fae43399 MD |
38 | }; |
39 | ||
3d8d9f1d LP |
40 | #define SH_PFC_PIN_GROUP(n) \ |
41 | { \ | |
42 | .name = #n, \ | |
43 | .pins = n##_pins, \ | |
44 | .mux = n##_mux, \ | |
45 | .nr_pins = ARRAY_SIZE(n##_pins), \ | |
46 | } | |
47 | ||
48 | struct sh_pfc_pin_group { | |
49 | const char *name; | |
50 | const unsigned int *pins; | |
51 | const unsigned int *mux; | |
52 | unsigned int nr_pins; | |
53 | }; | |
54 | ||
55 | #define SH_PFC_FUNCTION(n) \ | |
56 | { \ | |
57 | .name = #n, \ | |
58 | .groups = n##_groups, \ | |
59 | .nr_groups = ARRAY_SIZE(n##_groups), \ | |
60 | } | |
61 | ||
62 | struct sh_pfc_function { | |
63 | const char *name; | |
64 | const char * const *groups; | |
65 | unsigned int nr_groups; | |
66 | }; | |
67 | ||
a373ed0a | 68 | struct pinmux_func { |
533743dc | 69 | u16 enum_id; |
a373ed0a LP |
70 | const char *name; |
71 | }; | |
72 | ||
fae43399 | 73 | struct pinmux_cfg_reg { |
1f34de05 | 74 | u32 reg; |
dc700715 | 75 | u8 reg_width, field_width; |
533743dc | 76 | const u16 *enum_ids; |
dc700715 | 77 | const u8 *var_field_width; |
fae43399 MD |
78 | }; |
79 | ||
80 | #define PINMUX_CFG_REG(name, r, r_width, f_width) \ | |
81 | .reg = r, .reg_width = r_width, .field_width = f_width, \ | |
9aecff58 | 82 | .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) |
f78a26f5 MD |
83 | |
84 | #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ | |
85 | .reg = r, .reg_width = r_width, \ | |
dc700715 | 86 | .var_field_width = (const u8 [r_width]) \ |
9aecff58 LP |
87 | { var_fw0, var_fwn, 0 }, \ |
88 | .enum_ids = (const u16 []) | |
fae43399 MD |
89 | |
90 | struct pinmux_data_reg { | |
1f34de05 | 91 | u32 reg; |
dc700715 | 92 | u8 reg_width; |
533743dc | 93 | const u16 *enum_ids; |
fae43399 MD |
94 | }; |
95 | ||
96 | #define PINMUX_DATA_REG(name, r, r_width) \ | |
97 | .reg = r, .reg_width = r_width, \ | |
9aecff58 | 98 | .enum_ids = (const u16 [r_width]) \ |
fae43399 | 99 | |
ad2a8e7e MD |
100 | struct pinmux_irq { |
101 | int irq; | |
6d5bddd5 | 102 | const short *gpios; |
ad2a8e7e MD |
103 | }; |
104 | ||
0e26e8df LP |
105 | #ifdef CONFIG_ARCH_MULTIPLATFORM |
106 | #define PINMUX_IRQ(irq_nr, ids...) \ | |
107 | { .gpios = (const short []) { ids, -1 } } | |
108 | #else | |
ad2a8e7e | 109 | #define PINMUX_IRQ(irq_nr, ids...) \ |
6d5bddd5 | 110 | { .irq = irq_nr, .gpios = (const short []) { ids, -1 } } |
0e26e8df | 111 | #endif |
ad2a8e7e | 112 | |
fae43399 | 113 | struct pinmux_range { |
533743dc LP |
114 | u16 begin; |
115 | u16 end; | |
116 | u16 force; | |
fae43399 MD |
117 | }; |
118 | ||
c58d9c1b LP |
119 | struct sh_pfc; |
120 | ||
121 | struct sh_pfc_soc_operations { | |
0c151062 | 122 | int (*init)(struct sh_pfc *pfc); |
c58d9c1b LP |
123 | unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); |
124 | void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, | |
125 | unsigned int bias); | |
5b9eaa56 BH |
126 | int (*get_io_voltage)(struct sh_pfc *pfc, unsigned int pin); |
127 | int (*set_io_voltage)(struct sh_pfc *pfc, unsigned int pin, | |
128 | u16 voltage_mV); | |
c58d9c1b LP |
129 | }; |
130 | ||
19bb7fe3 | 131 | struct sh_pfc_soc_info { |
cd3c1bee | 132 | const char *name; |
c58d9c1b LP |
133 | const struct sh_pfc_soc_operations *ops; |
134 | ||
fae43399 | 135 | struct pinmux_range input; |
fae43399 | 136 | struct pinmux_range output; |
fae43399 MD |
137 | struct pinmux_range function; |
138 | ||
cd3c1bee | 139 | const struct sh_pfc_pin *pins; |
caa5bac3 | 140 | unsigned int nr_pins; |
3d8d9f1d LP |
141 | const struct sh_pfc_pin_group *groups; |
142 | unsigned int nr_groups; | |
143 | const struct sh_pfc_function *functions; | |
144 | unsigned int nr_functions; | |
145 | ||
cd3c1bee | 146 | const struct pinmux_func *func_gpios; |
a373ed0a | 147 | unsigned int nr_func_gpios; |
d7a7ca57 | 148 | |
cd3c1bee LP |
149 | const struct pinmux_cfg_reg *cfg_regs; |
150 | const struct pinmux_data_reg *data_regs; | |
fae43399 | 151 | |
533743dc | 152 | const u16 *gpio_data; |
fae43399 MD |
153 | unsigned int gpio_data_size; |
154 | ||
cd3c1bee | 155 | const struct pinmux_irq *gpio_irq; |
ad2a8e7e MD |
156 | unsigned int gpio_irq_size; |
157 | ||
1f34de05 | 158 | u32 unlock_reg; |
fae43399 MD |
159 | }; |
160 | ||
e3d93b46 LP |
161 | /* ----------------------------------------------------------------------------- |
162 | * Helper macros to create pin and port lists | |
163 | */ | |
164 | ||
165 | /* | |
166 | * sh_pfc_soc_info gpio_data array macros | |
167 | */ | |
168 | ||
169 | #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 | |
170 | ||
171 | #define PINMUX_IPSR_NOGP(ispr, fn) \ | |
172 | PINMUX_DATA(fn##_MARK, FN_##fn) | |
173 | #define PINMUX_IPSR_DATA(ipsr, fn) \ | |
174 | PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr) | |
175 | #define PINMUX_IPSR_NOGM(ispr, fn, ms) \ | |
176 | PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms) | |
4c9e4735 NS |
177 | #define PINMUX_IPSR_NOFN(ipsr, fn, ms) \ |
178 | PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##ms) | |
e3d93b46 LP |
179 | #define PINMUX_IPSR_MSEL(ipsr, fn, ms) \ |
180 | PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms) | |
181 | #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) \ | |
182 | PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn) | |
183 | ||
184 | /* | |
185 | * GP port style (32 ports banks) | |
186 | */ | |
187 | ||
188 | #define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx) | |
189 | ||
190 | #define PORT_GP_32(bank, fn, sfx) \ | |
191 | PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ | |
192 | PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ | |
193 | PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ | |
194 | PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ | |
195 | PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ | |
196 | PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ | |
197 | PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ | |
198 | PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ | |
199 | PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ | |
200 | PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ | |
201 | PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ | |
202 | PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ | |
203 | PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ | |
204 | PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ | |
205 | PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \ | |
206 | PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx) | |
207 | ||
208 | #define PORT_GP_32_REV(bank, fn, sfx) \ | |
209 | PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ | |
210 | PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \ | |
211 | PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \ | |
212 | PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \ | |
213 | PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \ | |
214 | PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \ | |
215 | PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \ | |
216 | PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \ | |
217 | PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \ | |
218 | PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \ | |
219 | PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \ | |
220 | PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \ | |
221 | PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \ | |
222 | PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \ | |
223 | PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \ | |
224 | PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) | |
225 | ||
226 | /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */ | |
227 | #define _GP_ALL(bank, pin, name, sfx) name##_##sfx | |
228 | #define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str) | |
229 | ||
230 | /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ | |
9689896c | 231 | #define _GP_GPIO(bank, _pin, _name, sfx) \ |
61bb3aef | 232 | { \ |
9689896c | 233 | .pin = (bank * 32) + _pin, \ |
e3d93b46 LP |
234 | .name = __stringify(_name), \ |
235 | .enum_id = _name##_DATA, \ | |
236 | } | |
237 | #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) | |
238 | ||
239 | /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */ | |
240 | #define _GP_DATA(bank, pin, name, sfx) PINMUX_DATA(name##_DATA, name##_FN) | |
241 | #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) | |
242 | ||
243 | /* | |
244 | * PORT style (linear pin space) | |
245 | */ | |
246 | ||
3ce0d7eb | 247 | #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx) |
16b915e4 LP |
248 | |
249 | #define PORT_10(pn, fn, pfx, sfx) \ | |
250 | PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \ | |
251 | PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \ | |
252 | PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \ | |
253 | PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \ | |
254 | PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx) | |
255 | ||
256 | #define PORT_90(pn, fn, pfx, sfx) \ | |
257 | PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \ | |
258 | PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \ | |
259 | PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \ | |
260 | PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \ | |
261 | PORT_10(pn+90, fn, pfx##9, sfx) | |
972c3fb6 | 262 | |
e3d93b46 | 263 | /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */ |
3ce0d7eb | 264 | #define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx |
e3d93b46 | 265 | #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) |
972c3fb6 | 266 | |
e3d93b46 | 267 | /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */ |
9689896c LP |
268 | #define PINMUX_GPIO(_pin) \ |
269 | [GPIO_##_pin] = { \ | |
270 | .pin = (u16)-1, \ | |
8620f394 | 271 | .name = __stringify(GPIO_##_pin), \ |
9689896c | 272 | .enum_id = _pin##_DATA, \ |
e3d93b46 LP |
273 | } |
274 | ||
df020272 | 275 | /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */ |
9689896c | 276 | #define SH_PFC_PIN_CFG(_pin, cfgs) \ |
df020272 | 277 | { \ |
9689896c LP |
278 | .pin = _pin, \ |
279 | .name = __stringify(PORT##_pin), \ | |
280 | .enum_id = PORT##_pin##_DATA, \ | |
df020272 LP |
281 | .configs = cfgs, \ |
282 | } | |
283 | ||
4f82e3ee LP |
284 | /* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */ |
285 | #define SH_PFC_PIN_NAMED(row, col, _name) \ | |
286 | { \ | |
287 | .pin = PIN_NUMBER(row, col), \ | |
288 | .name = __stringify(PIN_##_name), \ | |
289 | .configs = SH_PFC_PIN_CFG_NO_GPIO, \ | |
290 | } | |
291 | ||
e3d93b46 LP |
292 | /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0, |
293 | * PORT_name_OUT, PORT_name_IN marks | |
294 | */ | |
3ce0d7eb | 295 | #define _PORT_DATA(pn, pfx, sfx) \ |
e3d93b46 LP |
296 | PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \ |
297 | PORT##pfx##_OUT, PORT##pfx##_IN) | |
298 | #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) | |
299 | ||
300 | /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */ | |
301 | #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ | |
302 | [gpio - (base)] = { \ | |
303 | .name = __stringify(gpio), \ | |
304 | .enum_id = data_or_mark, \ | |
305 | } | |
306 | #define GPIO_FN(str) \ | |
307 | PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) | |
bd8d0cba | 308 | |
e3d93b46 LP |
309 | /* |
310 | * PORTnCR macro | |
311 | */ | |
9b49139b KM |
312 | #define PORTCR(nr, reg) \ |
313 | { \ | |
05c5f265 GU |
314 | PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\ |
315 | /* PULMD[1:0], handled by .set_bias() */ \ | |
316 | 0, 0, 0, 0, \ | |
317 | /* IE and OE */ \ | |
318 | 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \ | |
319 | /* SEC, not supported */ \ | |
320 | 0, 0, \ | |
321 | /* PTMD[2:0] */ \ | |
322 | PORT##nr##_FN0, PORT##nr##_FN1, \ | |
323 | PORT##nr##_FN2, PORT##nr##_FN3, \ | |
324 | PORT##nr##_FN4, PORT##nr##_FN5, \ | |
325 | PORT##nr##_FN6, PORT##nr##_FN7 \ | |
326 | } \ | |
9b49139b | 327 | } |
bd8d0cba | 328 | |
fae43399 | 329 | #endif /* __SH_PFC_H */ |