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fae43399 MD |
1 | /* |
2 | * SuperH Pin Function Controller Support | |
3 | * | |
4 | * Copyright (c) 2008 Magnus Damm | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | ||
11 | #ifndef __SH_PFC_H | |
12 | #define __SH_PFC_H | |
13 | ||
bf9f0674 | 14 | #include <linux/bug.h> |
72c7afa1 | 15 | #include <linux/stringify.h> |
fae43399 | 16 | |
06d5631f PM |
17 | enum { |
18 | PINMUX_TYPE_NONE, | |
06d5631f PM |
19 | PINMUX_TYPE_FUNCTION, |
20 | PINMUX_TYPE_GPIO, | |
21 | PINMUX_TYPE_OUTPUT, | |
22 | PINMUX_TYPE_INPUT, | |
06d5631f | 23 | }; |
fae43399 | 24 | |
c58d9c1b LP |
25 | #define SH_PFC_PIN_CFG_INPUT (1 << 0) |
26 | #define SH_PFC_PIN_CFG_OUTPUT (1 << 1) | |
27 | #define SH_PFC_PIN_CFG_PULL_UP (1 << 2) | |
28 | #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) | |
29 | ||
a3db40a6 | 30 | struct sh_pfc_pin { |
533743dc | 31 | u16 enum_id; |
72c7afa1 | 32 | const char *name; |
c58d9c1b | 33 | unsigned int configs; |
fae43399 MD |
34 | }; |
35 | ||
3d8d9f1d LP |
36 | #define SH_PFC_PIN_GROUP(n) \ |
37 | { \ | |
38 | .name = #n, \ | |
39 | .pins = n##_pins, \ | |
40 | .mux = n##_mux, \ | |
41 | .nr_pins = ARRAY_SIZE(n##_pins), \ | |
42 | } | |
43 | ||
44 | struct sh_pfc_pin_group { | |
45 | const char *name; | |
46 | const unsigned int *pins; | |
47 | const unsigned int *mux; | |
48 | unsigned int nr_pins; | |
49 | }; | |
50 | ||
51 | #define SH_PFC_FUNCTION(n) \ | |
52 | { \ | |
53 | .name = #n, \ | |
54 | .groups = n##_groups, \ | |
55 | .nr_groups = ARRAY_SIZE(n##_groups), \ | |
56 | } | |
57 | ||
58 | struct sh_pfc_function { | |
59 | const char *name; | |
60 | const char * const *groups; | |
61 | unsigned int nr_groups; | |
62 | }; | |
63 | ||
a373ed0a | 64 | struct pinmux_func { |
533743dc | 65 | u16 enum_id; |
a373ed0a LP |
66 | const char *name; |
67 | }; | |
68 | ||
380c2ed9 LP |
69 | #define PINMUX_GPIO(gpio, data_or_mark) \ |
70 | [gpio] = { \ | |
71 | .name = __stringify(gpio), \ | |
72 | .enum_id = data_or_mark, \ | |
380c2ed9 | 73 | } |
a373ed0a LP |
74 | #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ |
75 | [gpio - (base)] = { \ | |
380c2ed9 LP |
76 | .name = __stringify(gpio), \ |
77 | .enum_id = data_or_mark, \ | |
380c2ed9 | 78 | } |
06d5631f | 79 | |
fae43399 MD |
80 | #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 |
81 | ||
82 | struct pinmux_cfg_reg { | |
83 | unsigned long reg, reg_width, field_width; | |
533743dc | 84 | const u16 *enum_ids; |
cd3c1bee | 85 | const unsigned long *var_field_width; |
fae43399 MD |
86 | }; |
87 | ||
88 | #define PINMUX_CFG_REG(name, r, r_width, f_width) \ | |
89 | .reg = r, .reg_width = r_width, .field_width = f_width, \ | |
533743dc | 90 | .enum_ids = (u16 [(r_width / f_width) * (1 << f_width)]) |
f78a26f5 MD |
91 | |
92 | #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ | |
93 | .reg = r, .reg_width = r_width, \ | |
f78a26f5 | 94 | .var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \ |
533743dc | 95 | .enum_ids = (u16 []) |
fae43399 MD |
96 | |
97 | struct pinmux_data_reg { | |
51cb226b | 98 | unsigned long reg, reg_width; |
533743dc | 99 | const u16 *enum_ids; |
fae43399 MD |
100 | }; |
101 | ||
102 | #define PINMUX_DATA_REG(name, r, r_width) \ | |
103 | .reg = r, .reg_width = r_width, \ | |
533743dc | 104 | .enum_ids = (u16 [r_width]) \ |
fae43399 | 105 | |
ad2a8e7e MD |
106 | struct pinmux_irq { |
107 | int irq; | |
c07f54f6 | 108 | unsigned short *gpios; |
ad2a8e7e MD |
109 | }; |
110 | ||
111 | #define PINMUX_IRQ(irq_nr, ids...) \ | |
c07f54f6 | 112 | { .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } } \ |
ad2a8e7e | 113 | |
fae43399 | 114 | struct pinmux_range { |
533743dc LP |
115 | u16 begin; |
116 | u16 end; | |
117 | u16 force; | |
fae43399 MD |
118 | }; |
119 | ||
c58d9c1b LP |
120 | struct sh_pfc; |
121 | ||
122 | struct sh_pfc_soc_operations { | |
0c151062 LP |
123 | int (*init)(struct sh_pfc *pfc); |
124 | void (*exit)(struct sh_pfc *pfc); | |
c58d9c1b LP |
125 | unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); |
126 | void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, | |
127 | unsigned int bias); | |
128 | }; | |
129 | ||
19bb7fe3 | 130 | struct sh_pfc_soc_info { |
cd3c1bee | 131 | const char *name; |
c58d9c1b LP |
132 | const struct sh_pfc_soc_operations *ops; |
133 | ||
fae43399 | 134 | struct pinmux_range input; |
fae43399 | 135 | struct pinmux_range output; |
fae43399 MD |
136 | struct pinmux_range function; |
137 | ||
cd3c1bee | 138 | const struct sh_pfc_pin *pins; |
caa5bac3 | 139 | unsigned int nr_pins; |
63d57383 LP |
140 | const struct pinmux_range *ranges; |
141 | unsigned int nr_ranges; | |
3d8d9f1d LP |
142 | const struct sh_pfc_pin_group *groups; |
143 | unsigned int nr_groups; | |
144 | const struct sh_pfc_function *functions; | |
145 | unsigned int nr_functions; | |
146 | ||
cd3c1bee | 147 | const struct pinmux_func *func_gpios; |
a373ed0a | 148 | unsigned int nr_func_gpios; |
d7a7ca57 | 149 | |
cd3c1bee LP |
150 | const struct pinmux_cfg_reg *cfg_regs; |
151 | const struct pinmux_data_reg *data_regs; | |
fae43399 | 152 | |
533743dc | 153 | const u16 *gpio_data; |
fae43399 MD |
154 | unsigned int gpio_data_size; |
155 | ||
cd3c1bee | 156 | const struct pinmux_irq *gpio_irq; |
ad2a8e7e MD |
157 | unsigned int gpio_irq_size; |
158 | ||
e499ada8 | 159 | unsigned long unlock_reg; |
fae43399 MD |
160 | }; |
161 | ||
972c3fb6 KM |
162 | /* helper macro for port */ |
163 | #define PORT_1(fn, pfx, sfx) fn(pfx, sfx) | |
164 | ||
165 | #define PORT_10(fn, pfx, sfx) \ | |
166 | PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ | |
167 | PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ | |
168 | PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \ | |
169 | PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ | |
170 | PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx) | |
171 | ||
17dffe48 LP |
172 | #define PORT_10_REV(fn, pfx, sfx) \ |
173 | PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ | |
174 | PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ | |
175 | PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ | |
176 | PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ | |
177 | PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) | |
178 | ||
179 | #define PORT_32(fn, pfx, sfx) \ | |
180 | PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ | |
181 | PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ | |
182 | PORT_1(fn, pfx##31, sfx) | |
183 | ||
184 | #define PORT_32_REV(fn, pfx, sfx) \ | |
185 | PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ | |
186 | PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ | |
187 | PORT_10_REV(fn, pfx, sfx) | |
188 | ||
972c3fb6 KM |
189 | #define PORT_90(fn, pfx, sfx) \ |
190 | PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \ | |
191 | PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \ | |
192 | PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx), \ | |
193 | PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx), \ | |
194 | PORT_10(fn, pfx##9, sfx) | |
195 | ||
196 | #define _PORT_ALL(pfx, sfx) pfx##_##sfx | |
972c3fb6 | 197 | #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) |
a373ed0a | 198 | #define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) |
972c3fb6 | 199 | |
533743dc | 200 | /* helper macro for pinmux data arrays */ |
bd8d0cba KM |
201 | #define PORT_DATA_IO(nr) \ |
202 | PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ | |
203 | PORT##nr##_IN) | |
204 | ||
9b49139b KM |
205 | /* helper macro for top 4 bits in PORTnCR */ |
206 | #define _PCRH(in, in_pd, in_pu, out) \ | |
207 | 0, (out), (in), 0, \ | |
208 | 0, 0, 0, 0, \ | |
209 | 0, 0, (in_pd), 0, \ | |
210 | 0, 0, (in_pu), 0 | |
211 | ||
212 | #define PORTCR(nr, reg) \ | |
213 | { \ | |
214 | PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ | |
215 | _PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \ | |
216 | PORT##nr##_IN_PU, PORT##nr##_OUT), \ | |
217 | PORT##nr##_FN0, PORT##nr##_FN1, \ | |
218 | PORT##nr##_FN2, PORT##nr##_FN3, \ | |
219 | PORT##nr##_FN4, PORT##nr##_FN5, \ | |
220 | PORT##nr##_FN6, PORT##nr##_FN7 } \ | |
221 | } | |
bd8d0cba | 222 | |
fae43399 | 223 | #endif /* __SH_PFC_H */ |