[deliverable/linux.git] / drivers / pinctrl / sh-pfc / sh_pfc.h

/*
 * SuperH Pin Function Controller Support
 *
 * Copyright (c) 2008 Magnus Damm
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#ifndef __SH_PFC_H
#define __SH_PFC_H

#include <linux/stringify.h>
#include <asm-generic/gpio.h>

typedef unsigned short pinmux_enum_t;

enum {
	PINMUX_TYPE_NONE,

	PINMUX_TYPE_FUNCTION,
	PINMUX_TYPE_GPIO,
	PINMUX_TYPE_OUTPUT,
	PINMUX_TYPE_INPUT,
	PINMUX_TYPE_INPUT_PULLUP,
	PINMUX_TYPE_INPUT_PULLDOWN,

	PINMUX_FLAG_TYPE,	/* must be last */
};

#define PINMUX_FLAG_DBIT_SHIFT      5
#define PINMUX_FLAG_DBIT            (0x1f << PINMUX_FLAG_DBIT_SHIFT)
#define PINMUX_FLAG_DREG_SHIFT      10
#define PINMUX_FLAG_DREG            (0x3f << PINMUX_FLAG_DREG_SHIFT)

struct sh_pfc_pin {
	const pinmux_enum_t enum_id;
	unsigned short flags;
	const char *name;
};

struct pinmux_func {
	const pinmux_enum_t enum_id;
	const char *name;
};

#define PINMUX_GPIO(gpio, data_or_mark)			\
	[gpio] = {					\
		.name = __stringify(gpio),		\
		.enum_id = data_or_mark,		\
		.flags = PINMUX_TYPE_GPIO		\
	}
#define PINMUX_GPIO_FN(gpio, base, data_or_mark)	\
	[gpio - (base)] = {				\
		.name = __stringify(gpio),		\
		.enum_id = data_or_mark,		\
	}

#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0

struct pinmux_cfg_reg {
	unsigned long reg, reg_width, field_width;
	unsigned long *cnt;
	pinmux_enum_t *enum_ids;
	unsigned long *var_field_width;
};

#define PINMUX_CFG_REG(name, r, r_width, f_width) \
	.reg = r, .reg_width = r_width, .field_width = f_width,		\
	.cnt = (unsigned long [r_width / f_width]) {}, \
	.enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])

#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
	.reg = r, .reg_width = r_width,	\
	.cnt = (unsigned long [r_width]) {}, \
	.var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
	.enum_ids = (pinmux_enum_t [])

struct pinmux_data_reg {
	unsigned long reg, reg_width, reg_shadow;
	pinmux_enum_t *enum_ids;
	void __iomem *mapped_reg;
};

#define PINMUX_DATA_REG(name, r, r_width) \
	.reg = r, .reg_width = r_width,	\
	.enum_ids = (pinmux_enum_t [r_width]) \

struct pinmux_irq {
	int irq;
	unsigned short *gpios;
};

#define PINMUX_IRQ(irq_nr, ids...)			   \
	{ .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } }	\

struct pinmux_range {
	pinmux_enum_t begin;
	pinmux_enum_t end;
	pinmux_enum_t force;
};

struct sh_pfc_soc_info {
	char *name;
	struct pinmux_range input;
	struct pinmux_range input_pd;
	struct pinmux_range input_pu;
	struct pinmux_range output;
	struct pinmux_range function;

	struct sh_pfc_pin *pins;
	unsigned int nr_pins;
	const struct pinmux_range *ranges;
	unsigned int nr_ranges;
	struct pinmux_func *func_gpios;
	unsigned int nr_func_gpios;

	struct pinmux_cfg_reg *cfg_regs;
	struct pinmux_data_reg *data_regs;

	pinmux_enum_t *gpio_data;
	unsigned int gpio_data_size;

	struct pinmux_irq *gpio_irq;
	unsigned int gpio_irq_size;

	unsigned long unlock_reg;
};

enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };

/* helper macro for port */
#define PORT_1(fn, pfx, sfx) fn(pfx, sfx)

#define PORT_10(fn, pfx, sfx) \
	PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx),	\
	PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx),	\
	PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx),	\
	PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx),	\
	PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)

#define PORT_10_REV(fn, pfx, sfx)	\
	PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx),	\
	PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx),	\
	PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx),	\
	PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx),	\
	PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)

#define PORT_32(fn, pfx, sfx)					\
	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
	PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx),	\
	PORT_1(fn, pfx##31, sfx)

#define PORT_32_REV(fn, pfx, sfx)					\
	PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx),		\
	PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx),	\
	PORT_10_REV(fn, pfx, sfx)

#define PORT_90(fn, pfx, sfx) \
	PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx),	\
	PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx),	\
	PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx),	\
	PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx),	\
	PORT_10(fn, pfx##9, sfx)

#define _PORT_ALL(pfx, sfx) pfx##_##sfx
#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
#define PORT_ALL(str)	CPU_ALL_PORT(_PORT_ALL, PORT, str)
#define GPIO_PORT_ALL()	CPU_ALL_PORT(_GPIO_PORT, , unused)
#define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)

/* helper macro for pinmux_enum_t */
#define PORT_DATA_I(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)

#define PORT_DATA_I_PD(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,	\
		    PORT##nr##_IN, PORT##nr##_IN_PD)

#define PORT_DATA_I_PU(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,	\
		    PORT##nr##_IN, PORT##nr##_IN_PU)

#define PORT_DATA_I_PU_PD(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,			\
		    PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)

#define PORT_DATA_O(nr)		\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)

#define PORT_DATA_IO(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
		    PORT##nr##_IN)

#define PORT_DATA_IO_PD(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
		    PORT##nr##_IN, PORT##nr##_IN_PD)

#define PORT_DATA_IO_PU(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
		    PORT##nr##_IN, PORT##nr##_IN_PU)

#define PORT_DATA_IO_PU_PD(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
		    PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)

/* helper macro for top 4 bits in PORTnCR */
#define _PCRH(in, in_pd, in_pu, out)	\
	0, (out), (in), 0,		\
	0, 0, 0, 0,			\
	0, 0, (in_pd), 0,		\
	0, 0, (in_pu), 0

#define PORTCR(nr, reg)							\
	{								\
		PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {		\
			_PCRH(PORT##nr##_IN, PORT##nr##_IN_PD,		\
			      PORT##nr##_IN_PU, PORT##nr##_OUT),	\
				PORT##nr##_FN0, PORT##nr##_FN1,		\
				PORT##nr##_FN2, PORT##nr##_FN3,		\
				PORT##nr##_FN4, PORT##nr##_FN5,		\
				PORT##nr##_FN6, PORT##nr##_FN7 }	\
	}

#endif /* __SH_PFC_H */
Commit	Line	Data
fae43399 MD	1	/*
	2	* SuperH Pin Function Controller Support
	3	*
	4	* Copyright (c) 2008 Magnus Damm
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10
	11	#ifndef __SH_PFC_H
	12	#define __SH_PFC_H
	13
72c7afa1	14	#include <linux/stringify.h>
fae43399 MD	15	#include <asm-generic/gpio.h>
	16
	17	typedef unsigned short pinmux_enum_t;
fae43399	18
06d5631f PM	19	enum {
06d5631f PM	20	PINMUX_TYPE_NONE,
fae43399	21
06d5631f PM	22	PINMUX_TYPE_FUNCTION,
	23	PINMUX_TYPE_GPIO,
	24	PINMUX_TYPE_OUTPUT,
	25	PINMUX_TYPE_INPUT,
	26	PINMUX_TYPE_INPUT_PULLUP,
	27	PINMUX_TYPE_INPUT_PULLDOWN,
	28
	29	PINMUX_FLAG_TYPE, /* must be last */
	30	};
fae43399 MD	31
	32	#define PINMUX_FLAG_DBIT_SHIFT 5
	33	#define PINMUX_FLAG_DBIT (0x1f << PINMUX_FLAG_DBIT_SHIFT)
	34	#define PINMUX_FLAG_DREG_SHIFT 10
	35	#define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT)
	36
a3db40a6	37	struct sh_pfc_pin {
051fae4b	38	const pinmux_enum_t enum_id;
a3db40a6	39	unsigned short flags;
72c7afa1	40	const char *name;
fae43399 MD	41	};
fae43399 MD	42
a373ed0a LP	43	struct pinmux_func {
	44	const pinmux_enum_t enum_id;
	45	const char *name;
	46	};
	47
380c2ed9 LP	48	#define PINMUX_GPIO(gpio, data_or_mark) \
	49	[gpio] = { \
	50	.name = __stringify(gpio), \
	51	.enum_id = data_or_mark, \
	52	.flags = PINMUX_TYPE_GPIO \
	53	}
a373ed0a LP	54	#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
a373ed0a LP	55	[gpio - (base)] = { \
380c2ed9 LP	56	.name = __stringify(gpio), \
380c2ed9 LP	57	.enum_id = data_or_mark, \
380c2ed9	58	}
06d5631f	59
fae43399 MD	60	#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
	61
	62	struct pinmux_cfg_reg {
	63	unsigned long reg, reg_width, field_width;
	64	unsigned long *cnt;
	65	pinmux_enum_t *enum_ids;
f78a26f5	66	unsigned long *var_field_width;
fae43399 MD	67	};
	68
	69	#define PINMUX_CFG_REG(name, r, r_width, f_width) \
	70	.reg = r, .reg_width = r_width, .field_width = f_width, \
	71	.cnt = (unsigned long [r_width / f_width]) {}, \
f78a26f5 MD	72	.enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])
	73
	74	#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
	75	.reg = r, .reg_width = r_width, \
	76	.cnt = (unsigned long [r_width]) {}, \
	77	.var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
	78	.enum_ids = (pinmux_enum_t [])
fae43399 MD	79
	80	struct pinmux_data_reg {
	81	unsigned long reg, reg_width, reg_shadow;
	82	pinmux_enum_t *enum_ids;
b0e10211	83	void __iomem *mapped_reg;
fae43399 MD	84	};
	85
	86	#define PINMUX_DATA_REG(name, r, r_width) \
	87	.reg = r, .reg_width = r_width, \
	88	.enum_ids = (pinmux_enum_t [r_width]) \
	89
ad2a8e7e MD	90	struct pinmux_irq {
ad2a8e7e MD	91	int irq;
c07f54f6	92	unsigned short *gpios;
ad2a8e7e MD	93	};
	94
	95	#define PINMUX_IRQ(irq_nr, ids...) \
c07f54f6	96	{ .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } } \
ad2a8e7e	97
fae43399 MD	98	struct pinmux_range {
	99	pinmux_enum_t begin;
	100	pinmux_enum_t end;
	101	pinmux_enum_t force;
	102	};
	103
19bb7fe3	104	struct sh_pfc_soc_info {
fae43399	105	char *name;
fae43399 MD	106	struct pinmux_range input;
	107	struct pinmux_range input_pd;
	108	struct pinmux_range input_pu;
	109	struct pinmux_range output;
fae43399 MD	110	struct pinmux_range function;
fae43399 MD	111
a3db40a6	112	struct sh_pfc_pin *pins;
caa5bac3	113	unsigned int nr_pins;
63d57383 LP	114	const struct pinmux_range *ranges;
63d57383 LP	115	unsigned int nr_ranges;
a373ed0a LP	116	struct pinmux_func *func_gpios;
a373ed0a LP	117	unsigned int nr_func_gpios;
d7a7ca57	118
fae43399 MD	119	struct pinmux_cfg_reg *cfg_regs;
	120	struct pinmux_data_reg *data_regs;
	121
	122	pinmux_enum_t *gpio_data;
	123	unsigned int gpio_data_size;
	124
ad2a8e7e MD	125	struct pinmux_irq *gpio_irq;
	126	unsigned int gpio_irq_size;
	127
e499ada8	128	unsigned long unlock_reg;
fae43399 MD	129	};
fae43399 MD	130
b3c185a7	131	enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
fae43399	132
972c3fb6 KM	133	/* helper macro for port */
	134	#define PORT_1(fn, pfx, sfx) fn(pfx, sfx)
	135
	136	#define PORT_10(fn, pfx, sfx) \
	137	PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
	138	PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
	139	PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \
	140	PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
	141	PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)
	142
17dffe48 LP	143	#define PORT_10_REV(fn, pfx, sfx) \
	144	PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
	145	PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
	146	PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
	147	PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
	148	PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
	149
	150	#define PORT_32(fn, pfx, sfx) \
	151	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
	152	PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
	153	PORT_1(fn, pfx##31, sfx)
	154
	155	#define PORT_32_REV(fn, pfx, sfx) \
	156	PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
	157	PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
	158	PORT_10_REV(fn, pfx, sfx)
	159
972c3fb6 KM	160	#define PORT_90(fn, pfx, sfx) \
	161	PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \
	162	PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \
	163	PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx), \
	164	PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx), \
	165	PORT_10(fn, pfx##9, sfx)
	166
	167	#define _PORT_ALL(pfx, sfx) pfx##_##sfx
	168	#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
	169	#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
	170	#define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused)
a373ed0a	171	#define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
972c3fb6	172
bd8d0cba KM	173	/* helper macro for pinmux_enum_t */
	174	#define PORT_DATA_I(nr) \
	175	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
	176
	177	#define PORT_DATA_I_PD(nr) \
	178	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
	179	PORT##nr##_IN, PORT##nr##_IN_PD)
	180
	181	#define PORT_DATA_I_PU(nr) \
	182	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
	183	PORT##nr##_IN, PORT##nr##_IN_PU)
	184
	185	#define PORT_DATA_I_PU_PD(nr) \
	186	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
	187	PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
	188
	189	#define PORT_DATA_O(nr) \
	190	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)
	191
	192	#define PORT_DATA_IO(nr) \
	193	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
	194	PORT##nr##_IN)
	195
	196	#define PORT_DATA_IO_PD(nr) \
	197	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
	198	PORT##nr##_IN, PORT##nr##_IN_PD)
	199
	200	#define PORT_DATA_IO_PU(nr) \
	201	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
	202	PORT##nr##_IN, PORT##nr##_IN_PU)
	203
	204	#define PORT_DATA_IO_PU_PD(nr) \
	205	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
	206	PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
	207
9b49139b KM	208	/* helper macro for top 4 bits in PORTnCR */
	209	#define _PCRH(in, in_pd, in_pu, out) \
	210	0, (out), (in), 0, \
	211	0, 0, 0, 0, \
	212	0, 0, (in_pd), 0, \
	213	0, 0, (in_pu), 0
	214
	215	#define PORTCR(nr, reg) \
	216	{ \
	217	PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
	218	_PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \
	219	PORT##nr##_IN_PU, PORT##nr##_OUT), \
	220	PORT##nr##_FN0, PORT##nr##_FN1, \
	221	PORT##nr##_FN2, PORT##nr##_FN3, \
	222	PORT##nr##_FN4, PORT##nr##_FN5, \
	223	PORT##nr##_FN6, PORT##nr##_FN7 } \
	224	}
bd8d0cba	225
fae43399	226	#endif /* __SH_PFC_H */