[deliverable/linux.git] / drivers / pinctrl / sh-pfc / sh_pfc.h

/*
 * SuperH Pin Function Controller Support
 *
 * Copyright (c) 2008 Magnus Damm
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#ifndef __SH_PFC_H
#define __SH_PFC_H

#include <linux/stringify.h>
#include <asm-generic/gpio.h>

typedef unsigned short pinmux_enum_t;

#define SH_PFC_MARK_INVALID	((pinmux_enum_t)-1)

enum {
	PINMUX_TYPE_NONE,

	PINMUX_TYPE_FUNCTION,
	PINMUX_TYPE_GPIO,
	PINMUX_TYPE_OUTPUT,
	PINMUX_TYPE_INPUT,
	PINMUX_TYPE_INPUT_PULLUP,
	PINMUX_TYPE_INPUT_PULLDOWN,

	PINMUX_FLAG_TYPE,	/* must be last */
};

struct sh_pfc_pin {
	const pinmux_enum_t enum_id;
	const char *name;
};

#define SH_PFC_PIN_GROUP(n)				\
	{						\
		.name = #n,				\
		.pins = n##_pins,			\
		.mux = n##_mux,				\
		.nr_pins = ARRAY_SIZE(n##_pins),	\
	}

struct sh_pfc_pin_group {
	const char *name;
	const unsigned int *pins;
	const unsigned int *mux;
	unsigned int nr_pins;
};

#define SH_PFC_FUNCTION(n)				\
	{						\
		.name = #n,				\
		.groups = n##_groups,			\
		.nr_groups = ARRAY_SIZE(n##_groups),	\
	}

struct sh_pfc_function {
	const char *name;
	const char * const *groups;
	unsigned int nr_groups;
};

struct pinmux_func {
	const pinmux_enum_t enum_id;
	const char *name;
};

#define PINMUX_GPIO(gpio, data_or_mark)			\
	[gpio] = {					\
		.name = __stringify(gpio),		\
		.enum_id = data_or_mark,		\
	}
#define PINMUX_GPIO_FN(gpio, base, data_or_mark)	\
	[gpio - (base)] = {				\
		.name = __stringify(gpio),		\
		.enum_id = data_or_mark,		\
	}

#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0

struct pinmux_cfg_reg {
	unsigned long reg, reg_width, field_width;
	pinmux_enum_t *enum_ids;
	unsigned long *var_field_width;
};

#define PINMUX_CFG_REG(name, r, r_width, f_width) \
	.reg = r, .reg_width = r_width, .field_width = f_width,		\
	.enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])

#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
	.reg = r, .reg_width = r_width,	\
	.var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
	.enum_ids = (pinmux_enum_t [])

struct pinmux_data_reg {
	unsigned long reg, reg_width;
	pinmux_enum_t *enum_ids;
};

#define PINMUX_DATA_REG(name, r, r_width) \
	.reg = r, .reg_width = r_width,	\
	.enum_ids = (pinmux_enum_t [r_width]) \

struct pinmux_irq {
	int irq;
	unsigned short *gpios;
};

#define PINMUX_IRQ(irq_nr, ids...)			   \
	{ .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } }	\

struct pinmux_range {
	pinmux_enum_t begin;
	pinmux_enum_t end;
	pinmux_enum_t force;
};

struct sh_pfc_soc_info {
	char *name;
	struct pinmux_range input;
	struct pinmux_range input_pd;
	struct pinmux_range input_pu;
	struct pinmux_range output;
	struct pinmux_range function;

	struct sh_pfc_pin *pins;
	unsigned int nr_pins;
	const struct pinmux_range *ranges;
	unsigned int nr_ranges;
	const struct sh_pfc_pin_group *groups;
	unsigned int nr_groups;
	const struct sh_pfc_function *functions;
	unsigned int nr_functions;

	struct pinmux_func *func_gpios;
	unsigned int nr_func_gpios;

	struct pinmux_cfg_reg *cfg_regs;
	struct pinmux_data_reg *data_regs;

	pinmux_enum_t *gpio_data;
	unsigned int gpio_data_size;

	struct pinmux_irq *gpio_irq;
	unsigned int gpio_irq_size;

	unsigned long unlock_reg;
};

enum { GPIO_CFG_REQ, GPIO_CFG_FREE };

/* helper macro for port */
#define PORT_1(fn, pfx, sfx) fn(pfx, sfx)

#define PORT_10(fn, pfx, sfx) \
	PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx),	\
	PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx),	\
	PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx),	\
	PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx),	\
	PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)

#define PORT_10_REV(fn, pfx, sfx)	\
	PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx),	\
	PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx),	\
	PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx),	\
	PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx),	\
	PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)

#define PORT_32(fn, pfx, sfx)					\
	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
	PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx),	\
	PORT_1(fn, pfx##31, sfx)

#define PORT_32_REV(fn, pfx, sfx)					\
	PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx),		\
	PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx),	\
	PORT_10_REV(fn, pfx, sfx)

#define PORT_90(fn, pfx, sfx) \
	PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx),	\
	PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx),	\
	PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx),	\
	PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx),	\
	PORT_10(fn, pfx##9, sfx)

#define _PORT_ALL(pfx, sfx) pfx##_##sfx
#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
#define PORT_ALL(str)	CPU_ALL_PORT(_PORT_ALL, PORT, str)
#define GPIO_PORT_ALL()	CPU_ALL_PORT(_GPIO_PORT, , unused)
#define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)

/* helper macro for pinmux_enum_t */
#define PORT_DATA_I(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)

#define PORT_DATA_I_PD(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,	\
		    PORT##nr##_IN, PORT##nr##_IN_PD)

#define PORT_DATA_I_PU(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,	\
		    PORT##nr##_IN, PORT##nr##_IN_PU)

#define PORT_DATA_I_PU_PD(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,			\
		    PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)

#define PORT_DATA_O(nr)		\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)

#define PORT_DATA_IO(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
		    PORT##nr##_IN)

#define PORT_DATA_IO_PD(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
		    PORT##nr##_IN, PORT##nr##_IN_PD)

#define PORT_DATA_IO_PU(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
		    PORT##nr##_IN, PORT##nr##_IN_PU)

#define PORT_DATA_IO_PU_PD(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
		    PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)

/* helper macro for top 4 bits in PORTnCR */
#define _PCRH(in, in_pd, in_pu, out)	\
	0, (out), (in), 0,		\
	0, 0, 0, 0,			\
	0, 0, (in_pd), 0,		\
	0, 0, (in_pu), 0

#define PORTCR(nr, reg)							\
	{								\
		PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {		\
			_PCRH(PORT##nr##_IN, PORT##nr##_IN_PD,		\
			      PORT##nr##_IN_PU, PORT##nr##_OUT),	\
				PORT##nr##_FN0, PORT##nr##_FN1,		\
				PORT##nr##_FN2, PORT##nr##_FN3,		\
				PORT##nr##_FN4, PORT##nr##_FN5,		\
				PORT##nr##_FN6, PORT##nr##_FN7 }	\
	}

#endif /* __SH_PFC_H */
Commit	Line	Data
fae43399 MD	1	/*
	2	* SuperH Pin Function Controller Support
	3	*
	4	* Copyright (c) 2008 Magnus Damm
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10
	11	#ifndef __SH_PFC_H
	12	#define __SH_PFC_H
	13
72c7afa1	14	#include <linux/stringify.h>
fae43399 MD	15	#include <asm-generic/gpio.h>
	16
	17	typedef unsigned short pinmux_enum_t;
fae43399	18
3d8d9f1d LP	19	#define SH_PFC_MARK_INVALID ((pinmux_enum_t)-1)
3d8d9f1d LP	20
06d5631f PM	21	enum {
06d5631f PM	22	PINMUX_TYPE_NONE,
fae43399	23
06d5631f PM	24	PINMUX_TYPE_FUNCTION,
	25	PINMUX_TYPE_GPIO,
	26	PINMUX_TYPE_OUTPUT,
	27	PINMUX_TYPE_INPUT,
	28	PINMUX_TYPE_INPUT_PULLUP,
	29	PINMUX_TYPE_INPUT_PULLDOWN,
	30
	31	PINMUX_FLAG_TYPE, /* must be last */
	32	};
fae43399	33
a3db40a6	34	struct sh_pfc_pin {
051fae4b	35	const pinmux_enum_t enum_id;
72c7afa1	36	const char *name;
fae43399 MD	37	};
fae43399 MD	38
3d8d9f1d LP	39	#define SH_PFC_PIN_GROUP(n) \
	40	{ \
	41	.name = #n, \
	42	.pins = n##_pins, \
	43	.mux = n##_mux, \
	44	.nr_pins = ARRAY_SIZE(n##_pins), \
	45	}
	46
	47	struct sh_pfc_pin_group {
	48	const char *name;
	49	const unsigned int *pins;
	50	const unsigned int *mux;
	51	unsigned int nr_pins;
	52	};
	53
	54	#define SH_PFC_FUNCTION(n) \
	55	{ \
	56	.name = #n, \
	57	.groups = n##_groups, \
	58	.nr_groups = ARRAY_SIZE(n##_groups), \
	59	}
	60
	61	struct sh_pfc_function {
	62	const char *name;
	63	const char * const *groups;
	64	unsigned int nr_groups;
	65	};
	66
a373ed0a LP	67	struct pinmux_func {
	68	const pinmux_enum_t enum_id;
	69	const char *name;
	70	};
	71
380c2ed9 LP	72	#define PINMUX_GPIO(gpio, data_or_mark) \
	73	[gpio] = { \
	74	.name = __stringify(gpio), \
	75	.enum_id = data_or_mark, \
380c2ed9	76	}
a373ed0a LP	77	#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
a373ed0a LP	78	[gpio - (base)] = { \
380c2ed9 LP	79	.name = __stringify(gpio), \
380c2ed9 LP	80	.enum_id = data_or_mark, \
380c2ed9	81	}
06d5631f	82
fae43399 MD	83	#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
	84
	85	struct pinmux_cfg_reg {
	86	unsigned long reg, reg_width, field_width;
fae43399	87	pinmux_enum_t *enum_ids;
f78a26f5	88	unsigned long *var_field_width;
fae43399 MD	89	};
	90
	91	#define PINMUX_CFG_REG(name, r, r_width, f_width) \
	92	.reg = r, .reg_width = r_width, .field_width = f_width, \
f78a26f5 MD	93	.enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])
	94
	95	#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
	96	.reg = r, .reg_width = r_width, \
f78a26f5 MD	97	.var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
f78a26f5 MD	98	.enum_ids = (pinmux_enum_t [])
fae43399 MD	99
fae43399 MD	100	struct pinmux_data_reg {
51cb226b	101	unsigned long reg, reg_width;
fae43399 MD	102	pinmux_enum_t *enum_ids;
	103	};
	104
	105	#define PINMUX_DATA_REG(name, r, r_width) \
	106	.reg = r, .reg_width = r_width, \
	107	.enum_ids = (pinmux_enum_t [r_width]) \
	108
ad2a8e7e MD	109	struct pinmux_irq {
ad2a8e7e MD	110	int irq;
c07f54f6	111	unsigned short *gpios;
ad2a8e7e MD	112	};
	113
	114	#define PINMUX_IRQ(irq_nr, ids...) \
c07f54f6	115	{ .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } } \
ad2a8e7e	116
fae43399 MD	117	struct pinmux_range {
	118	pinmux_enum_t begin;
	119	pinmux_enum_t end;
	120	pinmux_enum_t force;
	121	};
	122
19bb7fe3	123	struct sh_pfc_soc_info {
fae43399	124	char *name;
fae43399 MD	125	struct pinmux_range input;
	126	struct pinmux_range input_pd;
	127	struct pinmux_range input_pu;
	128	struct pinmux_range output;
fae43399 MD	129	struct pinmux_range function;
fae43399 MD	130
a3db40a6	131	struct sh_pfc_pin *pins;
caa5bac3	132	unsigned int nr_pins;
63d57383 LP	133	const struct pinmux_range *ranges;
63d57383 LP	134	unsigned int nr_ranges;
3d8d9f1d LP	135	const struct sh_pfc_pin_group *groups;
	136	unsigned int nr_groups;
	137	const struct sh_pfc_function *functions;
	138	unsigned int nr_functions;
	139
a373ed0a LP	140	struct pinmux_func *func_gpios;
a373ed0a LP	141	unsigned int nr_func_gpios;
d7a7ca57	142
fae43399 MD	143	struct pinmux_cfg_reg *cfg_regs;
	144	struct pinmux_data_reg *data_regs;
	145
	146	pinmux_enum_t *gpio_data;
	147	unsigned int gpio_data_size;
	148
ad2a8e7e MD	149	struct pinmux_irq *gpio_irq;
	150	unsigned int gpio_irq_size;
	151
e499ada8	152	unsigned long unlock_reg;
fae43399 MD	153	};
fae43399 MD	154
861601de	155	enum { GPIO_CFG_REQ, GPIO_CFG_FREE };
fae43399	156
972c3fb6 KM	157	/* helper macro for port */
	158	#define PORT_1(fn, pfx, sfx) fn(pfx, sfx)
	159
	160	#define PORT_10(fn, pfx, sfx) \
	161	PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
	162	PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
	163	PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \
	164	PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
	165	PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)
	166
17dffe48 LP	167	#define PORT_10_REV(fn, pfx, sfx) \
	168	PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
	169	PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
	170	PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
	171	PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
	172	PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
	173
	174	#define PORT_32(fn, pfx, sfx) \
	175	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
	176	PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
	177	PORT_1(fn, pfx##31, sfx)
	178
	179	#define PORT_32_REV(fn, pfx, sfx) \
	180	PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
	181	PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
	182	PORT_10_REV(fn, pfx, sfx)
	183
972c3fb6 KM	184	#define PORT_90(fn, pfx, sfx) \
	185	PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \
	186	PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \
	187	PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx), \
	188	PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx), \
	189	PORT_10(fn, pfx##9, sfx)
	190
	191	#define _PORT_ALL(pfx, sfx) pfx##_##sfx
	192	#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
	193	#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
	194	#define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused)
a373ed0a	195	#define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
972c3fb6	196
bd8d0cba KM	197	/* helper macro for pinmux_enum_t */
	198	#define PORT_DATA_I(nr) \
	199	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
	200
	201	#define PORT_DATA_I_PD(nr) \
	202	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
	203	PORT##nr##_IN, PORT##nr##_IN_PD)
	204
	205	#define PORT_DATA_I_PU(nr) \
	206	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
	207	PORT##nr##_IN, PORT##nr##_IN_PU)
	208
	209	#define PORT_DATA_I_PU_PD(nr) \
	210	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
	211	PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
	212
	213	#define PORT_DATA_O(nr) \
	214	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)
	215
	216	#define PORT_DATA_IO(nr) \
	217	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
	218	PORT##nr##_IN)
	219
	220	#define PORT_DATA_IO_PD(nr) \
	221	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
	222	PORT##nr##_IN, PORT##nr##_IN_PD)
	223
	224	#define PORT_DATA_IO_PU(nr) \
	225	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
	226	PORT##nr##_IN, PORT##nr##_IN_PU)
	227
	228	#define PORT_DATA_IO_PU_PD(nr) \
	229	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
	230	PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
	231
9b49139b KM	232	/* helper macro for top 4 bits in PORTnCR */
	233	#define _PCRH(in, in_pd, in_pu, out) \
	234	0, (out), (in), 0, \
	235	0, 0, 0, 0, \
	236	0, 0, (in_pd), 0, \
	237	0, 0, (in_pu), 0
	238
	239	#define PORTCR(nr, reg) \
	240	{ \
	241	PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
	242	_PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \
	243	PORT##nr##_IN_PU, PORT##nr##_OUT), \
	244	PORT##nr##_FN0, PORT##nr##_FN1, \
	245	PORT##nr##_FN2, PORT##nr##_FN3, \
	246	PORT##nr##_FN4, PORT##nr##_FN5, \
	247	PORT##nr##_FN6, PORT##nr##_FN7 } \
	248	}
bd8d0cba	249
fae43399	250	#endif /* __SH_PFC_H */