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fae43399 MD |
1 | /* |
2 | * SuperH Pin Function Controller Support | |
3 | * | |
4 | * Copyright (c) 2008 Magnus Damm | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | ||
11 | #ifndef __SH_PFC_H | |
12 | #define __SH_PFC_H | |
13 | ||
bf9f0674 | 14 | #include <linux/bug.h> |
72c7afa1 | 15 | #include <linux/stringify.h> |
fae43399 MD |
16 | |
17 | typedef unsigned short pinmux_enum_t; | |
fae43399 | 18 | |
06d5631f PM |
19 | enum { |
20 | PINMUX_TYPE_NONE, | |
06d5631f PM |
21 | PINMUX_TYPE_FUNCTION, |
22 | PINMUX_TYPE_GPIO, | |
23 | PINMUX_TYPE_OUTPUT, | |
24 | PINMUX_TYPE_INPUT, | |
06d5631f | 25 | }; |
fae43399 | 26 | |
c58d9c1b LP |
27 | #define SH_PFC_PIN_CFG_INPUT (1 << 0) |
28 | #define SH_PFC_PIN_CFG_OUTPUT (1 << 1) | |
29 | #define SH_PFC_PIN_CFG_PULL_UP (1 << 2) | |
30 | #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) | |
31 | ||
a3db40a6 | 32 | struct sh_pfc_pin { |
94e74601 | 33 | pinmux_enum_t enum_id; |
72c7afa1 | 34 | const char *name; |
c58d9c1b | 35 | unsigned int configs; |
fae43399 MD |
36 | }; |
37 | ||
3d8d9f1d LP |
38 | #define SH_PFC_PIN_GROUP(n) \ |
39 | { \ | |
40 | .name = #n, \ | |
41 | .pins = n##_pins, \ | |
42 | .mux = n##_mux, \ | |
43 | .nr_pins = ARRAY_SIZE(n##_pins), \ | |
44 | } | |
45 | ||
46 | struct sh_pfc_pin_group { | |
47 | const char *name; | |
48 | const unsigned int *pins; | |
49 | const unsigned int *mux; | |
50 | unsigned int nr_pins; | |
51 | }; | |
52 | ||
53 | #define SH_PFC_FUNCTION(n) \ | |
54 | { \ | |
55 | .name = #n, \ | |
56 | .groups = n##_groups, \ | |
57 | .nr_groups = ARRAY_SIZE(n##_groups), \ | |
58 | } | |
59 | ||
60 | struct sh_pfc_function { | |
61 | const char *name; | |
62 | const char * const *groups; | |
63 | unsigned int nr_groups; | |
64 | }; | |
65 | ||
a373ed0a | 66 | struct pinmux_func { |
94e74601 | 67 | pinmux_enum_t enum_id; |
a373ed0a LP |
68 | const char *name; |
69 | }; | |
70 | ||
380c2ed9 LP |
71 | #define PINMUX_GPIO(gpio, data_or_mark) \ |
72 | [gpio] = { \ | |
73 | .name = __stringify(gpio), \ | |
74 | .enum_id = data_or_mark, \ | |
380c2ed9 | 75 | } |
a373ed0a LP |
76 | #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ |
77 | [gpio - (base)] = { \ | |
380c2ed9 LP |
78 | .name = __stringify(gpio), \ |
79 | .enum_id = data_or_mark, \ | |
380c2ed9 | 80 | } |
06d5631f | 81 | |
fae43399 MD |
82 | #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 |
83 | ||
84 | struct pinmux_cfg_reg { | |
85 | unsigned long reg, reg_width, field_width; | |
cd3c1bee LP |
86 | const pinmux_enum_t *enum_ids; |
87 | const unsigned long *var_field_width; | |
fae43399 MD |
88 | }; |
89 | ||
90 | #define PINMUX_CFG_REG(name, r, r_width, f_width) \ | |
91 | .reg = r, .reg_width = r_width, .field_width = f_width, \ | |
f78a26f5 MD |
92 | .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)]) |
93 | ||
94 | #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ | |
95 | .reg = r, .reg_width = r_width, \ | |
f78a26f5 MD |
96 | .var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \ |
97 | .enum_ids = (pinmux_enum_t []) | |
fae43399 MD |
98 | |
99 | struct pinmux_data_reg { | |
51cb226b | 100 | unsigned long reg, reg_width; |
cd3c1bee | 101 | const pinmux_enum_t *enum_ids; |
fae43399 MD |
102 | }; |
103 | ||
104 | #define PINMUX_DATA_REG(name, r, r_width) \ | |
105 | .reg = r, .reg_width = r_width, \ | |
106 | .enum_ids = (pinmux_enum_t [r_width]) \ | |
107 | ||
ad2a8e7e MD |
108 | struct pinmux_irq { |
109 | int irq; | |
c07f54f6 | 110 | unsigned short *gpios; |
ad2a8e7e MD |
111 | }; |
112 | ||
113 | #define PINMUX_IRQ(irq_nr, ids...) \ | |
c07f54f6 | 114 | { .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } } \ |
ad2a8e7e | 115 | |
fae43399 MD |
116 | struct pinmux_range { |
117 | pinmux_enum_t begin; | |
118 | pinmux_enum_t end; | |
119 | pinmux_enum_t force; | |
120 | }; | |
121 | ||
c58d9c1b LP |
122 | struct sh_pfc; |
123 | ||
124 | struct sh_pfc_soc_operations { | |
0c151062 LP |
125 | int (*init)(struct sh_pfc *pfc); |
126 | void (*exit)(struct sh_pfc *pfc); | |
c58d9c1b LP |
127 | unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); |
128 | void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, | |
129 | unsigned int bias); | |
130 | }; | |
131 | ||
19bb7fe3 | 132 | struct sh_pfc_soc_info { |
cd3c1bee | 133 | const char *name; |
c58d9c1b LP |
134 | const struct sh_pfc_soc_operations *ops; |
135 | ||
fae43399 | 136 | struct pinmux_range input; |
fae43399 | 137 | struct pinmux_range output; |
fae43399 MD |
138 | struct pinmux_range function; |
139 | ||
cd3c1bee | 140 | const struct sh_pfc_pin *pins; |
caa5bac3 | 141 | unsigned int nr_pins; |
63d57383 LP |
142 | const struct pinmux_range *ranges; |
143 | unsigned int nr_ranges; | |
3d8d9f1d LP |
144 | const struct sh_pfc_pin_group *groups; |
145 | unsigned int nr_groups; | |
146 | const struct sh_pfc_function *functions; | |
147 | unsigned int nr_functions; | |
148 | ||
cd3c1bee | 149 | const struct pinmux_func *func_gpios; |
a373ed0a | 150 | unsigned int nr_func_gpios; |
d7a7ca57 | 151 | |
cd3c1bee LP |
152 | const struct pinmux_cfg_reg *cfg_regs; |
153 | const struct pinmux_data_reg *data_regs; | |
fae43399 | 154 | |
cd3c1bee | 155 | const pinmux_enum_t *gpio_data; |
fae43399 MD |
156 | unsigned int gpio_data_size; |
157 | ||
cd3c1bee | 158 | const struct pinmux_irq *gpio_irq; |
ad2a8e7e MD |
159 | unsigned int gpio_irq_size; |
160 | ||
e499ada8 | 161 | unsigned long unlock_reg; |
fae43399 MD |
162 | }; |
163 | ||
972c3fb6 KM |
164 | /* helper macro for port */ |
165 | #define PORT_1(fn, pfx, sfx) fn(pfx, sfx) | |
166 | ||
167 | #define PORT_10(fn, pfx, sfx) \ | |
168 | PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ | |
169 | PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ | |
170 | PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \ | |
171 | PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ | |
172 | PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx) | |
173 | ||
17dffe48 LP |
174 | #define PORT_10_REV(fn, pfx, sfx) \ |
175 | PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ | |
176 | PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ | |
177 | PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ | |
178 | PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ | |
179 | PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) | |
180 | ||
181 | #define PORT_32(fn, pfx, sfx) \ | |
182 | PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ | |
183 | PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ | |
184 | PORT_1(fn, pfx##31, sfx) | |
185 | ||
186 | #define PORT_32_REV(fn, pfx, sfx) \ | |
187 | PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ | |
188 | PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ | |
189 | PORT_10_REV(fn, pfx, sfx) | |
190 | ||
972c3fb6 KM |
191 | #define PORT_90(fn, pfx, sfx) \ |
192 | PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \ | |
193 | PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \ | |
194 | PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx), \ | |
195 | PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx), \ | |
196 | PORT_10(fn, pfx##9, sfx) | |
197 | ||
198 | #define _PORT_ALL(pfx, sfx) pfx##_##sfx | |
972c3fb6 | 199 | #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) |
a373ed0a | 200 | #define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) |
972c3fb6 | 201 | |
bd8d0cba | 202 | /* helper macro for pinmux_enum_t */ |
bd8d0cba KM |
203 | #define PORT_DATA_IO(nr) \ |
204 | PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ | |
205 | PORT##nr##_IN) | |
206 | ||
9b49139b KM |
207 | /* helper macro for top 4 bits in PORTnCR */ |
208 | #define _PCRH(in, in_pd, in_pu, out) \ | |
209 | 0, (out), (in), 0, \ | |
210 | 0, 0, 0, 0, \ | |
211 | 0, 0, (in_pd), 0, \ | |
212 | 0, 0, (in_pu), 0 | |
213 | ||
214 | #define PORTCR(nr, reg) \ | |
215 | { \ | |
216 | PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ | |
217 | _PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \ | |
218 | PORT##nr##_IN_PU, PORT##nr##_OUT), \ | |
219 | PORT##nr##_FN0, PORT##nr##_FN1, \ | |
220 | PORT##nr##_FN2, PORT##nr##_FN3, \ | |
221 | PORT##nr##_FN4, PORT##nr##_FN5, \ | |
222 | PORT##nr##_FN6, PORT##nr##_FN7 } \ | |
223 | } | |
bd8d0cba | 224 | |
fae43399 | 225 | #endif /* __SH_PFC_H */ |