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pinctrl: SPEAr: Add plgpio driver
[deliverable/linux.git] / drivers / pinctrl / spear / pinctrl-plgpio.c
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604bb7da
VK		 1/*
2 * SPEAr platform PLGPIO driver
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@linaro.org>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/clk.h>
13#include <linux/err.h>
14#include <linux/gpio.h>
15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/irqdomain.h>
18#include <linux/module.h>
19#include <linux/pinctrl/consumer.h>
20#include <linux/platform_device.h>
21#include <linux/pm.h>
22#include <linux/spinlock.h>
23#include <asm/mach/irq.h>
24
25#define MAX_GPIO_PER_REG 32
26#define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG)
27#define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG) \
28 * sizeof(int *))
29
30/*
31 * plgpio pins in all machines are not one to one mapped, bitwise with registers
32 * bits. These set of macros define register masks for which below functions
33 * (pin_to_offset and offset_to_pin) are required to be called.
34 */
35#define PTO_ENB_REG 0x001
36#define PTO_WDATA_REG 0x002
37#define PTO_DIR_REG 0x004
38#define PTO_IE_REG 0x008
39#define PTO_RDATA_REG 0x010
40#define PTO_MIS_REG 0x020
41
42struct plgpio_regs {
43 u32 enb; /* enable register */
44 u32 wdata; /* write data register */
45 u32 dir; /* direction set register */
46 u32 rdata; /* read data register */
47 u32 ie; /* interrupt enable register */
48 u32 mis; /* mask interrupt status register */
49 u32 eit; /* edge interrupt type */
50};
51
52/*
53 * struct plgpio: plgpio driver specific structure
54 *
55 * lock: lock for guarding gpio registers
56 * base: base address of plgpio block
57 * irq_base: irq number of plgpio0
58 * chip: gpio framework specific chip information structure
59 * p2o: function ptr for pin to offset conversion. This is required only for
60 * machines where mapping b/w pin and offset is not 1-to-1.
61 * o2p: function ptr for offset to pin conversion. This is required only for
62 * machines where mapping b/w pin and offset is not 1-to-1.
63 * p2o_regs: mask of registers for which p2o and o2p are applicable
64 * regs: register offsets
65 * csave_regs: context save registers for standby/sleep/hibernate cases
66 */
67struct plgpio {
68 spinlock_t lock;
69 void __iomem *base;
70 struct clk *clk;
71 unsigned irq_base;
72 struct irq_domain *irq_domain;
73 struct gpio_chip chip;
74 int (*p2o)(int pin); /* pin_to_offset */
75 int (*o2p)(int offset); /* offset_to_pin */
76 u32 p2o_regs;
77 struct plgpio_regs regs;
78#ifdef CONFIG_PM
79 struct plgpio_regs *csave_regs;
80#endif
81};
82
83/* register manipulation inline functions */
84static inline u32 is_plgpio_set(void __iomem *base, u32 pin, u32 reg)
85{
86 u32 offset = PIN_OFFSET(pin);
87 void __iomem *reg_off = REG_OFFSET(base, reg, pin);
88 u32 val = readl_relaxed(reg_off);
89
90 return !!(val & (1 << offset));
91}
92
93static inline void plgpio_reg_set(void __iomem *base, u32 pin, u32 reg)
94{
95 u32 offset = PIN_OFFSET(pin);
96 void __iomem *reg_off = REG_OFFSET(base, reg, pin);
97 u32 val = readl_relaxed(reg_off);
98
99 writel_relaxed(val | (1 << offset), reg_off);
100}
101
102static inline void plgpio_reg_reset(void __iomem *base, u32 pin, u32 reg)
103{
104 u32 offset = PIN_OFFSET(pin);
105 void __iomem *reg_off = REG_OFFSET(base, reg, pin);
106 u32 val = readl_relaxed(reg_off);
107
108 writel_relaxed(val & ~(1 << offset), reg_off);
109}
110
111/* gpio framework specific routines */
112static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset)
113{
114 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
115 unsigned long flags;
116
117 /* get correct offset for "offset" pin */
118 if (plgpio->p2o && (plgpio->p2o_regs & PTO_DIR_REG)) {
119 offset = plgpio->p2o(offset);
120 if (offset == -1)
121 return -EINVAL;
122 }
123
124 spin_lock_irqsave(&plgpio->lock, flags);
125 plgpio_reg_set(plgpio->base, offset, plgpio->regs.dir);
126 spin_unlock_irqrestore(&plgpio->lock, flags);
127
128 return 0;
129}
130
131static int plgpio_direction_output(struct gpio_chip *chip, unsigned offset,
132 int value)
133{
134 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
135 unsigned long flags;
136 unsigned dir_offset = offset, wdata_offset = offset, tmp;
137
138 /* get correct offset for "offset" pin */
139 if (plgpio->p2o && (plgpio->p2o_regs & (PTO_DIR_REG | PTO_WDATA_REG))) {
140 tmp = plgpio->p2o(offset);
141 if (tmp == -1)
142 return -EINVAL;
143
144 if (plgpio->p2o_regs & PTO_DIR_REG)
145 dir_offset = tmp;
146 if (plgpio->p2o_regs & PTO_WDATA_REG)
147 wdata_offset = tmp;
148 }
149
150 spin_lock_irqsave(&plgpio->lock, flags);
151 if (value)
152 plgpio_reg_set(plgpio->base, wdata_offset,
153 plgpio->regs.wdata);
154 else
155 plgpio_reg_reset(plgpio->base, wdata_offset,
156 plgpio->regs.wdata);
157
158 plgpio_reg_reset(plgpio->base, dir_offset, plgpio->regs.dir);
159 spin_unlock_irqrestore(&plgpio->lock, flags);
160
161 return 0;
162}
163
164static int plgpio_get_value(struct gpio_chip *chip, unsigned offset)
165{
166 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
167
168 if (offset >= chip->ngpio)
169 return -EINVAL;
170
171 /* get correct offset for "offset" pin */
172 if (plgpio->p2o && (plgpio->p2o_regs & PTO_RDATA_REG)) {
173 offset = plgpio->p2o(offset);
174 if (offset == -1)
175 return -EINVAL;
176 }
177
178 return is_plgpio_set(plgpio->base, offset, plgpio->regs.rdata);
179}
180
181static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
182{
183 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
184
185 if (offset >= chip->ngpio)
186 return;
187
188 /* get correct offset for "offset" pin */
189 if (plgpio->p2o && (plgpio->p2o_regs & PTO_WDATA_REG)) {
190 offset = plgpio->p2o(offset);
191 if (offset == -1)
192 return;
193 }
194
195 if (value)
196 plgpio_reg_set(plgpio->base, offset, plgpio->regs.wdata);
197 else
198 plgpio_reg_reset(plgpio->base, offset, plgpio->regs.wdata);
199}
200
201static int plgpio_request(struct gpio_chip *chip, unsigned offset)
202{
203 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
204 int gpio = chip->base + offset;
205 unsigned long flags;
206 int ret = 0;
207
208 if (offset >= chip->ngpio)
209 return -EINVAL;
210
211 ret = pinctrl_request_gpio(gpio);
212 if (ret)
213 return ret;
214
215 if (!IS_ERR(plgpio->clk)) {
216 ret = clk_prepare_enable(plgpio->clk);
217 if (ret)
218 goto err0;
219 }
220
221 if (plgpio->regs.enb == -1)
222 return 0;
223
224 /*
225 * put gpio in IN mode before enabling it. This make enabling gpio safe
226 */
227 ret = plgpio_direction_input(chip, offset);
228 if (ret)
229 goto err1;
230
231 /* get correct offset for "offset" pin */
232 if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
233 offset = plgpio->p2o(offset);
234 if (offset == -1) {
235 ret = -EINVAL;
236 goto err1;
237 }
238 }
239
240 spin_lock_irqsave(&plgpio->lock, flags);
241 plgpio_reg_set(plgpio->base, offset, plgpio->regs.enb);
242 spin_unlock_irqrestore(&plgpio->lock, flags);
243 return 0;
244
245err1:
246 clk_disable_unprepare(plgpio->clk);
247err0:
248 pinctrl_free_gpio(gpio);
249 return ret;
250}
251
252static void plgpio_free(struct gpio_chip *chip, unsigned offset)
253{
254 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
255 int gpio = chip->base + offset;
256 unsigned long flags;
257
258 if (offset >= chip->ngpio)
259 return;
260
261 if (plgpio->regs.enb == -1)
262 goto disable_clk;
263
264 /* get correct offset for "offset" pin */
265 if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
266 offset = plgpio->p2o(offset);
267 if (offset == -1)
268 return;
269 }
270
271 spin_lock_irqsave(&plgpio->lock, flags);
272 plgpio_reg_reset(plgpio->base, offset, plgpio->regs.enb);
273 spin_unlock_irqrestore(&plgpio->lock, flags);
274
275disable_clk:
276 if (!IS_ERR(plgpio->clk))
277 clk_disable_unprepare(plgpio->clk);
278
279 pinctrl_free_gpio(gpio);
280}
281
282static int plgpio_to_irq(struct gpio_chip *chip, unsigned offset)
283{
284 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
285
286 if (plgpio->irq_base < 0)
287 return -EINVAL;
288
289 return irq_find_mapping(plgpio->irq_domain, offset);
290}
291
292/* PLGPIO IRQ */
293static void plgpio_irq_disable(struct irq_data *d)
294{
295 struct plgpio *plgpio = irq_data_get_irq_chip_data(d);
296 int offset = d->irq - plgpio->irq_base;
297 unsigned long flags;
298
299 /* get correct offset for "offset" pin */
300 if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
301 offset = plgpio->p2o(offset);
302 if (offset == -1)
303 return;
304 }
305
306 spin_lock_irqsave(&plgpio->lock, flags);
307 plgpio_reg_set(plgpio->base, offset, plgpio->regs.ie);
308 spin_unlock_irqrestore(&plgpio->lock, flags);
309}
310
311static void plgpio_irq_enable(struct irq_data *d)
312{
313 struct plgpio *plgpio = irq_data_get_irq_chip_data(d);
314 int offset = d->irq - plgpio->irq_base;
315 unsigned long flags;
316
317 /* get correct offset for "offset" pin */
318 if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
319 offset = plgpio->p2o(offset);
320 if (offset == -1)
321 return;
322 }
323
324 spin_lock_irqsave(&plgpio->lock, flags);
325 plgpio_reg_reset(plgpio->base, offset, plgpio->regs.ie);
326 spin_unlock_irqrestore(&plgpio->lock, flags);
327}
328
329static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger)
330{
331 struct plgpio *plgpio = irq_data_get_irq_chip_data(d);
332 int offset = d->irq - plgpio->irq_base;
333 void __iomem *reg_off;
334 unsigned int supported_type = 0, val;
335
336 if (offset >= plgpio->chip.ngpio)
337 return -EINVAL;
338
339 if (plgpio->regs.eit == -1)
340 supported_type = IRQ_TYPE_LEVEL_HIGH;
341 else
342 supported_type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
343
344 if (!(trigger & supported_type))
345 return -EINVAL;
346
347 if (plgpio->regs.eit == -1)
348 return 0;
349
350 reg_off = REG_OFFSET(plgpio->base, plgpio->regs.eit, offset);
351 val = readl_relaxed(reg_off);
352
353 offset = PIN_OFFSET(offset);
354 if (trigger & IRQ_TYPE_EDGE_RISING)
355 writel_relaxed(val | (1 << offset), reg_off);
356 else
357 writel_relaxed(val & ~(1 << offset), reg_off);
358
359 return 0;
360}
361
362static struct irq_chip plgpio_irqchip = {
363 .name = "PLGPIO",
364 .irq_enable = plgpio_irq_enable,
365 .irq_disable = plgpio_irq_disable,
366 .irq_set_type = plgpio_irq_set_type,
367};
368
369static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc)
370{
371 struct plgpio *plgpio = irq_get_handler_data(irq);
372 struct irq_chip *irqchip = irq_desc_get_chip(desc);
373 int regs_count, count, pin, offset, i = 0;
374 unsigned long pending;
375
376 count = plgpio->chip.ngpio;
377 regs_count = DIV_ROUND_UP(count, MAX_GPIO_PER_REG);
378
379 chained_irq_enter(irqchip, desc);
380 /* check all plgpio MIS registers for a possible interrupt */
381 for (; i < regs_count; i++) {
382 pending = readl_relaxed(plgpio->base + plgpio->regs.mis +
383 i * sizeof(int *));
384 if (!pending)
385 continue;
386
387 /* clear interrupts */
388 writel_relaxed(~pending, plgpio->base + plgpio->regs.mis +
389 i * sizeof(int *));
390 /*
391 * clear extra bits in last register having gpios < MAX/REG
392 * ex: Suppose there are max 102 plgpios. then last register
393 * must have only (102 - MAX_GPIO_PER_REG * 3) = 6 relevant bits
394 * so, we must not take other 28 bits into consideration for
395 * checking interrupt. so clear those bits.
396 */
397 count = count - i * MAX_GPIO_PER_REG;
398 if (count < MAX_GPIO_PER_REG)
399 pending &= (1 << count) - 1;
400
401 for_each_set_bit(offset, &pending, MAX_GPIO_PER_REG) {
402 /* get correct pin for "offset" */
403 if (plgpio->o2p && (plgpio->p2o_regs & PTO_MIS_REG)) {
404 pin = plgpio->o2p(offset);
405 if (pin == -1)
406 continue;
407 } else
408 pin = offset;
409
410 /* get correct irq line number */
411 pin = i * MAX_GPIO_PER_REG + pin;
412 generic_handle_irq(plgpio_to_irq(&plgpio->chip, pin));
413 }
414 }
415 chained_irq_exit(irqchip, desc);
416}
417
418/*
419 * pin to offset and offset to pin converter functions
420 *
421 * In spear310 there is inconsistency among bit positions in plgpio regiseters,
422 * for different plgpio pins. For example: for pin 27, bit offset is 23, pin
423 * 28-33 are not supported, pin 95 has offset bit 95, bit 100 has offset bit 1
424 */
425static int spear310_p2o(int pin)
426{
427 int offset = pin;
428
429 if (pin <= 27)
430 offset += 4;
431 else if (pin <= 33)
432 offset = -1;
433 else if (pin <= 97)
434 offset -= 2;
435 else if (pin <= 101)
436 offset = 101 - pin;
437 else
438 offset = -1;
439
440 return offset;
441}
442
443int spear310_o2p(int offset)
444{
445 if (offset <= 3)
446 return 101 - offset;
447 else if (offset <= 31)
448 return offset - 4;
449 else
450 return offset + 2;
451}
452
453static int __devinit plgpio_probe_dt(struct platform_device *pdev,
454 struct plgpio *plgpio)
455{
456 struct device_node *np = pdev->dev.of_node;
457 int ret = -EINVAL;
458 u32 val;
459
460 if (of_machine_is_compatible("st,spear310")) {
461 plgpio->p2o = spear310_p2o;
462 plgpio->o2p = spear310_o2p;
463 plgpio->p2o_regs = PTO_WDATA_REG | PTO_DIR_REG | PTO_IE_REG |
464 PTO_RDATA_REG | PTO_MIS_REG;
465 }
466
467 if (!of_property_read_u32(np, "st-plgpio,ngpio", &val)) {
468 plgpio->chip.ngpio = val;
469 } else {
470 dev_err(&pdev->dev, "DT: Invalid ngpio field\n");
471 goto end;
472 }
473
474 if (!of_property_read_u32(np, "st-plgpio,enb-reg", &val))
475 plgpio->regs.enb = val;
476 else
477 plgpio->regs.enb = -1;
478
479 if (!of_property_read_u32(np, "st-plgpio,wdata-reg", &val)) {
480 plgpio->regs.wdata = val;
481 } else {
482 dev_err(&pdev->dev, "DT: Invalid wdata reg\n");
483 goto end;
484 }
485
486 if (!of_property_read_u32(np, "st-plgpio,dir-reg", &val)) {
487 plgpio->regs.dir = val;
488 } else {
489 dev_err(&pdev->dev, "DT: Invalid dir reg\n");
490 goto end;
491 }
492
493 if (!of_property_read_u32(np, "st-plgpio,ie-reg", &val)) {
494 plgpio->regs.ie = val;
495 } else {
496 dev_err(&pdev->dev, "DT: Invalid ie reg\n");
497 goto end;
498 }
499
500 if (!of_property_read_u32(np, "st-plgpio,rdata-reg", &val)) {
501 plgpio->regs.rdata = val;
502 } else {
503 dev_err(&pdev->dev, "DT: Invalid rdata reg\n");
504 goto end;
505 }
506
507 if (!of_property_read_u32(np, "st-plgpio,mis-reg", &val)) {
508 plgpio->regs.mis = val;
509 } else {
510 dev_err(&pdev->dev, "DT: Invalid mis reg\n");
511 goto end;
512 }
513
514 if (!of_property_read_u32(np, "st-plgpio,eit-reg", &val))
515 plgpio->regs.eit = val;
516 else
517 plgpio->regs.eit = -1;
518
519 return 0;
520
521end:
522 return ret;
523}
524static int __devinit plgpio_probe(struct platform_device *pdev)
525{
526 struct device_node *np = pdev->dev.of_node;
527 struct plgpio *plgpio;
528 struct resource *res;
529 int ret, irq, i;
530
531 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
532 if (!res) {
533 dev_err(&pdev->dev, "invalid IORESOURCE_MEM\n");
534 return -EBUSY;
535 }
536
537 plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL);
538 if (!plgpio) {
539 dev_err(&pdev->dev, "memory allocation fail\n");
540 return -ENOMEM;
541 }
542
543 plgpio->base = devm_request_and_ioremap(&pdev->dev, res);
544 if (!plgpio->base) {
545 dev_err(&pdev->dev, "request and ioremap fail\n");
546 return -ENOMEM;
547 }
548
549 ret = plgpio_probe_dt(pdev, plgpio);
550 if (ret) {
551 dev_err(&pdev->dev, "DT probe failed\n");
552 return ret;
553 }
554
555 plgpio->clk = devm_clk_get(&pdev->dev, NULL);
556 if (IS_ERR(plgpio->clk))
557 dev_warn(&pdev->dev, "clk_get() failed, work without it\n");
558
559#ifdef CONFIG_PM
560 plgpio->csave_regs = devm_kzalloc(&pdev->dev,
561 sizeof(*plgpio->csave_regs) *
562 DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG),
563 GFP_KERNEL);
564 if (!plgpio->csave_regs) {
565 dev_err(&pdev->dev, "csave registers memory allocation fail\n");
566 return -ENOMEM;
567 }
568#endif
569
570 platform_set_drvdata(pdev, plgpio);
571 spin_lock_init(&plgpio->lock);
572
573 plgpio->irq_base = -1;
574 plgpio->chip.base = -1;
575 plgpio->chip.request = plgpio_request;
576 plgpio->chip.free = plgpio_free;
577 plgpio->chip.direction_input = plgpio_direction_input;
578 plgpio->chip.direction_output = plgpio_direction_output;
579 plgpio->chip.get = plgpio_get_value;
580 plgpio->chip.set = plgpio_set_value;
581 plgpio->chip.to_irq = plgpio_to_irq;
582 plgpio->chip.label = dev_name(&pdev->dev);
583 plgpio->chip.dev = &pdev->dev;
584 plgpio->chip.owner = THIS_MODULE;
585
586 ret = gpiochip_add(&plgpio->chip);
587 if (ret) {
588 dev_err(&pdev->dev, "unable to add gpio chip\n");
589 return ret;
590 }
591
592 irq = platform_get_irq(pdev, 0);
593 if (irq < 0) {
594 dev_info(&pdev->dev, "irqs not supported\n");
595 return 0;
596 }
597
598 plgpio->irq_base = irq_alloc_descs(-1, 0, plgpio->chip.ngpio, 0);
599 if (IS_ERR_VALUE(plgpio->irq_base)) {
600 /* we would not support irq for gpio */
601 dev_warn(&pdev->dev, "couldn't allocate irq base\n");
602 return 0;
603 }
604
605 plgpio->irq_domain = irq_domain_add_legacy(np, plgpio->chip.ngpio,
606 plgpio->irq_base, 0, &irq_domain_simple_ops, NULL);
607 if (WARN_ON(!plgpio->irq_domain)) {
608 dev_err(&pdev->dev, "irq domain init failed\n");
609 irq_free_descs(plgpio->irq_base, plgpio->chip.ngpio);
610 ret = -ENXIO;
611 goto remove_gpiochip;
612 }
613
614 irq_set_chained_handler(irq, plgpio_irq_handler);
615 for (i = 0; i < plgpio->chip.ngpio; i++) {
616 irq_set_chip_and_handler(i + plgpio->irq_base, &plgpio_irqchip,
617 handle_simple_irq);
618 set_irq_flags(i + plgpio->irq_base, IRQF_VALID);
619 irq_set_chip_data(i + plgpio->irq_base, plgpio);
620 }
621
622 irq_set_handler_data(irq, plgpio);
623 dev_info(&pdev->dev, "PLGPIO registered with IRQs\n");
624
625 return 0;
626
627remove_gpiochip:
628 dev_info(&pdev->dev, "Remove gpiochip\n");
629 if (gpiochip_remove(&plgpio->chip))
630 dev_err(&pdev->dev, "unable to remove gpiochip\n");
631
632 return ret;
633}
634
635#ifdef CONFIG_PM
636static int plgpio_suspend(struct device *dev)
637{
638 struct plgpio *plgpio = dev_get_drvdata(dev);
639 int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG);
640 void __iomem *off;
641
642 for (i = 0; i < reg_count; i++) {
643 off = plgpio->base + i * sizeof(int *);
644
645 if (plgpio->regs.enb != -1)
646 plgpio->csave_regs[i].enb =
647 readl_relaxed(plgpio->regs.enb + off);
648 if (plgpio->regs.eit != -1)
649 plgpio->csave_regs[i].eit =
650 readl_relaxed(plgpio->regs.eit + off);
651 plgpio->csave_regs[i].wdata = readl_relaxed(plgpio->regs.wdata +
652 off);
653 plgpio->csave_regs[i].dir = readl_relaxed(plgpio->regs.dir +
654 off);
655 plgpio->csave_regs[i].ie = readl_relaxed(plgpio->regs.ie + off);
656 }
657
658 return 0;
659}
660
661/*
662 * This is used to correct the values in end registers. End registers contain
663 * extra bits that might be used for other purpose in platform. So, we shouldn't
664 * overwrite these bits. This macro, reads given register again, preserves other
665 * bit values (non-plgpio bits), and retain captured value (plgpio bits).
666 */
667#define plgpio_prepare_reg(__reg, _off, _mask, _tmp) \
668{ \
669 _tmp = readl_relaxed(plgpio->regs.__reg + _off); \
670 _tmp &= ~_mask; \
671 plgpio->csave_regs[i].__reg = \
672 _tmp | (plgpio->csave_regs[i].__reg & _mask); \
673}
674
675static int plgpio_resume(struct device *dev)
676{
677 struct plgpio *plgpio = dev_get_drvdata(dev);
678 int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG);
679 void __iomem *off;
680 u32 mask, tmp;
681
682 for (i = 0; i < reg_count; i++) {
683 off = plgpio->base + i * sizeof(int *);
684
685 if (i == reg_count - 1) {
686 mask = (1 << (plgpio->chip.ngpio - i *
687 MAX_GPIO_PER_REG)) - 1;
688
689 if (plgpio->regs.enb != -1)
690 plgpio_prepare_reg(enb, off, mask, tmp);
691
692 if (plgpio->regs.eit != -1)
693 plgpio_prepare_reg(eit, off, mask, tmp);
694
695 plgpio_prepare_reg(wdata, off, mask, tmp);
696 plgpio_prepare_reg(dir, off, mask, tmp);
697 plgpio_prepare_reg(ie, off, mask, tmp);
698 }
699
700 writel_relaxed(plgpio->csave_regs[i].wdata, plgpio->regs.wdata +
701 off);
702 writel_relaxed(plgpio->csave_regs[i].dir, plgpio->regs.dir +
703 off);
704
705 if (plgpio->regs.eit != -1)
706 writel_relaxed(plgpio->csave_regs[i].eit,
707 plgpio->regs.eit + off);
708
709 writel_relaxed(plgpio->csave_regs[i].ie, plgpio->regs.ie + off);
710
711 if (plgpio->regs.enb != -1)
712 writel_relaxed(plgpio->csave_regs[i].enb,
713 plgpio->regs.enb + off);
714 }
715
716 return 0;
717}
718#endif
719
720static SIMPLE_DEV_PM_OPS(plgpio_dev_pm_ops, plgpio_suspend, plgpio_resume);
721
722static const struct of_device_id plgpio_of_match[] = {
723 { .compatible = "st,spear-plgpio" },
724 {}
725};
726MODULE_DEVICE_TABLE(of, plgpio_of_match);
727
728static struct platform_driver plgpio_driver = {
729 .probe = plgpio_probe,
730 .driver = {
731 .owner = THIS_MODULE,
732 .name = "spear-plgpio",
733 .pm = &plgpio_dev_pm_ops,
734 .of_match_table = of_match_ptr(plgpio_of_match),
735 },
736};
737
738static int __init plgpio_init(void)
739{
740 return platform_driver_register(&plgpio_driver);
741}
742subsys_initcall(plgpio_init);
743
744MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
745MODULE_DESCRIPTION("ST Microlectronics SPEAr PLGPIO driver");
746MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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