[deliverable/linux.git] / drivers / pinctrl / spear / pinctrl-spear.h

/*
 * Driver header file for the ST Microelectronics SPEAr pinmux
 *
 * Copyright (C) 2012 ST Microelectronics
 * Viresh Kumar <viresh.linux@gmail.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#ifndef __PINMUX_SPEAR_H__
#define __PINMUX_SPEAR_H__

#include <linux/gpio.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/types.h>

struct platform_device;
struct device;

/**
 * struct spear_pmx_mode - SPEAr pmx mode
 * @name: name of pmx mode
 * @mode: mode id
 * @reg: register for configuring this mode
 * @mask: mask of this mode in reg
 * @val: val to be configured at reg after doing (val & mask)
 */
struct spear_pmx_mode {
	const char *const name;
	u16 mode;
	u16 reg;
	u16 mask;
	u32 val;
};

/**
 * struct spear_muxreg - SPEAr mux reg configuration
 * @reg: register offset
 * @mask: mask bits
 * @val: val to be written on mask bits
 */
struct spear_muxreg {
	u16 reg;
	u32 mask;
	u32 val;
};

struct spear_gpio_pingroup {
	const unsigned *pins;
	unsigned npins;
	struct spear_muxreg *muxregs;
	u8 nmuxregs;
};

/* ste: set to enable */
#define DEFINE_MUXREG(__pins, __muxreg, __mask, __ste)		\
static struct spear_muxreg __pins##_muxregs[] = {		\
	{							\
		.reg = __muxreg,				\
		.mask = __mask,					\
		.val = __ste ? __mask : 0,			\
	},							\
}

#define DEFINE_2_MUXREG(__pins, __muxreg1, __muxreg2, __mask, __ste1, __ste2) \
static struct spear_muxreg __pins##_muxregs[] = {		\
	{							\
		.reg = __muxreg1,				\
		.mask = __mask,					\
		.val = __ste1 ? __mask : 0,			\
	}, {							\
		.reg = __muxreg2,				\
		.mask = __mask,					\
		.val = __ste2 ? __mask : 0,			\
	},							\
}

#define GPIO_PINGROUP(__pins)					\
	{							\
		.pins = __pins,					\
		.npins = ARRAY_SIZE(__pins),			\
		.muxregs = __pins##_muxregs,			\
		.nmuxregs = ARRAY_SIZE(__pins##_muxregs),	\
	}

/**
 * struct spear_modemux - SPEAr mode mux configuration
 * @modes: mode ids supported by this group of muxregs
 * @nmuxregs: number of muxreg configurations to be done for modes
 * @muxregs: array of muxreg configurations to be done for modes
 */
struct spear_modemux {
	u16 modes;
	u8 nmuxregs;
	struct spear_muxreg *muxregs;
};

/**
 * struct spear_pingroup - SPEAr pin group configurations
 * @name: name of pin group
 * @pins: array containing pin numbers
 * @npins: size of pins array
 * @modemuxs: array of modemux configurations for this pin group
 * @nmodemuxs: size of array modemuxs
 *
 * A representation of a group of pins in the SPEAr pin controller. Each group
 * allows some parameter or parameters to be configured.
 */
struct spear_pingroup {
	const char *name;
	const unsigned *pins;
	unsigned npins;
	struct spear_modemux *modemuxs;
	unsigned nmodemuxs;
};

/**
 * struct spear_function - SPEAr pinctrl mux function
 * @name: The name of the function, exported to pinctrl core.
 * @groups: An array of pin groups that may select this function.
 * @ngroups: The number of entries in @groups.
 */
struct spear_function {
	const char *name;
	const char *const *groups;
	unsigned ngroups;
};

/**
 * struct spear_pinctrl_machdata - SPEAr pin controller machine driver
 *	configuration
 * @pins: An array describing all pins the pin controller affects.
 *	All pins which are also GPIOs must be listed first within the *array,
 *	and be numbered identically to the GPIO controller's *numbering.
 * @npins: The numbmer of entries in @pins.
 * @functions: An array describing all mux functions the SoC supports.
 * @nfunctions: The numbmer of entries in @functions.
 * @groups: An array describing all pin groups the pin SoC supports.
 * @ngroups: The numbmer of entries in @groups.
 * @gpio_pingroups: gpio pingroups
 * @ngpio_pingroups: gpio pingroups count
 *
 * @modes_supported: Does SoC support modes
 * @mode: mode configured from probe
 * @pmx_modes: array of modes supported by SoC
 * @npmx_modes: number of entries in pmx_modes.
 */
struct spear_pinctrl_machdata {
	const struct pinctrl_pin_desc *pins;
	unsigned npins;
	struct spear_function **functions;
	unsigned nfunctions;
	struct spear_pingroup **groups;
	unsigned ngroups;
	struct spear_gpio_pingroup *gpio_pingroups;
	unsigned ngpio_pingroups;

	bool modes_supported;
	u16 mode;
	struct spear_pmx_mode **pmx_modes;
	unsigned npmx_modes;
};

/**
 * struct spear_pmx - SPEAr pinctrl mux
 * @dev: pointer to struct dev of platform_device registered
 * @pctl: pointer to struct pinctrl_dev
 * @machdata: pointer to SoC or machine specific structure
 * @vbase: virtual base address of pinmux controller
 */
struct spear_pmx {
	struct device *dev;
	struct pinctrl_dev *pctl;
	struct spear_pinctrl_machdata *machdata;
	void __iomem *vbase;
};

/* exported routines */
void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
void __devinit
pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup,
		unsigned count, u16 reg);
int __devinit spear_pinctrl_probe(struct platform_device *pdev,
		struct spear_pinctrl_machdata *machdata);
int __devexit spear_pinctrl_remove(struct platform_device *pdev);

#define SPEAR_PIN_0_TO_101		\
	PINCTRL_PIN(0, "PLGPIO0"),	\
	PINCTRL_PIN(1, "PLGPIO1"),	\
	PINCTRL_PIN(2, "PLGPIO2"),	\
	PINCTRL_PIN(3, "PLGPIO3"),	\
	PINCTRL_PIN(4, "PLGPIO4"),	\
	PINCTRL_PIN(5, "PLGPIO5"),	\
	PINCTRL_PIN(6, "PLGPIO6"),	\
	PINCTRL_PIN(7, "PLGPIO7"),	\
	PINCTRL_PIN(8, "PLGPIO8"),	\
	PINCTRL_PIN(9, "PLGPIO9"),	\
	PINCTRL_PIN(10, "PLGPIO10"),	\
	PINCTRL_PIN(11, "PLGPIO11"),	\
	PINCTRL_PIN(12, "PLGPIO12"),	\
	PINCTRL_PIN(13, "PLGPIO13"),	\
	PINCTRL_PIN(14, "PLGPIO14"),	\
	PINCTRL_PIN(15, "PLGPIO15"),	\
	PINCTRL_PIN(16, "PLGPIO16"),	\
	PINCTRL_PIN(17, "PLGPIO17"),	\
	PINCTRL_PIN(18, "PLGPIO18"),	\
	PINCTRL_PIN(19, "PLGPIO19"),	\
	PINCTRL_PIN(20, "PLGPIO20"),	\
	PINCTRL_PIN(21, "PLGPIO21"),	\
	PINCTRL_PIN(22, "PLGPIO22"),	\
	PINCTRL_PIN(23, "PLGPIO23"),	\
	PINCTRL_PIN(24, "PLGPIO24"),	\
	PINCTRL_PIN(25, "PLGPIO25"),	\
	PINCTRL_PIN(26, "PLGPIO26"),	\
	PINCTRL_PIN(27, "PLGPIO27"),	\
	PINCTRL_PIN(28, "PLGPIO28"),	\
	PINCTRL_PIN(29, "PLGPIO29"),	\
	PINCTRL_PIN(30, "PLGPIO30"),	\
	PINCTRL_PIN(31, "PLGPIO31"),	\
	PINCTRL_PIN(32, "PLGPIO32"),	\
	PINCTRL_PIN(33, "PLGPIO33"),	\
	PINCTRL_PIN(34, "PLGPIO34"),	\
	PINCTRL_PIN(35, "PLGPIO35"),	\
	PINCTRL_PIN(36, "PLGPIO36"),	\
	PINCTRL_PIN(37, "PLGPIO37"),	\
	PINCTRL_PIN(38, "PLGPIO38"),	\
	PINCTRL_PIN(39, "PLGPIO39"),	\
	PINCTRL_PIN(40, "PLGPIO40"),	\
	PINCTRL_PIN(41, "PLGPIO41"),	\
	PINCTRL_PIN(42, "PLGPIO42"),	\
	PINCTRL_PIN(43, "PLGPIO43"),	\
	PINCTRL_PIN(44, "PLGPIO44"),	\
	PINCTRL_PIN(45, "PLGPIO45"),	\
	PINCTRL_PIN(46, "PLGPIO46"),	\
	PINCTRL_PIN(47, "PLGPIO47"),	\
	PINCTRL_PIN(48, "PLGPIO48"),	\
	PINCTRL_PIN(49, "PLGPIO49"),	\
	PINCTRL_PIN(50, "PLGPIO50"),	\
	PINCTRL_PIN(51, "PLGPIO51"),	\
	PINCTRL_PIN(52, "PLGPIO52"),	\
	PINCTRL_PIN(53, "PLGPIO53"),	\
	PINCTRL_PIN(54, "PLGPIO54"),	\
	PINCTRL_PIN(55, "PLGPIO55"),	\
	PINCTRL_PIN(56, "PLGPIO56"),	\
	PINCTRL_PIN(57, "PLGPIO57"),	\
	PINCTRL_PIN(58, "PLGPIO58"),	\
	PINCTRL_PIN(59, "PLGPIO59"),	\
	PINCTRL_PIN(60, "PLGPIO60"),	\
	PINCTRL_PIN(61, "PLGPIO61"),	\
	PINCTRL_PIN(62, "PLGPIO62"),	\
	PINCTRL_PIN(63, "PLGPIO63"),	\
	PINCTRL_PIN(64, "PLGPIO64"),	\
	PINCTRL_PIN(65, "PLGPIO65"),	\
	PINCTRL_PIN(66, "PLGPIO66"),	\
	PINCTRL_PIN(67, "PLGPIO67"),	\
	PINCTRL_PIN(68, "PLGPIO68"),	\
	PINCTRL_PIN(69, "PLGPIO69"),	\
	PINCTRL_PIN(70, "PLGPIO70"),	\
	PINCTRL_PIN(71, "PLGPIO71"),	\
	PINCTRL_PIN(72, "PLGPIO72"),	\
	PINCTRL_PIN(73, "PLGPIO73"),	\
	PINCTRL_PIN(74, "PLGPIO74"),	\
	PINCTRL_PIN(75, "PLGPIO75"),	\
	PINCTRL_PIN(76, "PLGPIO76"),	\
	PINCTRL_PIN(77, "PLGPIO77"),	\
	PINCTRL_PIN(78, "PLGPIO78"),	\
	PINCTRL_PIN(79, "PLGPIO79"),	\
	PINCTRL_PIN(80, "PLGPIO80"),	\
	PINCTRL_PIN(81, "PLGPIO81"),	\
	PINCTRL_PIN(82, "PLGPIO82"),	\
	PINCTRL_PIN(83, "PLGPIO83"),	\
	PINCTRL_PIN(84, "PLGPIO84"),	\
	PINCTRL_PIN(85, "PLGPIO85"),	\
	PINCTRL_PIN(86, "PLGPIO86"),	\
	PINCTRL_PIN(87, "PLGPIO87"),	\
	PINCTRL_PIN(88, "PLGPIO88"),	\
	PINCTRL_PIN(89, "PLGPIO89"),	\
	PINCTRL_PIN(90, "PLGPIO90"),	\
	PINCTRL_PIN(91, "PLGPIO91"),	\
	PINCTRL_PIN(92, "PLGPIO92"),	\
	PINCTRL_PIN(93, "PLGPIO93"),	\
	PINCTRL_PIN(94, "PLGPIO94"),	\
	PINCTRL_PIN(95, "PLGPIO95"),	\
	PINCTRL_PIN(96, "PLGPIO96"),	\
	PINCTRL_PIN(97, "PLGPIO97"),	\
	PINCTRL_PIN(98, "PLGPIO98"),	\
	PINCTRL_PIN(99, "PLGPIO99"),	\
	PINCTRL_PIN(100, "PLGPIO100"),	\
	PINCTRL_PIN(101, "PLGPIO101")

#define SPEAR_PIN_102_TO_245		\
	PINCTRL_PIN(102, "PLGPIO102"),	\
	PINCTRL_PIN(103, "PLGPIO103"),	\
	PINCTRL_PIN(104, "PLGPIO104"),	\
	PINCTRL_PIN(105, "PLGPIO105"),	\
	PINCTRL_PIN(106, "PLGPIO106"),	\
	PINCTRL_PIN(107, "PLGPIO107"),	\
	PINCTRL_PIN(108, "PLGPIO108"),	\
	PINCTRL_PIN(109, "PLGPIO109"),	\
	PINCTRL_PIN(110, "PLGPIO110"),	\
	PINCTRL_PIN(111, "PLGPIO111"),	\
	PINCTRL_PIN(112, "PLGPIO112"),	\
	PINCTRL_PIN(113, "PLGPIO113"),	\
	PINCTRL_PIN(114, "PLGPIO114"),	\
	PINCTRL_PIN(115, "PLGPIO115"),	\
	PINCTRL_PIN(116, "PLGPIO116"),	\
	PINCTRL_PIN(117, "PLGPIO117"),	\
	PINCTRL_PIN(118, "PLGPIO118"),	\
	PINCTRL_PIN(119, "PLGPIO119"),	\
	PINCTRL_PIN(120, "PLGPIO120"),	\
	PINCTRL_PIN(121, "PLGPIO121"),	\
	PINCTRL_PIN(122, "PLGPIO122"),	\
	PINCTRL_PIN(123, "PLGPIO123"),	\
	PINCTRL_PIN(124, "PLGPIO124"),	\
	PINCTRL_PIN(125, "PLGPIO125"),	\
	PINCTRL_PIN(126, "PLGPIO126"),	\
	PINCTRL_PIN(127, "PLGPIO127"),	\
	PINCTRL_PIN(128, "PLGPIO128"),	\
	PINCTRL_PIN(129, "PLGPIO129"),	\
	PINCTRL_PIN(130, "PLGPIO130"),	\
	PINCTRL_PIN(131, "PLGPIO131"),	\
	PINCTRL_PIN(132, "PLGPIO132"),	\
	PINCTRL_PIN(133, "PLGPIO133"),	\
	PINCTRL_PIN(134, "PLGPIO134"),	\
	PINCTRL_PIN(135, "PLGPIO135"),	\
	PINCTRL_PIN(136, "PLGPIO136"),	\
	PINCTRL_PIN(137, "PLGPIO137"),	\
	PINCTRL_PIN(138, "PLGPIO138"),	\
	PINCTRL_PIN(139, "PLGPIO139"),	\
	PINCTRL_PIN(140, "PLGPIO140"),	\
	PINCTRL_PIN(141, "PLGPIO141"),	\
	PINCTRL_PIN(142, "PLGPIO142"),	\
	PINCTRL_PIN(143, "PLGPIO143"),	\
	PINCTRL_PIN(144, "PLGPIO144"),	\
	PINCTRL_PIN(145, "PLGPIO145"),	\
	PINCTRL_PIN(146, "PLGPIO146"),	\
	PINCTRL_PIN(147, "PLGPIO147"),	\
	PINCTRL_PIN(148, "PLGPIO148"),	\
	PINCTRL_PIN(149, "PLGPIO149"),	\
	PINCTRL_PIN(150, "PLGPIO150"),	\
	PINCTRL_PIN(151, "PLGPIO151"),	\
	PINCTRL_PIN(152, "PLGPIO152"),	\
	PINCTRL_PIN(153, "PLGPIO153"),	\
	PINCTRL_PIN(154, "PLGPIO154"),	\
	PINCTRL_PIN(155, "PLGPIO155"),	\
	PINCTRL_PIN(156, "PLGPIO156"),	\
	PINCTRL_PIN(157, "PLGPIO157"),	\
	PINCTRL_PIN(158, "PLGPIO158"),	\
	PINCTRL_PIN(159, "PLGPIO159"),	\
	PINCTRL_PIN(160, "PLGPIO160"),	\
	PINCTRL_PIN(161, "PLGPIO161"),	\
	PINCTRL_PIN(162, "PLGPIO162"),	\
	PINCTRL_PIN(163, "PLGPIO163"),	\
	PINCTRL_PIN(164, "PLGPIO164"),	\
	PINCTRL_PIN(165, "PLGPIO165"),	\
	PINCTRL_PIN(166, "PLGPIO166"),	\
	PINCTRL_PIN(167, "PLGPIO167"),	\
	PINCTRL_PIN(168, "PLGPIO168"),	\
	PINCTRL_PIN(169, "PLGPIO169"),	\
	PINCTRL_PIN(170, "PLGPIO170"),	\
	PINCTRL_PIN(171, "PLGPIO171"),	\
	PINCTRL_PIN(172, "PLGPIO172"),	\
	PINCTRL_PIN(173, "PLGPIO173"),	\
	PINCTRL_PIN(174, "PLGPIO174"),	\
	PINCTRL_PIN(175, "PLGPIO175"),	\
	PINCTRL_PIN(176, "PLGPIO176"),	\
	PINCTRL_PIN(177, "PLGPIO177"),	\
	PINCTRL_PIN(178, "PLGPIO178"),	\
	PINCTRL_PIN(179, "PLGPIO179"),	\
	PINCTRL_PIN(180, "PLGPIO180"),	\
	PINCTRL_PIN(181, "PLGPIO181"),	\
	PINCTRL_PIN(182, "PLGPIO182"),	\
	PINCTRL_PIN(183, "PLGPIO183"),	\
	PINCTRL_PIN(184, "PLGPIO184"),	\
	PINCTRL_PIN(185, "PLGPIO185"),	\
	PINCTRL_PIN(186, "PLGPIO186"),	\
	PINCTRL_PIN(187, "PLGPIO187"),	\
	PINCTRL_PIN(188, "PLGPIO188"),	\
	PINCTRL_PIN(189, "PLGPIO189"),	\
	PINCTRL_PIN(190, "PLGPIO190"),	\
	PINCTRL_PIN(191, "PLGPIO191"),	\
	PINCTRL_PIN(192, "PLGPIO192"),	\
	PINCTRL_PIN(193, "PLGPIO193"),	\
	PINCTRL_PIN(194, "PLGPIO194"),	\
	PINCTRL_PIN(195, "PLGPIO195"),	\
	PINCTRL_PIN(196, "PLGPIO196"),	\
	PINCTRL_PIN(197, "PLGPIO197"),	\
	PINCTRL_PIN(198, "PLGPIO198"),	\
	PINCTRL_PIN(199, "PLGPIO199"),	\
	PINCTRL_PIN(200, "PLGPIO200"),	\
	PINCTRL_PIN(201, "PLGPIO201"),	\
	PINCTRL_PIN(202, "PLGPIO202"),	\
	PINCTRL_PIN(203, "PLGPIO203"),	\
	PINCTRL_PIN(204, "PLGPIO204"),	\
	PINCTRL_PIN(205, "PLGPIO205"),	\
	PINCTRL_PIN(206, "PLGPIO206"),	\
	PINCTRL_PIN(207, "PLGPIO207"),	\
	PINCTRL_PIN(208, "PLGPIO208"),	\
	PINCTRL_PIN(209, "PLGPIO209"),	\
	PINCTRL_PIN(210, "PLGPIO210"),	\
	PINCTRL_PIN(211, "PLGPIO211"),	\
	PINCTRL_PIN(212, "PLGPIO212"),	\
	PINCTRL_PIN(213, "PLGPIO213"),	\
	PINCTRL_PIN(214, "PLGPIO214"),	\
	PINCTRL_PIN(215, "PLGPIO215"),	\
	PINCTRL_PIN(216, "PLGPIO216"),	\
	PINCTRL_PIN(217, "PLGPIO217"),	\
	PINCTRL_PIN(218, "PLGPIO218"),	\
	PINCTRL_PIN(219, "PLGPIO219"),	\
	PINCTRL_PIN(220, "PLGPIO220"),	\
	PINCTRL_PIN(221, "PLGPIO221"),	\
	PINCTRL_PIN(222, "PLGPIO222"),	\
	PINCTRL_PIN(223, "PLGPIO223"),	\
	PINCTRL_PIN(224, "PLGPIO224"),	\
	PINCTRL_PIN(225, "PLGPIO225"),	\
	PINCTRL_PIN(226, "PLGPIO226"),	\
	PINCTRL_PIN(227, "PLGPIO227"),	\
	PINCTRL_PIN(228, "PLGPIO228"),	\
	PINCTRL_PIN(229, "PLGPIO229"),	\
	PINCTRL_PIN(230, "PLGPIO230"),	\
	PINCTRL_PIN(231, "PLGPIO231"),	\
	PINCTRL_PIN(232, "PLGPIO232"),	\
	PINCTRL_PIN(233, "PLGPIO233"),	\
	PINCTRL_PIN(234, "PLGPIO234"),	\
	PINCTRL_PIN(235, "PLGPIO235"),	\
	PINCTRL_PIN(236, "PLGPIO236"),	\
	PINCTRL_PIN(237, "PLGPIO237"),	\
	PINCTRL_PIN(238, "PLGPIO238"),	\
	PINCTRL_PIN(239, "PLGPIO239"),	\
	PINCTRL_PIN(240, "PLGPIO240"),	\
	PINCTRL_PIN(241, "PLGPIO241"),	\
	PINCTRL_PIN(242, "PLGPIO242"),	\
	PINCTRL_PIN(243, "PLGPIO243"),	\
	PINCTRL_PIN(244, "PLGPIO244"),	\
	PINCTRL_PIN(245, "PLGPIO245")

#endif /* __PINMUX_SPEAR_H__ */
Commit	Line	Data
deda8287 VK	1	/*
	2	* Driver header file for the ST Microelectronics SPEAr pinmux
	3	*
	4	* Copyright (C) 2012 ST Microelectronics
10d8935f	5	* Viresh Kumar <viresh.linux@gmail.com>
deda8287 VK	6	*
	7	* This file is licensed under the terms of the GNU General Public
	8	* License version 2. This program is licensed "as is" without any
	9	* warranty of any kind, whether express or implied.
	10	*/
	11
	12	#ifndef __PINMUX_SPEAR_H__
	13	#define __PINMUX_SPEAR_H__
	14
f4f8e563	15	#include <linux/gpio.h>
deda8287 VK	16	#include <linux/pinctrl/pinctrl.h>
	17	#include <linux/types.h>
	18
	19	struct platform_device;
	20	struct device;
	21
	22	/**
	23	* struct spear_pmx_mode - SPEAr pmx mode
	24	* @name: name of pmx mode
	25	* @mode: mode id
	26	* @reg: register for configuring this mode
	27	* @mask: mask of this mode in reg
	28	* @val: val to be configured at reg after doing (val & mask)
	29	*/
	30	struct spear_pmx_mode {
	31	const char *const name;
	32	u16 mode;
	33	u16 reg;
	34	u16 mask;
	35	u32 val;
	36	};
	37
	38	/**
	39	* struct spear_muxreg - SPEAr mux reg configuration
	40	* @reg: register offset
	41	* @mask: mask bits
	42	* @val: val to be written on mask bits
	43	*/
	44	struct spear_muxreg {
	45	u16 reg;
	46	u32 mask;
	47	u32 val;
	48	};
	49
f4f8e563 VK	50	struct spear_gpio_pingroup {
	51	const unsigned *pins;
	52	unsigned npins;
	53	struct spear_muxreg *muxregs;
	54	u8 nmuxregs;
	55	};
	56
	57	/* ste: set to enable */
	58	#define DEFINE_MUXREG(__pins, __muxreg, __mask, __ste) \
	59	static struct spear_muxreg __pins##_muxregs[] = { \
	60	{ \
	61	.reg = __muxreg, \
	62	.mask = __mask, \
	63	.val = __ste ? __mask : 0, \
	64	}, \
	65	}
	66
	67	#define DEFINE_2_MUXREG(__pins, __muxreg1, __muxreg2, __mask, __ste1, __ste2) \
	68	static struct spear_muxreg __pins##_muxregs[] = { \
	69	{ \
	70	.reg = __muxreg1, \
	71	.mask = __mask, \
	72	.val = __ste1 ? __mask : 0, \
	73	}, { \
	74	.reg = __muxreg2, \
	75	.mask = __mask, \
	76	.val = __ste2 ? __mask : 0, \
	77	}, \
	78	}
	79
	80	#define GPIO_PINGROUP(__pins) \
	81	{ \
	82	.pins = __pins, \
	83	.npins = ARRAY_SIZE(__pins), \
	84	.muxregs = __pins##_muxregs, \
	85	.nmuxregs = ARRAY_SIZE(__pins##_muxregs), \
	86	}
	87
deda8287 VK	88	/**
	89	* struct spear_modemux - SPEAr mode mux configuration
	90	* @modes: mode ids supported by this group of muxregs
	91	* @nmuxregs: number of muxreg configurations to be done for modes
	92	* @muxregs: array of muxreg configurations to be done for modes
	93	*/
	94	struct spear_modemux {
	95	u16 modes;
	96	u8 nmuxregs;
	97	struct spear_muxreg *muxregs;
	98	};
	99
	100	/**
	101	* struct spear_pingroup - SPEAr pin group configurations
	102	* @name: name of pin group
	103	* @pins: array containing pin numbers
	104	* @npins: size of pins array
	105	* @modemuxs: array of modemux configurations for this pin group
	106	* @nmodemuxs: size of array modemuxs
	107	*
	108	* A representation of a group of pins in the SPEAr pin controller. Each group
	109	* allows some parameter or parameters to be configured.
	110	*/
	111	struct spear_pingroup {
	112	const char *name;
	113	const unsigned *pins;
	114	unsigned npins;
	115	struct spear_modemux *modemuxs;
	116	unsigned nmodemuxs;
	117	};
	118
	119	/**
	120	* struct spear_function - SPEAr pinctrl mux function
	121	* @name: The name of the function, exported to pinctrl core.
	122	* @groups: An array of pin groups that may select this function.
	123	* @ngroups: The number of entries in @groups.
	124	*/
	125	struct spear_function {
	126	const char *name;
	127	const char const groups;
	128	unsigned ngroups;
	129	};
	130
	131	/**
	132	* struct spear_pinctrl_machdata - SPEAr pin controller machine driver
	133	* configuration
	134	* @pins: An array describing all pins the pin controller affects.
	135	* All pins which are also GPIOs must be listed first within the *array,
	136	* and be numbered identically to the GPIO controller's *numbering.
	137	* @npins: The numbmer of entries in @pins.
	138	* @functions: An array describing all mux functions the SoC supports.
	139	* @nfunctions: The numbmer of entries in @functions.
	140	* @groups: An array describing all pin groups the pin SoC supports.
	141	* @ngroups: The numbmer of entries in @groups.
f4f8e563 VK	142	* @gpio_pingroups: gpio pingroups
f4f8e563 VK	143	* @ngpio_pingroups: gpio pingroups count
deda8287 VK	144	*
	145	* @modes_supported: Does SoC support modes
	146	* @mode: mode configured from probe
	147	* @pmx_modes: array of modes supported by SoC
	148	* @npmx_modes: number of entries in pmx_modes.
	149	*/
	150	struct spear_pinctrl_machdata {
	151	const struct pinctrl_pin_desc *pins;
	152	unsigned npins;
	153	struct spear_function **functions;
	154	unsigned nfunctions;
	155	struct spear_pingroup **groups;
	156	unsigned ngroups;
f4f8e563 VK	157	struct spear_gpio_pingroup *gpio_pingroups;
f4f8e563 VK	158	unsigned ngpio_pingroups;
deda8287 VK	159
	160	bool modes_supported;
	161	u16 mode;
	162	struct spear_pmx_mode **pmx_modes;
	163	unsigned npmx_modes;
	164	};
	165
	166	/**
	167	* struct spear_pmx - SPEAr pinctrl mux
	168	* @dev: pointer to struct dev of platform_device registered
	169	* @pctl: pointer to struct pinctrl_dev
	170	* @machdata: pointer to SoC or machine specific structure
	171	* @vbase: virtual base address of pinmux controller
	172	*/
	173	struct spear_pmx {
	174	struct device *dev;
	175	struct pinctrl_dev *pctl;
	176	struct spear_pinctrl_machdata *machdata;
	177	void __iomem *vbase;
	178	};
	179
	180	/* exported routines */
	181	void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
f4f8e563 VK	182	void __devinit
	183	pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup,
	184	unsigned count, u16 reg);
deda8287 VK	185	int __devinit spear_pinctrl_probe(struct platform_device *pdev,
	186	struct spear_pinctrl_machdata *machdata);
	187	int __devexit spear_pinctrl_remove(struct platform_device *pdev);
d1e77afe VK	188
	189	#define SPEAR_PIN_0_TO_101 \
	190	PINCTRL_PIN(0, "PLGPIO0"), \
	191	PINCTRL_PIN(1, "PLGPIO1"), \
	192	PINCTRL_PIN(2, "PLGPIO2"), \
	193	PINCTRL_PIN(3, "PLGPIO3"), \
	194	PINCTRL_PIN(4, "PLGPIO4"), \
	195	PINCTRL_PIN(5, "PLGPIO5"), \
	196	PINCTRL_PIN(6, "PLGPIO6"), \
	197	PINCTRL_PIN(7, "PLGPIO7"), \
	198	PINCTRL_PIN(8, "PLGPIO8"), \
	199	PINCTRL_PIN(9, "PLGPIO9"), \
	200	PINCTRL_PIN(10, "PLGPIO10"), \
	201	PINCTRL_PIN(11, "PLGPIO11"), \
	202	PINCTRL_PIN(12, "PLGPIO12"), \
	203	PINCTRL_PIN(13, "PLGPIO13"), \
	204	PINCTRL_PIN(14, "PLGPIO14"), \
	205	PINCTRL_PIN(15, "PLGPIO15"), \
	206	PINCTRL_PIN(16, "PLGPIO16"), \
	207	PINCTRL_PIN(17, "PLGPIO17"), \
	208	PINCTRL_PIN(18, "PLGPIO18"), \
	209	PINCTRL_PIN(19, "PLGPIO19"), \
	210	PINCTRL_PIN(20, "PLGPIO20"), \
	211	PINCTRL_PIN(21, "PLGPIO21"), \
	212	PINCTRL_PIN(22, "PLGPIO22"), \
	213	PINCTRL_PIN(23, "PLGPIO23"), \
	214	PINCTRL_PIN(24, "PLGPIO24"), \
	215	PINCTRL_PIN(25, "PLGPIO25"), \
	216	PINCTRL_PIN(26, "PLGPIO26"), \
	217	PINCTRL_PIN(27, "PLGPIO27"), \
	218	PINCTRL_PIN(28, "PLGPIO28"), \
	219	PINCTRL_PIN(29, "PLGPIO29"), \
	220	PINCTRL_PIN(30, "PLGPIO30"), \
	221	PINCTRL_PIN(31, "PLGPIO31"), \
	222	PINCTRL_PIN(32, "PLGPIO32"), \
	223	PINCTRL_PIN(33, "PLGPIO33"), \
	224	PINCTRL_PIN(34, "PLGPIO34"), \
	225	PINCTRL_PIN(35, "PLGPIO35"), \
	226	PINCTRL_PIN(36, "PLGPIO36"), \
	227	PINCTRL_PIN(37, "PLGPIO37"), \
	228	PINCTRL_PIN(38, "PLGPIO38"), \
	229	PINCTRL_PIN(39, "PLGPIO39"), \
	230	PINCTRL_PIN(40, "PLGPIO40"), \
	231	PINCTRL_PIN(41, "PLGPIO41"), \
	232	PINCTRL_PIN(42, "PLGPIO42"), \
	233	PINCTRL_PIN(43, "PLGPIO43"), \
	234	PINCTRL_PIN(44, "PLGPIO44"), \
	235	PINCTRL_PIN(45, "PLGPIO45"), \
	236	PINCTRL_PIN(46, "PLGPIO46"), \
	237	PINCTRL_PIN(47, "PLGPIO47"), \
	238	PINCTRL_PIN(48, "PLGPIO48"), \
	239	PINCTRL_PIN(49, "PLGPIO49"), \
	240	PINCTRL_PIN(50, "PLGPIO50"), \
	241	PINCTRL_PIN(51, "PLGPIO51"), \
	242	PINCTRL_PIN(52, "PLGPIO52"), \
	243	PINCTRL_PIN(53, "PLGPIO53"), \
	244	PINCTRL_PIN(54, "PLGPIO54"), \
	245	PINCTRL_PIN(55, "PLGPIO55"), \
	246	PINCTRL_PIN(56, "PLGPIO56"), \
	247	PINCTRL_PIN(57, "PLGPIO57"), \
	248	PINCTRL_PIN(58, "PLGPIO58"), \
	249	PINCTRL_PIN(59, "PLGPIO59"), \
	250	PINCTRL_PIN(60, "PLGPIO60"), \
	251	PINCTRL_PIN(61, "PLGPIO61"), \
252	PINCTRL_PIN(62, "PLGPIO62"), \
253	PINCTRL_PIN(63, "PLGPIO63"), \
254	PINCTRL_PIN(64, "PLGPIO64"), \
255	PINCTRL_PIN(65, "PLGPIO65"), \
256	PINCTRL_PIN(66, "PLGPIO66"), \
257	PINCTRL_PIN(67, "PLGPIO67"), \
258	PINCTRL_PIN(68, "PLGPIO68"), \
259	PINCTRL_PIN(69, "PLGPIO69"), \
260	PINCTRL_PIN(70, "PLGPIO70"), \
261	PINCTRL_PIN(71, "PLGPIO71"), \
262	PINCTRL_PIN(72, "PLGPIO72"), \
263	PINCTRL_PIN(73, "PLGPIO73"), \
264	PINCTRL_PIN(74, "PLGPIO74"), \
265	PINCTRL_PIN(75, "PLGPIO75"), \
266	PINCTRL_PIN(76, "PLGPIO76"), \
267	PINCTRL_PIN(77, "PLGPIO77"), \
268	PINCTRL_PIN(78, "PLGPIO78"), \
269	PINCTRL_PIN(79, "PLGPIO79"), \
270	PINCTRL_PIN(80, "PLGPIO80"), \
271	PINCTRL_PIN(81, "PLGPIO81"), \
272	PINCTRL_PIN(82, "PLGPIO82"), \
273	PINCTRL_PIN(83, "PLGPIO83"), \
274	PINCTRL_PIN(84, "PLGPIO84"), \
275	PINCTRL_PIN(85, "PLGPIO85"), \
276	PINCTRL_PIN(86, "PLGPIO86"), \
277	PINCTRL_PIN(87, "PLGPIO87"), \
278	PINCTRL_PIN(88, "PLGPIO88"), \
279	PINCTRL_PIN(89, "PLGPIO89"), \
280	PINCTRL_PIN(90, "PLGPIO90"), \
281	PINCTRL_PIN(91, "PLGPIO91"), \
282	PINCTRL_PIN(92, "PLGPIO92"), \
283	PINCTRL_PIN(93, "PLGPIO93"), \
284	PINCTRL_PIN(94, "PLGPIO94"), \
285	PINCTRL_PIN(95, "PLGPIO95"), \
286	PINCTRL_PIN(96, "PLGPIO96"), \
287	PINCTRL_PIN(97, "PLGPIO97"), \
288	PINCTRL_PIN(98, "PLGPIO98"), \
289	PINCTRL_PIN(99, "PLGPIO99"), \
290	PINCTRL_PIN(100, "PLGPIO100"), \
291	PINCTRL_PIN(101, "PLGPIO101")
292
85ed41a7 VK	293	#define SPEAR_PIN_102_TO_245 \
	294	PINCTRL_PIN(102, "PLGPIO102"), \
	295	PINCTRL_PIN(103, "PLGPIO103"), \
	296	PINCTRL_PIN(104, "PLGPIO104"), \
	297	PINCTRL_PIN(105, "PLGPIO105"), \
	298	PINCTRL_PIN(106, "PLGPIO106"), \
	299	PINCTRL_PIN(107, "PLGPIO107"), \
	300	PINCTRL_PIN(108, "PLGPIO108"), \
	301	PINCTRL_PIN(109, "PLGPIO109"), \
	302	PINCTRL_PIN(110, "PLGPIO110"), \
	303	PINCTRL_PIN(111, "PLGPIO111"), \
	304	PINCTRL_PIN(112, "PLGPIO112"), \
	305	PINCTRL_PIN(113, "PLGPIO113"), \
	306	PINCTRL_PIN(114, "PLGPIO114"), \
	307	PINCTRL_PIN(115, "PLGPIO115"), \
	308	PINCTRL_PIN(116, "PLGPIO116"), \
	309	PINCTRL_PIN(117, "PLGPIO117"), \
	310	PINCTRL_PIN(118, "PLGPIO118"), \
	311	PINCTRL_PIN(119, "PLGPIO119"), \
	312	PINCTRL_PIN(120, "PLGPIO120"), \
	313	PINCTRL_PIN(121, "PLGPIO121"), \
	314	PINCTRL_PIN(122, "PLGPIO122"), \
	315	PINCTRL_PIN(123, "PLGPIO123"), \
	316	PINCTRL_PIN(124, "PLGPIO124"), \
	317	PINCTRL_PIN(125, "PLGPIO125"), \
	318	PINCTRL_PIN(126, "PLGPIO126"), \
	319	PINCTRL_PIN(127, "PLGPIO127"), \
	320	PINCTRL_PIN(128, "PLGPIO128"), \
	321	PINCTRL_PIN(129, "PLGPIO129"), \
	322	PINCTRL_PIN(130, "PLGPIO130"), \
	323	PINCTRL_PIN(131, "PLGPIO131"), \
	324	PINCTRL_PIN(132, "PLGPIO132"), \
	325	PINCTRL_PIN(133, "PLGPIO133"), \
	326	PINCTRL_PIN(134, "PLGPIO134"), \
	327	PINCTRL_PIN(135, "PLGPIO135"), \
	328	PINCTRL_PIN(136, "PLGPIO136"), \
	329	PINCTRL_PIN(137, "PLGPIO137"), \
	330	PINCTRL_PIN(138, "PLGPIO138"), \
	331	PINCTRL_PIN(139, "PLGPIO139"), \
	332	PINCTRL_PIN(140, "PLGPIO140"), \
	333	PINCTRL_PIN(141, "PLGPIO141"), \
	334	PINCTRL_PIN(142, "PLGPIO142"), \
	335	PINCTRL_PIN(143, "PLGPIO143"), \
	336	PINCTRL_PIN(144, "PLGPIO144"), \
	337	PINCTRL_PIN(145, "PLGPIO145"), \
	338	PINCTRL_PIN(146, "PLGPIO146"), \
	339	PINCTRL_PIN(147, "PLGPIO147"), \
	340	PINCTRL_PIN(148, "PLGPIO148"), \
	341	PINCTRL_PIN(149, "PLGPIO149"), \
	342	PINCTRL_PIN(150, "PLGPIO150"), \
	343	PINCTRL_PIN(151, "PLGPIO151"), \
	344	PINCTRL_PIN(152, "PLGPIO152"), \
	345	PINCTRL_PIN(153, "PLGPIO153"), \
	346	PINCTRL_PIN(154, "PLGPIO154"), \
	347	PINCTRL_PIN(155, "PLGPIO155"), \
	348	PINCTRL_PIN(156, "PLGPIO156"), \
	349	PINCTRL_PIN(157, "PLGPIO157"), \
	350	PINCTRL_PIN(158, "PLGPIO158"), \
	351	PINCTRL_PIN(159, "PLGPIO159"), \
	352	PINCTRL_PIN(160, "PLGPIO160"), \
	353	PINCTRL_PIN(161, "PLGPIO161"), \
	354	PINCTRL_PIN(162, "PLGPIO162"), \
	355	PINCTRL_PIN(163, "PLGPIO163"), \
	356	PINCTRL_PIN(164, "PLGPIO164"), \
357	PINCTRL_PIN(165, "PLGPIO165"), \
358	PINCTRL_PIN(166, "PLGPIO166"), \
359	PINCTRL_PIN(167, "PLGPIO167"), \
360	PINCTRL_PIN(168, "PLGPIO168"), \
361	PINCTRL_PIN(169, "PLGPIO169"), \
362	PINCTRL_PIN(170, "PLGPIO170"), \
363	PINCTRL_PIN(171, "PLGPIO171"), \
364	PINCTRL_PIN(172, "PLGPIO172"), \
365	PINCTRL_PIN(173, "PLGPIO173"), \
366	PINCTRL_PIN(174, "PLGPIO174"), \
367	PINCTRL_PIN(175, "PLGPIO175"), \
368	PINCTRL_PIN(176, "PLGPIO176"), \
369	PINCTRL_PIN(177, "PLGPIO177"), \
370	PINCTRL_PIN(178, "PLGPIO178"), \
371	PINCTRL_PIN(179, "PLGPIO179"), \
372	PINCTRL_PIN(180, "PLGPIO180"), \
373	PINCTRL_PIN(181, "PLGPIO181"), \
374	PINCTRL_PIN(182, "PLGPIO182"), \
375	PINCTRL_PIN(183, "PLGPIO183"), \
376	PINCTRL_PIN(184, "PLGPIO184"), \
377	PINCTRL_PIN(185, "PLGPIO185"), \
378	PINCTRL_PIN(186, "PLGPIO186"), \
379	PINCTRL_PIN(187, "PLGPIO187"), \
380	PINCTRL_PIN(188, "PLGPIO188"), \
381	PINCTRL_PIN(189, "PLGPIO189"), \
382	PINCTRL_PIN(190, "PLGPIO190"), \
383	PINCTRL_PIN(191, "PLGPIO191"), \
384	PINCTRL_PIN(192, "PLGPIO192"), \
385	PINCTRL_PIN(193, "PLGPIO193"), \
386	PINCTRL_PIN(194, "PLGPIO194"), \
387	PINCTRL_PIN(195, "PLGPIO195"), \
388	PINCTRL_PIN(196, "PLGPIO196"), \
389	PINCTRL_PIN(197, "PLGPIO197"), \
390	PINCTRL_PIN(198, "PLGPIO198"), \
391	PINCTRL_PIN(199, "PLGPIO199"), \
392	PINCTRL_PIN(200, "PLGPIO200"), \
393	PINCTRL_PIN(201, "PLGPIO201"), \
394	PINCTRL_PIN(202, "PLGPIO202"), \
395	PINCTRL_PIN(203, "PLGPIO203"), \
396	PINCTRL_PIN(204, "PLGPIO204"), \
397	PINCTRL_PIN(205, "PLGPIO205"), \
398	PINCTRL_PIN(206, "PLGPIO206"), \
399	PINCTRL_PIN(207, "PLGPIO207"), \
400	PINCTRL_PIN(208, "PLGPIO208"), \
401	PINCTRL_PIN(209, "PLGPIO209"), \
402	PINCTRL_PIN(210, "PLGPIO210"), \
403	PINCTRL_PIN(211, "PLGPIO211"), \
404	PINCTRL_PIN(212, "PLGPIO212"), \
405	PINCTRL_PIN(213, "PLGPIO213"), \
406	PINCTRL_PIN(214, "PLGPIO214"), \
407	PINCTRL_PIN(215, "PLGPIO215"), \
408	PINCTRL_PIN(216, "PLGPIO216"), \
409	PINCTRL_PIN(217, "PLGPIO217"), \
410	PINCTRL_PIN(218, "PLGPIO218"), \
411	PINCTRL_PIN(219, "PLGPIO219"), \
412	PINCTRL_PIN(220, "PLGPIO220"), \
413	PINCTRL_PIN(221, "PLGPIO221"), \
414	PINCTRL_PIN(222, "PLGPIO222"), \
415	PINCTRL_PIN(223, "PLGPIO223"), \
416	PINCTRL_PIN(224, "PLGPIO224"), \
417	PINCTRL_PIN(225, "PLGPIO225"), \
418	PINCTRL_PIN(226, "PLGPIO226"), \
419	PINCTRL_PIN(227, "PLGPIO227"), \
420	PINCTRL_PIN(228, "PLGPIO228"), \
421	PINCTRL_PIN(229, "PLGPIO229"), \
422	PINCTRL_PIN(230, "PLGPIO230"), \
423	PINCTRL_PIN(231, "PLGPIO231"), \
424	PINCTRL_PIN(232, "PLGPIO232"), \
425	PINCTRL_PIN(233, "PLGPIO233"), \
426	PINCTRL_PIN(234, "PLGPIO234"), \
427	PINCTRL_PIN(235, "PLGPIO235"), \
428	PINCTRL_PIN(236, "PLGPIO236"), \
429	PINCTRL_PIN(237, "PLGPIO237"), \
430	PINCTRL_PIN(238, "PLGPIO238"), \
431	PINCTRL_PIN(239, "PLGPIO239"), \
432	PINCTRL_PIN(240, "PLGPIO240"), \
433	PINCTRL_PIN(241, "PLGPIO241"), \
434	PINCTRL_PIN(242, "PLGPIO242"), \
435	PINCTRL_PIN(243, "PLGPIO243"), \
436	PINCTRL_PIN(244, "PLGPIO244"), \
437	PINCTRL_PIN(245, "PLGPIO245")
438
deda8287	439	#endif /* __PINMUX_SPEAR_H__ */