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52130b60 VK |
1 | /* |
2 | * Driver for the ST Microelectronics SPEAr3xx pinmux | |
3 | * | |
4 | * Copyright (C) 2012 ST Microelectronics | |
5 | * Viresh Kumar <viresh.kumar@st.com> | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public | |
8 | * License version 2. This program is licensed "as is" without any | |
9 | * warranty of any kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/pinctrl/pinctrl.h> | |
13 | ||
14 | #include "pinctrl-spear3xx.h" | |
15 | ||
16 | /* pins */ | |
17 | static const struct pinctrl_pin_desc spear3xx_pins[] = { | |
18 | PINCTRL_PIN(0, "PLGPIO0"), | |
19 | PINCTRL_PIN(1, "PLGPIO1"), | |
20 | PINCTRL_PIN(2, "PLGPIO2"), | |
21 | PINCTRL_PIN(3, "PLGPIO3"), | |
22 | PINCTRL_PIN(4, "PLGPIO4"), | |
23 | PINCTRL_PIN(5, "PLGPIO5"), | |
24 | PINCTRL_PIN(6, "PLGPIO6"), | |
25 | PINCTRL_PIN(7, "PLGPIO7"), | |
26 | PINCTRL_PIN(8, "PLGPIO8"), | |
27 | PINCTRL_PIN(9, "PLGPIO9"), | |
28 | PINCTRL_PIN(10, "PLGPIO10"), | |
29 | PINCTRL_PIN(11, "PLGPIO11"), | |
30 | PINCTRL_PIN(12, "PLGPIO12"), | |
31 | PINCTRL_PIN(13, "PLGPIO13"), | |
32 | PINCTRL_PIN(14, "PLGPIO14"), | |
33 | PINCTRL_PIN(15, "PLGPIO15"), | |
34 | PINCTRL_PIN(16, "PLGPIO16"), | |
35 | PINCTRL_PIN(17, "PLGPIO17"), | |
36 | PINCTRL_PIN(18, "PLGPIO18"), | |
37 | PINCTRL_PIN(19, "PLGPIO19"), | |
38 | PINCTRL_PIN(20, "PLGPIO20"), | |
39 | PINCTRL_PIN(21, "PLGPIO21"), | |
40 | PINCTRL_PIN(22, "PLGPIO22"), | |
41 | PINCTRL_PIN(23, "PLGPIO23"), | |
42 | PINCTRL_PIN(24, "PLGPIO24"), | |
43 | PINCTRL_PIN(25, "PLGPIO25"), | |
44 | PINCTRL_PIN(26, "PLGPIO26"), | |
45 | PINCTRL_PIN(27, "PLGPIO27"), | |
46 | PINCTRL_PIN(28, "PLGPIO28"), | |
47 | PINCTRL_PIN(29, "PLGPIO29"), | |
48 | PINCTRL_PIN(30, "PLGPIO30"), | |
49 | PINCTRL_PIN(31, "PLGPIO31"), | |
50 | PINCTRL_PIN(32, "PLGPIO32"), | |
51 | PINCTRL_PIN(33, "PLGPIO33"), | |
52 | PINCTRL_PIN(34, "PLGPIO34"), | |
53 | PINCTRL_PIN(35, "PLGPIO35"), | |
54 | PINCTRL_PIN(36, "PLGPIO36"), | |
55 | PINCTRL_PIN(37, "PLGPIO37"), | |
56 | PINCTRL_PIN(38, "PLGPIO38"), | |
57 | PINCTRL_PIN(39, "PLGPIO39"), | |
58 | PINCTRL_PIN(40, "PLGPIO40"), | |
59 | PINCTRL_PIN(41, "PLGPIO41"), | |
60 | PINCTRL_PIN(42, "PLGPIO42"), | |
61 | PINCTRL_PIN(43, "PLGPIO43"), | |
62 | PINCTRL_PIN(44, "PLGPIO44"), | |
63 | PINCTRL_PIN(45, "PLGPIO45"), | |
64 | PINCTRL_PIN(46, "PLGPIO46"), | |
65 | PINCTRL_PIN(47, "PLGPIO47"), | |
66 | PINCTRL_PIN(48, "PLGPIO48"), | |
67 | PINCTRL_PIN(49, "PLGPIO49"), | |
68 | PINCTRL_PIN(50, "PLGPIO50"), | |
69 | PINCTRL_PIN(51, "PLGPIO51"), | |
70 | PINCTRL_PIN(52, "PLGPIO52"), | |
71 | PINCTRL_PIN(53, "PLGPIO53"), | |
72 | PINCTRL_PIN(54, "PLGPIO54"), | |
73 | PINCTRL_PIN(55, "PLGPIO55"), | |
74 | PINCTRL_PIN(56, "PLGPIO56"), | |
75 | PINCTRL_PIN(57, "PLGPIO57"), | |
76 | PINCTRL_PIN(58, "PLGPIO58"), | |
77 | PINCTRL_PIN(59, "PLGPIO59"), | |
78 | PINCTRL_PIN(60, "PLGPIO60"), | |
79 | PINCTRL_PIN(61, "PLGPIO61"), | |
80 | PINCTRL_PIN(62, "PLGPIO62"), | |
81 | PINCTRL_PIN(63, "PLGPIO63"), | |
82 | PINCTRL_PIN(64, "PLGPIO64"), | |
83 | PINCTRL_PIN(65, "PLGPIO65"), | |
84 | PINCTRL_PIN(66, "PLGPIO66"), | |
85 | PINCTRL_PIN(67, "PLGPIO67"), | |
86 | PINCTRL_PIN(68, "PLGPIO68"), | |
87 | PINCTRL_PIN(69, "PLGPIO69"), | |
88 | PINCTRL_PIN(70, "PLGPIO70"), | |
89 | PINCTRL_PIN(71, "PLGPIO71"), | |
90 | PINCTRL_PIN(72, "PLGPIO72"), | |
91 | PINCTRL_PIN(73, "PLGPIO73"), | |
92 | PINCTRL_PIN(74, "PLGPIO74"), | |
93 | PINCTRL_PIN(75, "PLGPIO75"), | |
94 | PINCTRL_PIN(76, "PLGPIO76"), | |
95 | PINCTRL_PIN(77, "PLGPIO77"), | |
96 | PINCTRL_PIN(78, "PLGPIO78"), | |
97 | PINCTRL_PIN(79, "PLGPIO79"), | |
98 | PINCTRL_PIN(80, "PLGPIO80"), | |
99 | PINCTRL_PIN(81, "PLGPIO81"), | |
100 | PINCTRL_PIN(82, "PLGPIO82"), | |
101 | PINCTRL_PIN(83, "PLGPIO83"), | |
102 | PINCTRL_PIN(84, "PLGPIO84"), | |
103 | PINCTRL_PIN(85, "PLGPIO85"), | |
104 | PINCTRL_PIN(86, "PLGPIO86"), | |
105 | PINCTRL_PIN(87, "PLGPIO87"), | |
106 | PINCTRL_PIN(88, "PLGPIO88"), | |
107 | PINCTRL_PIN(89, "PLGPIO89"), | |
108 | PINCTRL_PIN(90, "PLGPIO90"), | |
109 | PINCTRL_PIN(91, "PLGPIO91"), | |
110 | PINCTRL_PIN(92, "PLGPIO92"), | |
111 | PINCTRL_PIN(93, "PLGPIO93"), | |
112 | PINCTRL_PIN(94, "PLGPIO94"), | |
113 | PINCTRL_PIN(95, "PLGPIO95"), | |
114 | PINCTRL_PIN(96, "PLGPIO96"), | |
115 | PINCTRL_PIN(97, "PLGPIO97"), | |
116 | PINCTRL_PIN(98, "PLGPIO98"), | |
117 | PINCTRL_PIN(99, "PLGPIO99"), | |
118 | PINCTRL_PIN(100, "PLGPIO100"), | |
119 | PINCTRL_PIN(101, "PLGPIO101"), | |
120 | }; | |
121 | ||
122 | /* firda_pins */ | |
123 | static const unsigned firda_pins[] = { 0, 1 }; | |
124 | static struct spear_muxreg firda_muxreg[] = { | |
125 | { | |
126 | .reg = -1, | |
127 | .mask = PMX_FIRDA_MASK, | |
128 | .val = PMX_FIRDA_MASK, | |
129 | }, | |
130 | }; | |
131 | ||
132 | static struct spear_modemux firda_modemux[] = { | |
133 | { | |
134 | .modes = ~0, | |
135 | .muxregs = firda_muxreg, | |
136 | .nmuxregs = ARRAY_SIZE(firda_muxreg), | |
137 | }, | |
138 | }; | |
139 | ||
140 | struct spear_pingroup spear3xx_firda_pingroup = { | |
141 | .name = "firda_grp", | |
142 | .pins = firda_pins, | |
143 | .npins = ARRAY_SIZE(firda_pins), | |
144 | .modemuxs = firda_modemux, | |
145 | .nmodemuxs = ARRAY_SIZE(firda_modemux), | |
146 | }; | |
147 | ||
148 | static const char *const firda_grps[] = { "firda_grp" }; | |
149 | struct spear_function spear3xx_firda_function = { | |
150 | .name = "firda", | |
151 | .groups = firda_grps, | |
152 | .ngroups = ARRAY_SIZE(firda_grps), | |
153 | }; | |
154 | ||
155 | /* i2c_pins */ | |
156 | static const unsigned i2c_pins[] = { 4, 5 }; | |
157 | static struct spear_muxreg i2c_muxreg[] = { | |
158 | { | |
159 | .reg = -1, | |
160 | .mask = PMX_I2C_MASK, | |
161 | .val = PMX_I2C_MASK, | |
162 | }, | |
163 | }; | |
164 | ||
165 | static struct spear_modemux i2c_modemux[] = { | |
166 | { | |
167 | .modes = ~0, | |
168 | .muxregs = i2c_muxreg, | |
169 | .nmuxregs = ARRAY_SIZE(i2c_muxreg), | |
170 | }, | |
171 | }; | |
172 | ||
173 | struct spear_pingroup spear3xx_i2c_pingroup = { | |
174 | .name = "i2c0_grp", | |
175 | .pins = i2c_pins, | |
176 | .npins = ARRAY_SIZE(i2c_pins), | |
177 | .modemuxs = i2c_modemux, | |
178 | .nmodemuxs = ARRAY_SIZE(i2c_modemux), | |
179 | }; | |
180 | ||
181 | static const char *const i2c_grps[] = { "i2c0_grp" }; | |
182 | struct spear_function spear3xx_i2c_function = { | |
183 | .name = "i2c0", | |
184 | .groups = i2c_grps, | |
185 | .ngroups = ARRAY_SIZE(i2c_grps), | |
186 | }; | |
187 | ||
188 | /* ssp_cs_pins */ | |
189 | static const unsigned ssp_cs_pins[] = { 34, 35, 36 }; | |
190 | static struct spear_muxreg ssp_cs_muxreg[] = { | |
191 | { | |
192 | .reg = -1, | |
193 | .mask = PMX_SSP_CS_MASK, | |
194 | .val = PMX_SSP_CS_MASK, | |
195 | }, | |
196 | }; | |
197 | ||
198 | static struct spear_modemux ssp_cs_modemux[] = { | |
199 | { | |
200 | .modes = ~0, | |
201 | .muxregs = ssp_cs_muxreg, | |
202 | .nmuxregs = ARRAY_SIZE(ssp_cs_muxreg), | |
203 | }, | |
204 | }; | |
205 | ||
206 | struct spear_pingroup spear3xx_ssp_cs_pingroup = { | |
207 | .name = "ssp_cs_grp", | |
208 | .pins = ssp_cs_pins, | |
209 | .npins = ARRAY_SIZE(ssp_cs_pins), | |
210 | .modemuxs = ssp_cs_modemux, | |
211 | .nmodemuxs = ARRAY_SIZE(ssp_cs_modemux), | |
212 | }; | |
213 | ||
214 | static const char *const ssp_cs_grps[] = { "ssp_cs_grp" }; | |
215 | struct spear_function spear3xx_ssp_cs_function = { | |
216 | .name = "ssp_cs", | |
217 | .groups = ssp_cs_grps, | |
218 | .ngroups = ARRAY_SIZE(ssp_cs_grps), | |
219 | }; | |
220 | ||
221 | /* ssp_pins */ | |
222 | static const unsigned ssp_pins[] = { 6, 7, 8, 9 }; | |
223 | static struct spear_muxreg ssp_muxreg[] = { | |
224 | { | |
225 | .reg = -1, | |
226 | .mask = PMX_SSP_MASK, | |
227 | .val = PMX_SSP_MASK, | |
228 | }, | |
229 | }; | |
230 | ||
231 | static struct spear_modemux ssp_modemux[] = { | |
232 | { | |
233 | .modes = ~0, | |
234 | .muxregs = ssp_muxreg, | |
235 | .nmuxregs = ARRAY_SIZE(ssp_muxreg), | |
236 | }, | |
237 | }; | |
238 | ||
239 | struct spear_pingroup spear3xx_ssp_pingroup = { | |
240 | .name = "ssp0_grp", | |
241 | .pins = ssp_pins, | |
242 | .npins = ARRAY_SIZE(ssp_pins), | |
243 | .modemuxs = ssp_modemux, | |
244 | .nmodemuxs = ARRAY_SIZE(ssp_modemux), | |
245 | }; | |
246 | ||
247 | static const char *const ssp_grps[] = { "ssp0_grp" }; | |
248 | struct spear_function spear3xx_ssp_function = { | |
249 | .name = "ssp0", | |
250 | .groups = ssp_grps, | |
251 | .ngroups = ARRAY_SIZE(ssp_grps), | |
252 | }; | |
253 | ||
254 | /* mii_pins */ | |
255 | static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, | |
256 | 21, 22, 23, 24, 25, 26, 27 }; | |
257 | static struct spear_muxreg mii_muxreg[] = { | |
258 | { | |
259 | .reg = -1, | |
260 | .mask = PMX_MII_MASK, | |
261 | .val = PMX_MII_MASK, | |
262 | }, | |
263 | }; | |
264 | ||
265 | static struct spear_modemux mii_modemux[] = { | |
266 | { | |
267 | .modes = ~0, | |
268 | .muxregs = mii_muxreg, | |
269 | .nmuxregs = ARRAY_SIZE(mii_muxreg), | |
270 | }, | |
271 | }; | |
272 | ||
273 | struct spear_pingroup spear3xx_mii_pingroup = { | |
274 | .name = "mii0_grp", | |
275 | .pins = mii_pins, | |
276 | .npins = ARRAY_SIZE(mii_pins), | |
277 | .modemuxs = mii_modemux, | |
278 | .nmodemuxs = ARRAY_SIZE(mii_modemux), | |
279 | }; | |
280 | ||
281 | static const char *const mii_grps[] = { "mii0_grp" }; | |
282 | struct spear_function spear3xx_mii_function = { | |
283 | .name = "mii0", | |
284 | .groups = mii_grps, | |
285 | .ngroups = ARRAY_SIZE(mii_grps), | |
286 | }; | |
287 | ||
288 | /* gpio0_pin0_pins */ | |
289 | static const unsigned gpio0_pin0_pins[] = { 28 }; | |
290 | static struct spear_muxreg gpio0_pin0_muxreg[] = { | |
291 | { | |
292 | .reg = -1, | |
293 | .mask = PMX_GPIO_PIN0_MASK, | |
294 | .val = PMX_GPIO_PIN0_MASK, | |
295 | }, | |
296 | }; | |
297 | ||
298 | static struct spear_modemux gpio0_pin0_modemux[] = { | |
299 | { | |
300 | .modes = ~0, | |
301 | .muxregs = gpio0_pin0_muxreg, | |
302 | .nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg), | |
303 | }, | |
304 | }; | |
305 | ||
306 | struct spear_pingroup spear3xx_gpio0_pin0_pingroup = { | |
307 | .name = "gpio0_pin0_grp", | |
308 | .pins = gpio0_pin0_pins, | |
309 | .npins = ARRAY_SIZE(gpio0_pin0_pins), | |
310 | .modemuxs = gpio0_pin0_modemux, | |
311 | .nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux), | |
312 | }; | |
313 | ||
314 | /* gpio0_pin1_pins */ | |
315 | static const unsigned gpio0_pin1_pins[] = { 29 }; | |
316 | static struct spear_muxreg gpio0_pin1_muxreg[] = { | |
317 | { | |
318 | .reg = -1, | |
319 | .mask = PMX_GPIO_PIN1_MASK, | |
320 | .val = PMX_GPIO_PIN1_MASK, | |
321 | }, | |
322 | }; | |
323 | ||
324 | static struct spear_modemux gpio0_pin1_modemux[] = { | |
325 | { | |
326 | .modes = ~0, | |
327 | .muxregs = gpio0_pin1_muxreg, | |
328 | .nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg), | |
329 | }, | |
330 | }; | |
331 | ||
332 | struct spear_pingroup spear3xx_gpio0_pin1_pingroup = { | |
333 | .name = "gpio0_pin1_grp", | |
334 | .pins = gpio0_pin1_pins, | |
335 | .npins = ARRAY_SIZE(gpio0_pin1_pins), | |
336 | .modemuxs = gpio0_pin1_modemux, | |
337 | .nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux), | |
338 | }; | |
339 | ||
340 | /* gpio0_pin2_pins */ | |
341 | static const unsigned gpio0_pin2_pins[] = { 30 }; | |
342 | static struct spear_muxreg gpio0_pin2_muxreg[] = { | |
343 | { | |
344 | .reg = -1, | |
345 | .mask = PMX_GPIO_PIN2_MASK, | |
346 | .val = PMX_GPIO_PIN2_MASK, | |
347 | }, | |
348 | }; | |
349 | ||
350 | static struct spear_modemux gpio0_pin2_modemux[] = { | |
351 | { | |
352 | .modes = ~0, | |
353 | .muxregs = gpio0_pin2_muxreg, | |
354 | .nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg), | |
355 | }, | |
356 | }; | |
357 | ||
358 | struct spear_pingroup spear3xx_gpio0_pin2_pingroup = { | |
359 | .name = "gpio0_pin2_grp", | |
360 | .pins = gpio0_pin2_pins, | |
361 | .npins = ARRAY_SIZE(gpio0_pin2_pins), | |
362 | .modemuxs = gpio0_pin2_modemux, | |
363 | .nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux), | |
364 | }; | |
365 | ||
366 | /* gpio0_pin3_pins */ | |
367 | static const unsigned gpio0_pin3_pins[] = { 31 }; | |
368 | static struct spear_muxreg gpio0_pin3_muxreg[] = { | |
369 | { | |
370 | .reg = -1, | |
371 | .mask = PMX_GPIO_PIN3_MASK, | |
372 | .val = PMX_GPIO_PIN3_MASK, | |
373 | }, | |
374 | }; | |
375 | ||
376 | static struct spear_modemux gpio0_pin3_modemux[] = { | |
377 | { | |
378 | .modes = ~0, | |
379 | .muxregs = gpio0_pin3_muxreg, | |
380 | .nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg), | |
381 | }, | |
382 | }; | |
383 | ||
384 | struct spear_pingroup spear3xx_gpio0_pin3_pingroup = { | |
385 | .name = "gpio0_pin3_grp", | |
386 | .pins = gpio0_pin3_pins, | |
387 | .npins = ARRAY_SIZE(gpio0_pin3_pins), | |
388 | .modemuxs = gpio0_pin3_modemux, | |
389 | .nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux), | |
390 | }; | |
391 | ||
392 | /* gpio0_pin4_pins */ | |
393 | static const unsigned gpio0_pin4_pins[] = { 32 }; | |
394 | static struct spear_muxreg gpio0_pin4_muxreg[] = { | |
395 | { | |
396 | .reg = -1, | |
397 | .mask = PMX_GPIO_PIN4_MASK, | |
398 | .val = PMX_GPIO_PIN4_MASK, | |
399 | }, | |
400 | }; | |
401 | ||
402 | static struct spear_modemux gpio0_pin4_modemux[] = { | |
403 | { | |
404 | .modes = ~0, | |
405 | .muxregs = gpio0_pin4_muxreg, | |
406 | .nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg), | |
407 | }, | |
408 | }; | |
409 | ||
410 | struct spear_pingroup spear3xx_gpio0_pin4_pingroup = { | |
411 | .name = "gpio0_pin4_grp", | |
412 | .pins = gpio0_pin4_pins, | |
413 | .npins = ARRAY_SIZE(gpio0_pin4_pins), | |
414 | .modemuxs = gpio0_pin4_modemux, | |
415 | .nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux), | |
416 | }; | |
417 | ||
418 | /* gpio0_pin5_pins */ | |
419 | static const unsigned gpio0_pin5_pins[] = { 33 }; | |
420 | static struct spear_muxreg gpio0_pin5_muxreg[] = { | |
421 | { | |
422 | .reg = -1, | |
423 | .mask = PMX_GPIO_PIN5_MASK, | |
424 | .val = PMX_GPIO_PIN5_MASK, | |
425 | }, | |
426 | }; | |
427 | ||
428 | static struct spear_modemux gpio0_pin5_modemux[] = { | |
429 | { | |
430 | .modes = ~0, | |
431 | .muxregs = gpio0_pin5_muxreg, | |
432 | .nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg), | |
433 | }, | |
434 | }; | |
435 | ||
436 | struct spear_pingroup spear3xx_gpio0_pin5_pingroup = { | |
437 | .name = "gpio0_pin5_grp", | |
438 | .pins = gpio0_pin5_pins, | |
439 | .npins = ARRAY_SIZE(gpio0_pin5_pins), | |
440 | .modemuxs = gpio0_pin5_modemux, | |
441 | .nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux), | |
442 | }; | |
443 | ||
444 | static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp", | |
445 | "gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp", | |
446 | }; | |
447 | struct spear_function spear3xx_gpio0_function = { | |
448 | .name = "gpio0", | |
449 | .groups = gpio0_grps, | |
450 | .ngroups = ARRAY_SIZE(gpio0_grps), | |
451 | }; | |
452 | ||
453 | /* uart0_ext_pins */ | |
454 | static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 }; | |
455 | static struct spear_muxreg uart0_ext_muxreg[] = { | |
456 | { | |
457 | .reg = -1, | |
458 | .mask = PMX_UART0_MODEM_MASK, | |
459 | .val = PMX_UART0_MODEM_MASK, | |
460 | }, | |
461 | }; | |
462 | ||
463 | static struct spear_modemux uart0_ext_modemux[] = { | |
464 | { | |
465 | .modes = ~0, | |
466 | .muxregs = uart0_ext_muxreg, | |
467 | .nmuxregs = ARRAY_SIZE(uart0_ext_muxreg), | |
468 | }, | |
469 | }; | |
470 | ||
471 | struct spear_pingroup spear3xx_uart0_ext_pingroup = { | |
472 | .name = "uart0_ext_grp", | |
473 | .pins = uart0_ext_pins, | |
474 | .npins = ARRAY_SIZE(uart0_ext_pins), | |
475 | .modemuxs = uart0_ext_modemux, | |
476 | .nmodemuxs = ARRAY_SIZE(uart0_ext_modemux), | |
477 | }; | |
478 | ||
479 | static const char *const uart0_ext_grps[] = { "uart0_ext_grp" }; | |
480 | struct spear_function spear3xx_uart0_ext_function = { | |
481 | .name = "uart0_ext", | |
482 | .groups = uart0_ext_grps, | |
483 | .ngroups = ARRAY_SIZE(uart0_ext_grps), | |
484 | }; | |
485 | ||
486 | /* uart0_pins */ | |
487 | static const unsigned uart0_pins[] = { 2, 3 }; | |
488 | static struct spear_muxreg uart0_muxreg[] = { | |
489 | { | |
490 | .reg = -1, | |
491 | .mask = PMX_UART0_MASK, | |
492 | .val = PMX_UART0_MASK, | |
493 | }, | |
494 | }; | |
495 | ||
496 | static struct spear_modemux uart0_modemux[] = { | |
497 | { | |
498 | .modes = ~0, | |
499 | .muxregs = uart0_muxreg, | |
500 | .nmuxregs = ARRAY_SIZE(uart0_muxreg), | |
501 | }, | |
502 | }; | |
503 | ||
504 | struct spear_pingroup spear3xx_uart0_pingroup = { | |
505 | .name = "uart0_grp", | |
506 | .pins = uart0_pins, | |
507 | .npins = ARRAY_SIZE(uart0_pins), | |
508 | .modemuxs = uart0_modemux, | |
509 | .nmodemuxs = ARRAY_SIZE(uart0_modemux), | |
510 | }; | |
511 | ||
512 | static const char *const uart0_grps[] = { "uart0_grp" }; | |
513 | struct spear_function spear3xx_uart0_function = { | |
514 | .name = "uart0", | |
515 | .groups = uart0_grps, | |
516 | .ngroups = ARRAY_SIZE(uart0_grps), | |
517 | }; | |
518 | ||
519 | /* timer_0_1_pins */ | |
520 | static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 }; | |
521 | static struct spear_muxreg timer_0_1_muxreg[] = { | |
522 | { | |
523 | .reg = -1, | |
524 | .mask = PMX_TIMER_0_1_MASK, | |
525 | .val = PMX_TIMER_0_1_MASK, | |
526 | }, | |
527 | }; | |
528 | ||
529 | static struct spear_modemux timer_0_1_modemux[] = { | |
530 | { | |
531 | .modes = ~0, | |
532 | .muxregs = timer_0_1_muxreg, | |
533 | .nmuxregs = ARRAY_SIZE(timer_0_1_muxreg), | |
534 | }, | |
535 | }; | |
536 | ||
537 | struct spear_pingroup spear3xx_timer_0_1_pingroup = { | |
538 | .name = "timer_0_1_grp", | |
539 | .pins = timer_0_1_pins, | |
540 | .npins = ARRAY_SIZE(timer_0_1_pins), | |
541 | .modemuxs = timer_0_1_modemux, | |
542 | .nmodemuxs = ARRAY_SIZE(timer_0_1_modemux), | |
543 | }; | |
544 | ||
545 | static const char *const timer_0_1_grps[] = { "timer_0_1_grp" }; | |
546 | struct spear_function spear3xx_timer_0_1_function = { | |
547 | .name = "timer_0_1", | |
548 | .groups = timer_0_1_grps, | |
549 | .ngroups = ARRAY_SIZE(timer_0_1_grps), | |
550 | }; | |
551 | ||
552 | /* timer_2_3_pins */ | |
553 | static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 }; | |
554 | static struct spear_muxreg timer_2_3_muxreg[] = { | |
555 | { | |
556 | .reg = -1, | |
557 | .mask = PMX_TIMER_2_3_MASK, | |
558 | .val = PMX_TIMER_2_3_MASK, | |
559 | }, | |
560 | }; | |
561 | ||
562 | static struct spear_modemux timer_2_3_modemux[] = { | |
563 | { | |
564 | .modes = ~0, | |
565 | .muxregs = timer_2_3_muxreg, | |
566 | .nmuxregs = ARRAY_SIZE(timer_2_3_muxreg), | |
567 | }, | |
568 | }; | |
569 | ||
570 | struct spear_pingroup spear3xx_timer_2_3_pingroup = { | |
571 | .name = "timer_2_3_grp", | |
572 | .pins = timer_2_3_pins, | |
573 | .npins = ARRAY_SIZE(timer_2_3_pins), | |
574 | .modemuxs = timer_2_3_modemux, | |
575 | .nmodemuxs = ARRAY_SIZE(timer_2_3_modemux), | |
576 | }; | |
577 | ||
578 | static const char *const timer_2_3_grps[] = { "timer_2_3_grp" }; | |
579 | struct spear_function spear3xx_timer_2_3_function = { | |
580 | .name = "timer_2_3", | |
581 | .groups = timer_2_3_grps, | |
582 | .ngroups = ARRAY_SIZE(timer_2_3_grps), | |
583 | }; | |
584 | ||
585 | struct spear_pinctrl_machdata spear3xx_machdata = { | |
586 | .pins = spear3xx_pins, | |
587 | .npins = ARRAY_SIZE(spear3xx_pins), | |
588 | }; |