[deliverable/linux.git] / drivers / pinctrl / sunxi / pinctrl-sun6i-a31-r.c

/*
 * Allwinner A31 SoCs special pins pinctrl driver.
 *
 * Copyright (C) 2014 Boris Brezillon
 * Boris Brezillon <boris.brezillon@free-electrons.com>
 *
 * Copyright (C) 2014 Maxime Ripard
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/reset.h>

#include "pinctrl-sunxi.h"

static const struct sunxi_desc_pin sun6i_a31_r_pins[] = {
	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
		  SUNXI_FUNCTION(0x0, "gpio_in"),
		  SUNXI_FUNCTION(0x1, "gpio_out"),
		  SUNXI_FUNCTION(0x2, "s_twi"),		/* SCK */
		  SUNXI_FUNCTION(0x3, "s_p2wi")),	/* SCK */
	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
		  SUNXI_FUNCTION(0x0, "gpio_in"),
		  SUNXI_FUNCTION(0x1, "gpio_out"),
		  SUNXI_FUNCTION(0x2, "s_twi"),		/* SDA */
		  SUNXI_FUNCTION(0x3, "s_p2wi")),	/* SDA */
	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
		  SUNXI_FUNCTION(0x0, "gpio_in"),
		  SUNXI_FUNCTION(0x1, "gpio_out"),
		  SUNXI_FUNCTION(0x2, "s_uart")),	/* TX */
	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
		  SUNXI_FUNCTION(0x0, "gpio_in"),
		  SUNXI_FUNCTION(0x1, "gpio_out"),
		  SUNXI_FUNCTION(0x2, "s_uart")),	/* RX */
	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
		  SUNXI_FUNCTION(0x0, "gpio_in"),
		  SUNXI_FUNCTION(0x1, "gpio_out"),
		  SUNXI_FUNCTION(0x2, "s_ir")),		/* RX */
	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
		  SUNXI_FUNCTION(0x0, "gpio_in"),
		  SUNXI_FUNCTION(0x1, "gpio_out"),
		  SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 0),	/* PL_EINT0 */
		  SUNXI_FUNCTION(0x3, "s_jtag")),	/* MS */
	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
		  SUNXI_FUNCTION(0x0, "gpio_in"),
		  SUNXI_FUNCTION(0x1, "gpio_out"),
		  SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 1),	/* PL_EINT1 */
		  SUNXI_FUNCTION(0x3, "s_jtag")),	/* CK */
	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
		  SUNXI_FUNCTION(0x0, "gpio_in"),
		  SUNXI_FUNCTION(0x1, "gpio_out"),
		  SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 2),	/* PL_EINT2 */
		  SUNXI_FUNCTION(0x3, "s_jtag")),	/* DO */
	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
		  SUNXI_FUNCTION(0x0, "gpio_in"),
		  SUNXI_FUNCTION(0x1, "gpio_out"),
		  SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 3),	/* PL_EINT3 */
		  SUNXI_FUNCTION(0x3, "s_jtag")),	/* DI */
	/* Hole */
	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
		  SUNXI_FUNCTION(0x0, "gpio_in"),
		  SUNXI_FUNCTION(0x1, "gpio_out"),
		  SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 0)),	/* PM_EINT0 */
	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
		  SUNXI_FUNCTION(0x0, "gpio_in"),
		  SUNXI_FUNCTION(0x1, "gpio_out"),
		  SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 1)),	/* PM_EINT1 */
	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
		  SUNXI_FUNCTION(0x0, "gpio_in"),
		  SUNXI_FUNCTION(0x1, "gpio_out"),
		  SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 2),	/* PM_EINT2 */
		  SUNXI_FUNCTION(0x3, "1wire")),
	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
		  SUNXI_FUNCTION(0x0, "gpio_in"),
		  SUNXI_FUNCTION(0x1, "gpio_out"),
		  SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 3)),	/* PM_EINT3 */
	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
		  SUNXI_FUNCTION(0x0, "gpio_in"),
		  SUNXI_FUNCTION(0x1, "gpio_out"),
		  SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 4)),	/* PM_EINT4 */
	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 5),
		  SUNXI_FUNCTION(0x0, "gpio_in"),
		  SUNXI_FUNCTION(0x1, "gpio_out"),
		  SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 5)),	/* PM_EINT5 */
	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 6),
		  SUNXI_FUNCTION(0x0, "gpio_in"),
		  SUNXI_FUNCTION(0x1, "gpio_out"),
		  SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 6)),	/* PM_EINT6 */
	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 7),
		  SUNXI_FUNCTION(0x0, "gpio_in"),
		  SUNXI_FUNCTION(0x1, "gpio_out"),
		  SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 7),	/* PM_EINT7 */
		  SUNXI_FUNCTION(0x3, "rtc")),		/* CLKO */
};

static const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_data = {
	.pins = sun6i_a31_r_pins,
	.npins = ARRAY_SIZE(sun6i_a31_r_pins),
	.pin_base = PL_BASE,
	.irq_banks = 2,
};

static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev)
{
	struct reset_control *rstc;
	int ret;

	rstc = devm_reset_control_get(&pdev->dev, NULL);
	if (IS_ERR(rstc)) {
		dev_err(&pdev->dev, "Reset controller missing\n");
		return PTR_ERR(rstc);
	}

	ret = reset_control_deassert(rstc);
	if (ret)
		return ret;

	ret = sunxi_pinctrl_init(pdev,
				 &sun6i_a31_r_pinctrl_data);

	if (ret)
		reset_control_assert(rstc);

	return ret;
}

static const struct of_device_id sun6i_a31_r_pinctrl_match[] = {
	{ .compatible = "allwinner,sun6i-a31-r-pinctrl", },
	{}
};
MODULE_DEVICE_TABLE(of, sun6i_a31_r_pinctrl_match);

static struct platform_driver sun6i_a31_r_pinctrl_driver = {
	.probe	= sun6i_a31_r_pinctrl_probe,
	.driver	= {
		.name		= "sun6i-a31-r-pinctrl",
		.of_match_table	= sun6i_a31_r_pinctrl_match,
	},
};
module_platform_driver(sun6i_a31_r_pinctrl_driver);

MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com");
MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
MODULE_DESCRIPTION("Allwinner A31 R_PIO pinctrl driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
16c675f9 MR	1	/*
	2	* Allwinner A31 SoCs special pins pinctrl driver.
	3	*
	4	* Copyright (C) 2014 Boris Brezillon
	5	* Boris Brezillon <boris.brezillon@free-electrons.com>
	6	*
	7	* Copyright (C) 2014 Maxime Ripard
	8	* Maxime Ripard <maxime.ripard@free-electrons.com>
	9	*
	10	* This file is licensed under the terms of the GNU General Public
	11	* License version 2. This program is licensed "as is" without any
	12	* warranty of any kind, whether express or implied.
	13	*/
	14
	15	#include <linux/module.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/of.h>
	18	#include <linux/of_device.h>
	19	#include <linux/pinctrl/pinctrl.h>
dc969106	20	#include <linux/reset.h>
16c675f9 MR	21
	22	#include "pinctrl-sunxi.h"
	23
	24	static const struct sunxi_desc_pin sun6i_a31_r_pins[] = {
	25	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
	26	SUNXI_FUNCTION(0x0, "gpio_in"),
	27	SUNXI_FUNCTION(0x1, "gpio_out"),
	28	SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */
	29	SUNXI_FUNCTION(0x3, "s_p2wi")), /* SCK */
	30	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
	31	SUNXI_FUNCTION(0x0, "gpio_in"),
	32	SUNXI_FUNCTION(0x1, "gpio_out"),
	33	SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */
	34	SUNXI_FUNCTION(0x3, "s_p2wi")), /* SDA */
	35	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
	36	SUNXI_FUNCTION(0x0, "gpio_in"),
	37	SUNXI_FUNCTION(0x1, "gpio_out"),
	38	SUNXI_FUNCTION(0x2, "s_uart")), /* TX */
	39	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
	40	SUNXI_FUNCTION(0x0, "gpio_in"),
	41	SUNXI_FUNCTION(0x1, "gpio_out"),
	42	SUNXI_FUNCTION(0x2, "s_uart")), /* RX */
	43	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
	44	SUNXI_FUNCTION(0x0, "gpio_in"),
	45	SUNXI_FUNCTION(0x1, "gpio_out"),
	46	SUNXI_FUNCTION(0x2, "s_ir")), /* RX */
	47	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
	48	SUNXI_FUNCTION(0x0, "gpio_in"),
	49	SUNXI_FUNCTION(0x1, "gpio_out"),
3f84ccf6	50	SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 0), /* PL_EINT0 */
16c675f9 MR	51	SUNXI_FUNCTION(0x3, "s_jtag")), /* MS */
	52	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
	53	SUNXI_FUNCTION(0x0, "gpio_in"),
	54	SUNXI_FUNCTION(0x1, "gpio_out"),
3f84ccf6	55	SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 1), /* PL_EINT1 */
16c675f9 MR	56	SUNXI_FUNCTION(0x3, "s_jtag")), /* CK */
	57	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
	58	SUNXI_FUNCTION(0x0, "gpio_in"),
	59	SUNXI_FUNCTION(0x1, "gpio_out"),
3f84ccf6	60	SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 2), /* PL_EINT2 */
16c675f9 MR	61	SUNXI_FUNCTION(0x3, "s_jtag")), /* DO */
	62	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
	63	SUNXI_FUNCTION(0x0, "gpio_in"),
	64	SUNXI_FUNCTION(0x1, "gpio_out"),
3f84ccf6	65	SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 3), /* PL_EINT3 */
16c675f9 MR	66	SUNXI_FUNCTION(0x3, "s_jtag")), /* DI */
	67	/* Hole */
	68	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
	69	SUNXI_FUNCTION(0x0, "gpio_in"),
3f84ccf6 HG	70	SUNXI_FUNCTION(0x1, "gpio_out"),
3f84ccf6 HG	71	SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 0)), /* PM_EINT0 */
16c675f9 MR	72	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
16c675f9 MR	73	SUNXI_FUNCTION(0x0, "gpio_in"),
3f84ccf6 HG	74	SUNXI_FUNCTION(0x1, "gpio_out"),
3f84ccf6 HG	75	SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 1)), /* PM_EINT1 */
16c675f9 MR	76	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
	77	SUNXI_FUNCTION(0x0, "gpio_in"),
	78	SUNXI_FUNCTION(0x1, "gpio_out"),
3f84ccf6	79	SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 2), /* PM_EINT2 */
16c675f9 MR	80	SUNXI_FUNCTION(0x3, "1wire")),
	81	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
	82	SUNXI_FUNCTION(0x0, "gpio_in"),
3f84ccf6 HG	83	SUNXI_FUNCTION(0x1, "gpio_out"),
3f84ccf6 HG	84	SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 3)), /* PM_EINT3 */
16c675f9 MR	85	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
16c675f9 MR	86	SUNXI_FUNCTION(0x0, "gpio_in"),
3f84ccf6 HG	87	SUNXI_FUNCTION(0x1, "gpio_out"),
3f84ccf6 HG	88	SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 4)), /* PM_EINT4 */
16c675f9 MR	89	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 5),
16c675f9 MR	90	SUNXI_FUNCTION(0x0, "gpio_in"),
3f84ccf6 HG	91	SUNXI_FUNCTION(0x1, "gpio_out"),
3f84ccf6 HG	92	SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 5)), /* PM_EINT5 */
16c675f9 MR	93	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 6),
16c675f9 MR	94	SUNXI_FUNCTION(0x0, "gpio_in"),
3f84ccf6 HG	95	SUNXI_FUNCTION(0x1, "gpio_out"),
3f84ccf6 HG	96	SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 6)), /* PM_EINT6 */
16c675f9 MR	97	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 7),
	98	SUNXI_FUNCTION(0x0, "gpio_in"),
	99	SUNXI_FUNCTION(0x1, "gpio_out"),
3f84ccf6	100	SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 7), /* PM_EINT7 */
16c675f9 MR	101	SUNXI_FUNCTION(0x3, "rtc")), /* CLKO */
	102	};
	103
	104	static const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_data = {
	105	.pins = sun6i_a31_r_pins,
	106	.npins = ARRAY_SIZE(sun6i_a31_r_pins),
	107	.pin_base = PL_BASE,
8966ada2	108	.irq_banks = 2,
16c675f9 MR	109	};
	110
	111	static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev)
	112	{
dc969106 MR	113	struct reset_control *rstc;
	114	int ret;
	115
	116	rstc = devm_reset_control_get(&pdev->dev, NULL);
	117	if (IS_ERR(rstc)) {
	118	dev_err(&pdev->dev, "Reset controller missing\n");
	119	return PTR_ERR(rstc);
	120	}
	121
	122	ret = reset_control_deassert(rstc);
	123	if (ret)
	124	return ret;
	125
	126	ret = sunxi_pinctrl_init(pdev,
	127	&sun6i_a31_r_pinctrl_data);
	128
	129	if (ret)
	130	reset_control_assert(rstc);
	131
	132	return ret;
16c675f9 MR	133	}
16c675f9 MR	134
baa9946e	135	static const struct of_device_id sun6i_a31_r_pinctrl_match[] = {
16c675f9 MR	136	{ .compatible = "allwinner,sun6i-a31-r-pinctrl", },
	137	{}
	138	};
	139	MODULE_DEVICE_TABLE(of, sun6i_a31_r_pinctrl_match);
	140
	141	static struct platform_driver sun6i_a31_r_pinctrl_driver = {
	142	.probe = sun6i_a31_r_pinctrl_probe,
	143	.driver = {
	144	.name = "sun6i-a31-r-pinctrl",
16c675f9 MR	145	.of_match_table = sun6i_a31_r_pinctrl_match,
	146	},
	147	};
	148	module_platform_driver(sun6i_a31_r_pinctrl_driver);
	149
	150	MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com");
	151	MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
	152	MODULE_DESCRIPTION("Allwinner A31 R_PIO pinctrl driver");
	153	MODULE_LICENSE("GPL");