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Merge tag 'pinctrl-v3.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
[deliverable/linux.git] / drivers / pinctrl / sunxi / pinctrl-sunxi.c
CommitLineData
0e37f88d
MR		 1/*
2 * Allwinner A1X SoCs pinctrl driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/io.h>
950707c0 14#include <linux/clk.h>
08e9e614 15#include <linux/gpio.h>
60242db1 16#include <linux/irqdomain.h>
905a5117 17#include <linux/irqchip/chained_irq.h>
0e37f88d
MR		 18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/of_device.h>
60242db1 22#include <linux/of_irq.h>
0e37f88d
MR		 23#include <linux/pinctrl/consumer.h>
24#include <linux/pinctrl/machine.h>
25#include <linux/pinctrl/pinctrl.h>
26#include <linux/pinctrl/pinconf-generic.h>
27#include <linux/pinctrl/pinmux.h>
28#include <linux/platform_device.h>
29#include <linux/slab.h>
30
5f910777 31#include "../core.h"
0e37f88d 32#include "pinctrl-sunxi.h"
eaa3d848 33
f4c51c10
HG		 34static struct irq_chip sunxi_pinctrl_edge_irq_chip;
35static struct irq_chip sunxi_pinctrl_level_irq_chip;
36
0e37f88d
MR		 37static struct sunxi_pinctrl_group *
38sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
39{
40 int i;
41
42 for (i = 0; i < pctl->ngroups; i++) {
43 struct sunxi_pinctrl_group *grp = pctl->groups + i;
44
45 if (!strcmp(grp->name, group))
46 return grp;
47 }
48
49 return NULL;
50}
51
52static struct sunxi_pinctrl_function *
53sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
54 const char *name)
55{
56 struct sunxi_pinctrl_function *func = pctl->functions;
57 int i;
58
59 for (i = 0; i < pctl->nfunctions; i++) {
60 if (!func[i].name)
61 break;
62
63 if (!strcmp(func[i].name, name))
64 return func + i;
65 }
66
67 return NULL;
68}
69
70static struct sunxi_desc_function *
71sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
72 const char *pin_name,
73 const char *func_name)
74{
75 int i;
76
77 for (i = 0; i < pctl->desc->npins; i++) {
78 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
79
80 if (!strcmp(pin->pin.name, pin_name)) {
81 struct sunxi_desc_function *func = pin->functions;
82
83 while (func->name) {
84 if (!strcmp(func->name, func_name))
85 return func;
86
87 func++;
88 }
89 }
90 }
91
92 return NULL;
93}
94
814d4f2e
MR		 95static struct sunxi_desc_function *
96sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
97 const u16 pin_num,
98 const char *func_name)
99{
100 int i;
101
102 for (i = 0; i < pctl->desc->npins; i++) {
103 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
104
105 if (pin->pin.number == pin_num) {
106 struct sunxi_desc_function *func = pin->functions;
107
108 while (func->name) {
109 if (!strcmp(func->name, func_name))
110 return func;
111
112 func++;
113 }
114 }
115 }
116
117 return NULL;
118}
119
0e37f88d
MR		 120static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
121{
122 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
123
124 return pctl->ngroups;
125}
126
127static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
128 unsigned group)
129{
130 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
131
132 return pctl->groups[group].name;
133}
134
135static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
136 unsigned group,
137 const unsigned **pins,
138 unsigned *num_pins)
139{
140 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
141
142 *pins = (unsigned *)&pctl->groups[group].pin;
143 *num_pins = 1;
144
145 return 0;
146}
147
148static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
149 struct device_node *node,
150 struct pinctrl_map **map,
151 unsigned *num_maps)
152{
153 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
154 unsigned long *pinconfig;
155 struct property *prop;
156 const char *function;
157 const char *group;
158 int ret, nmaps, i = 0;
159 u32 val;
160
161 *map = NULL;
162 *num_maps = 0;
163
164 ret = of_property_read_string(node, "allwinner,function", &function);
165 if (ret) {
166 dev_err(pctl->dev,
167 "missing allwinner,function property in node %s\n",
168 node->name);
169 return -EINVAL;
170 }
171
172 nmaps = of_property_count_strings(node, "allwinner,pins") * 2;
173 if (nmaps < 0) {
174 dev_err(pctl->dev,
175 "missing allwinner,pins property in node %s\n",
176 node->name);
177 return -EINVAL;
178 }
179
180 *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
3efa921d 181 if (!*map)
0e37f88d
MR		 182 return -ENOMEM;
183
184 of_property_for_each_string(node, "allwinner,pins", prop, group) {
185 struct sunxi_pinctrl_group *grp =
186 sunxi_pinctrl_find_group_by_name(pctl, group);
187 int j = 0, configlen = 0;
188
189 if (!grp) {
190 dev_err(pctl->dev, "unknown pin %s", group);
191 continue;
192 }
193
194 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
195 grp->name,
196 function)) {
197 dev_err(pctl->dev, "unsupported function %s on pin %s",
198 function, group);
199 continue;
200 }
201
202 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
203 (*map)[i].data.mux.group = group;
204 (*map)[i].data.mux.function = function;
205
206 i++;
207
208 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
209 (*map)[i].data.configs.group_or_pin = group;
210
211 if (of_find_property(node, "allwinner,drive", NULL))
212 configlen++;
213 if (of_find_property(node, "allwinner,pull", NULL))
214 configlen++;
215
216 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
bd07894e
SK		 217 if (!pinconfig) {
218 kfree(*map);
219 return -ENOMEM;
220 }
0e37f88d
MR		 221
222 if (!of_property_read_u32(node, "allwinner,drive", &val)) {
223 u16 strength = (val + 1) * 10;
224 pinconfig[j++] =
225 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
226 strength);
227 }
228
229 if (!of_property_read_u32(node, "allwinner,pull", &val)) {
230 enum pin_config_param pull = PIN_CONFIG_END;
231 if (val == 1)
232 pull = PIN_CONFIG_BIAS_PULL_UP;
233 else if (val == 2)
234 pull = PIN_CONFIG_BIAS_PULL_DOWN;
235 pinconfig[j++] = pinconf_to_config_packed(pull, 0);
236 }
237
238 (*map)[i].data.configs.configs = pinconfig;
239 (*map)[i].data.configs.num_configs = configlen;
240
241 i++;
242 }
243
244 *num_maps = nmaps;
245
246 return 0;
247}
248
249static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
250 struct pinctrl_map *map,
251 unsigned num_maps)
252{
253 int i;
254
255 for (i = 0; i < num_maps; i++) {
256 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
257 kfree(map[i].data.configs.configs);
258 }
259
260 kfree(map);
261}
262
022ab148 263static const struct pinctrl_ops sunxi_pctrl_ops = {
0e37f88d
MR		 264 .dt_node_to_map = sunxi_pctrl_dt_node_to_map,
265 .dt_free_map = sunxi_pctrl_dt_free_map,
266 .get_groups_count = sunxi_pctrl_get_groups_count,
267 .get_group_name = sunxi_pctrl_get_group_name,
268 .get_group_pins = sunxi_pctrl_get_group_pins,
269};
270
271static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
272 unsigned group,
273 unsigned long *config)
274{
275 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
276
277 *config = pctl->groups[group].config;
278
279 return 0;
280}
281
282static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
283 unsigned group,
03b054e9
SY		 284 unsigned long *configs,
285 unsigned num_configs)
0e37f88d
MR		 286{
287 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
288 struct sunxi_pinctrl_group *g = &pctl->groups[group];
1bee963d 289 unsigned long flags;
b4575c69 290 unsigned pin = g->pin - pctl->desc->pin_base;
0e37f88d
MR		 291 u32 val, mask;
292 u16 strength;
293 u8 dlevel;
03b054e9 294 int i;
0e37f88d 295
6ad30ce0 296 spin_lock_irqsave(&pctl->lock, flags);
1bee963d 297
03b054e9
SY		 298 for (i = 0; i < num_configs; i++) {
299 switch (pinconf_to_config_param(configs[i])) {
300 case PIN_CONFIG_DRIVE_STRENGTH:
301 strength = pinconf_to_config_argument(configs[i]);
07b7eb92
LW		 302 if (strength > 40) {
303 spin_unlock_irqrestore(&pctl->lock, flags);
03b054e9 304 return -EINVAL;
07b7eb92 305 }
03b054e9
SY		 306 /*
307 * We convert from mA to what the register expects:
308 * 0: 10mA
309 * 1: 20mA
310 * 2: 30mA
311 * 3: 40mA
312 */
313 dlevel = strength / 10 - 1;
b4575c69
CYT		 314 val = readl(pctl->membase + sunxi_dlevel_reg(pin));
315 mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin);
03b054e9 316 writel((val & ~mask)
b4575c69
CYT		 317 | dlevel << sunxi_dlevel_offset(pin),
318 pctl->membase + sunxi_dlevel_reg(pin));
03b054e9
SY		 319 break;
320 case PIN_CONFIG_BIAS_PULL_UP:
b4575c69
CYT		 321 val = readl(pctl->membase + sunxi_pull_reg(pin));
322 mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
323 writel((val & ~mask) | 1 << sunxi_pull_offset(pin),
324 pctl->membase + sunxi_pull_reg(pin));
03b054e9
SY		 325 break;
326 case PIN_CONFIG_BIAS_PULL_DOWN:
b4575c69
CYT		 327 val = readl(pctl->membase + sunxi_pull_reg(pin));
328 mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
329 writel((val & ~mask) | 2 << sunxi_pull_offset(pin),
330 pctl->membase + sunxi_pull_reg(pin));
03b054e9
SY		 331 break;
332 default:
333 break;
334 }
03b054e9
SY		 335 /* cache the config value */
336 g->config = configs[i];
337 } /* for each config */
0e37f88d 338
6ad30ce0 339 spin_unlock_irqrestore(&pctl->lock, flags);
0e37f88d
MR		 340
341 return 0;
342}
343
022ab148 344static const struct pinconf_ops sunxi_pconf_ops = {
0e37f88d
MR		 345 .pin_config_group_get = sunxi_pconf_group_get,
346 .pin_config_group_set = sunxi_pconf_group_set,
347};
348
349static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
350{
351 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
352
353 return pctl->nfunctions;
354}
355
356static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
357 unsigned function)
358{
359 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
360
361 return pctl->functions[function].name;
362}
363
364static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
365 unsigned function,
366 const char * const **groups,
367 unsigned * const num_groups)
368{
369 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
370
371 *groups = pctl->functions[function].groups;
372 *num_groups = pctl->functions[function].ngroups;
373
374 return 0;
375}
376
377static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
378 unsigned pin,
379 u8 config)
380{
381 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1bee963d
MR		 382 unsigned long flags;
383 u32 val, mask;
384
385 spin_lock_irqsave(&pctl->lock, flags);
0e37f88d 386
b4575c69 387 pin -= pctl->desc->pin_base;
1bee963d
MR		 388 val = readl(pctl->membase + sunxi_mux_reg(pin));
389 mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
0e37f88d
MR		 390 writel((val & ~mask) | config << sunxi_mux_offset(pin),
391 pctl->membase + sunxi_mux_reg(pin));
1bee963d
MR		 392
393 spin_unlock_irqrestore(&pctl->lock, flags);
0e37f88d
MR		 394}
395
396static int sunxi_pmx_enable(struct pinctrl_dev *pctldev,
397 unsigned function,
398 unsigned group)
399{
400 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
401 struct sunxi_pinctrl_group *g = pctl->groups + group;
402 struct sunxi_pinctrl_function *func = pctl->functions + function;
403 struct sunxi_desc_function *desc =
404 sunxi_pinctrl_desc_find_function_by_name(pctl,
405 g->name,
406 func->name);
407
408 if (!desc)
409 return -EINVAL;
410
411 sunxi_pmx_set(pctldev, g->pin, desc->muxval);
412
413 return 0;
414}
415
08e9e614
MR		 416static int
417sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
418 struct pinctrl_gpio_range *range,
419 unsigned offset,
420 bool input)
421{
422 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
423 struct sunxi_desc_function *desc;
08e9e614 424 const char *func;
08e9e614
MR		 425
426 if (input)
427 func = "gpio_in";
428 else
429 func = "gpio_out";
430
814d4f2e
MR		 431 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
432 if (!desc)
433 return -EINVAL;
08e9e614
MR		 434
435 sunxi_pmx_set(pctldev, offset, desc->muxval);
436
814d4f2e 437 return 0;
08e9e614
MR		 438}
439
022ab148 440static const struct pinmux_ops sunxi_pmx_ops = {
0e37f88d
MR		 441 .get_functions_count = sunxi_pmx_get_funcs_cnt,
442 .get_function_name = sunxi_pmx_get_func_name,
443 .get_function_groups = sunxi_pmx_get_func_groups,
444 .enable = sunxi_pmx_enable,
08e9e614 445 .gpio_set_direction = sunxi_pmx_gpio_set_direction,
0e37f88d
MR		 446};
447
08e9e614
MR		 448static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset)
449{
450 return pinctrl_request_gpio(chip->base + offset);
451}
452
453static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset)
454{
455 pinctrl_free_gpio(chip->base + offset);
456}
457
458static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
459 unsigned offset)
460{
461 return pinctrl_gpio_direction_input(chip->base + offset);
462}
463
464static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
465{
466 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
467
468 u32 reg = sunxi_data_reg(offset);
469 u8 index = sunxi_data_offset(offset);
470 u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
471
472 return val;
473}
474
08e9e614
MR		 475static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
476 unsigned offset, int value)
477{
478 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
479 u32 reg = sunxi_data_reg(offset);
480 u8 index = sunxi_data_offset(offset);
1bee963d
MR		 481 unsigned long flags;
482 u32 regval;
483
484 spin_lock_irqsave(&pctl->lock, flags);
485
486 regval = readl(pctl->membase + reg);
08e9e614 487
df7b34f4
MR		 488 if (value)
489 regval |= BIT(index);
490 else
491 regval &= ~(BIT(index));
08e9e614 492
df7b34f4 493 writel(regval, pctl->membase + reg);
1bee963d
MR		 494
495 spin_unlock_irqrestore(&pctl->lock, flags);
08e9e614
MR		 496}
497
fa8cf57c
CYT		 498static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
499 unsigned offset, int value)
500{
501 sunxi_pinctrl_gpio_set(chip, offset, value);
502 return pinctrl_gpio_direction_output(chip->base + offset);
503}
504
a0d72094
MR		 505static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
506 const struct of_phandle_args *gpiospec,
507 u32 *flags)
508{
509 int pin, base;
510
511 base = PINS_PER_BANK * gpiospec->args[0];
512 pin = base + gpiospec->args[1];
513
343f1327 514 if (pin > gc->ngpio)
a0d72094
MR		 515 return -EINVAL;
516
517 if (flags)
518 *flags = gpiospec->args[2];
519
520 return pin;
521}
522
60242db1
MR		 523static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
524{
525 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
526 struct sunxi_desc_function *desc;
343f1327 527 unsigned pinnum = pctl->desc->pin_base + offset;
0d3bafac 528 unsigned irqnum;
60242db1 529
c9e3b2d8 530 if (offset >= chip->ngpio)
60242db1
MR		 531 return -ENXIO;
532
343f1327 533 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
60242db1
MR		 534 if (!desc)
535 return -EINVAL;
536
0d3bafac
CYT		 537 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
538
60242db1 539 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
0d3bafac 540 chip->label, offset + chip->base, irqnum);
60242db1 541
0d3bafac 542 return irq_find_mapping(pctl->domain, irqnum);
60242db1
MR		 543}
544
fea6d8ef
HG		 545static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
546{
547 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
548 struct sunxi_desc_function *func;
f83549d6 549 int ret;
fea6d8ef
HG		 550
551 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
552 pctl->irq_array[d->hwirq], "irq");
553 if (!func)
554 return -EINVAL;
555
343f1327
CYT		 556 ret = gpio_lock_as_irq(pctl->chip,
557 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
f83549d6
CYT		 558 if (ret) {
559 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
560 irqd_to_hwirq(d));
561 return ret;
562 }
563
fea6d8ef
HG		 564 /* Change muxing to INT mode */
565 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
08e9e614 566
fea6d8ef
HG		 567 return 0;
568}
08e9e614 569
f83549d6
CYT		 570static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
571{
572 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
573
343f1327
CYT		 574 gpio_unlock_as_irq(pctl->chip,
575 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
f83549d6
CYT		 576}
577
f4c51c10 578static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
60242db1
MR		 579{
580 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
f4c51c10 581 struct irq_desc *desc = container_of(d, struct irq_desc, irq_data);
60242db1
MR		 582 u32 reg = sunxi_irq_cfg_reg(d->hwirq);
583 u8 index = sunxi_irq_cfg_offset(d->hwirq);
1bee963d 584 unsigned long flags;
2aaaddff 585 u32 regval;
60242db1
MR		 586 u8 mode;
587
588 switch (type) {
589 case IRQ_TYPE_EDGE_RISING:
590 mode = IRQ_EDGE_RISING;
591 break;
592 case IRQ_TYPE_EDGE_FALLING:
593 mode = IRQ_EDGE_FALLING;
594 break;
595 case IRQ_TYPE_EDGE_BOTH:
596 mode = IRQ_EDGE_BOTH;
597 break;
598 case IRQ_TYPE_LEVEL_HIGH:
599 mode = IRQ_LEVEL_HIGH;
600 break;
601 case IRQ_TYPE_LEVEL_LOW:
602 mode = IRQ_LEVEL_LOW;
603 break;
604 default:
605 return -EINVAL;
606 }
607
f4c51c10
HG		 608 if (type & IRQ_TYPE_LEVEL_MASK) {
609 d->chip = &sunxi_pinctrl_level_irq_chip;
610 desc->handle_irq = handle_fasteoi_irq;
611 } else {
612 d->chip = &sunxi_pinctrl_edge_irq_chip;
613 desc->handle_irq = handle_edge_irq;
614 }
615
1bee963d
MR		 616 spin_lock_irqsave(&pctl->lock, flags);
617
2aaaddff 618 regval = readl(pctl->membase + reg);
d82f9401 619 regval &= ~(IRQ_CFG_IRQ_MASK << index);
2aaaddff 620 writel(regval | (mode << index), pctl->membase + reg);
60242db1 621
1bee963d 622 spin_unlock_irqrestore(&pctl->lock, flags);
60242db1
MR		 623
624 return 0;
625}
626
645ec714 627static void sunxi_pinctrl_irq_ack(struct irq_data *d)
60242db1
MR		 628{
629 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
60242db1
MR		 630 u32 status_reg = sunxi_irq_status_reg(d->hwirq);
631 u8 status_idx = sunxi_irq_status_offset(d->hwirq);
60242db1
MR		 632
633 /* Clear the IRQ */
634 writel(1 << status_idx, pctl->membase + status_reg);
635}
636
637static void sunxi_pinctrl_irq_mask(struct irq_data *d)
638{
639 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
640 u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
641 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
1bee963d 642 unsigned long flags;
60242db1
MR		 643 u32 val;
644
1bee963d
MR		 645 spin_lock_irqsave(&pctl->lock, flags);
646
60242db1
MR		 647 /* Mask the IRQ */
648 val = readl(pctl->membase + reg);
649 writel(val & ~(1 << idx), pctl->membase + reg);
1bee963d
MR		 650
651 spin_unlock_irqrestore(&pctl->lock, flags);
60242db1
MR		 652}
653
654static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
655{
656 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
60242db1
MR		 657 u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
658 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
1bee963d 659 unsigned long flags;
60242db1
MR		 660 u32 val;
661
1bee963d
MR		 662 spin_lock_irqsave(&pctl->lock, flags);
663
60242db1
MR		 664 /* Unmask the IRQ */
665 val = readl(pctl->membase + reg);
666 writel(val | (1 << idx), pctl->membase + reg);
1bee963d
MR		 667
668 spin_unlock_irqrestore(&pctl->lock, flags);
60242db1
MR		 669}
670
d61e23e5
HG		 671static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
672{
673 sunxi_pinctrl_irq_ack(d);
674 sunxi_pinctrl_irq_unmask(d);
675}
676
f4c51c10 677static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
645ec714 678 .irq_ack = sunxi_pinctrl_irq_ack,
60242db1 679 .irq_mask = sunxi_pinctrl_irq_mask,
60242db1 680 .irq_unmask = sunxi_pinctrl_irq_unmask,
fea6d8ef 681 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
f83549d6 682 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
60242db1 683 .irq_set_type = sunxi_pinctrl_irq_set_type,
578c0a87 684 .flags = IRQCHIP_SKIP_SET_WAKE,
60242db1
MR		 685};
686
f4c51c10
HG		 687static struct irq_chip sunxi_pinctrl_level_irq_chip = {
688 .irq_eoi = sunxi_pinctrl_irq_ack,
60242db1 689 .irq_mask = sunxi_pinctrl_irq_mask,
60242db1 690 .irq_unmask = sunxi_pinctrl_irq_unmask,
d61e23e5
HG		 691 /* Define irq_enable / disable to avoid spurious irqs for drivers
692 * using these to suppress irqs while they clear the irq source */
693 .irq_enable = sunxi_pinctrl_irq_ack_unmask,
694 .irq_disable = sunxi_pinctrl_irq_mask,
f4c51c10 695 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
f83549d6 696 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
60242db1 697 .irq_set_type = sunxi_pinctrl_irq_set_type,
f4c51c10
HG		 698 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED |
699 IRQCHIP_EOI_IF_HANDLED,
60242db1
MR		 700};
701
702static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
703{
905a5117 704 struct irq_chip *chip = irq_get_chip(irq);
60242db1 705 struct sunxi_pinctrl *pctl = irq_get_handler_data(irq);
aebdc8ab
MR		 706 unsigned long bank, reg, val;
707
708 for (bank = 0; bank < pctl->desc->irq_banks; bank++)
709 if (irq == pctl->irq[bank])
710 break;
711
712 if (bank == pctl->desc->irq_banks)
713 return;
60242db1 714
aebdc8ab
MR		 715 reg = sunxi_irq_status_reg_from_bank(bank);
716 val = readl(pctl->membase + reg);
60242db1 717
aebdc8ab 718 if (val) {
60242db1
MR		 719 int irqoffset;
720
905a5117 721 chained_irq_enter(chip, desc);
aebdc8ab
MR		 722 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
723 int pin_irq = irq_find_mapping(pctl->domain,
724 bank * IRQ_PER_BANK + irqoffset);
60242db1
MR		 725 generic_handle_irq(pin_irq);
726 }
905a5117 727 chained_irq_exit(chip, desc);
60242db1
MR		 728 }
729}
730
0e37f88d
MR		 731static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
732 const char *name)
733{
734 struct sunxi_pinctrl_function *func = pctl->functions;
735
736 while (func->name) {
737 /* function already there */
738 if (strcmp(func->name, name) == 0) {
739 func->ngroups++;
740 return -EEXIST;
741 }
742 func++;
743 }
744
745 func->name = name;
746 func->ngroups = 1;
747
748 pctl->nfunctions++;
749
750 return 0;
751}
752
753static int sunxi_pinctrl_build_state(struct platform_device *pdev)
754{
755 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
756 int i;
757
758 pctl->ngroups = pctl->desc->npins;
759
760 /* Allocate groups */
761 pctl->groups = devm_kzalloc(&pdev->dev,
762 pctl->ngroups * sizeof(*pctl->groups),
763 GFP_KERNEL);
764 if (!pctl->groups)
765 return -ENOMEM;
766
767 for (i = 0; i < pctl->desc->npins; i++) {
768 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
769 struct sunxi_pinctrl_group *group = pctl->groups + i;
770
771 group->name = pin->pin.name;
772 group->pin = pin->pin.number;
773 }
774
775 /*
776 * We suppose that we won't have any more functions than pins,
777 * we'll reallocate that later anyway
778 */
779 pctl->functions = devm_kzalloc(&pdev->dev,
780 pctl->desc->npins * sizeof(*pctl->functions),
781 GFP_KERNEL);
782 if (!pctl->functions)
783 return -ENOMEM;
784
785 /* Count functions and their associated groups */
786 for (i = 0; i < pctl->desc->npins; i++) {
787 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
788 struct sunxi_desc_function *func = pin->functions;
789
790 while (func->name) {
d54e9a28 791 /* Create interrupt mapping while we're at it */
aebdc8ab
MR		 792 if (!strcmp(func->name, "irq")) {
793 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
794 pctl->irq_array[irqnum] = pin->pin.number;
795 }
796
0e37f88d
MR		 797 sunxi_pinctrl_add_function(pctl, func->name);
798 func++;
799 }
800 }
801
802 pctl->functions = krealloc(pctl->functions,
803 pctl->nfunctions * sizeof(*pctl->functions),
804 GFP_KERNEL);
805
806 for (i = 0; i < pctl->desc->npins; i++) {
807 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
808 struct sunxi_desc_function *func = pin->functions;
809
810 while (func->name) {
811 struct sunxi_pinctrl_function *func_item;
812 const char **func_grp;
813
814 func_item = sunxi_pinctrl_find_function_by_name(pctl,
815 func->name);
816 if (!func_item)
817 return -EINVAL;
818
819 if (!func_item->groups) {
820 func_item->groups =
821 devm_kzalloc(&pdev->dev,
822 func_item->ngroups * sizeof(*func_item->groups),
823 GFP_KERNEL);
824 if (!func_item->groups)
825 return -ENOMEM;
826 }
827
828 func_grp = func_item->groups;
829 while (*func_grp)
830 func_grp++;
831
832 *func_grp = pin->pin.name;
833 func++;
834 }
835 }
836
837 return 0;
838}
839
2284ba6b
MR		 840int sunxi_pinctrl_init(struct platform_device *pdev,
841 const struct sunxi_pinctrl_desc *desc)
0e37f88d
MR		 842{
843 struct device_node *node = pdev->dev.of_node;
ba6764d5 844 struct pinctrl_desc *pctrl_desc;
0e37f88d
MR		 845 struct pinctrl_pin_desc *pins;
846 struct sunxi_pinctrl *pctl;
4409cafc 847 struct resource *res;
08e9e614 848 int i, ret, last_pin;
950707c0 849 struct clk *clk;
0e37f88d
MR		 850
851 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
852 if (!pctl)
853 return -ENOMEM;
854 platform_set_drvdata(pdev, pctl);
855
1bee963d
MR		 856 spin_lock_init(&pctl->lock);
857
4409cafc
MR		 858 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
859 pctl->membase = devm_ioremap_resource(&pdev->dev, res);
860 if (IS_ERR(pctl->membase))
861 return PTR_ERR(pctl->membase);
0e37f88d 862
ba6764d5 863 pctl->dev = &pdev->dev;
2284ba6b 864 pctl->desc = desc;
0e37f88d 865
aebdc8ab
MR		 866 pctl->irq_array = devm_kcalloc(&pdev->dev,
867 IRQ_PER_BANK * pctl->desc->irq_banks,
868 sizeof(*pctl->irq_array),
869 GFP_KERNEL);
870 if (!pctl->irq_array)
871 return -ENOMEM;
872
0e37f88d
MR		 873 ret = sunxi_pinctrl_build_state(pdev);
874 if (ret) {
875 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
876 return ret;
877 }
878
879 pins = devm_kzalloc(&pdev->dev,
880 pctl->desc->npins * sizeof(*pins),
881 GFP_KERNEL);
882 if (!pins)
883 return -ENOMEM;
884
885 for (i = 0; i < pctl->desc->npins; i++)
886 pins[i] = pctl->desc->pins[i].pin;
887
ba6764d5
MR		 888 pctrl_desc = devm_kzalloc(&pdev->dev,
889 sizeof(*pctrl_desc),
890 GFP_KERNEL);
891 if (!pctrl_desc)
892 return -ENOMEM;
893
894 pctrl_desc->name = dev_name(&pdev->dev);
895 pctrl_desc->owner = THIS_MODULE;
896 pctrl_desc->pins = pins;
897 pctrl_desc->npins = pctl->desc->npins;
898 pctrl_desc->confops = &sunxi_pconf_ops;
899 pctrl_desc->pctlops = &sunxi_pctrl_ops;
900 pctrl_desc->pmxops = &sunxi_pmx_ops;
901
902 pctl->pctl_dev = pinctrl_register(pctrl_desc,
0e37f88d
MR		 903 &pdev->dev, pctl);
904 if (!pctl->pctl_dev) {
905 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
906 return -EINVAL;
907 }
908
08e9e614
MR		 909 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
910 if (!pctl->chip) {
911 ret = -ENOMEM;
912 goto pinctrl_error;
913 }
914
915 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
d83c82ce
BB		 916 pctl->chip->owner = THIS_MODULE;
917 pctl->chip->request = sunxi_pinctrl_gpio_request,
918 pctl->chip->free = sunxi_pinctrl_gpio_free,
919 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input,
920 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output,
921 pctl->chip->get = sunxi_pinctrl_gpio_get,
922 pctl->chip->set = sunxi_pinctrl_gpio_set,
923 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate,
924 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq,
925 pctl->chip->of_gpio_n_cells = 3,
926 pctl->chip->can_sleep = false,
927 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
928 pctl->desc->pin_base;
08e9e614
MR		 929 pctl->chip->label = dev_name(&pdev->dev);
930 pctl->chip->dev = &pdev->dev;
d83c82ce 931 pctl->chip->base = pctl->desc->pin_base;
08e9e614
MR		 932
933 ret = gpiochip_add(pctl->chip);
934 if (ret)
935 goto pinctrl_error;
936
937 for (i = 0; i < pctl->desc->npins; i++) {
938 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
939
940 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
343f1327 941 pin->pin.number - pctl->desc->pin_base,
08e9e614
MR		 942 pin->pin.number, 1);
943 if (ret)
944 goto gpiochip_error;
945 }
946
950707c0 947 clk = devm_clk_get(&pdev->dev, NULL);
d72f88a4
WY		 948 if (IS_ERR(clk)) {
949 ret = PTR_ERR(clk);
950707c0 950 goto gpiochip_error;
d72f88a4 951 }
950707c0 952
6415093f
BB		 953 ret = clk_prepare_enable(clk);
954 if (ret)
955 goto gpiochip_error;
950707c0 956
aebdc8ab
MR		 957 pctl->irq = devm_kcalloc(&pdev->dev,
958 pctl->desc->irq_banks,
959 sizeof(*pctl->irq),
960 GFP_KERNEL);
60242db1 961 if (!pctl->irq) {
aebdc8ab 962 ret = -ENOMEM;
dc969106 963 goto clk_error;
60242db1
MR		 964 }
965
aebdc8ab
MR		 966 for (i = 0; i < pctl->desc->irq_banks; i++) {
967 pctl->irq[i] = platform_get_irq(pdev, i);
968 if (pctl->irq[i] < 0) {
969 ret = pctl->irq[i];
970 goto clk_error;
971 }
972 }
973
974 pctl->domain = irq_domain_add_linear(node,
975 pctl->desc->irq_banks * IRQ_PER_BANK,
976 &irq_domain_simple_ops,
977 NULL);
60242db1
MR		 978 if (!pctl->domain) {
979 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
980 ret = -ENOMEM;
dc969106 981 goto clk_error;
60242db1
MR		 982 }
983
aebdc8ab 984 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
60242db1
MR		 985 int irqno = irq_create_mapping(pctl->domain, i);
986
f4c51c10
HG		 987 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
988 handle_edge_irq);
60242db1
MR		 989 irq_set_chip_data(irqno, pctl);
990 };
991
aebdc8ab 992 for (i = 0; i < pctl->desc->irq_banks; i++) {
f4c51c10
HG		 993 /* Mask and clear all IRQs before registering a handler */
994 writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i));
995 writel(0xffffffff,
996 pctl->membase + sunxi_irq_status_reg_from_bank(i));
997
aebdc8ab
MR		 998 irq_set_chained_handler(pctl->irq[i],
999 sunxi_pinctrl_irq_handler);
1000 irq_set_handler_data(pctl->irq[i], pctl);
1001 }
60242db1 1002
08e9e614 1003 dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
0e37f88d
MR		 1004
1005 return 0;
08e9e614 1006
e2bddc6a
BB		 1007clk_error:
1008 clk_disable_unprepare(clk);
08e9e614 1009gpiochip_error:
b4e7c55d 1010 gpiochip_remove(pctl->chip);
08e9e614
MR		 1011pinctrl_error:
1012 pinctrl_unregister(pctl->pctl_dev);
1013 return ret;
0e37f88d 1014}
Linux kernel - Deliverables
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