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0e37f88d MR |
1 | /* |
2 | * Allwinner A1X SoCs pinctrl driver. | |
3 | * | |
4 | * Copyright (C) 2012 Maxime Ripard | |
5 | * | |
6 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
13 | #include <linux/io.h> | |
950707c0 | 14 | #include <linux/clk.h> |
08e9e614 | 15 | #include <linux/gpio.h> |
60242db1 | 16 | #include <linux/irqdomain.h> |
905a5117 | 17 | #include <linux/irqchip/chained_irq.h> |
0e37f88d MR |
18 | #include <linux/module.h> |
19 | #include <linux/of.h> | |
20 | #include <linux/of_address.h> | |
21 | #include <linux/of_device.h> | |
60242db1 | 22 | #include <linux/of_irq.h> |
0e37f88d MR |
23 | #include <linux/pinctrl/consumer.h> |
24 | #include <linux/pinctrl/machine.h> | |
25 | #include <linux/pinctrl/pinctrl.h> | |
26 | #include <linux/pinctrl/pinconf-generic.h> | |
27 | #include <linux/pinctrl/pinmux.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/slab.h> | |
30 | ||
5f910777 | 31 | #include "../core.h" |
0e37f88d | 32 | #include "pinctrl-sunxi.h" |
eaa3d848 | 33 | |
0e37f88d MR |
34 | static struct sunxi_pinctrl_group * |
35 | sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) | |
36 | { | |
37 | int i; | |
38 | ||
39 | for (i = 0; i < pctl->ngroups; i++) { | |
40 | struct sunxi_pinctrl_group *grp = pctl->groups + i; | |
41 | ||
42 | if (!strcmp(grp->name, group)) | |
43 | return grp; | |
44 | } | |
45 | ||
46 | return NULL; | |
47 | } | |
48 | ||
49 | static struct sunxi_pinctrl_function * | |
50 | sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, | |
51 | const char *name) | |
52 | { | |
53 | struct sunxi_pinctrl_function *func = pctl->functions; | |
54 | int i; | |
55 | ||
56 | for (i = 0; i < pctl->nfunctions; i++) { | |
57 | if (!func[i].name) | |
58 | break; | |
59 | ||
60 | if (!strcmp(func[i].name, name)) | |
61 | return func + i; | |
62 | } | |
63 | ||
64 | return NULL; | |
65 | } | |
66 | ||
67 | static struct sunxi_desc_function * | |
68 | sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, | |
69 | const char *pin_name, | |
70 | const char *func_name) | |
71 | { | |
72 | int i; | |
73 | ||
74 | for (i = 0; i < pctl->desc->npins; i++) { | |
75 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
76 | ||
77 | if (!strcmp(pin->pin.name, pin_name)) { | |
78 | struct sunxi_desc_function *func = pin->functions; | |
79 | ||
80 | while (func->name) { | |
81 | if (!strcmp(func->name, func_name)) | |
82 | return func; | |
83 | ||
84 | func++; | |
85 | } | |
86 | } | |
87 | } | |
88 | ||
89 | return NULL; | |
90 | } | |
91 | ||
814d4f2e MR |
92 | static struct sunxi_desc_function * |
93 | sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl, | |
94 | const u16 pin_num, | |
95 | const char *func_name) | |
96 | { | |
97 | int i; | |
98 | ||
99 | for (i = 0; i < pctl->desc->npins; i++) { | |
100 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
101 | ||
102 | if (pin->pin.number == pin_num) { | |
103 | struct sunxi_desc_function *func = pin->functions; | |
104 | ||
105 | while (func->name) { | |
106 | if (!strcmp(func->name, func_name)) | |
107 | return func; | |
108 | ||
109 | func++; | |
110 | } | |
111 | } | |
112 | } | |
113 | ||
114 | return NULL; | |
115 | } | |
116 | ||
0e37f88d MR |
117 | static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) |
118 | { | |
119 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
120 | ||
121 | return pctl->ngroups; | |
122 | } | |
123 | ||
124 | static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev, | |
125 | unsigned group) | |
126 | { | |
127 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
128 | ||
129 | return pctl->groups[group].name; | |
130 | } | |
131 | ||
132 | static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev, | |
133 | unsigned group, | |
134 | const unsigned **pins, | |
135 | unsigned *num_pins) | |
136 | { | |
137 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
138 | ||
139 | *pins = (unsigned *)&pctl->groups[group].pin; | |
140 | *num_pins = 1; | |
141 | ||
142 | return 0; | |
143 | } | |
144 | ||
145 | static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, | |
146 | struct device_node *node, | |
147 | struct pinctrl_map **map, | |
148 | unsigned *num_maps) | |
149 | { | |
150 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
151 | unsigned long *pinconfig; | |
152 | struct property *prop; | |
153 | const char *function; | |
154 | const char *group; | |
155 | int ret, nmaps, i = 0; | |
156 | u32 val; | |
157 | ||
158 | *map = NULL; | |
159 | *num_maps = 0; | |
160 | ||
161 | ret = of_property_read_string(node, "allwinner,function", &function); | |
162 | if (ret) { | |
163 | dev_err(pctl->dev, | |
164 | "missing allwinner,function property in node %s\n", | |
165 | node->name); | |
166 | return -EINVAL; | |
167 | } | |
168 | ||
169 | nmaps = of_property_count_strings(node, "allwinner,pins") * 2; | |
170 | if (nmaps < 0) { | |
171 | dev_err(pctl->dev, | |
172 | "missing allwinner,pins property in node %s\n", | |
173 | node->name); | |
174 | return -EINVAL; | |
175 | } | |
176 | ||
177 | *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL); | |
3efa921d | 178 | if (!*map) |
0e37f88d MR |
179 | return -ENOMEM; |
180 | ||
181 | of_property_for_each_string(node, "allwinner,pins", prop, group) { | |
182 | struct sunxi_pinctrl_group *grp = | |
183 | sunxi_pinctrl_find_group_by_name(pctl, group); | |
184 | int j = 0, configlen = 0; | |
185 | ||
186 | if (!grp) { | |
187 | dev_err(pctl->dev, "unknown pin %s", group); | |
188 | continue; | |
189 | } | |
190 | ||
191 | if (!sunxi_pinctrl_desc_find_function_by_name(pctl, | |
192 | grp->name, | |
193 | function)) { | |
194 | dev_err(pctl->dev, "unsupported function %s on pin %s", | |
195 | function, group); | |
196 | continue; | |
197 | } | |
198 | ||
199 | (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; | |
200 | (*map)[i].data.mux.group = group; | |
201 | (*map)[i].data.mux.function = function; | |
202 | ||
203 | i++; | |
204 | ||
205 | (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; | |
206 | (*map)[i].data.configs.group_or_pin = group; | |
207 | ||
208 | if (of_find_property(node, "allwinner,drive", NULL)) | |
209 | configlen++; | |
210 | if (of_find_property(node, "allwinner,pull", NULL)) | |
211 | configlen++; | |
212 | ||
213 | pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL); | |
214 | ||
215 | if (!of_property_read_u32(node, "allwinner,drive", &val)) { | |
216 | u16 strength = (val + 1) * 10; | |
217 | pinconfig[j++] = | |
218 | pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, | |
219 | strength); | |
220 | } | |
221 | ||
222 | if (!of_property_read_u32(node, "allwinner,pull", &val)) { | |
223 | enum pin_config_param pull = PIN_CONFIG_END; | |
224 | if (val == 1) | |
225 | pull = PIN_CONFIG_BIAS_PULL_UP; | |
226 | else if (val == 2) | |
227 | pull = PIN_CONFIG_BIAS_PULL_DOWN; | |
228 | pinconfig[j++] = pinconf_to_config_packed(pull, 0); | |
229 | } | |
230 | ||
231 | (*map)[i].data.configs.configs = pinconfig; | |
232 | (*map)[i].data.configs.num_configs = configlen; | |
233 | ||
234 | i++; | |
235 | } | |
236 | ||
237 | *num_maps = nmaps; | |
238 | ||
239 | return 0; | |
240 | } | |
241 | ||
242 | static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, | |
243 | struct pinctrl_map *map, | |
244 | unsigned num_maps) | |
245 | { | |
246 | int i; | |
247 | ||
248 | for (i = 0; i < num_maps; i++) { | |
249 | if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) | |
250 | kfree(map[i].data.configs.configs); | |
251 | } | |
252 | ||
253 | kfree(map); | |
254 | } | |
255 | ||
022ab148 | 256 | static const struct pinctrl_ops sunxi_pctrl_ops = { |
0e37f88d MR |
257 | .dt_node_to_map = sunxi_pctrl_dt_node_to_map, |
258 | .dt_free_map = sunxi_pctrl_dt_free_map, | |
259 | .get_groups_count = sunxi_pctrl_get_groups_count, | |
260 | .get_group_name = sunxi_pctrl_get_group_name, | |
261 | .get_group_pins = sunxi_pctrl_get_group_pins, | |
262 | }; | |
263 | ||
264 | static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, | |
265 | unsigned group, | |
266 | unsigned long *config) | |
267 | { | |
268 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
269 | ||
270 | *config = pctl->groups[group].config; | |
271 | ||
272 | return 0; | |
273 | } | |
274 | ||
275 | static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, | |
276 | unsigned group, | |
03b054e9 SY |
277 | unsigned long *configs, |
278 | unsigned num_configs) | |
0e37f88d MR |
279 | { |
280 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
281 | struct sunxi_pinctrl_group *g = &pctl->groups[group]; | |
1bee963d | 282 | unsigned long flags; |
b4575c69 | 283 | unsigned pin = g->pin - pctl->desc->pin_base; |
0e37f88d MR |
284 | u32 val, mask; |
285 | u16 strength; | |
286 | u8 dlevel; | |
03b054e9 | 287 | int i; |
0e37f88d | 288 | |
6ad30ce0 | 289 | spin_lock_irqsave(&pctl->lock, flags); |
1bee963d | 290 | |
03b054e9 SY |
291 | for (i = 0; i < num_configs; i++) { |
292 | switch (pinconf_to_config_param(configs[i])) { | |
293 | case PIN_CONFIG_DRIVE_STRENGTH: | |
294 | strength = pinconf_to_config_argument(configs[i]); | |
07b7eb92 LW |
295 | if (strength > 40) { |
296 | spin_unlock_irqrestore(&pctl->lock, flags); | |
03b054e9 | 297 | return -EINVAL; |
07b7eb92 | 298 | } |
03b054e9 SY |
299 | /* |
300 | * We convert from mA to what the register expects: | |
301 | * 0: 10mA | |
302 | * 1: 20mA | |
303 | * 2: 30mA | |
304 | * 3: 40mA | |
305 | */ | |
306 | dlevel = strength / 10 - 1; | |
b4575c69 CYT |
307 | val = readl(pctl->membase + sunxi_dlevel_reg(pin)); |
308 | mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin); | |
03b054e9 | 309 | writel((val & ~mask) |
b4575c69 CYT |
310 | | dlevel << sunxi_dlevel_offset(pin), |
311 | pctl->membase + sunxi_dlevel_reg(pin)); | |
03b054e9 SY |
312 | break; |
313 | case PIN_CONFIG_BIAS_PULL_UP: | |
b4575c69 CYT |
314 | val = readl(pctl->membase + sunxi_pull_reg(pin)); |
315 | mask = PULL_PINS_MASK << sunxi_pull_offset(pin); | |
316 | writel((val & ~mask) | 1 << sunxi_pull_offset(pin), | |
317 | pctl->membase + sunxi_pull_reg(pin)); | |
03b054e9 SY |
318 | break; |
319 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
b4575c69 CYT |
320 | val = readl(pctl->membase + sunxi_pull_reg(pin)); |
321 | mask = PULL_PINS_MASK << sunxi_pull_offset(pin); | |
322 | writel((val & ~mask) | 2 << sunxi_pull_offset(pin), | |
323 | pctl->membase + sunxi_pull_reg(pin)); | |
03b054e9 SY |
324 | break; |
325 | default: | |
326 | break; | |
327 | } | |
03b054e9 SY |
328 | /* cache the config value */ |
329 | g->config = configs[i]; | |
330 | } /* for each config */ | |
0e37f88d | 331 | |
6ad30ce0 | 332 | spin_unlock_irqrestore(&pctl->lock, flags); |
0e37f88d MR |
333 | |
334 | return 0; | |
335 | } | |
336 | ||
022ab148 | 337 | static const struct pinconf_ops sunxi_pconf_ops = { |
0e37f88d MR |
338 | .pin_config_group_get = sunxi_pconf_group_get, |
339 | .pin_config_group_set = sunxi_pconf_group_set, | |
340 | }; | |
341 | ||
342 | static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) | |
343 | { | |
344 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
345 | ||
346 | return pctl->nfunctions; | |
347 | } | |
348 | ||
349 | static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
350 | unsigned function) | |
351 | { | |
352 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
353 | ||
354 | return pctl->functions[function].name; | |
355 | } | |
356 | ||
357 | static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
358 | unsigned function, | |
359 | const char * const **groups, | |
360 | unsigned * const num_groups) | |
361 | { | |
362 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
363 | ||
364 | *groups = pctl->functions[function].groups; | |
365 | *num_groups = pctl->functions[function].ngroups; | |
366 | ||
367 | return 0; | |
368 | } | |
369 | ||
370 | static void sunxi_pmx_set(struct pinctrl_dev *pctldev, | |
371 | unsigned pin, | |
372 | u8 config) | |
373 | { | |
374 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
1bee963d MR |
375 | unsigned long flags; |
376 | u32 val, mask; | |
377 | ||
378 | spin_lock_irqsave(&pctl->lock, flags); | |
0e37f88d | 379 | |
b4575c69 | 380 | pin -= pctl->desc->pin_base; |
1bee963d MR |
381 | val = readl(pctl->membase + sunxi_mux_reg(pin)); |
382 | mask = MUX_PINS_MASK << sunxi_mux_offset(pin); | |
0e37f88d MR |
383 | writel((val & ~mask) | config << sunxi_mux_offset(pin), |
384 | pctl->membase + sunxi_mux_reg(pin)); | |
1bee963d MR |
385 | |
386 | spin_unlock_irqrestore(&pctl->lock, flags); | |
0e37f88d MR |
387 | } |
388 | ||
389 | static int sunxi_pmx_enable(struct pinctrl_dev *pctldev, | |
390 | unsigned function, | |
391 | unsigned group) | |
392 | { | |
393 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
394 | struct sunxi_pinctrl_group *g = pctl->groups + group; | |
395 | struct sunxi_pinctrl_function *func = pctl->functions + function; | |
396 | struct sunxi_desc_function *desc = | |
397 | sunxi_pinctrl_desc_find_function_by_name(pctl, | |
398 | g->name, | |
399 | func->name); | |
400 | ||
401 | if (!desc) | |
402 | return -EINVAL; | |
403 | ||
404 | sunxi_pmx_set(pctldev, g->pin, desc->muxval); | |
405 | ||
406 | return 0; | |
407 | } | |
408 | ||
08e9e614 MR |
409 | static int |
410 | sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, | |
411 | struct pinctrl_gpio_range *range, | |
412 | unsigned offset, | |
413 | bool input) | |
414 | { | |
415 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
416 | struct sunxi_desc_function *desc; | |
08e9e614 | 417 | const char *func; |
08e9e614 MR |
418 | |
419 | if (input) | |
420 | func = "gpio_in"; | |
421 | else | |
422 | func = "gpio_out"; | |
423 | ||
814d4f2e MR |
424 | desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func); |
425 | if (!desc) | |
426 | return -EINVAL; | |
08e9e614 MR |
427 | |
428 | sunxi_pmx_set(pctldev, offset, desc->muxval); | |
429 | ||
814d4f2e | 430 | return 0; |
08e9e614 MR |
431 | } |
432 | ||
022ab148 | 433 | static const struct pinmux_ops sunxi_pmx_ops = { |
0e37f88d MR |
434 | .get_functions_count = sunxi_pmx_get_funcs_cnt, |
435 | .get_function_name = sunxi_pmx_get_func_name, | |
436 | .get_function_groups = sunxi_pmx_get_func_groups, | |
437 | .enable = sunxi_pmx_enable, | |
08e9e614 | 438 | .gpio_set_direction = sunxi_pmx_gpio_set_direction, |
0e37f88d MR |
439 | }; |
440 | ||
08e9e614 MR |
441 | static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset) |
442 | { | |
443 | return pinctrl_request_gpio(chip->base + offset); | |
444 | } | |
445 | ||
446 | static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset) | |
447 | { | |
448 | pinctrl_free_gpio(chip->base + offset); | |
449 | } | |
450 | ||
451 | static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, | |
452 | unsigned offset) | |
453 | { | |
454 | return pinctrl_gpio_direction_input(chip->base + offset); | |
455 | } | |
456 | ||
457 | static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) | |
458 | { | |
459 | struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); | |
460 | ||
461 | u32 reg = sunxi_data_reg(offset); | |
462 | u8 index = sunxi_data_offset(offset); | |
463 | u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; | |
464 | ||
465 | return val; | |
466 | } | |
467 | ||
08e9e614 MR |
468 | static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, |
469 | unsigned offset, int value) | |
470 | { | |
471 | struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); | |
472 | u32 reg = sunxi_data_reg(offset); | |
473 | u8 index = sunxi_data_offset(offset); | |
1bee963d MR |
474 | unsigned long flags; |
475 | u32 regval; | |
476 | ||
477 | spin_lock_irqsave(&pctl->lock, flags); | |
478 | ||
479 | regval = readl(pctl->membase + reg); | |
08e9e614 | 480 | |
df7b34f4 MR |
481 | if (value) |
482 | regval |= BIT(index); | |
483 | else | |
484 | regval &= ~(BIT(index)); | |
08e9e614 | 485 | |
df7b34f4 | 486 | writel(regval, pctl->membase + reg); |
1bee963d MR |
487 | |
488 | spin_unlock_irqrestore(&pctl->lock, flags); | |
08e9e614 MR |
489 | } |
490 | ||
fa8cf57c CYT |
491 | static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, |
492 | unsigned offset, int value) | |
493 | { | |
494 | sunxi_pinctrl_gpio_set(chip, offset, value); | |
495 | return pinctrl_gpio_direction_output(chip->base + offset); | |
496 | } | |
497 | ||
a0d72094 MR |
498 | static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, |
499 | const struct of_phandle_args *gpiospec, | |
500 | u32 *flags) | |
501 | { | |
502 | int pin, base; | |
503 | ||
504 | base = PINS_PER_BANK * gpiospec->args[0]; | |
505 | pin = base + gpiospec->args[1]; | |
506 | ||
507 | if (pin > (gc->base + gc->ngpio)) | |
508 | return -EINVAL; | |
509 | ||
510 | if (flags) | |
511 | *flags = gpiospec->args[2]; | |
512 | ||
513 | return pin; | |
514 | } | |
515 | ||
60242db1 MR |
516 | static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
517 | { | |
518 | struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); | |
519 | struct sunxi_desc_function *desc; | |
520 | ||
c9e3b2d8 | 521 | if (offset >= chip->ngpio) |
60242db1 MR |
522 | return -ENXIO; |
523 | ||
524 | desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq"); | |
525 | if (!desc) | |
526 | return -EINVAL; | |
527 | ||
60242db1 MR |
528 | dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", |
529 | chip->label, offset + chip->base, desc->irqnum); | |
530 | ||
531 | return irq_find_mapping(pctl->domain, desc->irqnum); | |
532 | } | |
533 | ||
08e9e614 | 534 | |
60242db1 MR |
535 | static int sunxi_pinctrl_irq_set_type(struct irq_data *d, |
536 | unsigned int type) | |
537 | { | |
538 | struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
539 | u32 reg = sunxi_irq_cfg_reg(d->hwirq); | |
540 | u8 index = sunxi_irq_cfg_offset(d->hwirq); | |
1bee963d | 541 | unsigned long flags; |
2aaaddff | 542 | u32 regval; |
60242db1 MR |
543 | u8 mode; |
544 | ||
545 | switch (type) { | |
546 | case IRQ_TYPE_EDGE_RISING: | |
547 | mode = IRQ_EDGE_RISING; | |
548 | break; | |
549 | case IRQ_TYPE_EDGE_FALLING: | |
550 | mode = IRQ_EDGE_FALLING; | |
551 | break; | |
552 | case IRQ_TYPE_EDGE_BOTH: | |
553 | mode = IRQ_EDGE_BOTH; | |
554 | break; | |
555 | case IRQ_TYPE_LEVEL_HIGH: | |
556 | mode = IRQ_LEVEL_HIGH; | |
557 | break; | |
558 | case IRQ_TYPE_LEVEL_LOW: | |
559 | mode = IRQ_LEVEL_LOW; | |
560 | break; | |
561 | default: | |
562 | return -EINVAL; | |
563 | } | |
564 | ||
1bee963d MR |
565 | spin_lock_irqsave(&pctl->lock, flags); |
566 | ||
2aaaddff | 567 | regval = readl(pctl->membase + reg); |
d82f9401 | 568 | regval &= ~(IRQ_CFG_IRQ_MASK << index); |
2aaaddff | 569 | writel(regval | (mode << index), pctl->membase + reg); |
60242db1 | 570 | |
1bee963d | 571 | spin_unlock_irqrestore(&pctl->lock, flags); |
60242db1 MR |
572 | |
573 | return 0; | |
574 | } | |
575 | ||
645ec714 | 576 | static void sunxi_pinctrl_irq_ack(struct irq_data *d) |
60242db1 MR |
577 | { |
578 | struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
60242db1 MR |
579 | u32 status_reg = sunxi_irq_status_reg(d->hwirq); |
580 | u8 status_idx = sunxi_irq_status_offset(d->hwirq); | |
60242db1 MR |
581 | |
582 | /* Clear the IRQ */ | |
583 | writel(1 << status_idx, pctl->membase + status_reg); | |
584 | } | |
585 | ||
586 | static void sunxi_pinctrl_irq_mask(struct irq_data *d) | |
587 | { | |
588 | struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
589 | u32 reg = sunxi_irq_ctrl_reg(d->hwirq); | |
590 | u8 idx = sunxi_irq_ctrl_offset(d->hwirq); | |
1bee963d | 591 | unsigned long flags; |
60242db1 MR |
592 | u32 val; |
593 | ||
1bee963d MR |
594 | spin_lock_irqsave(&pctl->lock, flags); |
595 | ||
60242db1 MR |
596 | /* Mask the IRQ */ |
597 | val = readl(pctl->membase + reg); | |
598 | writel(val & ~(1 << idx), pctl->membase + reg); | |
1bee963d MR |
599 | |
600 | spin_unlock_irqrestore(&pctl->lock, flags); | |
60242db1 MR |
601 | } |
602 | ||
603 | static void sunxi_pinctrl_irq_unmask(struct irq_data *d) | |
604 | { | |
605 | struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
606 | struct sunxi_desc_function *func; | |
607 | u32 reg = sunxi_irq_ctrl_reg(d->hwirq); | |
608 | u8 idx = sunxi_irq_ctrl_offset(d->hwirq); | |
1bee963d | 609 | unsigned long flags; |
60242db1 MR |
610 | u32 val; |
611 | ||
612 | func = sunxi_pinctrl_desc_find_function_by_pin(pctl, | |
613 | pctl->irq_array[d->hwirq], | |
614 | "irq"); | |
615 | ||
616 | /* Change muxing to INT mode */ | |
617 | sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); | |
618 | ||
1bee963d MR |
619 | spin_lock_irqsave(&pctl->lock, flags); |
620 | ||
60242db1 MR |
621 | /* Unmask the IRQ */ |
622 | val = readl(pctl->membase + reg); | |
623 | writel(val | (1 << idx), pctl->membase + reg); | |
1bee963d MR |
624 | |
625 | spin_unlock_irqrestore(&pctl->lock, flags); | |
60242db1 MR |
626 | } |
627 | ||
628 | static struct irq_chip sunxi_pinctrl_irq_chip = { | |
645ec714 | 629 | .irq_ack = sunxi_pinctrl_irq_ack, |
60242db1 | 630 | .irq_mask = sunxi_pinctrl_irq_mask, |
60242db1 MR |
631 | .irq_unmask = sunxi_pinctrl_irq_unmask, |
632 | .irq_set_type = sunxi_pinctrl_irq_set_type, | |
633 | }; | |
634 | ||
635 | static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc) | |
636 | { | |
905a5117 | 637 | struct irq_chip *chip = irq_get_chip(irq); |
60242db1 MR |
638 | struct sunxi_pinctrl *pctl = irq_get_handler_data(irq); |
639 | const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG); | |
640 | ||
641 | /* Clear all interrupts */ | |
642 | writel(reg, pctl->membase + IRQ_STATUS_REG); | |
643 | ||
644 | if (reg) { | |
645 | int irqoffset; | |
646 | ||
905a5117 | 647 | chained_irq_enter(chip, desc); |
60242db1 MR |
648 | for_each_set_bit(irqoffset, ®, SUNXI_IRQ_NUMBER) { |
649 | int pin_irq = irq_find_mapping(pctl->domain, irqoffset); | |
650 | generic_handle_irq(pin_irq); | |
651 | } | |
905a5117 | 652 | chained_irq_exit(chip, desc); |
60242db1 MR |
653 | } |
654 | } | |
655 | ||
0e37f88d MR |
656 | static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, |
657 | const char *name) | |
658 | { | |
659 | struct sunxi_pinctrl_function *func = pctl->functions; | |
660 | ||
661 | while (func->name) { | |
662 | /* function already there */ | |
663 | if (strcmp(func->name, name) == 0) { | |
664 | func->ngroups++; | |
665 | return -EEXIST; | |
666 | } | |
667 | func++; | |
668 | } | |
669 | ||
670 | func->name = name; | |
671 | func->ngroups = 1; | |
672 | ||
673 | pctl->nfunctions++; | |
674 | ||
675 | return 0; | |
676 | } | |
677 | ||
678 | static int sunxi_pinctrl_build_state(struct platform_device *pdev) | |
679 | { | |
680 | struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); | |
681 | int i; | |
682 | ||
683 | pctl->ngroups = pctl->desc->npins; | |
684 | ||
685 | /* Allocate groups */ | |
686 | pctl->groups = devm_kzalloc(&pdev->dev, | |
687 | pctl->ngroups * sizeof(*pctl->groups), | |
688 | GFP_KERNEL); | |
689 | if (!pctl->groups) | |
690 | return -ENOMEM; | |
691 | ||
692 | for (i = 0; i < pctl->desc->npins; i++) { | |
693 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
694 | struct sunxi_pinctrl_group *group = pctl->groups + i; | |
695 | ||
696 | group->name = pin->pin.name; | |
697 | group->pin = pin->pin.number; | |
698 | } | |
699 | ||
700 | /* | |
701 | * We suppose that we won't have any more functions than pins, | |
702 | * we'll reallocate that later anyway | |
703 | */ | |
704 | pctl->functions = devm_kzalloc(&pdev->dev, | |
705 | pctl->desc->npins * sizeof(*pctl->functions), | |
706 | GFP_KERNEL); | |
707 | if (!pctl->functions) | |
708 | return -ENOMEM; | |
709 | ||
710 | /* Count functions and their associated groups */ | |
711 | for (i = 0; i < pctl->desc->npins; i++) { | |
712 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
713 | struct sunxi_desc_function *func = pin->functions; | |
714 | ||
715 | while (func->name) { | |
d54e9a28 CYT |
716 | /* Create interrupt mapping while we're at it */ |
717 | if (!strcmp(func->name, "irq")) | |
718 | pctl->irq_array[func->irqnum] = pin->pin.number; | |
0e37f88d MR |
719 | sunxi_pinctrl_add_function(pctl, func->name); |
720 | func++; | |
721 | } | |
722 | } | |
723 | ||
724 | pctl->functions = krealloc(pctl->functions, | |
725 | pctl->nfunctions * sizeof(*pctl->functions), | |
726 | GFP_KERNEL); | |
727 | ||
728 | for (i = 0; i < pctl->desc->npins; i++) { | |
729 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
730 | struct sunxi_desc_function *func = pin->functions; | |
731 | ||
732 | while (func->name) { | |
733 | struct sunxi_pinctrl_function *func_item; | |
734 | const char **func_grp; | |
735 | ||
736 | func_item = sunxi_pinctrl_find_function_by_name(pctl, | |
737 | func->name); | |
738 | if (!func_item) | |
739 | return -EINVAL; | |
740 | ||
741 | if (!func_item->groups) { | |
742 | func_item->groups = | |
743 | devm_kzalloc(&pdev->dev, | |
744 | func_item->ngroups * sizeof(*func_item->groups), | |
745 | GFP_KERNEL); | |
746 | if (!func_item->groups) | |
747 | return -ENOMEM; | |
748 | } | |
749 | ||
750 | func_grp = func_item->groups; | |
751 | while (*func_grp) | |
752 | func_grp++; | |
753 | ||
754 | *func_grp = pin->pin.name; | |
755 | func++; | |
756 | } | |
757 | } | |
758 | ||
759 | return 0; | |
760 | } | |
761 | ||
2284ba6b MR |
762 | int sunxi_pinctrl_init(struct platform_device *pdev, |
763 | const struct sunxi_pinctrl_desc *desc) | |
0e37f88d MR |
764 | { |
765 | struct device_node *node = pdev->dev.of_node; | |
ba6764d5 | 766 | struct pinctrl_desc *pctrl_desc; |
0e37f88d MR |
767 | struct pinctrl_pin_desc *pins; |
768 | struct sunxi_pinctrl *pctl; | |
4409cafc | 769 | struct resource *res; |
08e9e614 | 770 | int i, ret, last_pin; |
950707c0 | 771 | struct clk *clk; |
0e37f88d MR |
772 | |
773 | pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); | |
774 | if (!pctl) | |
775 | return -ENOMEM; | |
776 | platform_set_drvdata(pdev, pctl); | |
777 | ||
1bee963d MR |
778 | spin_lock_init(&pctl->lock); |
779 | ||
4409cafc MR |
780 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
781 | pctl->membase = devm_ioremap_resource(&pdev->dev, res); | |
782 | if (IS_ERR(pctl->membase)) | |
783 | return PTR_ERR(pctl->membase); | |
0e37f88d | 784 | |
ba6764d5 | 785 | pctl->dev = &pdev->dev; |
2284ba6b | 786 | pctl->desc = desc; |
0e37f88d MR |
787 | |
788 | ret = sunxi_pinctrl_build_state(pdev); | |
789 | if (ret) { | |
790 | dev_err(&pdev->dev, "dt probe failed: %d\n", ret); | |
791 | return ret; | |
792 | } | |
793 | ||
794 | pins = devm_kzalloc(&pdev->dev, | |
795 | pctl->desc->npins * sizeof(*pins), | |
796 | GFP_KERNEL); | |
797 | if (!pins) | |
798 | return -ENOMEM; | |
799 | ||
800 | for (i = 0; i < pctl->desc->npins; i++) | |
801 | pins[i] = pctl->desc->pins[i].pin; | |
802 | ||
ba6764d5 MR |
803 | pctrl_desc = devm_kzalloc(&pdev->dev, |
804 | sizeof(*pctrl_desc), | |
805 | GFP_KERNEL); | |
806 | if (!pctrl_desc) | |
807 | return -ENOMEM; | |
808 | ||
809 | pctrl_desc->name = dev_name(&pdev->dev); | |
810 | pctrl_desc->owner = THIS_MODULE; | |
811 | pctrl_desc->pins = pins; | |
812 | pctrl_desc->npins = pctl->desc->npins; | |
813 | pctrl_desc->confops = &sunxi_pconf_ops; | |
814 | pctrl_desc->pctlops = &sunxi_pctrl_ops; | |
815 | pctrl_desc->pmxops = &sunxi_pmx_ops; | |
816 | ||
817 | pctl->pctl_dev = pinctrl_register(pctrl_desc, | |
0e37f88d MR |
818 | &pdev->dev, pctl); |
819 | if (!pctl->pctl_dev) { | |
820 | dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); | |
821 | return -EINVAL; | |
822 | } | |
823 | ||
08e9e614 MR |
824 | pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); |
825 | if (!pctl->chip) { | |
826 | ret = -ENOMEM; | |
827 | goto pinctrl_error; | |
828 | } | |
829 | ||
830 | last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; | |
d83c82ce BB |
831 | pctl->chip->owner = THIS_MODULE; |
832 | pctl->chip->request = sunxi_pinctrl_gpio_request, | |
833 | pctl->chip->free = sunxi_pinctrl_gpio_free, | |
834 | pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input, | |
835 | pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output, | |
836 | pctl->chip->get = sunxi_pinctrl_gpio_get, | |
837 | pctl->chip->set = sunxi_pinctrl_gpio_set, | |
838 | pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate, | |
839 | pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq, | |
840 | pctl->chip->of_gpio_n_cells = 3, | |
841 | pctl->chip->can_sleep = false, | |
842 | pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) - | |
843 | pctl->desc->pin_base; | |
08e9e614 MR |
844 | pctl->chip->label = dev_name(&pdev->dev); |
845 | pctl->chip->dev = &pdev->dev; | |
d83c82ce | 846 | pctl->chip->base = pctl->desc->pin_base; |
08e9e614 MR |
847 | |
848 | ret = gpiochip_add(pctl->chip); | |
849 | if (ret) | |
850 | goto pinctrl_error; | |
851 | ||
852 | for (i = 0; i < pctl->desc->npins; i++) { | |
853 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
854 | ||
855 | ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), | |
856 | pin->pin.number, | |
857 | pin->pin.number, 1); | |
858 | if (ret) | |
859 | goto gpiochip_error; | |
860 | } | |
861 | ||
950707c0 | 862 | clk = devm_clk_get(&pdev->dev, NULL); |
d72f88a4 WY |
863 | if (IS_ERR(clk)) { |
864 | ret = PTR_ERR(clk); | |
950707c0 | 865 | goto gpiochip_error; |
d72f88a4 | 866 | } |
950707c0 | 867 | |
6415093f BB |
868 | ret = clk_prepare_enable(clk); |
869 | if (ret) | |
870 | goto gpiochip_error; | |
950707c0 | 871 | |
60242db1 MR |
872 | pctl->irq = irq_of_parse_and_map(node, 0); |
873 | if (!pctl->irq) { | |
874 | ret = -EINVAL; | |
dc969106 | 875 | goto clk_error; |
60242db1 MR |
876 | } |
877 | ||
878 | pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER, | |
879 | &irq_domain_simple_ops, NULL); | |
880 | if (!pctl->domain) { | |
881 | dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); | |
882 | ret = -ENOMEM; | |
dc969106 | 883 | goto clk_error; |
60242db1 MR |
884 | } |
885 | ||
886 | for (i = 0; i < SUNXI_IRQ_NUMBER; i++) { | |
887 | int irqno = irq_create_mapping(pctl->domain, i); | |
888 | ||
889 | irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip, | |
890 | handle_simple_irq); | |
891 | irq_set_chip_data(irqno, pctl); | |
892 | }; | |
893 | ||
894 | irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler); | |
895 | irq_set_handler_data(pctl->irq, pctl); | |
896 | ||
08e9e614 | 897 | dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); |
0e37f88d MR |
898 | |
899 | return 0; | |
08e9e614 | 900 | |
e2bddc6a BB |
901 | clk_error: |
902 | clk_disable_unprepare(clk); | |
08e9e614 | 903 | gpiochip_error: |
97fc4637 AL |
904 | if (gpiochip_remove(pctl->chip)) |
905 | dev_err(&pdev->dev, "failed to remove gpio chip\n"); | |
08e9e614 MR |
906 | pinctrl_error: |
907 | pinctrl_unregister(pctl->pctl_dev); | |
908 | return ret; | |
0e37f88d | 909 | } |