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0e37f88d MR |
1 | /* |
2 | * Allwinner A1X SoCs pinctrl driver. | |
3 | * | |
4 | * Copyright (C) 2012 Maxime Ripard | |
5 | * | |
6 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
13 | #include <linux/io.h> | |
950707c0 | 14 | #include <linux/clk.h> |
08e9e614 | 15 | #include <linux/gpio.h> |
60242db1 | 16 | #include <linux/irqdomain.h> |
905a5117 | 17 | #include <linux/irqchip/chained_irq.h> |
0e37f88d MR |
18 | #include <linux/module.h> |
19 | #include <linux/of.h> | |
20 | #include <linux/of_address.h> | |
21 | #include <linux/of_device.h> | |
60242db1 | 22 | #include <linux/of_irq.h> |
0e37f88d MR |
23 | #include <linux/pinctrl/consumer.h> |
24 | #include <linux/pinctrl/machine.h> | |
25 | #include <linux/pinctrl/pinctrl.h> | |
26 | #include <linux/pinctrl/pinconf-generic.h> | |
27 | #include <linux/pinctrl/pinmux.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/slab.h> | |
30 | ||
5f910777 | 31 | #include "../core.h" |
0e37f88d | 32 | #include "pinctrl-sunxi.h" |
eaa3d848 | 33 | |
0e37f88d MR |
34 | static struct sunxi_pinctrl_group * |
35 | sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) | |
36 | { | |
37 | int i; | |
38 | ||
39 | for (i = 0; i < pctl->ngroups; i++) { | |
40 | struct sunxi_pinctrl_group *grp = pctl->groups + i; | |
41 | ||
42 | if (!strcmp(grp->name, group)) | |
43 | return grp; | |
44 | } | |
45 | ||
46 | return NULL; | |
47 | } | |
48 | ||
49 | static struct sunxi_pinctrl_function * | |
50 | sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, | |
51 | const char *name) | |
52 | { | |
53 | struct sunxi_pinctrl_function *func = pctl->functions; | |
54 | int i; | |
55 | ||
56 | for (i = 0; i < pctl->nfunctions; i++) { | |
57 | if (!func[i].name) | |
58 | break; | |
59 | ||
60 | if (!strcmp(func[i].name, name)) | |
61 | return func + i; | |
62 | } | |
63 | ||
64 | return NULL; | |
65 | } | |
66 | ||
67 | static struct sunxi_desc_function * | |
68 | sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, | |
69 | const char *pin_name, | |
70 | const char *func_name) | |
71 | { | |
72 | int i; | |
73 | ||
74 | for (i = 0; i < pctl->desc->npins; i++) { | |
75 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
76 | ||
77 | if (!strcmp(pin->pin.name, pin_name)) { | |
78 | struct sunxi_desc_function *func = pin->functions; | |
79 | ||
80 | while (func->name) { | |
81 | if (!strcmp(func->name, func_name)) | |
82 | return func; | |
83 | ||
84 | func++; | |
85 | } | |
86 | } | |
87 | } | |
88 | ||
89 | return NULL; | |
90 | } | |
91 | ||
814d4f2e MR |
92 | static struct sunxi_desc_function * |
93 | sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl, | |
94 | const u16 pin_num, | |
95 | const char *func_name) | |
96 | { | |
97 | int i; | |
98 | ||
99 | for (i = 0; i < pctl->desc->npins; i++) { | |
100 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
101 | ||
102 | if (pin->pin.number == pin_num) { | |
103 | struct sunxi_desc_function *func = pin->functions; | |
104 | ||
105 | while (func->name) { | |
106 | if (!strcmp(func->name, func_name)) | |
107 | return func; | |
108 | ||
109 | func++; | |
110 | } | |
111 | } | |
112 | } | |
113 | ||
114 | return NULL; | |
115 | } | |
116 | ||
0e37f88d MR |
117 | static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) |
118 | { | |
119 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
120 | ||
121 | return pctl->ngroups; | |
122 | } | |
123 | ||
124 | static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev, | |
125 | unsigned group) | |
126 | { | |
127 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
128 | ||
129 | return pctl->groups[group].name; | |
130 | } | |
131 | ||
132 | static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev, | |
133 | unsigned group, | |
134 | const unsigned **pins, | |
135 | unsigned *num_pins) | |
136 | { | |
137 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
138 | ||
139 | *pins = (unsigned *)&pctl->groups[group].pin; | |
140 | *num_pins = 1; | |
141 | ||
142 | return 0; | |
143 | } | |
144 | ||
145 | static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, | |
146 | struct device_node *node, | |
147 | struct pinctrl_map **map, | |
148 | unsigned *num_maps) | |
149 | { | |
150 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
151 | unsigned long *pinconfig; | |
152 | struct property *prop; | |
153 | const char *function; | |
154 | const char *group; | |
155 | int ret, nmaps, i = 0; | |
156 | u32 val; | |
157 | ||
158 | *map = NULL; | |
159 | *num_maps = 0; | |
160 | ||
161 | ret = of_property_read_string(node, "allwinner,function", &function); | |
162 | if (ret) { | |
163 | dev_err(pctl->dev, | |
164 | "missing allwinner,function property in node %s\n", | |
165 | node->name); | |
166 | return -EINVAL; | |
167 | } | |
168 | ||
169 | nmaps = of_property_count_strings(node, "allwinner,pins") * 2; | |
170 | if (nmaps < 0) { | |
171 | dev_err(pctl->dev, | |
172 | "missing allwinner,pins property in node %s\n", | |
173 | node->name); | |
174 | return -EINVAL; | |
175 | } | |
176 | ||
177 | *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL); | |
3efa921d | 178 | if (!*map) |
0e37f88d MR |
179 | return -ENOMEM; |
180 | ||
181 | of_property_for_each_string(node, "allwinner,pins", prop, group) { | |
182 | struct sunxi_pinctrl_group *grp = | |
183 | sunxi_pinctrl_find_group_by_name(pctl, group); | |
184 | int j = 0, configlen = 0; | |
185 | ||
186 | if (!grp) { | |
187 | dev_err(pctl->dev, "unknown pin %s", group); | |
188 | continue; | |
189 | } | |
190 | ||
191 | if (!sunxi_pinctrl_desc_find_function_by_name(pctl, | |
192 | grp->name, | |
193 | function)) { | |
194 | dev_err(pctl->dev, "unsupported function %s on pin %s", | |
195 | function, group); | |
196 | continue; | |
197 | } | |
198 | ||
199 | (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; | |
200 | (*map)[i].data.mux.group = group; | |
201 | (*map)[i].data.mux.function = function; | |
202 | ||
203 | i++; | |
204 | ||
205 | (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; | |
206 | (*map)[i].data.configs.group_or_pin = group; | |
207 | ||
208 | if (of_find_property(node, "allwinner,drive", NULL)) | |
209 | configlen++; | |
210 | if (of_find_property(node, "allwinner,pull", NULL)) | |
211 | configlen++; | |
212 | ||
213 | pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL); | |
bd07894e SK |
214 | if (!pinconfig) { |
215 | kfree(*map); | |
216 | return -ENOMEM; | |
217 | } | |
0e37f88d MR |
218 | |
219 | if (!of_property_read_u32(node, "allwinner,drive", &val)) { | |
220 | u16 strength = (val + 1) * 10; | |
221 | pinconfig[j++] = | |
222 | pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, | |
223 | strength); | |
224 | } | |
225 | ||
226 | if (!of_property_read_u32(node, "allwinner,pull", &val)) { | |
227 | enum pin_config_param pull = PIN_CONFIG_END; | |
228 | if (val == 1) | |
229 | pull = PIN_CONFIG_BIAS_PULL_UP; | |
230 | else if (val == 2) | |
231 | pull = PIN_CONFIG_BIAS_PULL_DOWN; | |
232 | pinconfig[j++] = pinconf_to_config_packed(pull, 0); | |
233 | } | |
234 | ||
235 | (*map)[i].data.configs.configs = pinconfig; | |
236 | (*map)[i].data.configs.num_configs = configlen; | |
237 | ||
238 | i++; | |
239 | } | |
240 | ||
241 | *num_maps = nmaps; | |
242 | ||
243 | return 0; | |
244 | } | |
245 | ||
246 | static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, | |
247 | struct pinctrl_map *map, | |
248 | unsigned num_maps) | |
249 | { | |
250 | int i; | |
251 | ||
252 | for (i = 0; i < num_maps; i++) { | |
253 | if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) | |
254 | kfree(map[i].data.configs.configs); | |
255 | } | |
256 | ||
257 | kfree(map); | |
258 | } | |
259 | ||
022ab148 | 260 | static const struct pinctrl_ops sunxi_pctrl_ops = { |
0e37f88d MR |
261 | .dt_node_to_map = sunxi_pctrl_dt_node_to_map, |
262 | .dt_free_map = sunxi_pctrl_dt_free_map, | |
263 | .get_groups_count = sunxi_pctrl_get_groups_count, | |
264 | .get_group_name = sunxi_pctrl_get_group_name, | |
265 | .get_group_pins = sunxi_pctrl_get_group_pins, | |
266 | }; | |
267 | ||
268 | static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, | |
269 | unsigned group, | |
270 | unsigned long *config) | |
271 | { | |
272 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
273 | ||
274 | *config = pctl->groups[group].config; | |
275 | ||
276 | return 0; | |
277 | } | |
278 | ||
279 | static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, | |
280 | unsigned group, | |
03b054e9 SY |
281 | unsigned long *configs, |
282 | unsigned num_configs) | |
0e37f88d MR |
283 | { |
284 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
285 | struct sunxi_pinctrl_group *g = &pctl->groups[group]; | |
1bee963d | 286 | unsigned long flags; |
b4575c69 | 287 | unsigned pin = g->pin - pctl->desc->pin_base; |
0e37f88d MR |
288 | u32 val, mask; |
289 | u16 strength; | |
290 | u8 dlevel; | |
03b054e9 | 291 | int i; |
0e37f88d | 292 | |
6ad30ce0 | 293 | spin_lock_irqsave(&pctl->lock, flags); |
1bee963d | 294 | |
03b054e9 SY |
295 | for (i = 0; i < num_configs; i++) { |
296 | switch (pinconf_to_config_param(configs[i])) { | |
297 | case PIN_CONFIG_DRIVE_STRENGTH: | |
298 | strength = pinconf_to_config_argument(configs[i]); | |
07b7eb92 LW |
299 | if (strength > 40) { |
300 | spin_unlock_irqrestore(&pctl->lock, flags); | |
03b054e9 | 301 | return -EINVAL; |
07b7eb92 | 302 | } |
03b054e9 SY |
303 | /* |
304 | * We convert from mA to what the register expects: | |
305 | * 0: 10mA | |
306 | * 1: 20mA | |
307 | * 2: 30mA | |
308 | * 3: 40mA | |
309 | */ | |
310 | dlevel = strength / 10 - 1; | |
b4575c69 CYT |
311 | val = readl(pctl->membase + sunxi_dlevel_reg(pin)); |
312 | mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin); | |
03b054e9 | 313 | writel((val & ~mask) |
b4575c69 CYT |
314 | | dlevel << sunxi_dlevel_offset(pin), |
315 | pctl->membase + sunxi_dlevel_reg(pin)); | |
03b054e9 SY |
316 | break; |
317 | case PIN_CONFIG_BIAS_PULL_UP: | |
b4575c69 CYT |
318 | val = readl(pctl->membase + sunxi_pull_reg(pin)); |
319 | mask = PULL_PINS_MASK << sunxi_pull_offset(pin); | |
320 | writel((val & ~mask) | 1 << sunxi_pull_offset(pin), | |
321 | pctl->membase + sunxi_pull_reg(pin)); | |
03b054e9 SY |
322 | break; |
323 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
b4575c69 CYT |
324 | val = readl(pctl->membase + sunxi_pull_reg(pin)); |
325 | mask = PULL_PINS_MASK << sunxi_pull_offset(pin); | |
326 | writel((val & ~mask) | 2 << sunxi_pull_offset(pin), | |
327 | pctl->membase + sunxi_pull_reg(pin)); | |
03b054e9 SY |
328 | break; |
329 | default: | |
330 | break; | |
331 | } | |
03b054e9 SY |
332 | /* cache the config value */ |
333 | g->config = configs[i]; | |
334 | } /* for each config */ | |
0e37f88d | 335 | |
6ad30ce0 | 336 | spin_unlock_irqrestore(&pctl->lock, flags); |
0e37f88d MR |
337 | |
338 | return 0; | |
339 | } | |
340 | ||
022ab148 | 341 | static const struct pinconf_ops sunxi_pconf_ops = { |
0e37f88d MR |
342 | .pin_config_group_get = sunxi_pconf_group_get, |
343 | .pin_config_group_set = sunxi_pconf_group_set, | |
344 | }; | |
345 | ||
346 | static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) | |
347 | { | |
348 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
349 | ||
350 | return pctl->nfunctions; | |
351 | } | |
352 | ||
353 | static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
354 | unsigned function) | |
355 | { | |
356 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
357 | ||
358 | return pctl->functions[function].name; | |
359 | } | |
360 | ||
361 | static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
362 | unsigned function, | |
363 | const char * const **groups, | |
364 | unsigned * const num_groups) | |
365 | { | |
366 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
367 | ||
368 | *groups = pctl->functions[function].groups; | |
369 | *num_groups = pctl->functions[function].ngroups; | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
374 | static void sunxi_pmx_set(struct pinctrl_dev *pctldev, | |
375 | unsigned pin, | |
376 | u8 config) | |
377 | { | |
378 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
1bee963d MR |
379 | unsigned long flags; |
380 | u32 val, mask; | |
381 | ||
382 | spin_lock_irqsave(&pctl->lock, flags); | |
0e37f88d | 383 | |
b4575c69 | 384 | pin -= pctl->desc->pin_base; |
1bee963d MR |
385 | val = readl(pctl->membase + sunxi_mux_reg(pin)); |
386 | mask = MUX_PINS_MASK << sunxi_mux_offset(pin); | |
0e37f88d MR |
387 | writel((val & ~mask) | config << sunxi_mux_offset(pin), |
388 | pctl->membase + sunxi_mux_reg(pin)); | |
1bee963d MR |
389 | |
390 | spin_unlock_irqrestore(&pctl->lock, flags); | |
0e37f88d MR |
391 | } |
392 | ||
393 | static int sunxi_pmx_enable(struct pinctrl_dev *pctldev, | |
394 | unsigned function, | |
395 | unsigned group) | |
396 | { | |
397 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
398 | struct sunxi_pinctrl_group *g = pctl->groups + group; | |
399 | struct sunxi_pinctrl_function *func = pctl->functions + function; | |
400 | struct sunxi_desc_function *desc = | |
401 | sunxi_pinctrl_desc_find_function_by_name(pctl, | |
402 | g->name, | |
403 | func->name); | |
404 | ||
405 | if (!desc) | |
406 | return -EINVAL; | |
407 | ||
408 | sunxi_pmx_set(pctldev, g->pin, desc->muxval); | |
409 | ||
410 | return 0; | |
411 | } | |
412 | ||
08e9e614 MR |
413 | static int |
414 | sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, | |
415 | struct pinctrl_gpio_range *range, | |
416 | unsigned offset, | |
417 | bool input) | |
418 | { | |
419 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
420 | struct sunxi_desc_function *desc; | |
08e9e614 | 421 | const char *func; |
08e9e614 MR |
422 | |
423 | if (input) | |
424 | func = "gpio_in"; | |
425 | else | |
426 | func = "gpio_out"; | |
427 | ||
814d4f2e MR |
428 | desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func); |
429 | if (!desc) | |
430 | return -EINVAL; | |
08e9e614 MR |
431 | |
432 | sunxi_pmx_set(pctldev, offset, desc->muxval); | |
433 | ||
814d4f2e | 434 | return 0; |
08e9e614 MR |
435 | } |
436 | ||
022ab148 | 437 | static const struct pinmux_ops sunxi_pmx_ops = { |
0e37f88d MR |
438 | .get_functions_count = sunxi_pmx_get_funcs_cnt, |
439 | .get_function_name = sunxi_pmx_get_func_name, | |
440 | .get_function_groups = sunxi_pmx_get_func_groups, | |
441 | .enable = sunxi_pmx_enable, | |
08e9e614 | 442 | .gpio_set_direction = sunxi_pmx_gpio_set_direction, |
0e37f88d MR |
443 | }; |
444 | ||
08e9e614 MR |
445 | static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset) |
446 | { | |
447 | return pinctrl_request_gpio(chip->base + offset); | |
448 | } | |
449 | ||
450 | static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset) | |
451 | { | |
452 | pinctrl_free_gpio(chip->base + offset); | |
453 | } | |
454 | ||
455 | static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, | |
456 | unsigned offset) | |
457 | { | |
458 | return pinctrl_gpio_direction_input(chip->base + offset); | |
459 | } | |
460 | ||
461 | static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) | |
462 | { | |
463 | struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); | |
464 | ||
465 | u32 reg = sunxi_data_reg(offset); | |
466 | u8 index = sunxi_data_offset(offset); | |
467 | u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; | |
468 | ||
469 | return val; | |
470 | } | |
471 | ||
08e9e614 MR |
472 | static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, |
473 | unsigned offset, int value) | |
474 | { | |
475 | struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); | |
476 | u32 reg = sunxi_data_reg(offset); | |
477 | u8 index = sunxi_data_offset(offset); | |
1bee963d MR |
478 | unsigned long flags; |
479 | u32 regval; | |
480 | ||
481 | spin_lock_irqsave(&pctl->lock, flags); | |
482 | ||
483 | regval = readl(pctl->membase + reg); | |
08e9e614 | 484 | |
df7b34f4 MR |
485 | if (value) |
486 | regval |= BIT(index); | |
487 | else | |
488 | regval &= ~(BIT(index)); | |
08e9e614 | 489 | |
df7b34f4 | 490 | writel(regval, pctl->membase + reg); |
1bee963d MR |
491 | |
492 | spin_unlock_irqrestore(&pctl->lock, flags); | |
08e9e614 MR |
493 | } |
494 | ||
fa8cf57c CYT |
495 | static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, |
496 | unsigned offset, int value) | |
497 | { | |
498 | sunxi_pinctrl_gpio_set(chip, offset, value); | |
499 | return pinctrl_gpio_direction_output(chip->base + offset); | |
500 | } | |
501 | ||
a0d72094 MR |
502 | static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, |
503 | const struct of_phandle_args *gpiospec, | |
504 | u32 *flags) | |
505 | { | |
506 | int pin, base; | |
507 | ||
508 | base = PINS_PER_BANK * gpiospec->args[0]; | |
509 | pin = base + gpiospec->args[1]; | |
510 | ||
511 | if (pin > (gc->base + gc->ngpio)) | |
512 | return -EINVAL; | |
513 | ||
514 | if (flags) | |
515 | *flags = gpiospec->args[2]; | |
516 | ||
517 | return pin; | |
518 | } | |
519 | ||
60242db1 MR |
520 | static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
521 | { | |
522 | struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); | |
523 | struct sunxi_desc_function *desc; | |
524 | ||
c9e3b2d8 | 525 | if (offset >= chip->ngpio) |
60242db1 MR |
526 | return -ENXIO; |
527 | ||
528 | desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq"); | |
529 | if (!desc) | |
530 | return -EINVAL; | |
531 | ||
60242db1 MR |
532 | dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", |
533 | chip->label, offset + chip->base, desc->irqnum); | |
534 | ||
535 | return irq_find_mapping(pctl->domain, desc->irqnum); | |
536 | } | |
537 | ||
08e9e614 | 538 | |
60242db1 MR |
539 | static int sunxi_pinctrl_irq_set_type(struct irq_data *d, |
540 | unsigned int type) | |
541 | { | |
542 | struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
543 | u32 reg = sunxi_irq_cfg_reg(d->hwirq); | |
544 | u8 index = sunxi_irq_cfg_offset(d->hwirq); | |
1bee963d | 545 | unsigned long flags; |
2aaaddff | 546 | u32 regval; |
60242db1 MR |
547 | u8 mode; |
548 | ||
549 | switch (type) { | |
550 | case IRQ_TYPE_EDGE_RISING: | |
551 | mode = IRQ_EDGE_RISING; | |
552 | break; | |
553 | case IRQ_TYPE_EDGE_FALLING: | |
554 | mode = IRQ_EDGE_FALLING; | |
555 | break; | |
556 | case IRQ_TYPE_EDGE_BOTH: | |
557 | mode = IRQ_EDGE_BOTH; | |
558 | break; | |
559 | case IRQ_TYPE_LEVEL_HIGH: | |
560 | mode = IRQ_LEVEL_HIGH; | |
561 | break; | |
562 | case IRQ_TYPE_LEVEL_LOW: | |
563 | mode = IRQ_LEVEL_LOW; | |
564 | break; | |
565 | default: | |
566 | return -EINVAL; | |
567 | } | |
568 | ||
1bee963d MR |
569 | spin_lock_irqsave(&pctl->lock, flags); |
570 | ||
2aaaddff | 571 | regval = readl(pctl->membase + reg); |
d82f9401 | 572 | regval &= ~(IRQ_CFG_IRQ_MASK << index); |
2aaaddff | 573 | writel(regval | (mode << index), pctl->membase + reg); |
60242db1 | 574 | |
1bee963d | 575 | spin_unlock_irqrestore(&pctl->lock, flags); |
60242db1 MR |
576 | |
577 | return 0; | |
578 | } | |
579 | ||
580 | static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d) | |
581 | { | |
582 | struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
583 | u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq); | |
584 | u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq); | |
585 | u32 status_reg = sunxi_irq_status_reg(d->hwirq); | |
586 | u8 status_idx = sunxi_irq_status_offset(d->hwirq); | |
1bee963d | 587 | unsigned long flags; |
60242db1 MR |
588 | u32 val; |
589 | ||
1bee963d MR |
590 | spin_lock_irqsave(&pctl->lock, flags); |
591 | ||
60242db1 MR |
592 | /* Mask the IRQ */ |
593 | val = readl(pctl->membase + ctrl_reg); | |
594 | writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg); | |
595 | ||
596 | /* Clear the IRQ */ | |
597 | writel(1 << status_idx, pctl->membase + status_reg); | |
1bee963d MR |
598 | |
599 | spin_unlock_irqrestore(&pctl->lock, flags); | |
60242db1 MR |
600 | } |
601 | ||
602 | static void sunxi_pinctrl_irq_mask(struct irq_data *d) | |
603 | { | |
604 | struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
605 | u32 reg = sunxi_irq_ctrl_reg(d->hwirq); | |
606 | u8 idx = sunxi_irq_ctrl_offset(d->hwirq); | |
1bee963d | 607 | unsigned long flags; |
60242db1 MR |
608 | u32 val; |
609 | ||
1bee963d MR |
610 | spin_lock_irqsave(&pctl->lock, flags); |
611 | ||
60242db1 MR |
612 | /* Mask the IRQ */ |
613 | val = readl(pctl->membase + reg); | |
614 | writel(val & ~(1 << idx), pctl->membase + reg); | |
1bee963d MR |
615 | |
616 | spin_unlock_irqrestore(&pctl->lock, flags); | |
60242db1 MR |
617 | } |
618 | ||
619 | static void sunxi_pinctrl_irq_unmask(struct irq_data *d) | |
620 | { | |
621 | struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
622 | struct sunxi_desc_function *func; | |
623 | u32 reg = sunxi_irq_ctrl_reg(d->hwirq); | |
624 | u8 idx = sunxi_irq_ctrl_offset(d->hwirq); | |
1bee963d | 625 | unsigned long flags; |
60242db1 MR |
626 | u32 val; |
627 | ||
628 | func = sunxi_pinctrl_desc_find_function_by_pin(pctl, | |
629 | pctl->irq_array[d->hwirq], | |
630 | "irq"); | |
631 | ||
632 | /* Change muxing to INT mode */ | |
633 | sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); | |
634 | ||
1bee963d MR |
635 | spin_lock_irqsave(&pctl->lock, flags); |
636 | ||
60242db1 MR |
637 | /* Unmask the IRQ */ |
638 | val = readl(pctl->membase + reg); | |
639 | writel(val | (1 << idx), pctl->membase + reg); | |
1bee963d MR |
640 | |
641 | spin_unlock_irqrestore(&pctl->lock, flags); | |
60242db1 MR |
642 | } |
643 | ||
644 | static struct irq_chip sunxi_pinctrl_irq_chip = { | |
645 | .irq_mask = sunxi_pinctrl_irq_mask, | |
646 | .irq_mask_ack = sunxi_pinctrl_irq_mask_ack, | |
647 | .irq_unmask = sunxi_pinctrl_irq_unmask, | |
648 | .irq_set_type = sunxi_pinctrl_irq_set_type, | |
649 | }; | |
650 | ||
651 | static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc) | |
652 | { | |
905a5117 | 653 | struct irq_chip *chip = irq_get_chip(irq); |
60242db1 MR |
654 | struct sunxi_pinctrl *pctl = irq_get_handler_data(irq); |
655 | const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG); | |
656 | ||
657 | /* Clear all interrupts */ | |
658 | writel(reg, pctl->membase + IRQ_STATUS_REG); | |
659 | ||
660 | if (reg) { | |
661 | int irqoffset; | |
662 | ||
905a5117 | 663 | chained_irq_enter(chip, desc); |
60242db1 MR |
664 | for_each_set_bit(irqoffset, ®, SUNXI_IRQ_NUMBER) { |
665 | int pin_irq = irq_find_mapping(pctl->domain, irqoffset); | |
666 | generic_handle_irq(pin_irq); | |
667 | } | |
905a5117 | 668 | chained_irq_exit(chip, desc); |
60242db1 MR |
669 | } |
670 | } | |
671 | ||
0e37f88d MR |
672 | static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, |
673 | const char *name) | |
674 | { | |
675 | struct sunxi_pinctrl_function *func = pctl->functions; | |
676 | ||
677 | while (func->name) { | |
678 | /* function already there */ | |
679 | if (strcmp(func->name, name) == 0) { | |
680 | func->ngroups++; | |
681 | return -EEXIST; | |
682 | } | |
683 | func++; | |
684 | } | |
685 | ||
686 | func->name = name; | |
687 | func->ngroups = 1; | |
688 | ||
689 | pctl->nfunctions++; | |
690 | ||
691 | return 0; | |
692 | } | |
693 | ||
694 | static int sunxi_pinctrl_build_state(struct platform_device *pdev) | |
695 | { | |
696 | struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); | |
697 | int i; | |
698 | ||
699 | pctl->ngroups = pctl->desc->npins; | |
700 | ||
701 | /* Allocate groups */ | |
702 | pctl->groups = devm_kzalloc(&pdev->dev, | |
703 | pctl->ngroups * sizeof(*pctl->groups), | |
704 | GFP_KERNEL); | |
705 | if (!pctl->groups) | |
706 | return -ENOMEM; | |
707 | ||
708 | for (i = 0; i < pctl->desc->npins; i++) { | |
709 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
710 | struct sunxi_pinctrl_group *group = pctl->groups + i; | |
711 | ||
712 | group->name = pin->pin.name; | |
713 | group->pin = pin->pin.number; | |
714 | } | |
715 | ||
716 | /* | |
717 | * We suppose that we won't have any more functions than pins, | |
718 | * we'll reallocate that later anyway | |
719 | */ | |
720 | pctl->functions = devm_kzalloc(&pdev->dev, | |
721 | pctl->desc->npins * sizeof(*pctl->functions), | |
722 | GFP_KERNEL); | |
723 | if (!pctl->functions) | |
724 | return -ENOMEM; | |
725 | ||
726 | /* Count functions and their associated groups */ | |
727 | for (i = 0; i < pctl->desc->npins; i++) { | |
728 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
729 | struct sunxi_desc_function *func = pin->functions; | |
730 | ||
731 | while (func->name) { | |
d54e9a28 CYT |
732 | /* Create interrupt mapping while we're at it */ |
733 | if (!strcmp(func->name, "irq")) | |
734 | pctl->irq_array[func->irqnum] = pin->pin.number; | |
0e37f88d MR |
735 | sunxi_pinctrl_add_function(pctl, func->name); |
736 | func++; | |
737 | } | |
738 | } | |
739 | ||
740 | pctl->functions = krealloc(pctl->functions, | |
741 | pctl->nfunctions * sizeof(*pctl->functions), | |
742 | GFP_KERNEL); | |
743 | ||
744 | for (i = 0; i < pctl->desc->npins; i++) { | |
745 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
746 | struct sunxi_desc_function *func = pin->functions; | |
747 | ||
748 | while (func->name) { | |
749 | struct sunxi_pinctrl_function *func_item; | |
750 | const char **func_grp; | |
751 | ||
752 | func_item = sunxi_pinctrl_find_function_by_name(pctl, | |
753 | func->name); | |
754 | if (!func_item) | |
755 | return -EINVAL; | |
756 | ||
757 | if (!func_item->groups) { | |
758 | func_item->groups = | |
759 | devm_kzalloc(&pdev->dev, | |
760 | func_item->ngroups * sizeof(*func_item->groups), | |
761 | GFP_KERNEL); | |
762 | if (!func_item->groups) | |
763 | return -ENOMEM; | |
764 | } | |
765 | ||
766 | func_grp = func_item->groups; | |
767 | while (*func_grp) | |
768 | func_grp++; | |
769 | ||
770 | *func_grp = pin->pin.name; | |
771 | func++; | |
772 | } | |
773 | } | |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
2284ba6b MR |
778 | int sunxi_pinctrl_init(struct platform_device *pdev, |
779 | const struct sunxi_pinctrl_desc *desc) | |
0e37f88d MR |
780 | { |
781 | struct device_node *node = pdev->dev.of_node; | |
ba6764d5 | 782 | struct pinctrl_desc *pctrl_desc; |
0e37f88d MR |
783 | struct pinctrl_pin_desc *pins; |
784 | struct sunxi_pinctrl *pctl; | |
4409cafc | 785 | struct resource *res; |
08e9e614 | 786 | int i, ret, last_pin; |
950707c0 | 787 | struct clk *clk; |
0e37f88d MR |
788 | |
789 | pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); | |
790 | if (!pctl) | |
791 | return -ENOMEM; | |
792 | platform_set_drvdata(pdev, pctl); | |
793 | ||
1bee963d MR |
794 | spin_lock_init(&pctl->lock); |
795 | ||
4409cafc MR |
796 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
797 | pctl->membase = devm_ioremap_resource(&pdev->dev, res); | |
798 | if (IS_ERR(pctl->membase)) | |
799 | return PTR_ERR(pctl->membase); | |
0e37f88d | 800 | |
ba6764d5 | 801 | pctl->dev = &pdev->dev; |
2284ba6b | 802 | pctl->desc = desc; |
0e37f88d MR |
803 | |
804 | ret = sunxi_pinctrl_build_state(pdev); | |
805 | if (ret) { | |
806 | dev_err(&pdev->dev, "dt probe failed: %d\n", ret); | |
807 | return ret; | |
808 | } | |
809 | ||
810 | pins = devm_kzalloc(&pdev->dev, | |
811 | pctl->desc->npins * sizeof(*pins), | |
812 | GFP_KERNEL); | |
813 | if (!pins) | |
814 | return -ENOMEM; | |
815 | ||
816 | for (i = 0; i < pctl->desc->npins; i++) | |
817 | pins[i] = pctl->desc->pins[i].pin; | |
818 | ||
ba6764d5 MR |
819 | pctrl_desc = devm_kzalloc(&pdev->dev, |
820 | sizeof(*pctrl_desc), | |
821 | GFP_KERNEL); | |
822 | if (!pctrl_desc) | |
823 | return -ENOMEM; | |
824 | ||
825 | pctrl_desc->name = dev_name(&pdev->dev); | |
826 | pctrl_desc->owner = THIS_MODULE; | |
827 | pctrl_desc->pins = pins; | |
828 | pctrl_desc->npins = pctl->desc->npins; | |
829 | pctrl_desc->confops = &sunxi_pconf_ops; | |
830 | pctrl_desc->pctlops = &sunxi_pctrl_ops; | |
831 | pctrl_desc->pmxops = &sunxi_pmx_ops; | |
832 | ||
833 | pctl->pctl_dev = pinctrl_register(pctrl_desc, | |
0e37f88d MR |
834 | &pdev->dev, pctl); |
835 | if (!pctl->pctl_dev) { | |
836 | dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); | |
837 | return -EINVAL; | |
838 | } | |
839 | ||
08e9e614 MR |
840 | pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); |
841 | if (!pctl->chip) { | |
842 | ret = -ENOMEM; | |
843 | goto pinctrl_error; | |
844 | } | |
845 | ||
846 | last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; | |
d83c82ce BB |
847 | pctl->chip->owner = THIS_MODULE; |
848 | pctl->chip->request = sunxi_pinctrl_gpio_request, | |
849 | pctl->chip->free = sunxi_pinctrl_gpio_free, | |
850 | pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input, | |
851 | pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output, | |
852 | pctl->chip->get = sunxi_pinctrl_gpio_get, | |
853 | pctl->chip->set = sunxi_pinctrl_gpio_set, | |
854 | pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate, | |
855 | pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq, | |
856 | pctl->chip->of_gpio_n_cells = 3, | |
857 | pctl->chip->can_sleep = false, | |
858 | pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) - | |
859 | pctl->desc->pin_base; | |
08e9e614 MR |
860 | pctl->chip->label = dev_name(&pdev->dev); |
861 | pctl->chip->dev = &pdev->dev; | |
d83c82ce | 862 | pctl->chip->base = pctl->desc->pin_base; |
08e9e614 MR |
863 | |
864 | ret = gpiochip_add(pctl->chip); | |
865 | if (ret) | |
866 | goto pinctrl_error; | |
867 | ||
868 | for (i = 0; i < pctl->desc->npins; i++) { | |
869 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
870 | ||
871 | ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), | |
872 | pin->pin.number, | |
873 | pin->pin.number, 1); | |
874 | if (ret) | |
875 | goto gpiochip_error; | |
876 | } | |
877 | ||
950707c0 | 878 | clk = devm_clk_get(&pdev->dev, NULL); |
d72f88a4 WY |
879 | if (IS_ERR(clk)) { |
880 | ret = PTR_ERR(clk); | |
950707c0 | 881 | goto gpiochip_error; |
d72f88a4 | 882 | } |
950707c0 | 883 | |
6415093f BB |
884 | ret = clk_prepare_enable(clk); |
885 | if (ret) | |
886 | goto gpiochip_error; | |
950707c0 | 887 | |
60242db1 MR |
888 | pctl->irq = irq_of_parse_and_map(node, 0); |
889 | if (!pctl->irq) { | |
890 | ret = -EINVAL; | |
dc969106 | 891 | goto clk_error; |
60242db1 MR |
892 | } |
893 | ||
894 | pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER, | |
895 | &irq_domain_simple_ops, NULL); | |
896 | if (!pctl->domain) { | |
897 | dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); | |
898 | ret = -ENOMEM; | |
dc969106 | 899 | goto clk_error; |
60242db1 MR |
900 | } |
901 | ||
902 | for (i = 0; i < SUNXI_IRQ_NUMBER; i++) { | |
903 | int irqno = irq_create_mapping(pctl->domain, i); | |
904 | ||
905 | irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip, | |
906 | handle_simple_irq); | |
907 | irq_set_chip_data(irqno, pctl); | |
908 | }; | |
909 | ||
910 | irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler); | |
911 | irq_set_handler_data(pctl->irq, pctl); | |
912 | ||
08e9e614 | 913 | dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); |
0e37f88d MR |
914 | |
915 | return 0; | |
08e9e614 | 916 | |
e2bddc6a BB |
917 | clk_error: |
918 | clk_disable_unprepare(clk); | |
08e9e614 | 919 | gpiochip_error: |
97fc4637 AL |
920 | if (gpiochip_remove(pctl->chip)) |
921 | dev_err(&pdev->dev, "failed to remove gpio chip\n"); | |
08e9e614 MR |
922 | pinctrl_error: |
923 | pinctrl_unregister(pctl->pctl_dev); | |
924 | return ret; | |
0e37f88d | 925 | } |