[deliverable/linux.git] / drivers / pinctrl / uniphier / pinctrl-uniphier.h

/*
 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef __PINCTRL_UNIPHIER_H__
#define __PINCTRL_UNIPHIER_H__

#include <linux/bitops.h>
#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/types.h>

struct platform_device;

#define UNIPHIER_PINCTRL_PINMUX_BASE	0x0
#define UNIPHIER_PINCTRL_LOAD_PINMUX	0x700
#define UNIPHIER_PINCTRL_DRVCTRL_BASE	0x800
#define UNIPHIER_PINCTRL_DRV2CTRL_BASE	0x900
#define UNIPHIER_PINCTRL_DRV3CTRL_BASE	0x980
#define UNIPHIER_PINCTRL_PUPDCTRL_BASE	0xa00
#define UNIPHIER_PINCTRL_IECTRL		0xd00

/* input enable control register bit */
#define UNIPHIER_PIN_IECTRL_SHIFT	0
#define UNIPHIER_PIN_IECTRL_BITS	8
#define UNIPHIER_PIN_IECTRL_MASK	((1UL << (UNIPHIER_PIN_IECTRL_BITS)) \
					 - 1)

/* drive strength control register number */
#define UNIPHIER_PIN_DRVCTRL_SHIFT	((UNIPHIER_PIN_IECTRL_SHIFT) + \
					(UNIPHIER_PIN_IECTRL_BITS))
#define UNIPHIER_PIN_DRVCTRL_BITS	9
#define UNIPHIER_PIN_DRVCTRL_MASK	((1UL << (UNIPHIER_PIN_DRVCTRL_BITS)) \
					 - 1)

/* drive control type */
#define UNIPHIER_PIN_DRV_TYPE_SHIFT	((UNIPHIER_PIN_DRVCTRL_SHIFT) + \
					 (UNIPHIER_PIN_DRVCTRL_BITS))
#define UNIPHIER_PIN_DRV_TYPE_BITS	3
#define UNIPHIER_PIN_DRV_TYPE_MASK	((1UL << (UNIPHIER_PIN_DRV_TYPE_BITS)) \
					 - 1)

/* pull-up / pull-down register number */
#define UNIPHIER_PIN_PUPDCTRL_SHIFT	((UNIPHIER_PIN_DRV_TYPE_SHIFT) + \
					 (UNIPHIER_PIN_DRV_TYPE_BITS))
#define UNIPHIER_PIN_PUPDCTRL_BITS	9
#define UNIPHIER_PIN_PUPDCTRL_MASK	((1UL << (UNIPHIER_PIN_PUPDCTRL_BITS))\
					 - 1)

/* direction of pull register */
#define UNIPHIER_PIN_PULL_DIR_SHIFT	((UNIPHIER_PIN_PUPDCTRL_SHIFT) + \
					 (UNIPHIER_PIN_PUPDCTRL_BITS))
#define UNIPHIER_PIN_PULL_DIR_BITS	3
#define UNIPHIER_PIN_PULL_DIR_MASK	((1UL << (UNIPHIER_PIN_PULL_DIR_BITS))\
					 - 1)

#if UNIPHIER_PIN_PULL_DIR_SHIFT + UNIPHIER_PIN_PULL_DIR_BITS > BITS_PER_LONG
#error "unable to pack pin attributes."
#endif

#define UNIPHIER_PIN_IECTRL_NONE	(UNIPHIER_PIN_IECTRL_MASK)

/* drive control type */
enum uniphier_pin_drv_type {
	UNIPHIER_PIN_DRV_1BIT,		/* 2 level control: 4/8 mA */
	UNIPHIER_PIN_DRV_2BIT,		/* 4 level control: 8/12/16/20 mA */
	UNIPHIER_PIN_DRV_3BIT,		/* 8 level control: 4/5/7/9/11/12/14/16 mA */
	UNIPHIER_PIN_DRV_FIXED4,	/* fixed to 4mA */
	UNIPHIER_PIN_DRV_FIXED5,	/* fixed to 5mA */
	UNIPHIER_PIN_DRV_FIXED8,	/* fixed to 8mA */
	UNIPHIER_PIN_DRV_NONE,		/* no support (input only pin) */
};

/* direction of pull register (no pin supports bi-directional pull biasing) */
enum uniphier_pin_pull_dir {
	UNIPHIER_PIN_PULL_UP,		/* pull-up or disabled */
	UNIPHIER_PIN_PULL_DOWN,		/* pull-down or disabled */
	UNIPHIER_PIN_PULL_UP_FIXED,	/* always pull-up */
	UNIPHIER_PIN_PULL_DOWN_FIXED,	/* always pull-down */
	UNIPHIER_PIN_PULL_NONE,		/* no pull register */
};

#define UNIPHIER_PIN_IECTRL(x) \
	(((x) & (UNIPHIER_PIN_IECTRL_MASK)) << (UNIPHIER_PIN_IECTRL_SHIFT))
#define UNIPHIER_PIN_DRVCTRL(x) \
	(((x) & (UNIPHIER_PIN_DRVCTRL_MASK)) << (UNIPHIER_PIN_DRVCTRL_SHIFT))
#define UNIPHIER_PIN_DRV_TYPE(x) \
	(((x) & (UNIPHIER_PIN_DRV_TYPE_MASK)) << (UNIPHIER_PIN_DRV_TYPE_SHIFT))
#define UNIPHIER_PIN_PUPDCTRL(x) \
	(((x) & (UNIPHIER_PIN_PUPDCTRL_MASK)) << (UNIPHIER_PIN_PUPDCTRL_SHIFT))
#define UNIPHIER_PIN_PULL_DIR(x) \
	(((x) & (UNIPHIER_PIN_PULL_DIR_MASK)) << (UNIPHIER_PIN_PULL_DIR_SHIFT))

#define UNIPHIER_PIN_ATTR_PACKED(iectrl, drvctrl, drv_type, pupdctrl, pull_dir)\
				(UNIPHIER_PIN_IECTRL(iectrl) |		\
				 UNIPHIER_PIN_DRVCTRL(drvctrl) |	\
				 UNIPHIER_PIN_DRV_TYPE(drv_type) |	\
				 UNIPHIER_PIN_PUPDCTRL(pupdctrl) |	\
				 UNIPHIER_PIN_PULL_DIR(pull_dir))

static inline unsigned int uniphier_pin_get_iectrl(void *drv_data)
{
	return ((unsigned long)drv_data >> UNIPHIER_PIN_IECTRL_SHIFT) &
						UNIPHIER_PIN_IECTRL_MASK;
}

static inline unsigned int uniphier_pin_get_drvctrl(void *drv_data)
{
	return ((unsigned long)drv_data >> UNIPHIER_PIN_DRVCTRL_SHIFT) &
						UNIPHIER_PIN_DRVCTRL_MASK;
}

static inline unsigned int uniphier_pin_get_drv_type(void *drv_data)
{
	return ((unsigned long)drv_data >> UNIPHIER_PIN_DRV_TYPE_SHIFT) &
						UNIPHIER_PIN_DRV_TYPE_MASK;
}

static inline unsigned int uniphier_pin_get_pupdctrl(void *drv_data)
{
	return ((unsigned long)drv_data >> UNIPHIER_PIN_PUPDCTRL_SHIFT) &
						UNIPHIER_PIN_PUPDCTRL_MASK;
}

static inline unsigned int uniphier_pin_get_pull_dir(void *drv_data)
{
	return ((unsigned long)drv_data >> UNIPHIER_PIN_PULL_DIR_SHIFT) &
						UNIPHIER_PIN_PULL_DIR_MASK;
}

enum uniphier_pinmux_gpio_range_type {
	UNIPHIER_PINMUX_GPIO_RANGE_PORT,
	UNIPHIER_PINMUX_GPIO_RANGE_IRQ,
	UNIPHIER_PINMUX_GPIO_RANGE_NONE,
};

struct uniphier_pinctrl_group {
	const char *name;
	const unsigned *pins;
	unsigned num_pins;
	const int *muxvals;
	enum uniphier_pinmux_gpio_range_type range_type;
};

struct uniphier_pinmux_function {
	const char *name;
	const char * const *groups;
	unsigned num_groups;
};

struct uniphier_pinctrl_socdata {
	const struct pinctrl_pin_desc *pins;
	unsigned int npins;
	const struct uniphier_pinctrl_group *groups;
	int groups_count;
	const struct uniphier_pinmux_function *functions;
	int functions_count;
	unsigned int caps;
#define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL	BIT(1)
#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE	BIT(0)
};

#define UNIPHIER_PINCTRL_PIN(a, b, c, d, e, f, g)			\
{									\
	.number = a,							\
	.name = b,							\
	.drv_data = (void *)UNIPHIER_PIN_ATTR_PACKED(c, d, e, f, g),	\
}

#define __UNIPHIER_PINCTRL_GROUP(grp, type)				\
	{								\
		.name = #grp,						\
		.pins = grp##_pins,					\
		.num_pins = ARRAY_SIZE(grp##_pins),			\
		.muxvals = grp##_muxvals +				\
			BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) !=	\
					  ARRAY_SIZE(grp##_muxvals)),	\
		.range_type = type,					\
	}

#define UNIPHIER_PINCTRL_GROUP(grp)					\
	__UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_NONE)

#define UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(grp)			\
	__UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_PORT)

#define UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(grp)			\
	__UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_IRQ)

#define UNIPHIER_PINCTRL_GROUP_SINGLE(grp, array, ofst)			\
	{								\
		.name = #grp,						\
		.pins = array##_pins + ofst,				\
		.num_pins = 1,						\
		.muxvals = array##_muxvals + ofst,			\
	}

#define UNIPHIER_PINMUX_FUNCTION(func)					\
	{								\
		.name = #func,						\
		.groups = func##_groups,				\
		.num_groups = ARRAY_SIZE(func##_groups),		\
	}

int uniphier_pinctrl_probe(struct platform_device *pdev,
			   struct uniphier_pinctrl_socdata *socdata);

#endif /* __PINCTRL_UNIPHIER_H__ */
Commit	Line	Data
6e908892 MY	1	/*
	2	* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
	15	#ifndef __PINCTRL_UNIPHIER_H__
	16	#define __PINCTRL_UNIPHIER_H__
	17
c2ebf475	18	#include <linux/bitops.h>
6e908892 MY	19	#include <linux/bug.h>
	20	#include <linux/kernel.h>
	21	#include <linux/types.h>
	22
fc78a566 MY	23	struct platform_device;
fc78a566 MY	24
6e908892 MY	25	#define UNIPHIER_PINCTRL_PINMUX_BASE 0x0
	26	#define UNIPHIER_PINCTRL_LOAD_PINMUX 0x700
	27	#define UNIPHIER_PINCTRL_DRVCTRL_BASE 0x800
	28	#define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x900
72e5706a	29	#define UNIPHIER_PINCTRL_DRV3CTRL_BASE 0x980
6e908892 MY	30	#define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0xa00
	31	#define UNIPHIER_PINCTRL_IECTRL 0xd00
	32
	33	/* input enable control register bit */
	34	#define UNIPHIER_PIN_IECTRL_SHIFT 0
	35	#define UNIPHIER_PIN_IECTRL_BITS 8
	36	#define UNIPHIER_PIN_IECTRL_MASK ((1UL << (UNIPHIER_PIN_IECTRL_BITS)) \
	37	- 1)
	38
	39	/* drive strength control register number */
	40	#define UNIPHIER_PIN_DRVCTRL_SHIFT ((UNIPHIER_PIN_IECTRL_SHIFT) + \
	41	(UNIPHIER_PIN_IECTRL_BITS))
	42	#define UNIPHIER_PIN_DRVCTRL_BITS 9
	43	#define UNIPHIER_PIN_DRVCTRL_MASK ((1UL << (UNIPHIER_PIN_DRVCTRL_BITS)) \
	44	- 1)
	45
9eaa98a6 MY	46	/* drive control type */
9eaa98a6 MY	47	#define UNIPHIER_PIN_DRV_TYPE_SHIFT ((UNIPHIER_PIN_DRVCTRL_SHIFT) + \
6e908892	48	(UNIPHIER_PIN_DRVCTRL_BITS))
9eaa98a6 MY	49	#define UNIPHIER_PIN_DRV_TYPE_BITS 3
9eaa98a6 MY	50	#define UNIPHIER_PIN_DRV_TYPE_MASK ((1UL << (UNIPHIER_PIN_DRV_TYPE_BITS)) \
6e908892 MY	51	- 1)
	52
	53	/* pull-up / pull-down register number */
9eaa98a6 MY	54	#define UNIPHIER_PIN_PUPDCTRL_SHIFT ((UNIPHIER_PIN_DRV_TYPE_SHIFT) + \
9eaa98a6 MY	55	(UNIPHIER_PIN_DRV_TYPE_BITS))
6e908892 MY	56	#define UNIPHIER_PIN_PUPDCTRL_BITS 9
	57	#define UNIPHIER_PIN_PUPDCTRL_MASK ((1UL << (UNIPHIER_PIN_PUPDCTRL_BITS))\
	58	- 1)
	59
	60	/* direction of pull register */
	61	#define UNIPHIER_PIN_PULL_DIR_SHIFT ((UNIPHIER_PIN_PUPDCTRL_SHIFT) + \
	62	(UNIPHIER_PIN_PUPDCTRL_BITS))
	63	#define UNIPHIER_PIN_PULL_DIR_BITS 3
	64	#define UNIPHIER_PIN_PULL_DIR_MASK ((1UL << (UNIPHIER_PIN_PULL_DIR_BITS))\
	65	- 1)
	66
	67	#if UNIPHIER_PIN_PULL_DIR_SHIFT + UNIPHIER_PIN_PULL_DIR_BITS > BITS_PER_LONG
	68	#error "unable to pack pin attributes."
	69	#endif
	70
	71	#define UNIPHIER_PIN_IECTRL_NONE (UNIPHIER_PIN_IECTRL_MASK)
	72
9eaa98a6 MY	73	/* drive control type */
	74	enum uniphier_pin_drv_type {
	75	UNIPHIER_PIN_DRV_1BIT, /* 2 level control: 4/8 mA */
	76	UNIPHIER_PIN_DRV_2BIT, /* 4 level control: 8/12/16/20 mA */
72e5706a	77	UNIPHIER_PIN_DRV_3BIT, /* 8 level control: 4/5/7/9/11/12/14/16 mA */
9eaa98a6 MY	78	UNIPHIER_PIN_DRV_FIXED4, /* fixed to 4mA */
	79	UNIPHIER_PIN_DRV_FIXED5, /* fixed to 5mA */
	80	UNIPHIER_PIN_DRV_FIXED8, /* fixed to 8mA */
6e908892 MY	81	UNIPHIER_PIN_DRV_NONE, /* no support (input only pin) */
	82	};
	83
	84	/* direction of pull register (no pin supports bi-directional pull biasing) */
	85	enum uniphier_pin_pull_dir {
	86	UNIPHIER_PIN_PULL_UP, /* pull-up or disabled */
	87	UNIPHIER_PIN_PULL_DOWN, /* pull-down or disabled */
	88	UNIPHIER_PIN_PULL_UP_FIXED, /* always pull-up */
	89	UNIPHIER_PIN_PULL_DOWN_FIXED, /* always pull-down */
	90	UNIPHIER_PIN_PULL_NONE, /* no pull register */
	91	};
	92
	93	#define UNIPHIER_PIN_IECTRL(x) \
	94	(((x) & (UNIPHIER_PIN_IECTRL_MASK)) << (UNIPHIER_PIN_IECTRL_SHIFT))
	95	#define UNIPHIER_PIN_DRVCTRL(x) \
	96	(((x) & (UNIPHIER_PIN_DRVCTRL_MASK)) << (UNIPHIER_PIN_DRVCTRL_SHIFT))
9eaa98a6 MY	97	#define UNIPHIER_PIN_DRV_TYPE(x) \
9eaa98a6 MY	98	(((x) & (UNIPHIER_PIN_DRV_TYPE_MASK)) << (UNIPHIER_PIN_DRV_TYPE_SHIFT))
6e908892 MY	99	#define UNIPHIER_PIN_PUPDCTRL(x) \
	100	(((x) & (UNIPHIER_PIN_PUPDCTRL_MASK)) << (UNIPHIER_PIN_PUPDCTRL_SHIFT))
	101	#define UNIPHIER_PIN_PULL_DIR(x) \
	102	(((x) & (UNIPHIER_PIN_PULL_DIR_MASK)) << (UNIPHIER_PIN_PULL_DIR_SHIFT))
	103
9eaa98a6	104	#define UNIPHIER_PIN_ATTR_PACKED(iectrl, drvctrl, drv_type, pupdctrl, pull_dir)\
6e908892 MY	105	(UNIPHIER_PIN_IECTRL(iectrl) \| \
6e908892 MY	106	UNIPHIER_PIN_DRVCTRL(drvctrl) \| \
9eaa98a6	107	UNIPHIER_PIN_DRV_TYPE(drv_type) \| \
6e908892 MY	108	UNIPHIER_PIN_PUPDCTRL(pupdctrl) \| \
	109	UNIPHIER_PIN_PULL_DIR(pull_dir))
	110
	111	static inline unsigned int uniphier_pin_get_iectrl(void *drv_data)
	112	{
	113	return ((unsigned long)drv_data >> UNIPHIER_PIN_IECTRL_SHIFT) &
	114	UNIPHIER_PIN_IECTRL_MASK;
	115	}
	116
	117	static inline unsigned int uniphier_pin_get_drvctrl(void *drv_data)
	118	{
	119	return ((unsigned long)drv_data >> UNIPHIER_PIN_DRVCTRL_SHIFT) &
	120	UNIPHIER_PIN_DRVCTRL_MASK;
	121	}
	122
9eaa98a6	123	static inline unsigned int uniphier_pin_get_drv_type(void *drv_data)
6e908892	124	{
9eaa98a6 MY	125	return ((unsigned long)drv_data >> UNIPHIER_PIN_DRV_TYPE_SHIFT) &
9eaa98a6 MY	126	UNIPHIER_PIN_DRV_TYPE_MASK;
6e908892 MY	127	}
	128
	129	static inline unsigned int uniphier_pin_get_pupdctrl(void *drv_data)
	130	{
	131	return ((unsigned long)drv_data >> UNIPHIER_PIN_PUPDCTRL_SHIFT) &
	132	UNIPHIER_PIN_PUPDCTRL_MASK;
	133	}
	134
	135	static inline unsigned int uniphier_pin_get_pull_dir(void *drv_data)
	136	{
	137	return ((unsigned long)drv_data >> UNIPHIER_PIN_PULL_DIR_SHIFT) &
	138	UNIPHIER_PIN_PULL_DIR_MASK;
	139	}
	140
	141	enum uniphier_pinmux_gpio_range_type {
	142	UNIPHIER_PINMUX_GPIO_RANGE_PORT,
	143	UNIPHIER_PINMUX_GPIO_RANGE_IRQ,
	144	UNIPHIER_PINMUX_GPIO_RANGE_NONE,
	145	};
	146
	147	struct uniphier_pinctrl_group {
	148	const char *name;
	149	const unsigned *pins;
	150	unsigned num_pins;
39ec9ace	151	const int *muxvals;
6e908892 MY	152	enum uniphier_pinmux_gpio_range_type range_type;
	153	};
	154
	155	struct uniphier_pinmux_function {
	156	const char *name;
	157	const char * const *groups;
	158	unsigned num_groups;
	159	};
	160
	161	struct uniphier_pinctrl_socdata {
fc78a566 MY	162	const struct pinctrl_pin_desc *pins;
fc78a566 MY	163	unsigned int npins;
6e908892 MY	164	const struct uniphier_pinctrl_group *groups;
	165	int groups_count;
	166	const struct uniphier_pinmux_function *functions;
	167	int functions_count;
c2ebf475	168	unsigned int caps;
aa543888	169	#define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(1)
c2ebf475	170	#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(0)
6e908892 MY	171	};
	172
	173	#define UNIPHIER_PINCTRL_PIN(a, b, c, d, e, f, g) \
	174	{ \
	175	.number = a, \
	176	.name = b, \
	177	.drv_data = (void *)UNIPHIER_PIN_ATTR_PACKED(c, d, e, f, g), \
	178	}
	179
	180	#define __UNIPHIER_PINCTRL_GROUP(grp, type) \
	181	{ \
	182	.name = #grp, \
	183	.pins = grp##_pins, \
	184	.num_pins = ARRAY_SIZE(grp##_pins), \
	185	.muxvals = grp##_muxvals + \
	186	BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \
	187	ARRAY_SIZE(grp##_muxvals)), \
	188	.range_type = type, \
	189	}
	190
	191	#define UNIPHIER_PINCTRL_GROUP(grp) \
	192	__UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_NONE)
	193
	194	#define UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(grp) \
	195	__UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_PORT)
	196
	197	#define UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(grp) \
	198	__UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_IRQ)
	199
	200	#define UNIPHIER_PINCTRL_GROUP_SINGLE(grp, array, ofst) \
	201	{ \
	202	.name = #grp, \
	203	.pins = array##_pins + ofst, \
	204	.num_pins = 1, \
	205	.muxvals = array##_muxvals + ofst, \
	206	}
	207
	208	#define UNIPHIER_PINMUX_FUNCTION(func) \
	209	{ \
	210	.name = #func, \
	211	.groups = func##_groups, \
	212	.num_groups = ARRAY_SIZE(func##_groups), \
	213	}
	214
6e908892	215	int uniphier_pinctrl_probe(struct platform_device *pdev,
6e908892 MY	216	struct uniphier_pinctrl_socdata *socdata);
6e908892 MY	217
6e908892	218	#endif /* __PINCTRL_UNIPHIER_H__ */