[deliverable/linux.git] / drivers / platform / x86 / intel_pmic_gpio.c

/* Moorestown PMIC GPIO (access through IPC) driver
 * Copyright (c) 2008 - 2009, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

/* Supports:
 * Moorestown platform PMIC chip
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/stddef.h>
#include <linux/slab.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <asm/intel_scu_ipc.h>
#include <linux/device.h>
#include <linux/intel_pmic_gpio.h>
#include <linux/platform_device.h>

#define DRIVER_NAME "pmic_gpio"

/* register offset that IPC driver should use
 * 8 GPIO + 8 GPOSW (6 controllable) + 8GPO
 */
enum pmic_gpio_register {
	GPIO0		= 0xE0,
	GPIO7		= 0xE7,
	GPIOINT		= 0xE8,
	GPOSWCTL0	= 0xEC,
	GPOSWCTL5	= 0xF1,
	GPO		= 0xF4,
};

/* bits definition for GPIO & GPOSW */
#define GPIO_DRV 0x01
#define GPIO_DIR 0x02
#define GPIO_DIN 0x04
#define GPIO_DOU 0x08
#define GPIO_INTCTL 0x30
#define GPIO_DBC 0xc0

#define GPOSW_DRV 0x01
#define GPOSW_DOU 0x08
#define GPOSW_RDRV 0x30

#define GPIO_UPDATE_TYPE	0x80000000

#define NUM_GPIO 24

struct pmic_gpio {
	struct mutex		buslock;
	struct gpio_chip	chip;
	void			*gpiointr;
	int			irq;
	unsigned		irq_base;
	unsigned int		update_type;
	u32			trigger_type;
};

static void pmic_program_irqtype(int gpio, int type)
{
	if (type & IRQ_TYPE_EDGE_RISING)
		intel_scu_ipc_update_register(GPIO0 + gpio, 0x20, 0x20);
	else
		intel_scu_ipc_update_register(GPIO0 + gpio, 0x00, 0x20);

	if (type & IRQ_TYPE_EDGE_FALLING)
		intel_scu_ipc_update_register(GPIO0 + gpio, 0x10, 0x10);
	else
		intel_scu_ipc_update_register(GPIO0 + gpio, 0x00, 0x10);
};

static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	if (offset > 8) {
		printk(KERN_ERR
			"%s: only pin 0-7 support input\n", __func__);
		return -1;/* we only have 8 GPIO can use as input */
	}
	return intel_scu_ipc_update_register(GPIO0 + offset,
							GPIO_DIR, GPIO_DIR);
}

static int pmic_gpio_direction_output(struct gpio_chip *chip,
			unsigned offset, int value)
{
	int rc = 0;

	if (offset < 8)/* it is GPIO */
		rc = intel_scu_ipc_update_register(GPIO0 + offset,
				GPIO_DRV | (value ? GPIO_DOU : 0),
				GPIO_DRV | GPIO_DOU | GPIO_DIR);
	else if (offset < 16)/* it is GPOSW */
		rc = intel_scu_ipc_update_register(GPOSWCTL0 + offset - 8,
				GPOSW_DRV | (value ? GPOSW_DOU : 0),
				GPOSW_DRV | GPOSW_DOU | GPOSW_RDRV);
	else if (offset > 15 && offset < 24)/* it is GPO */
		rc = intel_scu_ipc_update_register(GPO,
				value ? 1 << (offset - 16) : 0,
				1 << (offset - 16));
	else {
		printk(KERN_ERR
			"%s: invalid PMIC GPIO pin %d!\n", __func__, offset);
		WARN_ON(1);
	}

	return rc;
}

static int pmic_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	u8 r;
	int ret;

	/* we only have 8 GPIO pins we can use as input */
	if (offset > 8)
		return -EOPNOTSUPP;
	ret = intel_scu_ipc_ioread8(GPIO0 + offset, &r);
	if (ret < 0)
		return ret;
	return r & GPIO_DIN;
}

static void pmic_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	if (offset < 8)/* it is GPIO */
		intel_scu_ipc_update_register(GPIO0 + offset,
			GPIO_DRV | (value ? GPIO_DOU : 0),
			GPIO_DRV | GPIO_DOU);
	else if (offset < 16)/* it is GPOSW */
		intel_scu_ipc_update_register(GPOSWCTL0 + offset - 8,
			GPOSW_DRV | (value ? GPOSW_DOU : 0),
			GPOSW_DRV | GPOSW_DOU | GPOSW_RDRV);
	else if (offset > 15 && offset < 24) /* it is GPO */
		intel_scu_ipc_update_register(GPO,
			value ? 1 << (offset - 16) : 0,
			1 << (offset - 16));
}

/*
 * This is called from genirq with pg->buslock locked and
 * irq_desc->lock held. We can not access the scu bus here, so we
 * store the change and update in the bus_sync_unlock() function below
 */
static int pmic_irq_type(struct irq_data *data, unsigned type)
{
	struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);
	u32 gpio = data->irq - pg->irq_base;

	if (gpio >= pg->chip.ngpio)
		return -EINVAL;

	pg->trigger_type = type;
	pg->update_type = gpio | GPIO_UPDATE_TYPE;
	return 0;
}

static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct pmic_gpio *pg = container_of(chip, struct pmic_gpio, chip);

	return pg->irq_base + offset;
}

static void pmic_bus_lock(struct irq_data *data)
{
	struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);

	mutex_lock(&pg->buslock);
}

static void pmic_bus_sync_unlock(struct irq_data *data)
{
	struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);

	if (pg->update_type) {
		unsigned int gpio = pg->update_type & ~GPIO_UPDATE_TYPE;

		pmic_program_irqtype(gpio, pg->trigger_type);
		pg->update_type = 0;
	}
	mutex_unlock(&pg->buslock);
}

/* the gpiointr register is read-clear, so just do nothing. */
static void pmic_irq_unmask(struct irq_data *data) { }

static void pmic_irq_mask(struct irq_data *data) { }

static struct irq_chip pmic_irqchip = {
	.name			= "PMIC-GPIO",
	.irq_mask		= pmic_irq_mask,
	.irq_unmask		= pmic_irq_unmask,
	.irq_set_type		= pmic_irq_type,
	.irq_bus_lock		= pmic_bus_lock,
	.irq_bus_sync_unlock	= pmic_bus_sync_unlock,
};

static irqreturn_t pmic_irq_handler(int irq, void *data)
{
	struct pmic_gpio *pg = data;
	u8 intsts = *((u8 *)pg->gpiointr + 4);
	int gpio;
	irqreturn_t ret = IRQ_NONE;

	for (gpio = 0; gpio < 8; gpio++) {
		if (intsts & (1 << gpio)) {
			pr_debug("pmic pin %d triggered\n", gpio);
			generic_handle_irq(pg->irq_base + gpio);
			ret = IRQ_HANDLED;
		}
	}
	return ret;
}

static int __devinit platform_pmic_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	int irq = platform_get_irq(pdev, 0);
	struct intel_pmic_gpio_platform_data *pdata = dev->platform_data;

	struct pmic_gpio *pg;
	int retval;
	int i;

	if (irq < 0) {
		dev_dbg(dev, "no IRQ line\n");
		return -EINVAL;
	}

	if (!pdata || !pdata->gpio_base || !pdata->irq_base) {
		dev_dbg(dev, "incorrect or missing platform data\n");
		return -EINVAL;
	}

	pg = kzalloc(sizeof(*pg), GFP_KERNEL);
	if (!pg)
		return -ENOMEM;

	dev_set_drvdata(dev, pg);

	pg->irq = irq;
	/* setting up SRAM mapping for GPIOINT register */
	pg->gpiointr = ioremap_nocache(pdata->gpiointr, 8);
	if (!pg->gpiointr) {
		printk(KERN_ERR "%s: Can not map GPIOINT.\n", __func__);
		retval = -EINVAL;
		goto err2;
	}
	pg->irq_base = pdata->irq_base;
	pg->chip.label = "intel_pmic";
	pg->chip.direction_input = pmic_gpio_direction_input;
	pg->chip.direction_output = pmic_gpio_direction_output;
	pg->chip.get = pmic_gpio_get;
	pg->chip.set = pmic_gpio_set;
	pg->chip.to_irq = pmic_gpio_to_irq;
	pg->chip.base = pdata->gpio_base;
	pg->chip.ngpio = NUM_GPIO;
	pg->chip.can_sleep = 1;
	pg->chip.dev = dev;

	mutex_init(&pg->buslock);

	pg->chip.dev = dev;
	retval = gpiochip_add(&pg->chip);
	if (retval) {
		printk(KERN_ERR "%s: Can not add pmic gpio chip.\n", __func__);
		goto err;
	}

	retval = request_irq(pg->irq, pmic_irq_handler, 0, "pmic", pg);
	if (retval) {
		printk(KERN_WARNING "pmic: Interrupt request failed\n");
		goto err;
	}

	for (i = 0; i < 8; i++) {
		irq_set_chip_and_handler_name(i + pg->irq_base,
					      &pmic_irqchip,
					      handle_simple_irq,
					      "demux");
		irq_set_chip_data(i + pg->irq_base, pg);
	}
	return 0;
err:
	iounmap(pg->gpiointr);
err2:
	kfree(pg);
	return retval;
}

/* at the same time, register a platform driver
 * this supports the sfi 0.81 fw */
static struct platform_driver platform_pmic_gpio_driver = {
	.driver = {
		.name		= DRIVER_NAME,
		.owner		= THIS_MODULE,
	},
	.probe		= platform_pmic_gpio_probe,
};

static int __init platform_pmic_gpio_init(void)
{
	return platform_driver_register(&platform_pmic_gpio_driver);
}

subsys_initcall(platform_pmic_gpio_init);

MODULE_AUTHOR("Alek Du <alek.du@intel.com>");
MODULE_DESCRIPTION("Intel Moorestown PMIC GPIO driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
89507787 AD	1	/* Moorestown PMIC GPIO (access through IPC) driver
	2	* Copyright (c) 2008 - 2009, Intel Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program; if not, write to the Free Software
	15	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	16	*/
	17
	18	/* Supports:
	19	* Moorestown platform PMIC chip
	20	*/
	21
	22	#include <linux/module.h>
	23	#include <linux/kernel.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/delay.h>
	26	#include <linux/stddef.h>
	27	#include <linux/slab.h>
	28	#include <linux/ioport.h>
	29	#include <linux/init.h>
	30	#include <linux/io.h>
	31	#include <linux/gpio.h>
89507787 AD	32	#include <asm/intel_scu_ipc.h>
	33	#include <linux/device.h>
	34	#include <linux/intel_pmic_gpio.h>
	35	#include <linux/platform_device.h>
	36
	37	#define DRIVER_NAME "pmic_gpio"
	38
	39	/* register offset that IPC driver should use
	40	* 8 GPIO + 8 GPOSW (6 controllable) + 8GPO
	41	*/
	42	enum pmic_gpio_register {
	43	GPIO0 = 0xE0,
	44	GPIO7 = 0xE7,
	45	GPIOINT = 0xE8,
	46	GPOSWCTL0 = 0xEC,
	47	GPOSWCTL5 = 0xF1,
	48	GPO = 0xF4,
	49	};
	50
	51	/* bits definition for GPIO & GPOSW */
	52	#define GPIO_DRV 0x01
	53	#define GPIO_DIR 0x02
	54	#define GPIO_DIN 0x04
	55	#define GPIO_DOU 0x08
	56	#define GPIO_INTCTL 0x30
	57	#define GPIO_DBC 0xc0
	58
	59	#define GPOSW_DRV 0x01
	60	#define GPOSW_DOU 0x08
	61	#define GPOSW_RDRV 0x30
	62
d4b7de61	63	#define GPIO_UPDATE_TYPE 0x80000000
89507787 AD	64
	65	#define NUM_GPIO 24
	66
89507787	67	struct pmic_gpio {
d4b7de61	68	struct mutex buslock;
89507787	69	struct gpio_chip chip;
89507787 AD	70	void *gpiointr;
	71	int irq;
	72	unsigned irq_base;
d4b7de61 TG	73	unsigned int update_type;
d4b7de61 TG	74	u32 trigger_type;
89507787 AD	75	};
89507787 AD	76
65d7ac03 TG	77	static void pmic_program_irqtype(int gpio, int type)
	78	{
	79	if (type & IRQ_TYPE_EDGE_RISING)
	80	intel_scu_ipc_update_register(GPIO0 + gpio, 0x20, 0x20);
	81	else
	82	intel_scu_ipc_update_register(GPIO0 + gpio, 0x00, 0x20);
	83
	84	if (type & IRQ_TYPE_EDGE_FALLING)
	85	intel_scu_ipc_update_register(GPIO0 + gpio, 0x10, 0x10);
	86	else
	87	intel_scu_ipc_update_register(GPIO0 + gpio, 0x00, 0x10);
	88	};
	89
89507787 AD	90	static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	91	{
	92	if (offset > 8) {
	93	printk(KERN_ERR
	94	"%s: only pin 0-7 support input\n", __func__);
	95	return -1;/* we only have 8 GPIO can use as input */
	96	}
	97	return intel_scu_ipc_update_register(GPIO0 + offset,
	98	GPIO_DIR, GPIO_DIR);
	99	}
	100
	101	static int pmic_gpio_direction_output(struct gpio_chip *chip,
	102	unsigned offset, int value)
	103	{
	104	int rc = 0;
	105
	106	if (offset < 8)/* it is GPIO */
	107	rc = intel_scu_ipc_update_register(GPIO0 + offset,
ffcfff3a AD	108	GPIO_DRV \| (value ? GPIO_DOU : 0),
ffcfff3a AD	109	GPIO_DRV \| GPIO_DOU \| GPIO_DIR);
89507787 AD	110	else if (offset < 16)/* it is GPOSW */
89507787 AD	111	rc = intel_scu_ipc_update_register(GPOSWCTL0 + offset - 8,
ffcfff3a AD	112	GPOSW_DRV \| (value ? GPOSW_DOU : 0),
ffcfff3a AD	113	GPOSW_DRV \| GPOSW_DOU \| GPOSW_RDRV);
89507787 AD	114	else if (offset > 15 && offset < 24)/* it is GPO */
89507787 AD	115	rc = intel_scu_ipc_update_register(GPO,
ffcfff3a AD	116	value ? 1 << (offset - 16) : 0,
ffcfff3a AD	117	1 << (offset - 16));
89507787 AD	118	else {
	119	printk(KERN_ERR
	120	"%s: invalid PMIC GPIO pin %d!\n", __func__, offset);
	121	WARN_ON(1);
	122	}
	123
	124	return rc;
	125	}
	126
	127	static int pmic_gpio_get(struct gpio_chip *chip, unsigned offset)
	128	{
	129	u8 r;
	130	int ret;
	131
	132	/* we only have 8 GPIO pins we can use as input */
	133	if (offset > 8)
	134	return -EOPNOTSUPP;
	135	ret = intel_scu_ipc_ioread8(GPIO0 + offset, &r);
	136	if (ret < 0)
	137	return ret;
	138	return r & GPIO_DIN;
	139	}
	140
	141	static void pmic_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	142	{
	143	if (offset < 8)/* it is GPIO */
	144	intel_scu_ipc_update_register(GPIO0 + offset,
ffcfff3a AD	145	GPIO_DRV \| (value ? GPIO_DOU : 0),
ffcfff3a AD	146	GPIO_DRV \| GPIO_DOU);
89507787 AD	147	else if (offset < 16)/* it is GPOSW */
89507787 AD	148	intel_scu_ipc_update_register(GPOSWCTL0 + offset - 8,
ffcfff3a AD	149	GPOSW_DRV \| (value ? GPOSW_DOU : 0),
ffcfff3a AD	150	GPOSW_DRV \| GPOSW_DOU \| GPOSW_RDRV);
89507787 AD	151	else if (offset > 15 && offset < 24) /* it is GPO */
89507787 AD	152	intel_scu_ipc_update_register(GPO,
ffcfff3a AD	153	value ? 1 << (offset - 16) : 0,
ffcfff3a AD	154	1 << (offset - 16));
89507787 AD	155	}
89507787 AD	156
d4b7de61 TG	157	/*
	158	* This is called from genirq with pg->buslock locked and
	159	* irq_desc->lock held. We can not access the scu bus here, so we
	160	* store the change and update in the bus_sync_unlock() function below
	161	*/
cb8e5e6a	162	static int pmic_irq_type(struct irq_data *data, unsigned type)
89507787	163	{
cb8e5e6a TG	164	struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);
cb8e5e6a TG	165	u32 gpio = data->irq - pg->irq_base;
89507787	166
41196179	167	if (gpio >= pg->chip.ngpio)
89507787 AD	168	return -EINVAL;
89507787 AD	169
d4b7de61 TG	170	pg->trigger_type = type;
d4b7de61 TG	171	pg->update_type = gpio \| GPIO_UPDATE_TYPE;
89507787 AD	172	return 0;
	173	}
	174
89507787 AD	175	static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
	176	{
	177	struct pmic_gpio *pg = container_of(chip, struct pmic_gpio, chip);
	178
	179	return pg->irq_base + offset;
	180	}
	181
65d7ac03 TG	182	static void pmic_bus_lock(struct irq_data *data)
	183	{
	184	struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);
	185
	186	mutex_lock(&pg->buslock);
	187	}
	188
	189	static void pmic_bus_sync_unlock(struct irq_data *data)
	190	{
	191	struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);
	192
	193	if (pg->update_type) {
	194	unsigned int gpio = pg->update_type & ~GPIO_UPDATE_TYPE;
	195
	196	pmic_program_irqtype(gpio, pg->trigger_type);
	197	pg->update_type = 0;
	198	}
	199	mutex_unlock(&pg->buslock);
	200	}
	201
89507787	202	/* the gpiointr register is read-clear, so just do nothing. */
cb8e5e6a	203	static void pmic_irq_unmask(struct irq_data *data) { }
89507787	204
cb8e5e6a	205	static void pmic_irq_mask(struct irq_data *data) { }
89507787 AD	206
89507787 AD	207	static struct irq_chip pmic_irqchip = {
65d7ac03 TG	208	.name = "PMIC-GPIO",
	209	.irq_mask = pmic_irq_mask,
	210	.irq_unmask = pmic_irq_unmask,
	211	.irq_set_type = pmic_irq_type,
21a8d026	212	.irq_bus_lock = pmic_bus_lock,
65d7ac03	213	.irq_bus_sync_unlock = pmic_bus_sync_unlock,
89507787 AD	214	};
89507787 AD	215
98401ae4	216	static irqreturn_t pmic_irq_handler(int irq, void *data)
89507787	217	{
98401ae4	218	struct pmic_gpio *pg = data;
89507787 AD	219	u8 intsts = ((u8 )pg->gpiointr + 4);
89507787 AD	220	int gpio;
98401ae4	221	irqreturn_t ret = IRQ_NONE;
89507787 AD	222
	223	for (gpio = 0; gpio < 8; gpio++) {
	224	if (intsts & (1 << gpio)) {
	225	pr_debug("pmic pin %d triggered\n", gpio);
	226	generic_handle_irq(pg->irq_base + gpio);
98401ae4	227	ret = IRQ_HANDLED;
89507787 AD	228	}
89507787 AD	229	}
98401ae4	230	return ret;
89507787 AD	231	}
	232
	233	static int __devinit platform_pmic_gpio_probe(struct platform_device *pdev)
	234	{
	235	struct device *dev = &pdev->dev;
	236	int irq = platform_get_irq(pdev, 0);
	237	struct intel_pmic_gpio_platform_data *pdata = dev->platform_data;
	238
	239	struct pmic_gpio *pg;
	240	int retval;
	241	int i;
	242
	243	if (irq < 0) {
	244	dev_dbg(dev, "no IRQ line\n");
	245	return -EINVAL;
	246	}
	247
	248	if (!pdata \|\| !pdata->gpio_base \|\| !pdata->irq_base) {
	249	dev_dbg(dev, "incorrect or missing platform data\n");
	250	return -EINVAL;
	251	}
	252
	253	pg = kzalloc(sizeof(*pg), GFP_KERNEL);
	254	if (!pg)
	255	return -ENOMEM;
	256
	257	dev_set_drvdata(dev, pg);
	258
	259	pg->irq = irq;
	260	/* setting up SRAM mapping for GPIOINT register */
	261	pg->gpiointr = ioremap_nocache(pdata->gpiointr, 8);
	262	if (!pg->gpiointr) {
	263	printk(KERN_ERR "%s: Can not map GPIOINT.\n", __func__);
	264	retval = -EINVAL;
	265	goto err2;
	266	}
	267	pg->irq_base = pdata->irq_base;
	268	pg->chip.label = "intel_pmic";
	269	pg->chip.direction_input = pmic_gpio_direction_input;
	270	pg->chip.direction_output = pmic_gpio_direction_output;
	271	pg->chip.get = pmic_gpio_get;
	272	pg->chip.set = pmic_gpio_set;
	273	pg->chip.to_irq = pmic_gpio_to_irq;
	274	pg->chip.base = pdata->gpio_base;
	275	pg->chip.ngpio = NUM_GPIO;
	276	pg->chip.can_sleep = 1;
	277	pg->chip.dev = dev;
	278
d4b7de61	279	mutex_init(&pg->buslock);
89507787 AD	280
	281	pg->chip.dev = dev;
	282	retval = gpiochip_add(&pg->chip);
	283	if (retval) {
	284	printk(KERN_ERR "%s: Can not add pmic gpio chip.\n", __func__);
	285	goto err;
	286	}
98401ae4 TG	287
	288	retval = request_irq(pg->irq, pmic_irq_handler, 0, "pmic", pg);
	289	if (retval) {
	290	printk(KERN_WARNING "pmic: Interrupt request failed\n");
	291	goto err;
	292	}
	293
89507787	294	for (i = 0; i < 8; i++) {
dced35ae TG	295	irq_set_chip_and_handler_name(i + pg->irq_base,
	296	&pmic_irqchip,
	297	handle_simple_irq,
	298	"demux");
	299	irq_set_chip_data(i + pg->irq_base, pg);
89507787 AD	300	}
	301	return 0;
	302	err:
	303	iounmap(pg->gpiointr);
	304	err2:
	305	kfree(pg);
	306	return retval;
	307	}
	308
	309	/* at the same time, register a platform driver
	310	* this supports the sfi 0.81 fw */
	311	static struct platform_driver platform_pmic_gpio_driver = {
	312	.driver = {
	313	.name = DRIVER_NAME,
	314	.owner = THIS_MODULE,
	315	},
	316	.probe = platform_pmic_gpio_probe,
	317	};
	318
	319	static int __init platform_pmic_gpio_init(void)
	320	{
	321	return platform_driver_register(&platform_pmic_gpio_driver);
	322	}
	323
	324	subsys_initcall(platform_pmic_gpio_init);
	325
	326	MODULE_AUTHOR("Alek Du <alek.du@intel.com>");
	327	MODULE_DESCRIPTION("Intel Moorestown PMIC GPIO driver");
	328	MODULE_LICENSE("GPL v2");