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2fa5b0f4 LJ |
1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2012 | |
3 | * | |
4 | * PM2301 power supply interface | |
5 | * | |
6 | * License terms: GNU General Public License (GPL), version 2 | |
7 | */ | |
8 | ||
9 | #ifndef PM2301_CHARGER_H | |
10 | #define PM2301_CHARGER_H | |
11 | ||
2fa5b0f4 LJ |
12 | /* Watchdog timeout constant */ |
13 | #define WD_TIMER 0x30 /* 4min */ | |
e07a5645 | 14 | #define WD_KICK_INTERVAL (30 * HZ) |
2fa5b0f4 | 15 | |
006f82d6 OC |
16 | #define PM2XXX_NUM_INT_REG 0x6 |
17 | ||
2fa5b0f4 LJ |
18 | /* Constant voltage/current */ |
19 | #define PM2XXX_CONST_CURR 0x0 | |
20 | #define PM2XXX_CONST_VOLT 0x1 | |
21 | ||
22 | /* Lowest charger voltage is 3.39V -> 0x4E */ | |
23 | #define LOW_VOLT_REG 0x4E | |
24 | ||
25 | #define PM2XXX_BATT_CTRL_REG1 0x00 | |
26 | #define PM2XXX_BATT_CTRL_REG2 0x01 | |
27 | #define PM2XXX_BATT_CTRL_REG3 0x02 | |
28 | #define PM2XXX_BATT_CTRL_REG4 0x03 | |
29 | #define PM2XXX_BATT_CTRL_REG5 0x04 | |
30 | #define PM2XXX_BATT_CTRL_REG6 0x05 | |
31 | #define PM2XXX_BATT_CTRL_REG7 0x06 | |
32 | #define PM2XXX_BATT_CTRL_REG8 0x07 | |
33 | #define PM2XXX_NTC_CTRL_REG1 0x08 | |
34 | #define PM2XXX_NTC_CTRL_REG2 0x09 | |
35 | #define PM2XXX_BATT_CTRL_REG9 0x0A | |
36 | #define PM2XXX_BATT_STAT_REG1 0x0B | |
37 | #define PM2XXX_INP_VOLT_VPWR2 0x11 | |
38 | #define PM2XXX_INP_DROP_VPWR2 0x13 | |
39 | #define PM2XXX_INP_VOLT_VPWR1 0x15 | |
40 | #define PM2XXX_INP_DROP_VPWR1 0x17 | |
41 | #define PM2XXX_INP_MODE_VPWR 0x18 | |
42 | #define PM2XXX_BATT_WD_KICK 0x70 | |
43 | #define PM2XXX_DEV_VER_STAT 0x0C | |
44 | #define PM2XXX_THERM_WARN_CTRL_REG 0x20 | |
45 | #define PM2XXX_BATT_DISC_REG 0x21 | |
46 | #define PM2XXX_BATT_LOW_LEV_COMP_REG 0x22 | |
47 | #define PM2XXX_BATT_LOW_LEV_VAL_REG 0x23 | |
48 | #define PM2XXX_I2C_PAD_CTRL_REG 0x24 | |
49 | #define PM2XXX_SW_CTRL_REG 0x26 | |
50 | #define PM2XXX_LED_CTRL_REG 0x28 | |
51 | ||
52 | #define PM2XXX_REG_INT1 0x40 | |
53 | #define PM2XXX_MASK_REG_INT1 0x50 | |
54 | #define PM2XXX_SRCE_REG_INT1 0x60 | |
55 | #define PM2XXX_REG_INT2 0x41 | |
56 | #define PM2XXX_MASK_REG_INT2 0x51 | |
57 | #define PM2XXX_SRCE_REG_INT2 0x61 | |
58 | #define PM2XXX_REG_INT3 0x42 | |
59 | #define PM2XXX_MASK_REG_INT3 0x52 | |
60 | #define PM2XXX_SRCE_REG_INT3 0x62 | |
61 | #define PM2XXX_REG_INT4 0x43 | |
62 | #define PM2XXX_MASK_REG_INT4 0x53 | |
63 | #define PM2XXX_SRCE_REG_INT4 0x63 | |
64 | #define PM2XXX_REG_INT5 0x44 | |
65 | #define PM2XXX_MASK_REG_INT5 0x54 | |
66 | #define PM2XXX_SRCE_REG_INT5 0x64 | |
67 | #define PM2XXX_REG_INT6 0x45 | |
68 | #define PM2XXX_MASK_REG_INT6 0x55 | |
69 | #define PM2XXX_SRCE_REG_INT6 0x65 | |
70 | ||
71 | #define VPWR_OVV 0x0 | |
72 | #define VSYSTEM_OVV 0x1 | |
73 | ||
74 | /* control Reg 1 */ | |
75 | #define PM2XXX_CH_RESUME_EN 0x1 | |
76 | #define PM2XXX_CH_RESUME_DIS 0x0 | |
77 | ||
78 | /* control Reg 2 */ | |
79 | #define PM2XXX_CH_AUTO_RESUME_EN 0X2 | |
80 | #define PM2XXX_CH_AUTO_RESUME_DIS 0X0 | |
81 | #define PM2XXX_CHARGER_ENA 0x4 | |
82 | #define PM2XXX_CHARGER_DIS 0x0 | |
83 | ||
84 | /* control Reg 3 */ | |
85 | #define PM2XXX_CH_WD_CC_PHASE_OFF 0x0 | |
86 | #define PM2XXX_CH_WD_CC_PHASE_5MIN 0x1 | |
87 | #define PM2XXX_CH_WD_CC_PHASE_10MIN 0x2 | |
88 | #define PM2XXX_CH_WD_CC_PHASE_30MIN 0x3 | |
89 | #define PM2XXX_CH_WD_CC_PHASE_60MIN 0x4 | |
90 | #define PM2XXX_CH_WD_CC_PHASE_120MIN 0x5 | |
91 | #define PM2XXX_CH_WD_CC_PHASE_240MIN 0x6 | |
92 | #define PM2XXX_CH_WD_CC_PHASE_360MIN 0x7 | |
93 | ||
94 | #define PM2XXX_CH_WD_CV_PHASE_OFF (0x0<<3) | |
95 | #define PM2XXX_CH_WD_CV_PHASE_5MIN (0x1<<3) | |
96 | #define PM2XXX_CH_WD_CV_PHASE_10MIN (0x2<<3) | |
97 | #define PM2XXX_CH_WD_CV_PHASE_30MIN (0x3<<3) | |
98 | #define PM2XXX_CH_WD_CV_PHASE_60MIN (0x4<<3) | |
99 | #define PM2XXX_CH_WD_CV_PHASE_120MIN (0x5<<3) | |
100 | #define PM2XXX_CH_WD_CV_PHASE_240MIN (0x6<<3) | |
101 | #define PM2XXX_CH_WD_CV_PHASE_360MIN (0x7<<3) | |
102 | ||
103 | /* control Reg 4 */ | |
104 | #define PM2XXX_CH_WD_PRECH_PHASE_OFF 0x0 | |
105 | #define PM2XXX_CH_WD_PRECH_PHASE_1MIN 0x1 | |
106 | #define PM2XXX_CH_WD_PRECH_PHASE_5MIN 0x2 | |
107 | #define PM2XXX_CH_WD_PRECH_PHASE_10MIN 0x3 | |
108 | #define PM2XXX_CH_WD_PRECH_PHASE_30MIN 0x4 | |
109 | #define PM2XXX_CH_WD_PRECH_PHASE_60MIN 0x5 | |
110 | #define PM2XXX_CH_WD_PRECH_PHASE_120MIN 0x6 | |
111 | #define PM2XXX_CH_WD_PRECH_PHASE_240MIN 0x7 | |
112 | ||
113 | /* control Reg 5 */ | |
114 | #define PM2XXX_CH_WD_AUTO_TIMEOUT_NONE 0x0 | |
115 | #define PM2XXX_CH_WD_AUTO_TIMEOUT_20MIN 0x1 | |
116 | ||
117 | /* control Reg 6 */ | |
118 | #define PM2XXX_DIR_CH_CC_CURRENT_MASK 0x0F | |
119 | #define PM2XXX_DIR_CH_CC_CURRENT_200MA 0x0 | |
120 | #define PM2XXX_DIR_CH_CC_CURRENT_400MA 0x2 | |
121 | #define PM2XXX_DIR_CH_CC_CURRENT_600MA 0x3 | |
122 | #define PM2XXX_DIR_CH_CC_CURRENT_800MA 0x4 | |
123 | #define PM2XXX_DIR_CH_CC_CURRENT_1000MA 0x5 | |
124 | #define PM2XXX_DIR_CH_CC_CURRENT_1200MA 0x6 | |
125 | #define PM2XXX_DIR_CH_CC_CURRENT_1400MA 0x7 | |
126 | #define PM2XXX_DIR_CH_CC_CURRENT_1600MA 0x8 | |
127 | #define PM2XXX_DIR_CH_CC_CURRENT_1800MA 0x9 | |
128 | #define PM2XXX_DIR_CH_CC_CURRENT_2000MA 0xA | |
129 | #define PM2XXX_DIR_CH_CC_CURRENT_2200MA 0xB | |
130 | #define PM2XXX_DIR_CH_CC_CURRENT_2400MA 0xC | |
131 | #define PM2XXX_DIR_CH_CC_CURRENT_2600MA 0xD | |
132 | #define PM2XXX_DIR_CH_CC_CURRENT_2800MA 0xE | |
133 | #define PM2XXX_DIR_CH_CC_CURRENT_3000MA 0xF | |
134 | ||
135 | #define PM2XXX_CH_PRECH_CURRENT_MASK 0x30 | |
136 | #define PM2XXX_CH_PRECH_CURRENT_25MA (0x0<<4) | |
137 | #define PM2XXX_CH_PRECH_CURRENT_50MA (0x1<<4) | |
138 | #define PM2XXX_CH_PRECH_CURRENT_75MA (0x2<<4) | |
139 | #define PM2XXX_CH_PRECH_CURRENT_100MA (0x3<<4) | |
140 | ||
141 | #define PM2XXX_CH_EOC_CURRENT_MASK 0xC0 | |
142 | #define PM2XXX_CH_EOC_CURRENT_100MA (0x0<<6) | |
143 | #define PM2XXX_CH_EOC_CURRENT_150MA (0x1<<6) | |
144 | #define PM2XXX_CH_EOC_CURRENT_300MA (0x2<<6) | |
145 | #define PM2XXX_CH_EOC_CURRENT_400MA (0x3<<6) | |
146 | ||
147 | /* control Reg 7 */ | |
148 | #define PM2XXX_CH_PRECH_VOL_2_5 0x0 | |
149 | #define PM2XXX_CH_PRECH_VOL_2_7 0x1 | |
150 | #define PM2XXX_CH_PRECH_VOL_2_9 0x2 | |
151 | #define PM2XXX_CH_PRECH_VOL_3_1 0x3 | |
152 | ||
153 | #define PM2XXX_CH_VRESUME_VOL_3_2 (0x0<<2) | |
154 | #define PM2XXX_CH_VRESUME_VOL_3_4 (0x1<<2) | |
155 | #define PM2XXX_CH_VRESUME_VOL_3_6 (0x2<<2) | |
156 | #define PM2XXX_CH_VRESUME_VOL_3_8 (0x3<<2) | |
157 | ||
158 | /* control Reg 8 */ | |
159 | #define PM2XXX_CH_VOLT_MASK 0x3F | |
160 | #define PM2XXX_CH_VOLT_3_5 0x0 | |
161 | #define PM2XXX_CH_VOLT_3_5225 0x1 | |
162 | #define PM2XXX_CH_VOLT_3_6 0x4 | |
163 | #define PM2XXX_CH_VOLT_3_7 0x8 | |
164 | #define PM2XXX_CH_VOLT_4_0 0x14 | |
165 | #define PM2XXX_CH_VOLT_4_175 0x1B | |
166 | #define PM2XXX_CH_VOLT_4_2 0x1C | |
167 | #define PM2XXX_CH_VOLT_4_275 0x1F | |
168 | #define PM2XXX_CH_VOLT_4_3 0x20 | |
169 | ||
170 | /*NTC control register 1*/ | |
171 | #define PM2XXX_BTEMP_HIGH_TH_45 0x0 | |
172 | #define PM2XXX_BTEMP_HIGH_TH_50 0x1 | |
173 | #define PM2XXX_BTEMP_HIGH_TH_55 0x2 | |
174 | #define PM2XXX_BTEMP_HIGH_TH_60 0x3 | |
175 | #define PM2XXX_BTEMP_HIGH_TH_65 0x4 | |
176 | ||
177 | #define PM2XXX_BTEMP_LOW_TH_N5 (0x0<<3) | |
178 | #define PM2XXX_BTEMP_LOW_TH_0 (0x1<<3) | |
179 | #define PM2XXX_BTEMP_LOW_TH_5 (0x2<<3) | |
180 | #define PM2XXX_BTEMP_LOW_TH_10 (0x3<<3) | |
181 | ||
182 | /*NTC control register 2*/ | |
183 | #define PM2XXX_NTC_BETA_COEFF_3477 0x0 | |
184 | #define PM2XXX_NTC_BETA_COEFF_3964 0x1 | |
185 | ||
186 | #define PM2XXX_NTC_RES_10K (0x0<<2) | |
187 | #define PM2XXX_NTC_RES_47K (0x1<<2) | |
188 | #define PM2XXX_NTC_RES_100K (0x2<<2) | |
189 | #define PM2XXX_NTC_RES_NO_NTC (0x3<<2) | |
190 | ||
191 | /* control Reg 9 */ | |
192 | #define PM2XXX_CH_CC_MODEDROP_EN 1 | |
193 | #define PM2XXX_CH_CC_MODEDROP_DIS 0 | |
194 | ||
195 | #define PM2XXX_CH_CC_REDUCED_CURRENT_100MA (0x0<<1) | |
196 | #define PM2XXX_CH_CC_REDUCED_CURRENT_200MA (0x1<<1) | |
197 | #define PM2XXX_CH_CC_REDUCED_CURRENT_400MA (0x2<<1) | |
198 | #define PM2XXX_CH_CC_REDUCED_CURRENT_IDENT (0x3<<1) | |
199 | ||
200 | #define PM2XXX_CHARCHING_INFO_DIS (0<<3) | |
201 | #define PM2XXX_CHARCHING_INFO_EN (1<<3) | |
202 | ||
203 | #define PM2XXX_CH_150MV_DROP_300MV (0<<4) | |
204 | #define PM2XXX_CH_150MV_DROP_150MV (1<<4) | |
205 | ||
206 | ||
207 | /* charger status register */ | |
208 | #define PM2XXX_CHG_STATUS_OFF 0x0 | |
209 | #define PM2XXX_CHG_STATUS_ON 0x1 | |
210 | #define PM2XXX_CHG_STATUS_FULL 0x2 | |
211 | #define PM2XXX_CHG_STATUS_ERR 0x3 | |
212 | #define PM2XXX_CHG_STATUS_WAIT 0x4 | |
213 | #define PM2XXX_CHG_STATUS_NOBAT 0x5 | |
214 | ||
215 | /* Input charger voltage VPWR2 */ | |
216 | #define PM2XXX_VPWR2_OVV_6_0 0x0 | |
217 | #define PM2XXX_VPWR2_OVV_6_3 0x1 | |
218 | #define PM2XXX_VPWR2_OVV_10 0x2 | |
219 | #define PM2XXX_VPWR2_OVV_NONE 0x3 | |
220 | ||
006f82d6 OC |
221 | /* Input charger drop VPWR2 */ |
222 | #define PM2XXX_VPWR2_HW_OPT_EN (0x1<<4) | |
223 | #define PM2XXX_VPWR2_HW_OPT_DIS (0x0<<4) | |
224 | ||
225 | #define PM2XXX_VPWR2_VALID_EN (0x1<<3) | |
226 | #define PM2XXX_VPWR2_VALID_DIS (0x0<<3) | |
227 | ||
228 | #define PM2XXX_VPWR2_DROP_EN (0x1<<2) | |
229 | #define PM2XXX_VPWR2_DROP_DIS (0x0<<2) | |
230 | ||
2fa5b0f4 LJ |
231 | /* Input charger voltage VPWR1 */ |
232 | #define PM2XXX_VPWR1_OVV_6_0 0x0 | |
233 | #define PM2XXX_VPWR1_OVV_6_3 0x1 | |
234 | #define PM2XXX_VPWR1_OVV_10 0x2 | |
235 | #define PM2XXX_VPWR1_OVV_NONE 0x3 | |
236 | ||
006f82d6 OC |
237 | /* Input charger drop VPWR1 */ |
238 | #define PM2XXX_VPWR1_HW_OPT_EN (0x1<<4) | |
239 | #define PM2XXX_VPWR1_HW_OPT_DIS (0x0<<4) | |
240 | ||
241 | #define PM2XXX_VPWR1_VALID_EN (0x1<<3) | |
242 | #define PM2XXX_VPWR1_VALID_DIS (0x0<<3) | |
243 | ||
244 | #define PM2XXX_VPWR1_DROP_EN (0x1<<2) | |
245 | #define PM2XXX_VPWR1_DROP_DIS (0x0<<2) | |
246 | ||
2fa5b0f4 LJ |
247 | /* Battery low level comparator control register */ |
248 | #define PM2XXX_VBAT_LOW_MONITORING_DIS 0x0 | |
249 | #define PM2XXX_VBAT_LOW_MONITORING_ENA 0x1 | |
250 | ||
251 | /* Battery low level value control register */ | |
252 | #define PM2XXX_VBAT_LOW_LEVEL_2_3 0x0 | |
253 | #define PM2XXX_VBAT_LOW_LEVEL_2_4 0x1 | |
254 | #define PM2XXX_VBAT_LOW_LEVEL_2_5 0x2 | |
255 | #define PM2XXX_VBAT_LOW_LEVEL_2_6 0x3 | |
256 | #define PM2XXX_VBAT_LOW_LEVEL_2_7 0x4 | |
257 | #define PM2XXX_VBAT_LOW_LEVEL_2_8 0x5 | |
258 | #define PM2XXX_VBAT_LOW_LEVEL_2_9 0x6 | |
259 | #define PM2XXX_VBAT_LOW_LEVEL_3_0 0x7 | |
260 | #define PM2XXX_VBAT_LOW_LEVEL_3_1 0x8 | |
261 | #define PM2XXX_VBAT_LOW_LEVEL_3_2 0x9 | |
262 | #define PM2XXX_VBAT_LOW_LEVEL_3_3 0xA | |
263 | #define PM2XXX_VBAT_LOW_LEVEL_3_4 0xB | |
264 | #define PM2XXX_VBAT_LOW_LEVEL_3_5 0xC | |
265 | #define PM2XXX_VBAT_LOW_LEVEL_3_6 0xD | |
266 | #define PM2XXX_VBAT_LOW_LEVEL_3_7 0xE | |
267 | #define PM2XXX_VBAT_LOW_LEVEL_3_8 0xF | |
268 | #define PM2XXX_VBAT_LOW_LEVEL_3_9 0x10 | |
269 | #define PM2XXX_VBAT_LOW_LEVEL_4_0 0x11 | |
270 | #define PM2XXX_VBAT_LOW_LEVEL_4_1 0x12 | |
271 | #define PM2XXX_VBAT_LOW_LEVEL_4_2 0x13 | |
272 | ||
273 | /* SW CTRL */ | |
274 | #define PM2XXX_SWCTRL_HW 0x0 | |
275 | #define PM2XXX_SWCTRL_SW 0x1 | |
276 | ||
277 | ||
278 | /* LED Driver Control */ | |
279 | #define PM2XXX_LED_CURRENT_MASK 0x0C | |
280 | #define PM2XXX_LED_CURRENT_2_5MA (0X0<<2) | |
281 | #define PM2XXX_LED_CURRENT_1MA (0X1<<2) | |
282 | #define PM2XXX_LED_CURRENT_5MA (0X2<<2) | |
283 | #define PM2XXX_LED_CURRENT_10MA (0X3<<2) | |
284 | ||
285 | #define PM2XXX_LED_SELECT_MASK 0x02 | |
286 | #define PM2XXX_LED_SELECT_EN (0X0<<1) | |
287 | #define PM2XXX_LED_SELECT_DIS (0X1<<1) | |
288 | ||
289 | #define PM2XXX_ANTI_OVERSHOOT_MASK 0x01 | |
290 | #define PM2XXX_ANTI_OVERSHOOT_DIS 0X0 | |
291 | #define PM2XXX_ANTI_OVERSHOOT_EN 0X1 | |
292 | ||
293 | enum pm2xxx_reg_int1 { | |
294 | PM2XXX_INT1_ITVBATDISCONNECT = 0x02, | |
295 | PM2XXX_INT1_ITVBATLOWR = 0x04, | |
296 | PM2XXX_INT1_ITVBATLOWF = 0x08, | |
297 | }; | |
298 | ||
299 | enum pm2xxx_mask_reg_int1 { | |
300 | PM2XXX_INT1_M_ITVBATDISCONNECT = 0x02, | |
301 | PM2XXX_INT1_M_ITVBATLOWR = 0x04, | |
302 | PM2XXX_INT1_M_ITVBATLOWF = 0x08, | |
303 | }; | |
304 | ||
305 | enum pm2xxx_source_reg_int1 { | |
306 | PM2XXX_INT1_S_ITVBATDISCONNECT = 0x02, | |
307 | PM2XXX_INT1_S_ITVBATLOWR = 0x04, | |
308 | PM2XXX_INT1_S_ITVBATLOWF = 0x08, | |
309 | }; | |
310 | ||
311 | enum pm2xxx_reg_int2 { | |
312 | PM2XXX_INT2_ITVPWR2PLUG = 0x01, | |
313 | PM2XXX_INT2_ITVPWR2UNPLUG = 0x02, | |
314 | PM2XXX_INT2_ITVPWR1PLUG = 0x04, | |
315 | PM2XXX_INT2_ITVPWR1UNPLUG = 0x08, | |
316 | }; | |
317 | ||
318 | enum pm2xxx_mask_reg_int2 { | |
319 | PM2XXX_INT2_M_ITVPWR2PLUG = 0x01, | |
320 | PM2XXX_INT2_M_ITVPWR2UNPLUG = 0x02, | |
321 | PM2XXX_INT2_M_ITVPWR1PLUG = 0x04, | |
322 | PM2XXX_INT2_M_ITVPWR1UNPLUG = 0x08, | |
323 | }; | |
324 | ||
325 | enum pm2xxx_source_reg_int2 { | |
326 | PM2XXX_INT2_S_ITVPWR2PLUG = 0x03, | |
327 | PM2XXX_INT2_S_ITVPWR1PLUG = 0x0c, | |
328 | }; | |
329 | ||
330 | enum pm2xxx_reg_int3 { | |
331 | PM2XXX_INT3_ITCHPRECHARGEWD = 0x01, | |
332 | PM2XXX_INT3_ITCHCCWD = 0x02, | |
333 | PM2XXX_INT3_ITCHCVWD = 0x04, | |
334 | PM2XXX_INT3_ITAUTOTIMEOUTWD = 0x08, | |
335 | }; | |
336 | ||
337 | enum pm2xxx_mask_reg_int3 { | |
338 | PM2XXX_INT3_M_ITCHPRECHARGEWD = 0x01, | |
339 | PM2XXX_INT3_M_ITCHCCWD = 0x02, | |
340 | PM2XXX_INT3_M_ITCHCVWD = 0x04, | |
341 | PM2XXX_INT3_M_ITAUTOTIMEOUTWD = 0x08, | |
342 | }; | |
343 | ||
344 | enum pm2xxx_source_reg_int3 { | |
345 | PM2XXX_INT3_S_ITCHPRECHARGEWD = 0x01, | |
346 | PM2XXX_INT3_S_ITCHCCWD = 0x02, | |
347 | PM2XXX_INT3_S_ITCHCVWD = 0x04, | |
348 | PM2XXX_INT3_S_ITAUTOTIMEOUTWD = 0x08, | |
349 | }; | |
350 | ||
351 | enum pm2xxx_reg_int4 { | |
352 | PM2XXX_INT4_ITBATTEMPCOLD = 0x01, | |
353 | PM2XXX_INT4_ITBATTEMPHOT = 0x02, | |
354 | PM2XXX_INT4_ITVPWR2OVV = 0x04, | |
355 | PM2XXX_INT4_ITVPWR1OVV = 0x08, | |
356 | PM2XXX_INT4_ITCHARGINGON = 0x10, | |
357 | PM2XXX_INT4_ITVRESUME = 0x20, | |
358 | PM2XXX_INT4_ITBATTFULL = 0x40, | |
359 | PM2XXX_INT4_ITCVPHASE = 0x80, | |
360 | }; | |
361 | ||
362 | enum pm2xxx_mask_reg_int4 { | |
363 | PM2XXX_INT4_M_ITBATTEMPCOLD = 0x01, | |
364 | PM2XXX_INT4_M_ITBATTEMPHOT = 0x02, | |
365 | PM2XXX_INT4_M_ITVPWR2OVV = 0x04, | |
366 | PM2XXX_INT4_M_ITVPWR1OVV = 0x08, | |
367 | PM2XXX_INT4_M_ITCHARGINGON = 0x10, | |
368 | PM2XXX_INT4_M_ITVRESUME = 0x20, | |
369 | PM2XXX_INT4_M_ITBATTFULL = 0x40, | |
370 | PM2XXX_INT4_M_ITCVPHASE = 0x80, | |
371 | }; | |
372 | ||
373 | enum pm2xxx_source_reg_int4 { | |
374 | PM2XXX_INT4_S_ITBATTEMPCOLD = 0x01, | |
375 | PM2XXX_INT4_S_ITBATTEMPHOT = 0x02, | |
376 | PM2XXX_INT4_S_ITVPWR2OVV = 0x04, | |
377 | PM2XXX_INT4_S_ITVPWR1OVV = 0x08, | |
378 | PM2XXX_INT4_S_ITCHARGINGON = 0x10, | |
379 | PM2XXX_INT4_S_ITVRESUME = 0x20, | |
380 | PM2XXX_INT4_S_ITBATTFULL = 0x40, | |
381 | PM2XXX_INT4_S_ITCVPHASE = 0x80, | |
382 | }; | |
383 | ||
384 | enum pm2xxx_reg_int5 { | |
385 | PM2XXX_INT5_ITTHERMALSHUTDOWNRISE = 0x01, | |
386 | PM2XXX_INT5_ITTHERMALSHUTDOWNFALL = 0x02, | |
387 | PM2XXX_INT5_ITTHERMALWARNINGRISE = 0x04, | |
388 | PM2XXX_INT5_ITTHERMALWARNINGFALL = 0x08, | |
389 | PM2XXX_INT5_ITVSYSTEMOVV = 0x10, | |
390 | }; | |
391 | ||
392 | enum pm2xxx_mask_reg_int5 { | |
393 | PM2XXX_INT5_M_ITTHERMALSHUTDOWNRISE = 0x01, | |
394 | PM2XXX_INT5_M_ITTHERMALSHUTDOWNFALL = 0x02, | |
395 | PM2XXX_INT5_M_ITTHERMALWARNINGRISE = 0x04, | |
396 | PM2XXX_INT5_M_ITTHERMALWARNINGFALL = 0x08, | |
397 | PM2XXX_INT5_M_ITVSYSTEMOVV = 0x10, | |
398 | }; | |
399 | ||
400 | enum pm2xxx_source_reg_int5 { | |
401 | PM2XXX_INT5_S_ITTHERMALSHUTDOWNRISE = 0x01, | |
402 | PM2XXX_INT5_S_ITTHERMALSHUTDOWNFALL = 0x02, | |
403 | PM2XXX_INT5_S_ITTHERMALWARNINGRISE = 0x04, | |
404 | PM2XXX_INT5_S_ITTHERMALWARNINGFALL = 0x08, | |
405 | PM2XXX_INT5_S_ITVSYSTEMOVV = 0x10, | |
406 | }; | |
407 | ||
408 | enum pm2xxx_reg_int6 { | |
409 | PM2XXX_INT6_ITVPWR2DROP = 0x01, | |
410 | PM2XXX_INT6_ITVPWR1DROP = 0x02, | |
411 | PM2XXX_INT6_ITVPWR2VALIDRISE = 0x04, | |
412 | PM2XXX_INT6_ITVPWR2VALIDFALL = 0x08, | |
413 | PM2XXX_INT6_ITVPWR1VALIDRISE = 0x10, | |
414 | PM2XXX_INT6_ITVPWR1VALIDFALL = 0x20, | |
415 | }; | |
416 | ||
417 | enum pm2xxx_mask_reg_int6 { | |
418 | PM2XXX_INT6_M_ITVPWR2DROP = 0x01, | |
419 | PM2XXX_INT6_M_ITVPWR1DROP = 0x02, | |
420 | PM2XXX_INT6_M_ITVPWR2VALIDRISE = 0x04, | |
421 | PM2XXX_INT6_M_ITVPWR2VALIDFALL = 0x08, | |
422 | PM2XXX_INT6_M_ITVPWR1VALIDRISE = 0x10, | |
423 | PM2XXX_INT6_M_ITVPWR1VALIDFALL = 0x20, | |
424 | }; | |
425 | ||
426 | enum pm2xxx_source_reg_int6 { | |
427 | PM2XXX_INT6_S_ITVPWR2DROP = 0x01, | |
428 | PM2XXX_INT6_S_ITVPWR1DROP = 0x02, | |
429 | PM2XXX_INT6_S_ITVPWR2VALIDRISE = 0x04, | |
430 | PM2XXX_INT6_S_ITVPWR2VALIDFALL = 0x08, | |
431 | PM2XXX_INT6_S_ITVPWR1VALIDRISE = 0x10, | |
432 | PM2XXX_INT6_S_ITVPWR1VALIDFALL = 0x20, | |
433 | }; | |
434 | ||
435 | struct pm2xxx_charger_info { | |
436 | int charger_connected; | |
437 | int charger_online; | |
2fa5b0f4 LJ |
438 | int cv_active; |
439 | bool wd_expired; | |
440 | }; | |
441 | ||
442 | struct pm2xxx_charger_event_flags { | |
443 | bool mainextchnotok; | |
444 | bool main_thermal_prot; | |
445 | bool ovv; | |
446 | bool chgwdexp; | |
447 | }; | |
448 | ||
006f82d6 OC |
449 | struct pm2xxx_interrupts { |
450 | u8 reg[PM2XXX_NUM_INT_REG]; | |
451 | int (*handler[PM2XXX_NUM_INT_REG])(void *, int); | |
452 | }; | |
453 | ||
2fa5b0f4 LJ |
454 | struct pm2xxx_config { |
455 | struct i2c_client *pm2xxx_i2c; | |
456 | struct i2c_device_id *pm2xxx_id; | |
457 | }; | |
458 | ||
459 | struct pm2xxx_irq { | |
460 | char *name; | |
461 | irqreturn_t (*isr)(int irq, void *data); | |
462 | }; | |
463 | ||
464 | struct pm2xxx_charger { | |
465 | struct device *dev; | |
466 | u8 chip_id; | |
467 | bool vddadc_en_ac; | |
468 | struct pm2xxx_config config; | |
469 | bool ac_conn; | |
470 | unsigned int gpio_irq; | |
471 | int vbat; | |
472 | int old_vbat; | |
473 | int failure_case; | |
474 | int failure_input_ovv; | |
3988043b | 475 | unsigned int lpn_pin; |
006f82d6 | 476 | struct pm2xxx_interrupts *pm2_int; |
2fa5b0f4 LJ |
477 | struct regulator *regu; |
478 | struct pm2xxx_bm_data *bat; | |
479 | struct mutex lock; | |
480 | struct ab8500 *parent; | |
481 | struct pm2xxx_charger_info ac; | |
482 | struct pm2xxx_charger_platform_data *pdata; | |
483 | struct workqueue_struct *charger_wq; | |
484 | struct delayed_work check_vbat_work; | |
485 | struct work_struct ac_work; | |
486 | struct work_struct check_main_thermal_prot_work; | |
789ca7b4 | 487 | struct delayed_work check_hw_failure_work; |
2fa5b0f4 | 488 | struct ux500_charger ac_chg; |
297d716f | 489 | struct power_supply_desc ac_chg_desc; |
2fa5b0f4 LJ |
490 | struct pm2xxx_charger_event_flags flags; |
491 | }; | |
492 | ||
493 | #endif /* PM2301_CHARGER_H */ |