Commit | Line | Data |
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2d281d81 JP |
1 | /* |
2 | * Intel Running Average Power Limit (RAPL) Driver | |
3 | * Copyright (c) 2013, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc. | |
16 | * | |
17 | */ | |
18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/list.h> | |
23 | #include <linux/types.h> | |
24 | #include <linux/device.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/log2.h> | |
27 | #include <linux/bitmap.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/sysfs.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/powercap.h> | |
3c2c0845 | 32 | #include <asm/iosf_mbi.h> |
2d281d81 JP |
33 | |
34 | #include <asm/processor.h> | |
35 | #include <asm/cpu_device_id.h> | |
36 | ||
37 | /* bitmasks for RAPL MSRs, used by primitive access functions */ | |
38 | #define ENERGY_STATUS_MASK 0xffffffff | |
39 | ||
40 | #define POWER_LIMIT1_MASK 0x7FFF | |
41 | #define POWER_LIMIT1_ENABLE BIT(15) | |
42 | #define POWER_LIMIT1_CLAMP BIT(16) | |
43 | ||
44 | #define POWER_LIMIT2_MASK (0x7FFFULL<<32) | |
45 | #define POWER_LIMIT2_ENABLE BIT_ULL(47) | |
46 | #define POWER_LIMIT2_CLAMP BIT_ULL(48) | |
47 | #define POWER_PACKAGE_LOCK BIT_ULL(63) | |
48 | #define POWER_PP_LOCK BIT(31) | |
49 | ||
50 | #define TIME_WINDOW1_MASK (0x7FULL<<17) | |
51 | #define TIME_WINDOW2_MASK (0x7FULL<<49) | |
52 | ||
53 | #define POWER_UNIT_OFFSET 0 | |
54 | #define POWER_UNIT_MASK 0x0F | |
55 | ||
56 | #define ENERGY_UNIT_OFFSET 0x08 | |
57 | #define ENERGY_UNIT_MASK 0x1F00 | |
58 | ||
59 | #define TIME_UNIT_OFFSET 0x10 | |
60 | #define TIME_UNIT_MASK 0xF0000 | |
61 | ||
62 | #define POWER_INFO_MAX_MASK (0x7fffULL<<32) | |
63 | #define POWER_INFO_MIN_MASK (0x7fffULL<<16) | |
64 | #define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48) | |
65 | #define POWER_INFO_THERMAL_SPEC_MASK 0x7fff | |
66 | ||
67 | #define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff | |
68 | #define PP_POLICY_MASK 0x1F | |
69 | ||
70 | /* Non HW constants */ | |
71 | #define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */ | |
72 | #define RAPL_PRIMITIVE_DUMMY BIT(2) | |
73 | ||
2d281d81 JP |
74 | #define TIME_WINDOW_MAX_MSEC 40000 |
75 | #define TIME_WINDOW_MIN_MSEC 250 | |
d474a4d3 | 76 | #define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */ |
2d281d81 JP |
77 | enum unit_type { |
78 | ARBITRARY_UNIT, /* no translation */ | |
79 | POWER_UNIT, | |
80 | ENERGY_UNIT, | |
81 | TIME_UNIT, | |
82 | }; | |
83 | ||
84 | enum rapl_domain_type { | |
85 | RAPL_DOMAIN_PACKAGE, /* entire package/socket */ | |
86 | RAPL_DOMAIN_PP0, /* core power plane */ | |
87 | RAPL_DOMAIN_PP1, /* graphics uncore */ | |
88 | RAPL_DOMAIN_DRAM,/* DRAM control_type */ | |
89 | RAPL_DOMAIN_MAX, | |
90 | }; | |
91 | ||
92 | enum rapl_domain_msr_id { | |
93 | RAPL_DOMAIN_MSR_LIMIT, | |
94 | RAPL_DOMAIN_MSR_STATUS, | |
95 | RAPL_DOMAIN_MSR_PERF, | |
96 | RAPL_DOMAIN_MSR_POLICY, | |
97 | RAPL_DOMAIN_MSR_INFO, | |
98 | RAPL_DOMAIN_MSR_MAX, | |
99 | }; | |
100 | ||
101 | /* per domain data, some are optional */ | |
102 | enum rapl_primitives { | |
103 | ENERGY_COUNTER, | |
104 | POWER_LIMIT1, | |
105 | POWER_LIMIT2, | |
106 | FW_LOCK, | |
107 | ||
108 | PL1_ENABLE, /* power limit 1, aka long term */ | |
109 | PL1_CLAMP, /* allow frequency to go below OS request */ | |
110 | PL2_ENABLE, /* power limit 2, aka short term, instantaneous */ | |
111 | PL2_CLAMP, | |
112 | ||
113 | TIME_WINDOW1, /* long term */ | |
114 | TIME_WINDOW2, /* short term */ | |
115 | THERMAL_SPEC_POWER, | |
116 | MAX_POWER, | |
117 | ||
118 | MIN_POWER, | |
119 | MAX_TIME_WINDOW, | |
120 | THROTTLED_TIME, | |
121 | PRIORITY_LEVEL, | |
122 | ||
123 | /* below are not raw primitive data */ | |
124 | AVERAGE_POWER, | |
125 | NR_RAPL_PRIMITIVES, | |
126 | }; | |
127 | ||
128 | #define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2) | |
129 | ||
130 | /* Can be expanded to include events, etc.*/ | |
131 | struct rapl_domain_data { | |
132 | u64 primitives[NR_RAPL_PRIMITIVES]; | |
133 | unsigned long timestamp; | |
134 | }; | |
135 | ||
f14a1396 JP |
136 | struct msrl_action { |
137 | u32 msr_no; | |
138 | u64 clear_mask; | |
139 | u64 set_mask; | |
140 | int err; | |
141 | }; | |
2d281d81 JP |
142 | |
143 | #define DOMAIN_STATE_INACTIVE BIT(0) | |
144 | #define DOMAIN_STATE_POWER_LIMIT_SET BIT(1) | |
145 | #define DOMAIN_STATE_BIOS_LOCKED BIT(2) | |
146 | ||
147 | #define NR_POWER_LIMITS (2) | |
148 | struct rapl_power_limit { | |
149 | struct powercap_zone_constraint *constraint; | |
150 | int prim_id; /* primitive ID used to enable */ | |
151 | struct rapl_domain *domain; | |
152 | const char *name; | |
153 | }; | |
154 | ||
155 | static const char pl1_name[] = "long_term"; | |
156 | static const char pl2_name[] = "short_term"; | |
157 | ||
309557f5 | 158 | struct rapl_package; |
2d281d81 JP |
159 | struct rapl_domain { |
160 | const char *name; | |
161 | enum rapl_domain_type id; | |
162 | int msrs[RAPL_DOMAIN_MSR_MAX]; | |
163 | struct powercap_zone power_zone; | |
164 | struct rapl_domain_data rdd; | |
165 | struct rapl_power_limit rpl[NR_POWER_LIMITS]; | |
166 | u64 attr_map; /* track capabilities */ | |
167 | unsigned int state; | |
d474a4d3 | 168 | unsigned int domain_energy_unit; |
309557f5 | 169 | struct rapl_package *rp; |
2d281d81 JP |
170 | }; |
171 | #define power_zone_to_rapl_domain(_zone) \ | |
172 | container_of(_zone, struct rapl_domain, power_zone) | |
173 | ||
174 | ||
175 | /* Each physical package contains multiple domains, these are the common | |
176 | * data across RAPL domains within a package. | |
177 | */ | |
178 | struct rapl_package { | |
179 | unsigned int id; /* physical package/socket id */ | |
180 | unsigned int nr_domains; | |
181 | unsigned long domain_map; /* bit map of active domains */ | |
3c2c0845 JP |
182 | unsigned int power_unit; |
183 | unsigned int energy_unit; | |
184 | unsigned int time_unit; | |
2d281d81 JP |
185 | struct rapl_domain *domains; /* array of domains, sized at runtime */ |
186 | struct powercap_zone *power_zone; /* keep track of parent zone */ | |
187 | int nr_cpus; /* active cpus on the package, topology info is lost during | |
188 | * cpu hotplug. so we have to track ourselves. | |
189 | */ | |
190 | unsigned long power_limit_irq; /* keep track of package power limit | |
191 | * notify interrupt enable status. | |
192 | */ | |
193 | struct list_head plist; | |
323ee64a | 194 | int lead_cpu; /* one active cpu per package for access */ |
2d281d81 | 195 | }; |
087e9cba JP |
196 | |
197 | struct rapl_defaults { | |
51b63409 | 198 | u8 floor_freq_reg_addr; |
087e9cba JP |
199 | int (*check_unit)(struct rapl_package *rp, int cpu); |
200 | void (*set_floor_freq)(struct rapl_domain *rd, bool mode); | |
201 | u64 (*compute_time_window)(struct rapl_package *rp, u64 val, | |
202 | bool to_raw); | |
d474a4d3 | 203 | unsigned int dram_domain_energy_unit; |
087e9cba JP |
204 | }; |
205 | static struct rapl_defaults *rapl_defaults; | |
206 | ||
3c2c0845 | 207 | /* Sideband MBI registers */ |
51b63409 AT |
208 | #define IOSF_CPU_POWER_BUDGET_CTL_BYT (0x2) |
209 | #define IOSF_CPU_POWER_BUDGET_CTL_TNG (0xdf) | |
3c2c0845 | 210 | |
2d281d81 JP |
211 | #define PACKAGE_PLN_INT_SAVED BIT(0) |
212 | #define MAX_PRIM_NAME (32) | |
213 | ||
214 | /* per domain data. used to describe individual knobs such that access function | |
215 | * can be consolidated into one instead of many inline functions. | |
216 | */ | |
217 | struct rapl_primitive_info { | |
218 | const char *name; | |
219 | u64 mask; | |
220 | int shift; | |
221 | enum rapl_domain_msr_id id; | |
222 | enum unit_type unit; | |
223 | u32 flag; | |
224 | }; | |
225 | ||
226 | #define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \ | |
227 | .name = #p, \ | |
228 | .mask = m, \ | |
229 | .shift = s, \ | |
230 | .id = i, \ | |
231 | .unit = u, \ | |
232 | .flag = f \ | |
233 | } | |
234 | ||
235 | static void rapl_init_domains(struct rapl_package *rp); | |
236 | static int rapl_read_data_raw(struct rapl_domain *rd, | |
237 | enum rapl_primitives prim, | |
238 | bool xlate, u64 *data); | |
239 | static int rapl_write_data_raw(struct rapl_domain *rd, | |
240 | enum rapl_primitives prim, | |
241 | unsigned long long value); | |
309557f5 | 242 | static u64 rapl_unit_xlate(struct rapl_domain *rd, |
d474a4d3 | 243 | enum unit_type type, u64 value, |
2d281d81 | 244 | int to_raw); |
309557f5 | 245 | static void package_power_limit_irq_save(struct rapl_package *rp); |
2d281d81 JP |
246 | |
247 | static LIST_HEAD(rapl_packages); /* guarded by CPU hotplug lock */ | |
248 | ||
249 | static const char * const rapl_domain_names[] = { | |
250 | "package", | |
251 | "core", | |
252 | "uncore", | |
253 | "dram", | |
254 | }; | |
255 | ||
256 | static struct powercap_control_type *control_type; /* PowerCap Controller */ | |
257 | ||
258 | /* caller to ensure CPU hotplug lock is held */ | |
259 | static struct rapl_package *find_package_by_id(int id) | |
260 | { | |
261 | struct rapl_package *rp; | |
262 | ||
263 | list_for_each_entry(rp, &rapl_packages, plist) { | |
264 | if (rp->id == id) | |
265 | return rp; | |
266 | } | |
267 | ||
268 | return NULL; | |
269 | } | |
270 | ||
2d281d81 JP |
271 | /* caller must hold cpu hotplug lock */ |
272 | static void rapl_cleanup_data(void) | |
273 | { | |
274 | struct rapl_package *p, *tmp; | |
275 | ||
276 | list_for_each_entry_safe(p, tmp, &rapl_packages, plist) { | |
277 | kfree(p->domains); | |
278 | list_del(&p->plist); | |
279 | kfree(p); | |
280 | } | |
281 | } | |
282 | ||
283 | static int get_energy_counter(struct powercap_zone *power_zone, u64 *energy_raw) | |
284 | { | |
285 | struct rapl_domain *rd; | |
286 | u64 energy_now; | |
287 | ||
288 | /* prevent CPU hotplug, make sure the RAPL domain does not go | |
289 | * away while reading the counter. | |
290 | */ | |
291 | get_online_cpus(); | |
292 | rd = power_zone_to_rapl_domain(power_zone); | |
293 | ||
294 | if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now)) { | |
295 | *energy_raw = energy_now; | |
296 | put_online_cpus(); | |
297 | ||
298 | return 0; | |
299 | } | |
300 | put_online_cpus(); | |
301 | ||
302 | return -EIO; | |
303 | } | |
304 | ||
305 | static int get_max_energy_counter(struct powercap_zone *pcd_dev, u64 *energy) | |
306 | { | |
d474a4d3 JP |
307 | struct rapl_domain *rd = power_zone_to_rapl_domain(pcd_dev); |
308 | ||
309557f5 | 309 | *energy = rapl_unit_xlate(rd, ENERGY_UNIT, ENERGY_STATUS_MASK, 0); |
2d281d81 JP |
310 | return 0; |
311 | } | |
312 | ||
313 | static int release_zone(struct powercap_zone *power_zone) | |
314 | { | |
315 | struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); | |
309557f5 | 316 | struct rapl_package *rp = rd->rp; |
2d281d81 JP |
317 | |
318 | /* package zone is the last zone of a package, we can free | |
319 | * memory here since all children has been unregistered. | |
320 | */ | |
321 | if (rd->id == RAPL_DOMAIN_PACKAGE) { | |
2d281d81 JP |
322 | kfree(rd); |
323 | rp->domains = NULL; | |
324 | } | |
325 | ||
326 | return 0; | |
327 | ||
328 | } | |
329 | ||
330 | static int find_nr_power_limit(struct rapl_domain *rd) | |
331 | { | |
332 | int i; | |
333 | ||
334 | for (i = 0; i < NR_POWER_LIMITS; i++) { | |
335 | if (rd->rpl[i].name == NULL) | |
336 | break; | |
337 | } | |
338 | ||
339 | return i; | |
340 | } | |
341 | ||
342 | static int set_domain_enable(struct powercap_zone *power_zone, bool mode) | |
343 | { | |
344 | struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); | |
2d281d81 JP |
345 | |
346 | if (rd->state & DOMAIN_STATE_BIOS_LOCKED) | |
347 | return -EACCES; | |
3c2c0845 | 348 | |
2d281d81 | 349 | get_online_cpus(); |
2d281d81 | 350 | rapl_write_data_raw(rd, PL1_ENABLE, mode); |
51b63409 AT |
351 | if (rapl_defaults->set_floor_freq) |
352 | rapl_defaults->set_floor_freq(rd, mode); | |
2d281d81 JP |
353 | put_online_cpus(); |
354 | ||
355 | return 0; | |
356 | } | |
357 | ||
358 | static int get_domain_enable(struct powercap_zone *power_zone, bool *mode) | |
359 | { | |
360 | struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); | |
361 | u64 val; | |
362 | ||
363 | if (rd->state & DOMAIN_STATE_BIOS_LOCKED) { | |
364 | *mode = false; | |
365 | return 0; | |
366 | } | |
367 | get_online_cpus(); | |
368 | if (rapl_read_data_raw(rd, PL1_ENABLE, true, &val)) { | |
369 | put_online_cpus(); | |
370 | return -EIO; | |
371 | } | |
372 | *mode = val; | |
373 | put_online_cpus(); | |
374 | ||
375 | return 0; | |
376 | } | |
377 | ||
378 | /* per RAPL domain ops, in the order of rapl_domain_type */ | |
600c395b | 379 | static const struct powercap_zone_ops zone_ops[] = { |
2d281d81 JP |
380 | /* RAPL_DOMAIN_PACKAGE */ |
381 | { | |
382 | .get_energy_uj = get_energy_counter, | |
383 | .get_max_energy_range_uj = get_max_energy_counter, | |
384 | .release = release_zone, | |
385 | .set_enable = set_domain_enable, | |
386 | .get_enable = get_domain_enable, | |
387 | }, | |
388 | /* RAPL_DOMAIN_PP0 */ | |
389 | { | |
390 | .get_energy_uj = get_energy_counter, | |
391 | .get_max_energy_range_uj = get_max_energy_counter, | |
392 | .release = release_zone, | |
393 | .set_enable = set_domain_enable, | |
394 | .get_enable = get_domain_enable, | |
395 | }, | |
396 | /* RAPL_DOMAIN_PP1 */ | |
397 | { | |
398 | .get_energy_uj = get_energy_counter, | |
399 | .get_max_energy_range_uj = get_max_energy_counter, | |
400 | .release = release_zone, | |
401 | .set_enable = set_domain_enable, | |
402 | .get_enable = get_domain_enable, | |
403 | }, | |
404 | /* RAPL_DOMAIN_DRAM */ | |
405 | { | |
406 | .get_energy_uj = get_energy_counter, | |
407 | .get_max_energy_range_uj = get_max_energy_counter, | |
408 | .release = release_zone, | |
409 | .set_enable = set_domain_enable, | |
410 | .get_enable = get_domain_enable, | |
411 | }, | |
412 | }; | |
413 | ||
414 | static int set_power_limit(struct powercap_zone *power_zone, int id, | |
415 | u64 power_limit) | |
416 | { | |
417 | struct rapl_domain *rd; | |
418 | struct rapl_package *rp; | |
419 | int ret = 0; | |
420 | ||
421 | get_online_cpus(); | |
422 | rd = power_zone_to_rapl_domain(power_zone); | |
309557f5 | 423 | rp = rd->rp; |
2d281d81 JP |
424 | |
425 | if (rd->state & DOMAIN_STATE_BIOS_LOCKED) { | |
426 | dev_warn(&power_zone->dev, "%s locked by BIOS, monitoring only\n", | |
427 | rd->name); | |
428 | ret = -EACCES; | |
429 | goto set_exit; | |
430 | } | |
431 | ||
432 | switch (rd->rpl[id].prim_id) { | |
433 | case PL1_ENABLE: | |
434 | rapl_write_data_raw(rd, POWER_LIMIT1, power_limit); | |
435 | break; | |
436 | case PL2_ENABLE: | |
437 | rapl_write_data_raw(rd, POWER_LIMIT2, power_limit); | |
438 | break; | |
439 | default: | |
440 | ret = -EINVAL; | |
441 | } | |
442 | if (!ret) | |
309557f5 | 443 | package_power_limit_irq_save(rp); |
2d281d81 JP |
444 | set_exit: |
445 | put_online_cpus(); | |
446 | return ret; | |
447 | } | |
448 | ||
449 | static int get_current_power_limit(struct powercap_zone *power_zone, int id, | |
450 | u64 *data) | |
451 | { | |
452 | struct rapl_domain *rd; | |
453 | u64 val; | |
454 | int prim; | |
455 | int ret = 0; | |
456 | ||
457 | get_online_cpus(); | |
458 | rd = power_zone_to_rapl_domain(power_zone); | |
459 | switch (rd->rpl[id].prim_id) { | |
460 | case PL1_ENABLE: | |
461 | prim = POWER_LIMIT1; | |
462 | break; | |
463 | case PL2_ENABLE: | |
464 | prim = POWER_LIMIT2; | |
465 | break; | |
466 | default: | |
467 | put_online_cpus(); | |
468 | return -EINVAL; | |
469 | } | |
470 | if (rapl_read_data_raw(rd, prim, true, &val)) | |
471 | ret = -EIO; | |
472 | else | |
473 | *data = val; | |
474 | ||
475 | put_online_cpus(); | |
476 | ||
477 | return ret; | |
478 | } | |
479 | ||
480 | static int set_time_window(struct powercap_zone *power_zone, int id, | |
481 | u64 window) | |
482 | { | |
483 | struct rapl_domain *rd; | |
484 | int ret = 0; | |
485 | ||
486 | get_online_cpus(); | |
487 | rd = power_zone_to_rapl_domain(power_zone); | |
488 | switch (rd->rpl[id].prim_id) { | |
489 | case PL1_ENABLE: | |
490 | rapl_write_data_raw(rd, TIME_WINDOW1, window); | |
491 | break; | |
492 | case PL2_ENABLE: | |
493 | rapl_write_data_raw(rd, TIME_WINDOW2, window); | |
494 | break; | |
495 | default: | |
496 | ret = -EINVAL; | |
497 | } | |
498 | put_online_cpus(); | |
499 | return ret; | |
500 | } | |
501 | ||
502 | static int get_time_window(struct powercap_zone *power_zone, int id, u64 *data) | |
503 | { | |
504 | struct rapl_domain *rd; | |
505 | u64 val; | |
506 | int ret = 0; | |
507 | ||
508 | get_online_cpus(); | |
509 | rd = power_zone_to_rapl_domain(power_zone); | |
510 | switch (rd->rpl[id].prim_id) { | |
511 | case PL1_ENABLE: | |
512 | ret = rapl_read_data_raw(rd, TIME_WINDOW1, true, &val); | |
513 | break; | |
514 | case PL2_ENABLE: | |
515 | ret = rapl_read_data_raw(rd, TIME_WINDOW2, true, &val); | |
516 | break; | |
517 | default: | |
518 | put_online_cpus(); | |
519 | return -EINVAL; | |
520 | } | |
521 | if (!ret) | |
522 | *data = val; | |
523 | put_online_cpus(); | |
524 | ||
525 | return ret; | |
526 | } | |
527 | ||
528 | static const char *get_constraint_name(struct powercap_zone *power_zone, int id) | |
529 | { | |
530 | struct rapl_power_limit *rpl; | |
531 | struct rapl_domain *rd; | |
532 | ||
533 | rd = power_zone_to_rapl_domain(power_zone); | |
534 | rpl = (struct rapl_power_limit *) &rd->rpl[id]; | |
535 | ||
536 | return rpl->name; | |
537 | } | |
538 | ||
539 | ||
540 | static int get_max_power(struct powercap_zone *power_zone, int id, | |
541 | u64 *data) | |
542 | { | |
543 | struct rapl_domain *rd; | |
544 | u64 val; | |
545 | int prim; | |
546 | int ret = 0; | |
547 | ||
548 | get_online_cpus(); | |
549 | rd = power_zone_to_rapl_domain(power_zone); | |
550 | switch (rd->rpl[id].prim_id) { | |
551 | case PL1_ENABLE: | |
552 | prim = THERMAL_SPEC_POWER; | |
553 | break; | |
554 | case PL2_ENABLE: | |
555 | prim = MAX_POWER; | |
556 | break; | |
557 | default: | |
558 | put_online_cpus(); | |
559 | return -EINVAL; | |
560 | } | |
561 | if (rapl_read_data_raw(rd, prim, true, &val)) | |
562 | ret = -EIO; | |
563 | else | |
564 | *data = val; | |
565 | ||
566 | put_online_cpus(); | |
567 | ||
568 | return ret; | |
569 | } | |
570 | ||
600c395b | 571 | static const struct powercap_zone_constraint_ops constraint_ops = { |
2d281d81 JP |
572 | .set_power_limit_uw = set_power_limit, |
573 | .get_power_limit_uw = get_current_power_limit, | |
574 | .set_time_window_us = set_time_window, | |
575 | .get_time_window_us = get_time_window, | |
576 | .get_max_power_uw = get_max_power, | |
577 | .get_name = get_constraint_name, | |
578 | }; | |
579 | ||
580 | /* called after domain detection and package level data are set */ | |
581 | static void rapl_init_domains(struct rapl_package *rp) | |
582 | { | |
583 | int i; | |
584 | struct rapl_domain *rd = rp->domains; | |
585 | ||
586 | for (i = 0; i < RAPL_DOMAIN_MAX; i++) { | |
587 | unsigned int mask = rp->domain_map & (1 << i); | |
588 | switch (mask) { | |
589 | case BIT(RAPL_DOMAIN_PACKAGE): | |
590 | rd->name = rapl_domain_names[RAPL_DOMAIN_PACKAGE]; | |
591 | rd->id = RAPL_DOMAIN_PACKAGE; | |
592 | rd->msrs[0] = MSR_PKG_POWER_LIMIT; | |
593 | rd->msrs[1] = MSR_PKG_ENERGY_STATUS; | |
594 | rd->msrs[2] = MSR_PKG_PERF_STATUS; | |
595 | rd->msrs[3] = 0; | |
596 | rd->msrs[4] = MSR_PKG_POWER_INFO; | |
597 | rd->rpl[0].prim_id = PL1_ENABLE; | |
598 | rd->rpl[0].name = pl1_name; | |
599 | rd->rpl[1].prim_id = PL2_ENABLE; | |
600 | rd->rpl[1].name = pl2_name; | |
601 | break; | |
602 | case BIT(RAPL_DOMAIN_PP0): | |
603 | rd->name = rapl_domain_names[RAPL_DOMAIN_PP0]; | |
604 | rd->id = RAPL_DOMAIN_PP0; | |
605 | rd->msrs[0] = MSR_PP0_POWER_LIMIT; | |
606 | rd->msrs[1] = MSR_PP0_ENERGY_STATUS; | |
607 | rd->msrs[2] = 0; | |
608 | rd->msrs[3] = MSR_PP0_POLICY; | |
609 | rd->msrs[4] = 0; | |
610 | rd->rpl[0].prim_id = PL1_ENABLE; | |
611 | rd->rpl[0].name = pl1_name; | |
612 | break; | |
613 | case BIT(RAPL_DOMAIN_PP1): | |
614 | rd->name = rapl_domain_names[RAPL_DOMAIN_PP1]; | |
615 | rd->id = RAPL_DOMAIN_PP1; | |
616 | rd->msrs[0] = MSR_PP1_POWER_LIMIT; | |
617 | rd->msrs[1] = MSR_PP1_ENERGY_STATUS; | |
618 | rd->msrs[2] = 0; | |
619 | rd->msrs[3] = MSR_PP1_POLICY; | |
620 | rd->msrs[4] = 0; | |
621 | rd->rpl[0].prim_id = PL1_ENABLE; | |
622 | rd->rpl[0].name = pl1_name; | |
623 | break; | |
624 | case BIT(RAPL_DOMAIN_DRAM): | |
625 | rd->name = rapl_domain_names[RAPL_DOMAIN_DRAM]; | |
626 | rd->id = RAPL_DOMAIN_DRAM; | |
627 | rd->msrs[0] = MSR_DRAM_POWER_LIMIT; | |
628 | rd->msrs[1] = MSR_DRAM_ENERGY_STATUS; | |
629 | rd->msrs[2] = MSR_DRAM_PERF_STATUS; | |
630 | rd->msrs[3] = 0; | |
631 | rd->msrs[4] = MSR_DRAM_POWER_INFO; | |
632 | rd->rpl[0].prim_id = PL1_ENABLE; | |
633 | rd->rpl[0].name = pl1_name; | |
d474a4d3 JP |
634 | rd->domain_energy_unit = |
635 | rapl_defaults->dram_domain_energy_unit; | |
636 | if (rd->domain_energy_unit) | |
637 | pr_info("DRAM domain energy unit %dpj\n", | |
638 | rd->domain_energy_unit); | |
2d281d81 JP |
639 | break; |
640 | } | |
641 | if (mask) { | |
309557f5 | 642 | rd->rp = rp; |
2d281d81 JP |
643 | rd++; |
644 | } | |
645 | } | |
646 | } | |
647 | ||
309557f5 JP |
648 | static u64 rapl_unit_xlate(struct rapl_domain *rd, enum unit_type type, |
649 | u64 value, int to_raw) | |
2d281d81 | 650 | { |
3c2c0845 | 651 | u64 units = 1; |
309557f5 | 652 | struct rapl_package *rp = rd->rp; |
d474a4d3 | 653 | u64 scale = 1; |
2d281d81 | 654 | |
2d281d81 JP |
655 | switch (type) { |
656 | case POWER_UNIT: | |
3c2c0845 | 657 | units = rp->power_unit; |
2d281d81 JP |
658 | break; |
659 | case ENERGY_UNIT: | |
d474a4d3 JP |
660 | scale = ENERGY_UNIT_SCALE; |
661 | /* per domain unit takes precedence */ | |
662 | if (rd && rd->domain_energy_unit) | |
663 | units = rd->domain_energy_unit; | |
664 | else | |
665 | units = rp->energy_unit; | |
2d281d81 JP |
666 | break; |
667 | case TIME_UNIT: | |
3c2c0845 | 668 | return rapl_defaults->compute_time_window(rp, value, to_raw); |
2d281d81 JP |
669 | case ARBITRARY_UNIT: |
670 | default: | |
671 | return value; | |
672 | }; | |
673 | ||
674 | if (to_raw) | |
d474a4d3 | 675 | return div64_u64(value, units) * scale; |
3c2c0845 JP |
676 | |
677 | value *= units; | |
678 | ||
d474a4d3 | 679 | return div64_u64(value, scale); |
2d281d81 JP |
680 | } |
681 | ||
682 | /* in the order of enum rapl_primitives */ | |
683 | static struct rapl_primitive_info rpi[] = { | |
684 | /* name, mask, shift, msr index, unit divisor */ | |
685 | PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0, | |
686 | RAPL_DOMAIN_MSR_STATUS, ENERGY_UNIT, 0), | |
687 | PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0, | |
688 | RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0), | |
689 | PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32, | |
690 | RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0), | |
691 | PRIMITIVE_INFO_INIT(FW_LOCK, POWER_PP_LOCK, 31, | |
692 | RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0), | |
693 | PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15, | |
694 | RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0), | |
695 | PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16, | |
696 | RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0), | |
697 | PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47, | |
698 | RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0), | |
699 | PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48, | |
700 | RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0), | |
701 | PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17, | |
702 | RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0), | |
703 | PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49, | |
704 | RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0), | |
705 | PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, POWER_INFO_THERMAL_SPEC_MASK, | |
706 | 0, RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0), | |
707 | PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32, | |
708 | RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0), | |
709 | PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16, | |
710 | RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0), | |
711 | PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, POWER_INFO_MAX_TIME_WIN_MASK, 48, | |
712 | RAPL_DOMAIN_MSR_INFO, TIME_UNIT, 0), | |
713 | PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0, | |
714 | RAPL_DOMAIN_MSR_PERF, TIME_UNIT, 0), | |
715 | PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0, | |
716 | RAPL_DOMAIN_MSR_POLICY, ARBITRARY_UNIT, 0), | |
717 | /* non-hardware */ | |
718 | PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT, | |
719 | RAPL_PRIMITIVE_DERIVED), | |
720 | {NULL, 0, 0, 0}, | |
721 | }; | |
722 | ||
723 | /* Read primitive data based on its related struct rapl_primitive_info. | |
724 | * if xlate flag is set, return translated data based on data units, i.e. | |
725 | * time, energy, and power. | |
726 | * RAPL MSRs are non-architectual and are laid out not consistently across | |
727 | * domains. Here we use primitive info to allow writing consolidated access | |
728 | * functions. | |
729 | * For a given primitive, it is processed by MSR mask and shift. Unit conversion | |
730 | * is pre-assigned based on RAPL unit MSRs read at init time. | |
731 | * 63-------------------------- 31--------------------------- 0 | |
732 | * | xxxxx (mask) | | |
733 | * | |<- shift ----------------| | |
734 | * 63-------------------------- 31--------------------------- 0 | |
735 | */ | |
736 | static int rapl_read_data_raw(struct rapl_domain *rd, | |
737 | enum rapl_primitives prim, | |
738 | bool xlate, u64 *data) | |
739 | { | |
740 | u64 value, final; | |
741 | u32 msr; | |
742 | struct rapl_primitive_info *rp = &rpi[prim]; | |
743 | int cpu; | |
744 | ||
745 | if (!rp->name || rp->flag & RAPL_PRIMITIVE_DUMMY) | |
746 | return -EINVAL; | |
747 | ||
748 | msr = rd->msrs[rp->id]; | |
749 | if (!msr) | |
750 | return -EINVAL; | |
323ee64a JP |
751 | |
752 | cpu = rd->rp->lead_cpu; | |
2d281d81 JP |
753 | |
754 | /* special-case package domain, which uses a different bit*/ | |
755 | if (prim == FW_LOCK && rd->id == RAPL_DOMAIN_PACKAGE) { | |
756 | rp->mask = POWER_PACKAGE_LOCK; | |
757 | rp->shift = 63; | |
758 | } | |
759 | /* non-hardware data are collected by the polling thread */ | |
760 | if (rp->flag & RAPL_PRIMITIVE_DERIVED) { | |
761 | *data = rd->rdd.primitives[prim]; | |
762 | return 0; | |
763 | } | |
764 | ||
765 | if (rdmsrl_safe_on_cpu(cpu, msr, &value)) { | |
766 | pr_debug("failed to read msr 0x%x on cpu %d\n", msr, cpu); | |
767 | return -EIO; | |
768 | } | |
769 | ||
770 | final = value & rp->mask; | |
771 | final = final >> rp->shift; | |
772 | if (xlate) | |
309557f5 | 773 | *data = rapl_unit_xlate(rd, rp->unit, final, 0); |
2d281d81 JP |
774 | else |
775 | *data = final; | |
776 | ||
777 | return 0; | |
778 | } | |
779 | ||
f14a1396 JP |
780 | |
781 | static int msrl_update_safe(u32 msr_no, u64 clear_mask, u64 set_mask) | |
782 | { | |
783 | int err; | |
784 | u64 val; | |
785 | ||
786 | err = rdmsrl_safe(msr_no, &val); | |
787 | if (err) | |
788 | goto out; | |
789 | ||
790 | val &= ~clear_mask; | |
791 | val |= set_mask; | |
792 | ||
793 | err = wrmsrl_safe(msr_no, val); | |
794 | ||
795 | out: | |
796 | return err; | |
797 | } | |
798 | ||
799 | static void msrl_update_func(void *info) | |
800 | { | |
801 | struct msrl_action *ma = info; | |
802 | ||
803 | ma->err = msrl_update_safe(ma->msr_no, ma->clear_mask, ma->set_mask); | |
804 | } | |
805 | ||
2d281d81 JP |
806 | /* Similar use of primitive info in the read counterpart */ |
807 | static int rapl_write_data_raw(struct rapl_domain *rd, | |
808 | enum rapl_primitives prim, | |
809 | unsigned long long value) | |
810 | { | |
2d281d81 JP |
811 | struct rapl_primitive_info *rp = &rpi[prim]; |
812 | int cpu; | |
f14a1396 JP |
813 | u64 bits; |
814 | struct msrl_action ma; | |
815 | int ret; | |
2d281d81 | 816 | |
323ee64a | 817 | cpu = rd->rp->lead_cpu; |
309557f5 | 818 | bits = rapl_unit_xlate(rd, rp->unit, value, 1); |
f14a1396 JP |
819 | bits |= bits << rp->shift; |
820 | memset(&ma, 0, sizeof(ma)); | |
821 | ||
822 | ma.msr_no = rd->msrs[rp->id]; | |
823 | ma.clear_mask = rp->mask; | |
824 | ma.set_mask = bits; | |
825 | ||
826 | ret = smp_call_function_single(cpu, msrl_update_func, &ma, 1); | |
827 | if (ret) | |
828 | WARN_ON_ONCE(ret); | |
829 | else | |
830 | ret = ma.err; | |
831 | ||
832 | return ret; | |
2d281d81 JP |
833 | } |
834 | ||
3c2c0845 JP |
835 | /* |
836 | * Raw RAPL data stored in MSRs are in certain scales. We need to | |
837 | * convert them into standard units based on the units reported in | |
838 | * the RAPL unit MSRs. This is specific to CPUs as the method to | |
839 | * calculate units differ on different CPUs. | |
840 | * We convert the units to below format based on CPUs. | |
841 | * i.e. | |
d474a4d3 | 842 | * energy unit: picoJoules : Represented in picoJoules by default |
3c2c0845 JP |
843 | * power unit : microWatts : Represented in milliWatts by default |
844 | * time unit : microseconds: Represented in seconds by default | |
845 | */ | |
846 | static int rapl_check_unit_core(struct rapl_package *rp, int cpu) | |
2d281d81 JP |
847 | { |
848 | u64 msr_val; | |
849 | u32 value; | |
850 | ||
851 | if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) { | |
852 | pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n", | |
853 | MSR_RAPL_POWER_UNIT, cpu); | |
854 | return -ENODEV; | |
855 | } | |
856 | ||
2d281d81 | 857 | value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; |
d474a4d3 | 858 | rp->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value); |
2d281d81 JP |
859 | |
860 | value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; | |
3c2c0845 | 861 | rp->power_unit = 1000000 / (1 << value); |
2d281d81 JP |
862 | |
863 | value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET; | |
3c2c0845 | 864 | rp->time_unit = 1000000 / (1 << value); |
2d281d81 | 865 | |
d474a4d3 | 866 | pr_debug("Core CPU package %d energy=%dpJ, time=%dus, power=%duW\n", |
3c2c0845 | 867 | rp->id, rp->energy_unit, rp->time_unit, rp->power_unit); |
2d281d81 JP |
868 | |
869 | return 0; | |
870 | } | |
871 | ||
3c2c0845 JP |
872 | static int rapl_check_unit_atom(struct rapl_package *rp, int cpu) |
873 | { | |
874 | u64 msr_val; | |
875 | u32 value; | |
876 | ||
877 | if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) { | |
878 | pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n", | |
879 | MSR_RAPL_POWER_UNIT, cpu); | |
880 | return -ENODEV; | |
881 | } | |
882 | value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; | |
d474a4d3 | 883 | rp->energy_unit = ENERGY_UNIT_SCALE * 1 << value; |
3c2c0845 JP |
884 | |
885 | value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; | |
886 | rp->power_unit = (1 << value) * 1000; | |
887 | ||
888 | value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET; | |
889 | rp->time_unit = 1000000 / (1 << value); | |
890 | ||
d474a4d3 | 891 | pr_debug("Atom package %d energy=%dpJ, time=%dus, power=%duW\n", |
3c2c0845 JP |
892 | rp->id, rp->energy_unit, rp->time_unit, rp->power_unit); |
893 | ||
894 | return 0; | |
895 | } | |
896 | ||
f14a1396 JP |
897 | static void power_limit_irq_save_cpu(void *info) |
898 | { | |
899 | u32 l, h = 0; | |
900 | struct rapl_package *rp = (struct rapl_package *)info; | |
901 | ||
902 | /* save the state of PLN irq mask bit before disabling it */ | |
903 | rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h); | |
904 | if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) { | |
905 | rp->power_limit_irq = l & PACKAGE_THERM_INT_PLN_ENABLE; | |
906 | rp->power_limit_irq |= PACKAGE_PLN_INT_SAVED; | |
907 | } | |
908 | l &= ~PACKAGE_THERM_INT_PLN_ENABLE; | |
909 | wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); | |
910 | } | |
911 | ||
3c2c0845 | 912 | |
2d281d81 JP |
913 | /* REVISIT: |
914 | * When package power limit is set artificially low by RAPL, LVT | |
915 | * thermal interrupt for package power limit should be ignored | |
916 | * since we are not really exceeding the real limit. The intention | |
917 | * is to avoid excessive interrupts while we are trying to save power. | |
918 | * A useful feature might be routing the package_power_limit interrupt | |
919 | * to userspace via eventfd. once we have a usecase, this is simple | |
920 | * to do by adding an atomic notifier. | |
921 | */ | |
922 | ||
309557f5 | 923 | static void package_power_limit_irq_save(struct rapl_package *rp) |
2d281d81 | 924 | { |
f14a1396 JP |
925 | if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN)) |
926 | return; | |
927 | ||
323ee64a | 928 | smp_call_function_single(rp->lead_cpu, power_limit_irq_save_cpu, rp, 1); |
f14a1396 JP |
929 | } |
930 | ||
931 | static void power_limit_irq_restore_cpu(void *info) | |
932 | { | |
933 | u32 l, h = 0; | |
934 | struct rapl_package *rp = (struct rapl_package *)info; | |
935 | ||
936 | rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h); | |
937 | ||
938 | if (rp->power_limit_irq & PACKAGE_THERM_INT_PLN_ENABLE) | |
939 | l |= PACKAGE_THERM_INT_PLN_ENABLE; | |
940 | else | |
941 | l &= ~PACKAGE_THERM_INT_PLN_ENABLE; | |
942 | ||
943 | wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); | |
2d281d81 JP |
944 | } |
945 | ||
946 | /* restore per package power limit interrupt enable state */ | |
309557f5 | 947 | static void package_power_limit_irq_restore(struct rapl_package *rp) |
2d281d81 | 948 | { |
2d281d81 JP |
949 | if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN)) |
950 | return; | |
951 | ||
2d281d81 JP |
952 | /* irq enable state not saved, nothing to restore */ |
953 | if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) | |
954 | return; | |
2d281d81 | 955 | |
323ee64a | 956 | smp_call_function_single(rp->lead_cpu, power_limit_irq_restore_cpu, rp, 1); |
2d281d81 JP |
957 | } |
958 | ||
3c2c0845 JP |
959 | static void set_floor_freq_default(struct rapl_domain *rd, bool mode) |
960 | { | |
961 | int nr_powerlimit = find_nr_power_limit(rd); | |
962 | ||
963 | /* always enable clamp such that p-state can go below OS requested | |
964 | * range. power capping priority over guranteed frequency. | |
965 | */ | |
966 | rapl_write_data_raw(rd, PL1_CLAMP, mode); | |
967 | ||
968 | /* some domains have pl2 */ | |
969 | if (nr_powerlimit > 1) { | |
970 | rapl_write_data_raw(rd, PL2_ENABLE, mode); | |
971 | rapl_write_data_raw(rd, PL2_CLAMP, mode); | |
972 | } | |
973 | } | |
974 | ||
975 | static void set_floor_freq_atom(struct rapl_domain *rd, bool enable) | |
976 | { | |
977 | static u32 power_ctrl_orig_val; | |
978 | u32 mdata; | |
979 | ||
51b63409 AT |
980 | if (!rapl_defaults->floor_freq_reg_addr) { |
981 | pr_err("Invalid floor frequency config register\n"); | |
982 | return; | |
983 | } | |
984 | ||
3c2c0845 | 985 | if (!power_ctrl_orig_val) |
4077a387 AS |
986 | iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ, |
987 | rapl_defaults->floor_freq_reg_addr, | |
988 | &power_ctrl_orig_val); | |
3c2c0845 JP |
989 | mdata = power_ctrl_orig_val; |
990 | if (enable) { | |
991 | mdata &= ~(0x7f << 8); | |
992 | mdata |= 1 << 8; | |
993 | } | |
4077a387 AS |
994 | iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE, |
995 | rapl_defaults->floor_freq_reg_addr, mdata); | |
3c2c0845 JP |
996 | } |
997 | ||
998 | static u64 rapl_compute_time_window_core(struct rapl_package *rp, u64 value, | |
999 | bool to_raw) | |
1000 | { | |
1001 | u64 f, y; /* fraction and exp. used for time unit */ | |
1002 | ||
1003 | /* | |
1004 | * Special processing based on 2^Y*(1+F/4), refer | |
1005 | * to Intel Software Developer's manual Vol.3B: CH 14.9.3. | |
1006 | */ | |
1007 | if (!to_raw) { | |
1008 | f = (value & 0x60) >> 5; | |
1009 | y = value & 0x1f; | |
1010 | value = (1 << y) * (4 + f) * rp->time_unit / 4; | |
1011 | } else { | |
1012 | do_div(value, rp->time_unit); | |
1013 | y = ilog2(value); | |
1014 | f = div64_u64(4 * (value - (1 << y)), 1 << y); | |
1015 | value = (y & 0x1f) | ((f & 0x3) << 5); | |
1016 | } | |
1017 | return value; | |
1018 | } | |
1019 | ||
1020 | static u64 rapl_compute_time_window_atom(struct rapl_package *rp, u64 value, | |
1021 | bool to_raw) | |
1022 | { | |
1023 | /* | |
1024 | * Atom time unit encoding is straight forward val * time_unit, | |
1025 | * where time_unit is default to 1 sec. Never 0. | |
1026 | */ | |
1027 | if (!to_raw) | |
1028 | return (value) ? value *= rp->time_unit : rp->time_unit; | |
1029 | else | |
1030 | value = div64_u64(value, rp->time_unit); | |
1031 | ||
1032 | return value; | |
1033 | } | |
1034 | ||
087e9cba | 1035 | static const struct rapl_defaults rapl_defaults_core = { |
51b63409 | 1036 | .floor_freq_reg_addr = 0, |
3c2c0845 JP |
1037 | .check_unit = rapl_check_unit_core, |
1038 | .set_floor_freq = set_floor_freq_default, | |
1039 | .compute_time_window = rapl_compute_time_window_core, | |
087e9cba JP |
1040 | }; |
1041 | ||
d474a4d3 JP |
1042 | static const struct rapl_defaults rapl_defaults_hsw_server = { |
1043 | .check_unit = rapl_check_unit_core, | |
1044 | .set_floor_freq = set_floor_freq_default, | |
1045 | .compute_time_window = rapl_compute_time_window_core, | |
1046 | .dram_domain_energy_unit = 15300, | |
1047 | }; | |
1048 | ||
51b63409 AT |
1049 | static const struct rapl_defaults rapl_defaults_byt = { |
1050 | .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT, | |
1051 | .check_unit = rapl_check_unit_atom, | |
1052 | .set_floor_freq = set_floor_freq_atom, | |
1053 | .compute_time_window = rapl_compute_time_window_atom, | |
1054 | }; | |
1055 | ||
1056 | static const struct rapl_defaults rapl_defaults_tng = { | |
1057 | .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG, | |
3c2c0845 JP |
1058 | .check_unit = rapl_check_unit_atom, |
1059 | .set_floor_freq = set_floor_freq_atom, | |
1060 | .compute_time_window = rapl_compute_time_window_atom, | |
087e9cba JP |
1061 | }; |
1062 | ||
51b63409 AT |
1063 | static const struct rapl_defaults rapl_defaults_ann = { |
1064 | .floor_freq_reg_addr = 0, | |
1065 | .check_unit = rapl_check_unit_atom, | |
1066 | .set_floor_freq = NULL, | |
1067 | .compute_time_window = rapl_compute_time_window_atom, | |
1068 | }; | |
1069 | ||
1070 | static const struct rapl_defaults rapl_defaults_cht = { | |
1071 | .floor_freq_reg_addr = 0, | |
1072 | .check_unit = rapl_check_unit_atom, | |
1073 | .set_floor_freq = NULL, | |
1074 | .compute_time_window = rapl_compute_time_window_atom, | |
1075 | }; | |
1076 | ||
087e9cba JP |
1077 | #define RAPL_CPU(_model, _ops) { \ |
1078 | .vendor = X86_VENDOR_INTEL, \ | |
1079 | .family = 6, \ | |
1080 | .model = _model, \ | |
1081 | .driver_data = (kernel_ulong_t)&_ops, \ | |
1082 | } | |
1083 | ||
ea85dbca | 1084 | static const struct x86_cpu_id rapl_ids[] __initconst = { |
087e9cba JP |
1085 | RAPL_CPU(0x2a, rapl_defaults_core),/* Sandy Bridge */ |
1086 | RAPL_CPU(0x2d, rapl_defaults_core),/* Sandy Bridge EP */ | |
51b63409 | 1087 | RAPL_CPU(0x37, rapl_defaults_byt),/* Valleyview */ |
087e9cba JP |
1088 | RAPL_CPU(0x3a, rapl_defaults_core),/* Ivy Bridge */ |
1089 | RAPL_CPU(0x3c, rapl_defaults_core),/* Haswell */ | |
1090 | RAPL_CPU(0x3d, rapl_defaults_core),/* Broadwell */ | |
d474a4d3 | 1091 | RAPL_CPU(0x3f, rapl_defaults_hsw_server),/* Haswell servers */ |
34dfa36c | 1092 | RAPL_CPU(0x4f, rapl_defaults_hsw_server),/* Broadwell servers */ |
087e9cba | 1093 | RAPL_CPU(0x45, rapl_defaults_core),/* Haswell ULT */ |
4e0bec9e | 1094 | RAPL_CPU(0x47, rapl_defaults_core),/* Broadwell-H */ |
5fa0fa4b | 1095 | RAPL_CPU(0x4E, rapl_defaults_core),/* Skylake */ |
51b63409 AT |
1096 | RAPL_CPU(0x4C, rapl_defaults_cht),/* Braswell/Cherryview */ |
1097 | RAPL_CPU(0x4A, rapl_defaults_tng),/* Tangier */ | |
d72be771 | 1098 | RAPL_CPU(0x56, rapl_defaults_core),/* Future Xeon */ |
51b63409 | 1099 | RAPL_CPU(0x5A, rapl_defaults_ann),/* Annidale */ |
89e7b255 | 1100 | RAPL_CPU(0X5C, rapl_defaults_core),/* Broxton */ |
2cac1f70 | 1101 | RAPL_CPU(0x5E, rapl_defaults_core),/* Skylake-H/S */ |
6f066d4d | 1102 | RAPL_CPU(0x57, rapl_defaults_hsw_server),/* Knights Landing */ |
2d281d81 JP |
1103 | {} |
1104 | }; | |
1105 | MODULE_DEVICE_TABLE(x86cpu, rapl_ids); | |
1106 | ||
1107 | /* read once for all raw primitive data for all packages, domains */ | |
1108 | static void rapl_update_domain_data(void) | |
1109 | { | |
1110 | int dmn, prim; | |
1111 | u64 val; | |
1112 | struct rapl_package *rp; | |
1113 | ||
1114 | list_for_each_entry(rp, &rapl_packages, plist) { | |
1115 | for (dmn = 0; dmn < rp->nr_domains; dmn++) { | |
1116 | pr_debug("update package %d domain %s data\n", rp->id, | |
1117 | rp->domains[dmn].name); | |
1118 | /* exclude non-raw primitives */ | |
1119 | for (prim = 0; prim < NR_RAW_PRIMITIVES; prim++) | |
1120 | if (!rapl_read_data_raw(&rp->domains[dmn], prim, | |
1121 | rpi[prim].unit, | |
1122 | &val)) | |
1123 | rp->domains[dmn].rdd.primitives[prim] = | |
1124 | val; | |
1125 | } | |
1126 | } | |
1127 | ||
1128 | } | |
1129 | ||
1130 | static int rapl_unregister_powercap(void) | |
1131 | { | |
1132 | struct rapl_package *rp; | |
1133 | struct rapl_domain *rd, *rd_package = NULL; | |
1134 | ||
1135 | /* unregister all active rapl packages from the powercap layer, | |
1136 | * hotplug lock held | |
1137 | */ | |
1138 | list_for_each_entry(rp, &rapl_packages, plist) { | |
309557f5 | 1139 | package_power_limit_irq_restore(rp); |
2d281d81 JP |
1140 | |
1141 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; | |
1142 | rd++) { | |
1143 | pr_debug("remove package, undo power limit on %d: %s\n", | |
1144 | rp->id, rd->name); | |
1145 | rapl_write_data_raw(rd, PL1_ENABLE, 0); | |
2d281d81 | 1146 | rapl_write_data_raw(rd, PL1_CLAMP, 0); |
5021282c SI |
1147 | if (find_nr_power_limit(rd) > 1) { |
1148 | rapl_write_data_raw(rd, PL2_ENABLE, 0); | |
1149 | rapl_write_data_raw(rd, PL2_CLAMP, 0); | |
1150 | } | |
2d281d81 JP |
1151 | if (rd->id == RAPL_DOMAIN_PACKAGE) { |
1152 | rd_package = rd; | |
1153 | continue; | |
1154 | } | |
1155 | powercap_unregister_zone(control_type, &rd->power_zone); | |
1156 | } | |
1157 | /* do the package zone last */ | |
1158 | if (rd_package) | |
1159 | powercap_unregister_zone(control_type, | |
1160 | &rd_package->power_zone); | |
1161 | } | |
1162 | powercap_unregister_control_type(control_type); | |
1163 | ||
1164 | return 0; | |
1165 | } | |
1166 | ||
1167 | static int rapl_package_register_powercap(struct rapl_package *rp) | |
1168 | { | |
1169 | struct rapl_domain *rd; | |
1170 | int ret = 0; | |
1171 | char dev_name[17]; /* max domain name = 7 + 1 + 8 for int + 1 for null*/ | |
1172 | struct powercap_zone *power_zone = NULL; | |
1173 | int nr_pl; | |
1174 | ||
1175 | /* first we register package domain as the parent zone*/ | |
1176 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { | |
1177 | if (rd->id == RAPL_DOMAIN_PACKAGE) { | |
1178 | nr_pl = find_nr_power_limit(rd); | |
1179 | pr_debug("register socket %d package domain %s\n", | |
1180 | rp->id, rd->name); | |
1181 | memset(dev_name, 0, sizeof(dev_name)); | |
1182 | snprintf(dev_name, sizeof(dev_name), "%s-%d", | |
1183 | rd->name, rp->id); | |
1184 | power_zone = powercap_register_zone(&rd->power_zone, | |
1185 | control_type, | |
1186 | dev_name, NULL, | |
1187 | &zone_ops[rd->id], | |
1188 | nr_pl, | |
1189 | &constraint_ops); | |
1190 | if (IS_ERR(power_zone)) { | |
1191 | pr_debug("failed to register package, %d\n", | |
1192 | rp->id); | |
1193 | ret = PTR_ERR(power_zone); | |
1194 | goto exit_package; | |
1195 | } | |
1196 | /* track parent zone in per package/socket data */ | |
1197 | rp->power_zone = power_zone; | |
1198 | /* done, only one package domain per socket */ | |
1199 | break; | |
1200 | } | |
1201 | } | |
1202 | if (!power_zone) { | |
1203 | pr_err("no package domain found, unknown topology!\n"); | |
1204 | ret = -ENODEV; | |
1205 | goto exit_package; | |
1206 | } | |
1207 | /* now register domains as children of the socket/package*/ | |
1208 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { | |
1209 | if (rd->id == RAPL_DOMAIN_PACKAGE) | |
1210 | continue; | |
1211 | /* number of power limits per domain varies */ | |
1212 | nr_pl = find_nr_power_limit(rd); | |
1213 | power_zone = powercap_register_zone(&rd->power_zone, | |
1214 | control_type, rd->name, | |
1215 | rp->power_zone, | |
1216 | &zone_ops[rd->id], nr_pl, | |
1217 | &constraint_ops); | |
1218 | ||
1219 | if (IS_ERR(power_zone)) { | |
1220 | pr_debug("failed to register power_zone, %d:%s:%s\n", | |
1221 | rp->id, rd->name, dev_name); | |
1222 | ret = PTR_ERR(power_zone); | |
1223 | goto err_cleanup; | |
1224 | } | |
1225 | } | |
1226 | ||
1227 | exit_package: | |
1228 | return ret; | |
1229 | err_cleanup: | |
1230 | /* clean up previously initialized domains within the package if we | |
1231 | * failed after the first domain setup. | |
1232 | */ | |
1233 | while (--rd >= rp->domains) { | |
1234 | pr_debug("unregister package %d domain %s\n", rp->id, rd->name); | |
1235 | powercap_unregister_zone(control_type, &rd->power_zone); | |
1236 | } | |
1237 | ||
1238 | return ret; | |
1239 | } | |
1240 | ||
1241 | static int rapl_register_powercap(void) | |
1242 | { | |
1243 | struct rapl_domain *rd; | |
1244 | struct rapl_package *rp; | |
1245 | int ret = 0; | |
1246 | ||
1247 | control_type = powercap_register_control_type(NULL, "intel-rapl", NULL); | |
1248 | if (IS_ERR(control_type)) { | |
1249 | pr_debug("failed to register powercap control_type.\n"); | |
1250 | return PTR_ERR(control_type); | |
1251 | } | |
1252 | /* read the initial data */ | |
1253 | rapl_update_domain_data(); | |
1254 | list_for_each_entry(rp, &rapl_packages, plist) | |
1255 | if (rapl_package_register_powercap(rp)) | |
1256 | goto err_cleanup_package; | |
1257 | return ret; | |
1258 | ||
1259 | err_cleanup_package: | |
1260 | /* clean up previously initialized packages */ | |
1261 | list_for_each_entry_continue_reverse(rp, &rapl_packages, plist) { | |
1262 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; | |
1263 | rd++) { | |
1264 | pr_debug("unregister zone/package %d, %s domain\n", | |
1265 | rp->id, rd->name); | |
1266 | powercap_unregister_zone(control_type, &rd->power_zone); | |
1267 | } | |
1268 | } | |
1269 | ||
1270 | return ret; | |
1271 | } | |
1272 | ||
1273 | static int rapl_check_domain(int cpu, int domain) | |
1274 | { | |
1275 | unsigned msr; | |
9d31c676 | 1276 | u64 val = 0; |
2d281d81 JP |
1277 | |
1278 | switch (domain) { | |
1279 | case RAPL_DOMAIN_PACKAGE: | |
1280 | msr = MSR_PKG_ENERGY_STATUS; | |
1281 | break; | |
1282 | case RAPL_DOMAIN_PP0: | |
1283 | msr = MSR_PP0_ENERGY_STATUS; | |
1284 | break; | |
1285 | case RAPL_DOMAIN_PP1: | |
1286 | msr = MSR_PP1_ENERGY_STATUS; | |
1287 | break; | |
1288 | case RAPL_DOMAIN_DRAM: | |
1289 | msr = MSR_DRAM_ENERGY_STATUS; | |
1290 | break; | |
1291 | default: | |
1292 | pr_err("invalid domain id %d\n", domain); | |
1293 | return -EINVAL; | |
1294 | } | |
9d31c676 JP |
1295 | /* make sure domain counters are available and contains non-zero |
1296 | * values, otherwise skip it. | |
7b874772 | 1297 | */ |
9d31c676 JP |
1298 | if (rdmsrl_safe_on_cpu(cpu, msr, &val) || !val) |
1299 | return -ENODEV; | |
2d281d81 | 1300 | |
9d31c676 | 1301 | return 0; |
2d281d81 JP |
1302 | } |
1303 | ||
1304 | /* Detect active and valid domains for the given CPU, caller must | |
1305 | * ensure the CPU belongs to the targeted package and CPU hotlug is disabled. | |
1306 | */ | |
1307 | static int rapl_detect_domains(struct rapl_package *rp, int cpu) | |
1308 | { | |
1309 | int i; | |
1310 | int ret = 0; | |
1311 | struct rapl_domain *rd; | |
1312 | u64 locked; | |
1313 | ||
1314 | for (i = 0; i < RAPL_DOMAIN_MAX; i++) { | |
1315 | /* use physical package id to read counters */ | |
fcdf1797 | 1316 | if (!rapl_check_domain(cpu, i)) { |
2d281d81 | 1317 | rp->domain_map |= 1 << i; |
fcdf1797 JP |
1318 | pr_info("Found RAPL domain %s\n", rapl_domain_names[i]); |
1319 | } | |
2d281d81 JP |
1320 | } |
1321 | rp->nr_domains = bitmap_weight(&rp->domain_map, RAPL_DOMAIN_MAX); | |
1322 | if (!rp->nr_domains) { | |
1323 | pr_err("no valid rapl domains found in package %d\n", rp->id); | |
1324 | ret = -ENODEV; | |
1325 | goto done; | |
1326 | } | |
1327 | pr_debug("found %d domains on package %d\n", rp->nr_domains, rp->id); | |
1328 | ||
1329 | rp->domains = kcalloc(rp->nr_domains + 1, sizeof(struct rapl_domain), | |
1330 | GFP_KERNEL); | |
1331 | if (!rp->domains) { | |
1332 | ret = -ENOMEM; | |
1333 | goto done; | |
1334 | } | |
1335 | rapl_init_domains(rp); | |
1336 | ||
1337 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { | |
1338 | /* check if the domain is locked by BIOS */ | |
79a21dbf PB |
1339 | ret = rapl_read_data_raw(rd, FW_LOCK, false, &locked); |
1340 | if (ret) | |
1341 | return ret; | |
1342 | if (locked) { | |
2d281d81 JP |
1343 | pr_info("RAPL package %d domain %s locked by BIOS\n", |
1344 | rp->id, rd->name); | |
79a21dbf | 1345 | rd->state |= DOMAIN_STATE_BIOS_LOCKED; |
2d281d81 JP |
1346 | } |
1347 | } | |
1348 | ||
1349 | ||
1350 | done: | |
1351 | return ret; | |
1352 | } | |
1353 | ||
1354 | static bool is_package_new(int package) | |
1355 | { | |
1356 | struct rapl_package *rp; | |
1357 | ||
1358 | /* caller prevents cpu hotplug, there will be no new packages added | |
1359 | * or deleted while traversing the package list, no need for locking. | |
1360 | */ | |
1361 | list_for_each_entry(rp, &rapl_packages, plist) | |
1362 | if (package == rp->id) | |
1363 | return false; | |
1364 | ||
1365 | return true; | |
1366 | } | |
1367 | ||
1368 | /* RAPL interface can be made of a two-level hierarchy: package level and domain | |
1369 | * level. We first detect the number of packages then domains of each package. | |
1370 | * We have to consider the possiblity of CPU online/offline due to hotplug and | |
1371 | * other scenarios. | |
1372 | */ | |
1373 | static int rapl_detect_topology(void) | |
1374 | { | |
1375 | int i; | |
1376 | int phy_package_id; | |
1377 | struct rapl_package *new_package, *rp; | |
1378 | ||
1379 | for_each_online_cpu(i) { | |
1380 | phy_package_id = topology_physical_package_id(i); | |
1381 | if (is_package_new(phy_package_id)) { | |
1382 | new_package = kzalloc(sizeof(*rp), GFP_KERNEL); | |
1383 | if (!new_package) { | |
1384 | rapl_cleanup_data(); | |
1385 | return -ENOMEM; | |
1386 | } | |
1387 | /* add the new package to the list */ | |
1388 | new_package->id = phy_package_id; | |
1389 | new_package->nr_cpus = 1; | |
323ee64a JP |
1390 | /* use the first active cpu of the package to access */ |
1391 | new_package->lead_cpu = i; | |
2d281d81 JP |
1392 | /* check if the package contains valid domains */ |
1393 | if (rapl_detect_domains(new_package, i) || | |
3c2c0845 | 1394 | rapl_defaults->check_unit(new_package, i)) { |
2d281d81 JP |
1395 | kfree(new_package->domains); |
1396 | kfree(new_package); | |
1397 | /* free up the packages already initialized */ | |
1398 | rapl_cleanup_data(); | |
1399 | return -ENODEV; | |
1400 | } | |
1401 | INIT_LIST_HEAD(&new_package->plist); | |
1402 | list_add(&new_package->plist, &rapl_packages); | |
1403 | } else { | |
1404 | rp = find_package_by_id(phy_package_id); | |
1405 | if (rp) | |
1406 | ++rp->nr_cpus; | |
1407 | } | |
1408 | } | |
1409 | ||
1410 | return 0; | |
1411 | } | |
1412 | ||
1413 | /* called from CPU hotplug notifier, hotplug lock held */ | |
1414 | static void rapl_remove_package(struct rapl_package *rp) | |
1415 | { | |
1416 | struct rapl_domain *rd, *rd_package = NULL; | |
1417 | ||
1418 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { | |
1419 | if (rd->id == RAPL_DOMAIN_PACKAGE) { | |
1420 | rd_package = rd; | |
1421 | continue; | |
1422 | } | |
1423 | pr_debug("remove package %d, %s domain\n", rp->id, rd->name); | |
1424 | powercap_unregister_zone(control_type, &rd->power_zone); | |
1425 | } | |
1426 | /* do parent zone last */ | |
1427 | powercap_unregister_zone(control_type, &rd_package->power_zone); | |
1428 | list_del(&rp->plist); | |
1429 | kfree(rp); | |
1430 | } | |
1431 | ||
1432 | /* called from CPU hotplug notifier, hotplug lock held */ | |
1433 | static int rapl_add_package(int cpu) | |
1434 | { | |
1435 | int ret = 0; | |
1436 | int phy_package_id; | |
1437 | struct rapl_package *rp; | |
1438 | ||
1439 | phy_package_id = topology_physical_package_id(cpu); | |
1440 | rp = kzalloc(sizeof(struct rapl_package), GFP_KERNEL); | |
1441 | if (!rp) | |
1442 | return -ENOMEM; | |
1443 | ||
1444 | /* add the new package to the list */ | |
1445 | rp->id = phy_package_id; | |
1446 | rp->nr_cpus = 1; | |
323ee64a JP |
1447 | rp->lead_cpu = cpu; |
1448 | ||
2d281d81 JP |
1449 | /* check if the package contains valid domains */ |
1450 | if (rapl_detect_domains(rp, cpu) || | |
3c2c0845 | 1451 | rapl_defaults->check_unit(rp, cpu)) { |
2d281d81 JP |
1452 | ret = -ENODEV; |
1453 | goto err_free_package; | |
1454 | } | |
1455 | if (!rapl_package_register_powercap(rp)) { | |
1456 | INIT_LIST_HEAD(&rp->plist); | |
1457 | list_add(&rp->plist, &rapl_packages); | |
1458 | return ret; | |
1459 | } | |
1460 | ||
1461 | err_free_package: | |
1462 | kfree(rp->domains); | |
1463 | kfree(rp); | |
1464 | ||
1465 | return ret; | |
1466 | } | |
1467 | ||
1468 | /* Handles CPU hotplug on multi-socket systems. | |
1469 | * If a CPU goes online as the first CPU of the physical package | |
1470 | * we add the RAPL package to the system. Similarly, when the last | |
1471 | * CPU of the package is removed, we remove the RAPL package and its | |
1472 | * associated domains. Cooling devices are handled accordingly at | |
1473 | * per-domain level. | |
1474 | */ | |
1475 | static int rapl_cpu_callback(struct notifier_block *nfb, | |
1476 | unsigned long action, void *hcpu) | |
1477 | { | |
1478 | unsigned long cpu = (unsigned long)hcpu; | |
1479 | int phy_package_id; | |
1480 | struct rapl_package *rp; | |
323ee64a | 1481 | int lead_cpu; |
2d281d81 JP |
1482 | |
1483 | phy_package_id = topology_physical_package_id(cpu); | |
1484 | switch (action) { | |
1485 | case CPU_ONLINE: | |
1486 | case CPU_ONLINE_FROZEN: | |
1487 | case CPU_DOWN_FAILED: | |
1488 | case CPU_DOWN_FAILED_FROZEN: | |
1489 | rp = find_package_by_id(phy_package_id); | |
1490 | if (rp) | |
1491 | ++rp->nr_cpus; | |
1492 | else | |
1493 | rapl_add_package(cpu); | |
1494 | break; | |
1495 | case CPU_DOWN_PREPARE: | |
1496 | case CPU_DOWN_PREPARE_FROZEN: | |
1497 | rp = find_package_by_id(phy_package_id); | |
1498 | if (!rp) | |
1499 | break; | |
1500 | if (--rp->nr_cpus == 0) | |
1501 | rapl_remove_package(rp); | |
323ee64a JP |
1502 | else if (cpu == rp->lead_cpu) { |
1503 | /* choose another active cpu in the package */ | |
1504 | lead_cpu = cpumask_any_but(topology_core_cpumask(cpu), cpu); | |
1505 | if (lead_cpu < nr_cpu_ids) | |
1506 | rp->lead_cpu = lead_cpu; | |
1507 | else /* should never go here */ | |
1508 | pr_err("no active cpu available for package %d\n", | |
1509 | phy_package_id); | |
1510 | } | |
2d281d81 JP |
1511 | } |
1512 | ||
1513 | return NOTIFY_OK; | |
1514 | } | |
1515 | ||
1516 | static struct notifier_block rapl_cpu_notifier = { | |
1517 | .notifier_call = rapl_cpu_callback, | |
1518 | }; | |
1519 | ||
1520 | static int __init rapl_init(void) | |
1521 | { | |
1522 | int ret = 0; | |
087e9cba | 1523 | const struct x86_cpu_id *id; |
2d281d81 | 1524 | |
087e9cba JP |
1525 | id = x86_match_cpu(rapl_ids); |
1526 | if (!id) { | |
2d281d81 JP |
1527 | pr_err("driver does not support CPU family %d model %d\n", |
1528 | boot_cpu_data.x86, boot_cpu_data.x86_model); | |
1529 | ||
1530 | return -ENODEV; | |
1531 | } | |
009f225e | 1532 | |
087e9cba JP |
1533 | rapl_defaults = (struct rapl_defaults *)id->driver_data; |
1534 | ||
009f225e SB |
1535 | cpu_notifier_register_begin(); |
1536 | ||
2d281d81 JP |
1537 | /* prevent CPU hotplug during detection */ |
1538 | get_online_cpus(); | |
1539 | ret = rapl_detect_topology(); | |
1540 | if (ret) | |
1541 | goto done; | |
1542 | ||
1543 | if (rapl_register_powercap()) { | |
1544 | rapl_cleanup_data(); | |
1545 | ret = -ENODEV; | |
1546 | goto done; | |
1547 | } | |
009f225e | 1548 | __register_hotcpu_notifier(&rapl_cpu_notifier); |
2d281d81 JP |
1549 | done: |
1550 | put_online_cpus(); | |
009f225e | 1551 | cpu_notifier_register_done(); |
2d281d81 JP |
1552 | |
1553 | return ret; | |
1554 | } | |
1555 | ||
1556 | static void __exit rapl_exit(void) | |
1557 | { | |
009f225e | 1558 | cpu_notifier_register_begin(); |
2d281d81 | 1559 | get_online_cpus(); |
009f225e | 1560 | __unregister_hotcpu_notifier(&rapl_cpu_notifier); |
2d281d81 JP |
1561 | rapl_unregister_powercap(); |
1562 | rapl_cleanup_data(); | |
1563 | put_online_cpus(); | |
009f225e | 1564 | cpu_notifier_register_done(); |
2d281d81 JP |
1565 | } |
1566 | ||
1567 | module_init(rapl_init); | |
1568 | module_exit(rapl_exit); | |
1569 | ||
1570 | MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit)"); | |
1571 | MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>"); | |
1572 | MODULE_LICENSE("GPL v2"); |