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powercap / RAPL: fix build dependency on iosf_mbi
[deliverable/linux.git] / drivers / powercap / intel_rapl.c
CommitLineData
2d281d81
JP		 1/*
2 * Intel Running Average Power Limit (RAPL) Driver
3 * Copyright (c) 2013, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.
16 *
17 */
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/list.h>
23#include <linux/types.h>
24#include <linux/device.h>
25#include <linux/slab.h>
26#include <linux/log2.h>
27#include <linux/bitmap.h>
28#include <linux/delay.h>
29#include <linux/sysfs.h>
30#include <linux/cpu.h>
31#include <linux/powercap.h>
3c2c0845 32#include <asm/iosf_mbi.h>
2d281d81
JP		 33
34#include <asm/processor.h>
35#include <asm/cpu_device_id.h>
36
37/* bitmasks for RAPL MSRs, used by primitive access functions */
38#define ENERGY_STATUS_MASK 0xffffffff
39
40#define POWER_LIMIT1_MASK 0x7FFF
41#define POWER_LIMIT1_ENABLE BIT(15)
42#define POWER_LIMIT1_CLAMP BIT(16)
43
44#define POWER_LIMIT2_MASK (0x7FFFULL<<32)
45#define POWER_LIMIT2_ENABLE BIT_ULL(47)
46#define POWER_LIMIT2_CLAMP BIT_ULL(48)
47#define POWER_PACKAGE_LOCK BIT_ULL(63)
48#define POWER_PP_LOCK BIT(31)
49
50#define TIME_WINDOW1_MASK (0x7FULL<<17)
51#define TIME_WINDOW2_MASK (0x7FULL<<49)
52
53#define POWER_UNIT_OFFSET 0
54#define POWER_UNIT_MASK 0x0F
55
56#define ENERGY_UNIT_OFFSET 0x08
57#define ENERGY_UNIT_MASK 0x1F00
58
59#define TIME_UNIT_OFFSET 0x10
60#define TIME_UNIT_MASK 0xF0000
61
62#define POWER_INFO_MAX_MASK (0x7fffULL<<32)
63#define POWER_INFO_MIN_MASK (0x7fffULL<<16)
64#define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48)
65#define POWER_INFO_THERMAL_SPEC_MASK 0x7fff
66
67#define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff
68#define PP_POLICY_MASK 0x1F
69
70/* Non HW constants */
71#define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */
72#define RAPL_PRIMITIVE_DUMMY BIT(2)
73
2d281d81
JP		 74#define TIME_WINDOW_MAX_MSEC 40000
75#define TIME_WINDOW_MIN_MSEC 250
76
77enum unit_type {
78 ARBITRARY_UNIT, /* no translation */
79 POWER_UNIT,
80 ENERGY_UNIT,
81 TIME_UNIT,
82};
83
84enum rapl_domain_type {
85 RAPL_DOMAIN_PACKAGE, /* entire package/socket */
86 RAPL_DOMAIN_PP0, /* core power plane */
87 RAPL_DOMAIN_PP1, /* graphics uncore */
88 RAPL_DOMAIN_DRAM,/* DRAM control_type */
89 RAPL_DOMAIN_MAX,
90};
91
92enum rapl_domain_msr_id {
93 RAPL_DOMAIN_MSR_LIMIT,
94 RAPL_DOMAIN_MSR_STATUS,
95 RAPL_DOMAIN_MSR_PERF,
96 RAPL_DOMAIN_MSR_POLICY,
97 RAPL_DOMAIN_MSR_INFO,
98 RAPL_DOMAIN_MSR_MAX,
99};
100
101/* per domain data, some are optional */
102enum rapl_primitives {
103 ENERGY_COUNTER,
104 POWER_LIMIT1,
105 POWER_LIMIT2,
106 FW_LOCK,
107
108 PL1_ENABLE, /* power limit 1, aka long term */
109 PL1_CLAMP, /* allow frequency to go below OS request */
110 PL2_ENABLE, /* power limit 2, aka short term, instantaneous */
111 PL2_CLAMP,
112
113 TIME_WINDOW1, /* long term */
114 TIME_WINDOW2, /* short term */
115 THERMAL_SPEC_POWER,
116 MAX_POWER,
117
118 MIN_POWER,
119 MAX_TIME_WINDOW,
120 THROTTLED_TIME,
121 PRIORITY_LEVEL,
122
123 /* below are not raw primitive data */
124 AVERAGE_POWER,
125 NR_RAPL_PRIMITIVES,
126};
127
128#define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2)
129
130/* Can be expanded to include events, etc.*/
131struct rapl_domain_data {
132 u64 primitives[NR_RAPL_PRIMITIVES];
133 unsigned long timestamp;
134};
135
136
137#define DOMAIN_STATE_INACTIVE BIT(0)
138#define DOMAIN_STATE_POWER_LIMIT_SET BIT(1)
139#define DOMAIN_STATE_BIOS_LOCKED BIT(2)
140
141#define NR_POWER_LIMITS (2)
142struct rapl_power_limit {
143 struct powercap_zone_constraint *constraint;
144 int prim_id; /* primitive ID used to enable */
145 struct rapl_domain *domain;
146 const char *name;
147};
148
149static const char pl1_name[] = "long_term";
150static const char pl2_name[] = "short_term";
151
152struct rapl_domain {
153 const char *name;
154 enum rapl_domain_type id;
155 int msrs[RAPL_DOMAIN_MSR_MAX];
156 struct powercap_zone power_zone;
157 struct rapl_domain_data rdd;
158 struct rapl_power_limit rpl[NR_POWER_LIMITS];
159 u64 attr_map; /* track capabilities */
160 unsigned int state;
161 int package_id;
162};
163#define power_zone_to_rapl_domain(_zone) \
164 container_of(_zone, struct rapl_domain, power_zone)
165
166
167/* Each physical package contains multiple domains, these are the common
168 * data across RAPL domains within a package.
169 */
170struct rapl_package {
171 unsigned int id; /* physical package/socket id */
172 unsigned int nr_domains;
173 unsigned long domain_map; /* bit map of active domains */
3c2c0845
JP		 174 unsigned int power_unit;
175 unsigned int energy_unit;
176 unsigned int time_unit;
2d281d81
JP		 177 struct rapl_domain *domains; /* array of domains, sized at runtime */
178 struct powercap_zone *power_zone; /* keep track of parent zone */
179 int nr_cpus; /* active cpus on the package, topology info is lost during
180 * cpu hotplug. so we have to track ourselves.
181 */
182 unsigned long power_limit_irq; /* keep track of package power limit
183 * notify interrupt enable status.
184 */
185 struct list_head plist;
186};
087e9cba
JP		 187
188struct rapl_defaults {
189 int (*check_unit)(struct rapl_package *rp, int cpu);
190 void (*set_floor_freq)(struct rapl_domain *rd, bool mode);
191 u64 (*compute_time_window)(struct rapl_package *rp, u64 val,
192 bool to_raw);
193};
194static struct rapl_defaults *rapl_defaults;
195
3c2c0845
JP		 196/* Sideband MBI registers */
197#define IOSF_CPU_POWER_BUDGET_CTL (0x2)
198
2d281d81
JP		 199#define PACKAGE_PLN_INT_SAVED BIT(0)
200#define MAX_PRIM_NAME (32)
201
202/* per domain data. used to describe individual knobs such that access function
203 * can be consolidated into one instead of many inline functions.
204 */
205struct rapl_primitive_info {
206 const char *name;
207 u64 mask;
208 int shift;
209 enum rapl_domain_msr_id id;
210 enum unit_type unit;
211 u32 flag;
212};
213
214#define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \
215 .name = #p, \
216 .mask = m, \
217 .shift = s, \
218 .id = i, \
219 .unit = u, \
220 .flag = f \
221 }
222
223static void rapl_init_domains(struct rapl_package *rp);
224static int rapl_read_data_raw(struct rapl_domain *rd,
225 enum rapl_primitives prim,
226 bool xlate, u64 *data);
227static int rapl_write_data_raw(struct rapl_domain *rd,
228 enum rapl_primitives prim,
229 unsigned long long value);
230static u64 rapl_unit_xlate(int package, enum unit_type type, u64 value,
231 int to_raw);
232static void package_power_limit_irq_save(int package_id);
233
234static LIST_HEAD(rapl_packages); /* guarded by CPU hotplug lock */
235
236static const char * const rapl_domain_names[] = {
237 "package",
238 "core",
239 "uncore",
240 "dram",
241};
242
243static struct powercap_control_type *control_type; /* PowerCap Controller */
244
245/* caller to ensure CPU hotplug lock is held */
246static struct rapl_package *find_package_by_id(int id)
247{
248 struct rapl_package *rp;
249
250 list_for_each_entry(rp, &rapl_packages, plist) {
251 if (rp->id == id)
252 return rp;
253 }
254
255 return NULL;
256}
257
258/* caller to ensure CPU hotplug lock is held */
259static int find_active_cpu_on_package(int package_id)
260{
261 int i;
262
263 for_each_online_cpu(i) {
264 if (topology_physical_package_id(i) == package_id)
265 return i;
266 }
267 /* all CPUs on this package are offline */
268
269 return -ENODEV;
270}
271
272/* caller must hold cpu hotplug lock */
273static void rapl_cleanup_data(void)
274{
275 struct rapl_package *p, *tmp;
276
277 list_for_each_entry_safe(p, tmp, &rapl_packages, plist) {
278 kfree(p->domains);
279 list_del(&p->plist);
280 kfree(p);
281 }
282}
283
284static int get_energy_counter(struct powercap_zone *power_zone, u64 *energy_raw)
285{
286 struct rapl_domain *rd;
287 u64 energy_now;
288
289 /* prevent CPU hotplug, make sure the RAPL domain does not go
290 * away while reading the counter.
291 */
292 get_online_cpus();
293 rd = power_zone_to_rapl_domain(power_zone);
294
295 if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now)) {
296 *energy_raw = energy_now;
297 put_online_cpus();
298
299 return 0;
300 }
301 put_online_cpus();
302
303 return -EIO;
304}
305
306static int get_max_energy_counter(struct powercap_zone *pcd_dev, u64 *energy)
307{
308 *energy = rapl_unit_xlate(0, ENERGY_UNIT, ENERGY_STATUS_MASK, 0);
309 return 0;
310}
311
312static int release_zone(struct powercap_zone *power_zone)
313{
314 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
315 struct rapl_package *rp;
316
317 /* package zone is the last zone of a package, we can free
318 * memory here since all children has been unregistered.
319 */
320 if (rd->id == RAPL_DOMAIN_PACKAGE) {
321 rp = find_package_by_id(rd->package_id);
322 if (!rp) {
323 dev_warn(&power_zone->dev, "no package id %s\n",
324 rd->name);
325 return -ENODEV;
326 }
327 kfree(rd);
328 rp->domains = NULL;
329 }
330
331 return 0;
332
333}
334
335static int find_nr_power_limit(struct rapl_domain *rd)
336{
337 int i;
338
339 for (i = 0; i < NR_POWER_LIMITS; i++) {
340 if (rd->rpl[i].name == NULL)
341 break;
342 }
343
344 return i;
345}
346
347static int set_domain_enable(struct powercap_zone *power_zone, bool mode)
348{
349 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
2d281d81
JP		 350
351 if (rd->state & DOMAIN_STATE_BIOS_LOCKED)
352 return -EACCES;
3c2c0845 353
2d281d81 354 get_online_cpus();
2d281d81 355 rapl_write_data_raw(rd, PL1_ENABLE, mode);
3c2c0845 356 rapl_defaults->set_floor_freq(rd, mode);
2d281d81
JP		 357 put_online_cpus();
358
359 return 0;
360}
361
362static int get_domain_enable(struct powercap_zone *power_zone, bool *mode)
363{
364 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
365 u64 val;
366
367 if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
368 *mode = false;
369 return 0;
370 }
371 get_online_cpus();
372 if (rapl_read_data_raw(rd, PL1_ENABLE, true, &val)) {
373 put_online_cpus();
374 return -EIO;
375 }
376 *mode = val;
377 put_online_cpus();
378
379 return 0;
380}
381
382/* per RAPL domain ops, in the order of rapl_domain_type */
383static struct powercap_zone_ops zone_ops[] = {
384 /* RAPL_DOMAIN_PACKAGE */
385 {
386 .get_energy_uj = get_energy_counter,
387 .get_max_energy_range_uj = get_max_energy_counter,
388 .release = release_zone,
389 .set_enable = set_domain_enable,
390 .get_enable = get_domain_enable,
391 },
392 /* RAPL_DOMAIN_PP0 */
393 {
394 .get_energy_uj = get_energy_counter,
395 .get_max_energy_range_uj = get_max_energy_counter,
396 .release = release_zone,
397 .set_enable = set_domain_enable,
398 .get_enable = get_domain_enable,
399 },
400 /* RAPL_DOMAIN_PP1 */
401 {
402 .get_energy_uj = get_energy_counter,
403 .get_max_energy_range_uj = get_max_energy_counter,
404 .release = release_zone,
405 .set_enable = set_domain_enable,
406 .get_enable = get_domain_enable,
407 },
408 /* RAPL_DOMAIN_DRAM */
409 {
410 .get_energy_uj = get_energy_counter,
411 .get_max_energy_range_uj = get_max_energy_counter,
412 .release = release_zone,
413 .set_enable = set_domain_enable,
414 .get_enable = get_domain_enable,
415 },
416};
417
418static int set_power_limit(struct powercap_zone *power_zone, int id,
419 u64 power_limit)
420{
421 struct rapl_domain *rd;
422 struct rapl_package *rp;
423 int ret = 0;
424
425 get_online_cpus();
426 rd = power_zone_to_rapl_domain(power_zone);
427 rp = find_package_by_id(rd->package_id);
428 if (!rp) {
429 ret = -ENODEV;
430 goto set_exit;
431 }
432
433 if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
434 dev_warn(&power_zone->dev, "%s locked by BIOS, monitoring only\n",
435 rd->name);
436 ret = -EACCES;
437 goto set_exit;
438 }
439
440 switch (rd->rpl[id].prim_id) {
441 case PL1_ENABLE:
442 rapl_write_data_raw(rd, POWER_LIMIT1, power_limit);
443 break;
444 case PL2_ENABLE:
445 rapl_write_data_raw(rd, POWER_LIMIT2, power_limit);
446 break;
447 default:
448 ret = -EINVAL;
449 }
450 if (!ret)
451 package_power_limit_irq_save(rd->package_id);
452set_exit:
453 put_online_cpus();
454 return ret;
455}
456
457static int get_current_power_limit(struct powercap_zone *power_zone, int id,
458 u64 *data)
459{
460 struct rapl_domain *rd;
461 u64 val;
462 int prim;
463 int ret = 0;
464
465 get_online_cpus();
466 rd = power_zone_to_rapl_domain(power_zone);
467 switch (rd->rpl[id].prim_id) {
468 case PL1_ENABLE:
469 prim = POWER_LIMIT1;
470 break;
471 case PL2_ENABLE:
472 prim = POWER_LIMIT2;
473 break;
474 default:
475 put_online_cpus();
476 return -EINVAL;
477 }
478 if (rapl_read_data_raw(rd, prim, true, &val))
479 ret = -EIO;
480 else
481 *data = val;
482
483 put_online_cpus();
484
485 return ret;
486}
487
488static int set_time_window(struct powercap_zone *power_zone, int id,
489 u64 window)
490{
491 struct rapl_domain *rd;
492 int ret = 0;
493
494 get_online_cpus();
495 rd = power_zone_to_rapl_domain(power_zone);
496 switch (rd->rpl[id].prim_id) {
497 case PL1_ENABLE:
498 rapl_write_data_raw(rd, TIME_WINDOW1, window);
499 break;
500 case PL2_ENABLE:
501 rapl_write_data_raw(rd, TIME_WINDOW2, window);
502 break;
503 default:
504 ret = -EINVAL;
505 }
506 put_online_cpus();
507 return ret;
508}
509
510static int get_time_window(struct powercap_zone *power_zone, int id, u64 *data)
511{
512 struct rapl_domain *rd;
513 u64 val;
514 int ret = 0;
515
516 get_online_cpus();
517 rd = power_zone_to_rapl_domain(power_zone);
518 switch (rd->rpl[id].prim_id) {
519 case PL1_ENABLE:
520 ret = rapl_read_data_raw(rd, TIME_WINDOW1, true, &val);
521 break;
522 case PL2_ENABLE:
523 ret = rapl_read_data_raw(rd, TIME_WINDOW2, true, &val);
524 break;
525 default:
526 put_online_cpus();
527 return -EINVAL;
528 }
529 if (!ret)
530 *data = val;
531 put_online_cpus();
532
533 return ret;
534}
535
536static const char *get_constraint_name(struct powercap_zone *power_zone, int id)
537{
538 struct rapl_power_limit *rpl;
539 struct rapl_domain *rd;
540
541 rd = power_zone_to_rapl_domain(power_zone);
542 rpl = (struct rapl_power_limit *) &rd->rpl[id];
543
544 return rpl->name;
545}
546
547
548static int get_max_power(struct powercap_zone *power_zone, int id,
549 u64 *data)
550{
551 struct rapl_domain *rd;
552 u64 val;
553 int prim;
554 int ret = 0;
555
556 get_online_cpus();
557 rd = power_zone_to_rapl_domain(power_zone);
558 switch (rd->rpl[id].prim_id) {
559 case PL1_ENABLE:
560 prim = THERMAL_SPEC_POWER;
561 break;
562 case PL2_ENABLE:
563 prim = MAX_POWER;
564 break;
565 default:
566 put_online_cpus();
567 return -EINVAL;
568 }
569 if (rapl_read_data_raw(rd, prim, true, &val))
570 ret = -EIO;
571 else
572 *data = val;
573
574 put_online_cpus();
575
576 return ret;
577}
578
579static struct powercap_zone_constraint_ops constraint_ops = {
580 .set_power_limit_uw = set_power_limit,
581 .get_power_limit_uw = get_current_power_limit,
582 .set_time_window_us = set_time_window,
583 .get_time_window_us = get_time_window,
584 .get_max_power_uw = get_max_power,
585 .get_name = get_constraint_name,
586};
587
588/* called after domain detection and package level data are set */
589static void rapl_init_domains(struct rapl_package *rp)
590{
591 int i;
592 struct rapl_domain *rd = rp->domains;
593
594 for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
595 unsigned int mask = rp->domain_map & (1 << i);
596 switch (mask) {
597 case BIT(RAPL_DOMAIN_PACKAGE):
598 rd->name = rapl_domain_names[RAPL_DOMAIN_PACKAGE];
599 rd->id = RAPL_DOMAIN_PACKAGE;
600 rd->msrs[0] = MSR_PKG_POWER_LIMIT;
601 rd->msrs[1] = MSR_PKG_ENERGY_STATUS;
602 rd->msrs[2] = MSR_PKG_PERF_STATUS;
603 rd->msrs[3] = 0;
604 rd->msrs[4] = MSR_PKG_POWER_INFO;
605 rd->rpl[0].prim_id = PL1_ENABLE;
606 rd->rpl[0].name = pl1_name;
607 rd->rpl[1].prim_id = PL2_ENABLE;
608 rd->rpl[1].name = pl2_name;
609 break;
610 case BIT(RAPL_DOMAIN_PP0):
611 rd->name = rapl_domain_names[RAPL_DOMAIN_PP0];
612 rd->id = RAPL_DOMAIN_PP0;
613 rd->msrs[0] = MSR_PP0_POWER_LIMIT;
614 rd->msrs[1] = MSR_PP0_ENERGY_STATUS;
615 rd->msrs[2] = 0;
616 rd->msrs[3] = MSR_PP0_POLICY;
617 rd->msrs[4] = 0;
618 rd->rpl[0].prim_id = PL1_ENABLE;
619 rd->rpl[0].name = pl1_name;
620 break;
621 case BIT(RAPL_DOMAIN_PP1):
622 rd->name = rapl_domain_names[RAPL_DOMAIN_PP1];
623 rd->id = RAPL_DOMAIN_PP1;
624 rd->msrs[0] = MSR_PP1_POWER_LIMIT;
625 rd->msrs[1] = MSR_PP1_ENERGY_STATUS;
626 rd->msrs[2] = 0;
627 rd->msrs[3] = MSR_PP1_POLICY;
628 rd->msrs[4] = 0;
629 rd->rpl[0].prim_id = PL1_ENABLE;
630 rd->rpl[0].name = pl1_name;
631 break;
632 case BIT(RAPL_DOMAIN_DRAM):
633 rd->name = rapl_domain_names[RAPL_DOMAIN_DRAM];
634 rd->id = RAPL_DOMAIN_DRAM;
635 rd->msrs[0] = MSR_DRAM_POWER_LIMIT;
636 rd->msrs[1] = MSR_DRAM_ENERGY_STATUS;
637 rd->msrs[2] = MSR_DRAM_PERF_STATUS;
638 rd->msrs[3] = 0;
639 rd->msrs[4] = MSR_DRAM_POWER_INFO;
640 rd->rpl[0].prim_id = PL1_ENABLE;
641 rd->rpl[0].name = pl1_name;
642 break;
643 }
644 if (mask) {
645 rd->package_id = rp->id;
646 rd++;
647 }
648 }
649}
650
651static u64 rapl_unit_xlate(int package, enum unit_type type, u64 value,
652 int to_raw)
653{
3c2c0845 654 u64 units = 1;
2d281d81
JP		 655 struct rapl_package *rp;
656
657 rp = find_package_by_id(package);
658 if (!rp)
659 return value;
660
661 switch (type) {
662 case POWER_UNIT:
3c2c0845 663 units = rp->power_unit;
2d281d81
JP		 664 break;
665 case ENERGY_UNIT:
3c2c0845 666 units = rp->energy_unit;
2d281d81
JP		 667 break;
668 case TIME_UNIT:
3c2c0845 669 return rapl_defaults->compute_time_window(rp, value, to_raw);
2d281d81
JP		 670 case ARBITRARY_UNIT:
671 default:
672 return value;
673 };
674
675 if (to_raw)
3c2c0845
JP		 676 return div64_u64(value, units);
677
678 value *= units;
679
680 return value;
2d281d81
JP		 681}
682
683/* in the order of enum rapl_primitives */
684static struct rapl_primitive_info rpi[] = {
685 /* name, mask, shift, msr index, unit divisor */
686 PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
687 RAPL_DOMAIN_MSR_STATUS, ENERGY_UNIT, 0),
688 PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,
689 RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0),
690 PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32,
691 RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0),
692 PRIMITIVE_INFO_INIT(FW_LOCK, POWER_PP_LOCK, 31,
693 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
694 PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15,
695 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
696 PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16,
697 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
698 PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47,
699 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
700 PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48,
701 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
702 PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17,
703 RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0),
704 PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49,
705 RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0),
706 PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, POWER_INFO_THERMAL_SPEC_MASK,
707 0, RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
708 PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32,
709 RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
710 PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16,
711 RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
712 PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, POWER_INFO_MAX_TIME_WIN_MASK, 48,
713 RAPL_DOMAIN_MSR_INFO, TIME_UNIT, 0),
714 PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0,
715 RAPL_DOMAIN_MSR_PERF, TIME_UNIT, 0),
716 PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0,
717 RAPL_DOMAIN_MSR_POLICY, ARBITRARY_UNIT, 0),
718 /* non-hardware */
719 PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT,
720 RAPL_PRIMITIVE_DERIVED),
721 {NULL, 0, 0, 0},
722};
723
724/* Read primitive data based on its related struct rapl_primitive_info.
725 * if xlate flag is set, return translated data based on data units, i.e.
726 * time, energy, and power.
727 * RAPL MSRs are non-architectual and are laid out not consistently across
728 * domains. Here we use primitive info to allow writing consolidated access
729 * functions.
730 * For a given primitive, it is processed by MSR mask and shift. Unit conversion
731 * is pre-assigned based on RAPL unit MSRs read at init time.
732 * 63-------------------------- 31--------------------------- 0
733 * | xxxxx (mask) |
734 * | |<- shift ----------------|
735 * 63-------------------------- 31--------------------------- 0
736 */
737static int rapl_read_data_raw(struct rapl_domain *rd,
738 enum rapl_primitives prim,
739 bool xlate, u64 *data)
740{
741 u64 value, final;
742 u32 msr;
743 struct rapl_primitive_info *rp = &rpi[prim];
744 int cpu;
745
746 if (!rp->name || rp->flag & RAPL_PRIMITIVE_DUMMY)
747 return -EINVAL;
748
749 msr = rd->msrs[rp->id];
750 if (!msr)
751 return -EINVAL;
752 /* use physical package id to look up active cpus */
753 cpu = find_active_cpu_on_package(rd->package_id);
754 if (cpu < 0)
755 return cpu;
756
757 /* special-case package domain, which uses a different bit*/
758 if (prim == FW_LOCK && rd->id == RAPL_DOMAIN_PACKAGE) {
759 rp->mask = POWER_PACKAGE_LOCK;
760 rp->shift = 63;
761 }
762 /* non-hardware data are collected by the polling thread */
763 if (rp->flag & RAPL_PRIMITIVE_DERIVED) {
764 *data = rd->rdd.primitives[prim];
765 return 0;
766 }
767
768 if (rdmsrl_safe_on_cpu(cpu, msr, &value)) {
769 pr_debug("failed to read msr 0x%x on cpu %d\n", msr, cpu);
770 return -EIO;
771 }
772
773 final = value & rp->mask;
774 final = final >> rp->shift;
775 if (xlate)
776 *data = rapl_unit_xlate(rd->package_id, rp->unit, final, 0);
777 else
778 *data = final;
779
780 return 0;
781}
782
783/* Similar use of primitive info in the read counterpart */
784static int rapl_write_data_raw(struct rapl_domain *rd,
785 enum rapl_primitives prim,
786 unsigned long long value)
787{
788 u64 msr_val;
789 u32 msr;
790 struct rapl_primitive_info *rp = &rpi[prim];
791 int cpu;
792
793 cpu = find_active_cpu_on_package(rd->package_id);
794 if (cpu < 0)
795 return cpu;
796 msr = rd->msrs[rp->id];
797 if (rdmsrl_safe_on_cpu(cpu, msr, &msr_val)) {
798 dev_dbg(&rd->power_zone.dev,
799 "failed to read msr 0x%x on cpu %d\n", msr, cpu);
800 return -EIO;
801 }
802 value = rapl_unit_xlate(rd->package_id, rp->unit, value, 1);
803 msr_val &= ~rp->mask;
804 msr_val |= value << rp->shift;
805 if (wrmsrl_safe_on_cpu(cpu, msr, msr_val)) {
806 dev_dbg(&rd->power_zone.dev,
807 "failed to write msr 0x%x on cpu %d\n", msr, cpu);
808 return -EIO;
809 }
810
811 return 0;
812}
813
3c2c0845
JP		 814/*
815 * Raw RAPL data stored in MSRs are in certain scales. We need to
816 * convert them into standard units based on the units reported in
817 * the RAPL unit MSRs. This is specific to CPUs as the method to
818 * calculate units differ on different CPUs.
819 * We convert the units to below format based on CPUs.
820 * i.e.
821 * energy unit: microJoules : Represented in microJoules by default
822 * power unit : microWatts : Represented in milliWatts by default
823 * time unit : microseconds: Represented in seconds by default
824 */
825static int rapl_check_unit_core(struct rapl_package *rp, int cpu)
2d281d81
JP		 826{
827 u64 msr_val;
828 u32 value;
829
830 if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) {
831 pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n",
832 MSR_RAPL_POWER_UNIT, cpu);
833 return -ENODEV;
834 }
835
2d281d81 836 value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
3c2c0845 837 rp->energy_unit = 1000000 / (1 << value);
2d281d81
JP		 838
839 value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
3c2c0845 840 rp->power_unit = 1000000 / (1 << value);
2d281d81
JP		 841
842 value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
3c2c0845 843 rp->time_unit = 1000000 / (1 << value);
2d281d81 844
3c2c0845
JP		 845 pr_debug("Core CPU package %d energy=%duJ, time=%dus, power=%duW\n",
846 rp->id, rp->energy_unit, rp->time_unit, rp->power_unit);
2d281d81
JP		 847
848 return 0;
849}
850
3c2c0845
JP		 851static int rapl_check_unit_atom(struct rapl_package *rp, int cpu)
852{
853 u64 msr_val;
854 u32 value;
855
856 if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) {
857 pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n",
858 MSR_RAPL_POWER_UNIT, cpu);
859 return -ENODEV;
860 }
861 value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
862 rp->energy_unit = 1 << value;
863
864 value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
865 rp->power_unit = (1 << value) * 1000;
866
867 value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
868 rp->time_unit = 1000000 / (1 << value);
869
870 pr_debug("Atom package %d energy=%duJ, time=%dus, power=%duW\n",
871 rp->id, rp->energy_unit, rp->time_unit, rp->power_unit);
872
873 return 0;
874}
875
876
2d281d81
JP		 877/* REVISIT:
878 * When package power limit is set artificially low by RAPL, LVT
879 * thermal interrupt for package power limit should be ignored
880 * since we are not really exceeding the real limit. The intention
881 * is to avoid excessive interrupts while we are trying to save power.
882 * A useful feature might be routing the package_power_limit interrupt
883 * to userspace via eventfd. once we have a usecase, this is simple
884 * to do by adding an atomic notifier.
885 */
886
887static void package_power_limit_irq_save(int package_id)
888{
889 u32 l, h = 0;
890 int cpu;
891 struct rapl_package *rp;
892
893 rp = find_package_by_id(package_id);
894 if (!rp)
895 return;
896
897 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
898 return;
899
900 cpu = find_active_cpu_on_package(package_id);
901 if (cpu < 0)
902 return;
903 /* save the state of PLN irq mask bit before disabling it */
904 rdmsr_safe_on_cpu(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
905 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) {
906 rp->power_limit_irq = l & PACKAGE_THERM_INT_PLN_ENABLE;
907 rp->power_limit_irq |= PACKAGE_PLN_INT_SAVED;
908 }
909 l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
910 wrmsr_on_cpu(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
911}
912
913/* restore per package power limit interrupt enable state */
914static void package_power_limit_irq_restore(int package_id)
915{
916 u32 l, h;
917 int cpu;
918 struct rapl_package *rp;
919
920 rp = find_package_by_id(package_id);
921 if (!rp)
922 return;
923
924 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
925 return;
926
927 cpu = find_active_cpu_on_package(package_id);
928 if (cpu < 0)
929 return;
930
931 /* irq enable state not saved, nothing to restore */
932 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED))
933 return;
934 rdmsr_safe_on_cpu(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
935
936 if (rp->power_limit_irq & PACKAGE_THERM_INT_PLN_ENABLE)
937 l |= PACKAGE_THERM_INT_PLN_ENABLE;
938 else
939 l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
940
941 wrmsr_on_cpu(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
942}
943
3c2c0845
JP		 944static void set_floor_freq_default(struct rapl_domain *rd, bool mode)
945{
946 int nr_powerlimit = find_nr_power_limit(rd);
947
948 /* always enable clamp such that p-state can go below OS requested
949 * range. power capping priority over guranteed frequency.
950 */
951 rapl_write_data_raw(rd, PL1_CLAMP, mode);
952
953 /* some domains have pl2 */
954 if (nr_powerlimit > 1) {
955 rapl_write_data_raw(rd, PL2_ENABLE, mode);
956 rapl_write_data_raw(rd, PL2_CLAMP, mode);
957 }
958}
959
960static void set_floor_freq_atom(struct rapl_domain *rd, bool enable)
961{
962 static u32 power_ctrl_orig_val;
963 u32 mdata;
964
965 if (!power_ctrl_orig_val)
966 iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_PMC_READ,
967 IOSF_CPU_POWER_BUDGET_CTL, &power_ctrl_orig_val);
968 mdata = power_ctrl_orig_val;
969 if (enable) {
970 mdata &= ~(0x7f << 8);
971 mdata |= 1 << 8;
972 }
973 iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_PMC_WRITE,
974 IOSF_CPU_POWER_BUDGET_CTL, mdata);
975}
976
977static u64 rapl_compute_time_window_core(struct rapl_package *rp, u64 value,
978 bool to_raw)
979{
980 u64 f, y; /* fraction and exp. used for time unit */
981
982 /*
983 * Special processing based on 2^Y*(1+F/4), refer
984 * to Intel Software Developer's manual Vol.3B: CH 14.9.3.
985 */
986 if (!to_raw) {
987 f = (value & 0x60) >> 5;
988 y = value & 0x1f;
989 value = (1 << y) * (4 + f) * rp->time_unit / 4;
990 } else {
991 do_div(value, rp->time_unit);
992 y = ilog2(value);
993 f = div64_u64(4 * (value - (1 << y)), 1 << y);
994 value = (y & 0x1f) | ((f & 0x3) << 5);
995 }
996 return value;
997}
998
999static u64 rapl_compute_time_window_atom(struct rapl_package *rp, u64 value,
1000 bool to_raw)
1001{
1002 /*
1003 * Atom time unit encoding is straight forward val * time_unit,
1004 * where time_unit is default to 1 sec. Never 0.
1005 */
1006 if (!to_raw)
1007 return (value) ? value *= rp->time_unit : rp->time_unit;
1008 else
1009 value = div64_u64(value, rp->time_unit);
1010
1011 return value;
1012}
1013
087e9cba 1014static const struct rapl_defaults rapl_defaults_core = {
3c2c0845
JP		 1015 .check_unit = rapl_check_unit_core,
1016 .set_floor_freq = set_floor_freq_default,
1017 .compute_time_window = rapl_compute_time_window_core,
087e9cba
JP		 1018};
1019
1020static const struct rapl_defaults rapl_defaults_atom = {
3c2c0845
JP		 1021 .check_unit = rapl_check_unit_atom,
1022 .set_floor_freq = set_floor_freq_atom,
1023 .compute_time_window = rapl_compute_time_window_atom,
087e9cba
JP		 1024};
1025
1026#define RAPL_CPU(_model, _ops) { \
1027 .vendor = X86_VENDOR_INTEL, \
1028 .family = 6, \
1029 .model = _model, \
1030 .driver_data = (kernel_ulong_t)&_ops, \
1031 }
1032
2d281d81 1033static const struct x86_cpu_id rapl_ids[] = {
087e9cba
JP		 1034 RAPL_CPU(0x2a, rapl_defaults_core),/* Sandy Bridge */
1035 RAPL_CPU(0x2d, rapl_defaults_core),/* Sandy Bridge EP */
1036 RAPL_CPU(0x37, rapl_defaults_atom),/* Valleyview */
1037 RAPL_CPU(0x3a, rapl_defaults_core),/* Ivy Bridge */
1038 RAPL_CPU(0x3c, rapl_defaults_core),/* Haswell */
1039 RAPL_CPU(0x3d, rapl_defaults_core),/* Broadwell */
1040 RAPL_CPU(0x3f, rapl_defaults_core),/* Haswell */
1041 RAPL_CPU(0x45, rapl_defaults_core),/* Haswell ULT */
74af752e
JP		 1042 RAPL_CPU(0x4C, rapl_defaults_atom),/* Braswell */
1043 RAPL_CPU(0x4A, rapl_defaults_atom),/* Tangier */
1044 RAPL_CPU(0x5A, rapl_defaults_atom),/* Annidale */
2d281d81
JP		 1045 {}
1046};
1047MODULE_DEVICE_TABLE(x86cpu, rapl_ids);
1048
1049/* read once for all raw primitive data for all packages, domains */
1050static void rapl_update_domain_data(void)
1051{
1052 int dmn, prim;
1053 u64 val;
1054 struct rapl_package *rp;
1055
1056 list_for_each_entry(rp, &rapl_packages, plist) {
1057 for (dmn = 0; dmn < rp->nr_domains; dmn++) {
1058 pr_debug("update package %d domain %s data\n", rp->id,
1059 rp->domains[dmn].name);
1060 /* exclude non-raw primitives */
1061 for (prim = 0; prim < NR_RAW_PRIMITIVES; prim++)
1062 if (!rapl_read_data_raw(&rp->domains[dmn], prim,
1063 rpi[prim].unit,
1064 &val))
1065 rp->domains[dmn].rdd.primitives[prim] =
1066 val;
1067 }
1068 }
1069
1070}
1071
1072static int rapl_unregister_powercap(void)
1073{
1074 struct rapl_package *rp;
1075 struct rapl_domain *rd, *rd_package = NULL;
1076
1077 /* unregister all active rapl packages from the powercap layer,
1078 * hotplug lock held
1079 */
1080 list_for_each_entry(rp, &rapl_packages, plist) {
1081 package_power_limit_irq_restore(rp->id);
1082
1083 for (rd = rp->domains; rd < rp->domains + rp->nr_domains;
1084 rd++) {
1085 pr_debug("remove package, undo power limit on %d: %s\n",
1086 rp->id, rd->name);
1087 rapl_write_data_raw(rd, PL1_ENABLE, 0);
1088 rapl_write_data_raw(rd, PL2_ENABLE, 0);
1089 rapl_write_data_raw(rd, PL1_CLAMP, 0);
1090 rapl_write_data_raw(rd, PL2_CLAMP, 0);
1091 if (rd->id == RAPL_DOMAIN_PACKAGE) {
1092 rd_package = rd;
1093 continue;
1094 }
1095 powercap_unregister_zone(control_type, &rd->power_zone);
1096 }
1097 /* do the package zone last */
1098 if (rd_package)
1099 powercap_unregister_zone(control_type,
1100 &rd_package->power_zone);
1101 }
1102 powercap_unregister_control_type(control_type);
1103
1104 return 0;
1105}
1106
1107static int rapl_package_register_powercap(struct rapl_package *rp)
1108{
1109 struct rapl_domain *rd;
1110 int ret = 0;
1111 char dev_name[17]; /* max domain name = 7 + 1 + 8 for int + 1 for null*/
1112 struct powercap_zone *power_zone = NULL;
1113 int nr_pl;
1114
1115 /* first we register package domain as the parent zone*/
1116 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1117 if (rd->id == RAPL_DOMAIN_PACKAGE) {
1118 nr_pl = find_nr_power_limit(rd);
1119 pr_debug("register socket %d package domain %s\n",
1120 rp->id, rd->name);
1121 memset(dev_name, 0, sizeof(dev_name));
1122 snprintf(dev_name, sizeof(dev_name), "%s-%d",
1123 rd->name, rp->id);
1124 power_zone = powercap_register_zone(&rd->power_zone,
1125 control_type,
1126 dev_name, NULL,
1127 &zone_ops[rd->id],
1128 nr_pl,
1129 &constraint_ops);
1130 if (IS_ERR(power_zone)) {
1131 pr_debug("failed to register package, %d\n",
1132 rp->id);
1133 ret = PTR_ERR(power_zone);
1134 goto exit_package;
1135 }
1136 /* track parent zone in per package/socket data */
1137 rp->power_zone = power_zone;
1138 /* done, only one package domain per socket */
1139 break;
1140 }
1141 }
1142 if (!power_zone) {
1143 pr_err("no package domain found, unknown topology!\n");
1144 ret = -ENODEV;
1145 goto exit_package;
1146 }
1147 /* now register domains as children of the socket/package*/
1148 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1149 if (rd->id == RAPL_DOMAIN_PACKAGE)
1150 continue;
1151 /* number of power limits per domain varies */
1152 nr_pl = find_nr_power_limit(rd);
1153 power_zone = powercap_register_zone(&rd->power_zone,
1154 control_type, rd->name,
1155 rp->power_zone,
1156 &zone_ops[rd->id], nr_pl,
1157 &constraint_ops);
1158
1159 if (IS_ERR(power_zone)) {
1160 pr_debug("failed to register power_zone, %d:%s:%s\n",
1161 rp->id, rd->name, dev_name);
1162 ret = PTR_ERR(power_zone);
1163 goto err_cleanup;
1164 }
1165 }
1166
1167exit_package:
1168 return ret;
1169err_cleanup:
1170 /* clean up previously initialized domains within the package if we
1171 * failed after the first domain setup.
1172 */
1173 while (--rd >= rp->domains) {
1174 pr_debug("unregister package %d domain %s\n", rp->id, rd->name);
1175 powercap_unregister_zone(control_type, &rd->power_zone);
1176 }
1177
1178 return ret;
1179}
1180
1181static int rapl_register_powercap(void)
1182{
1183 struct rapl_domain *rd;
1184 struct rapl_package *rp;
1185 int ret = 0;
1186
1187 control_type = powercap_register_control_type(NULL, "intel-rapl", NULL);
1188 if (IS_ERR(control_type)) {
1189 pr_debug("failed to register powercap control_type.\n");
1190 return PTR_ERR(control_type);
1191 }
1192 /* read the initial data */
1193 rapl_update_domain_data();
1194 list_for_each_entry(rp, &rapl_packages, plist)
1195 if (rapl_package_register_powercap(rp))
1196 goto err_cleanup_package;
1197 return ret;
1198
1199err_cleanup_package:
1200 /* clean up previously initialized packages */
1201 list_for_each_entry_continue_reverse(rp, &rapl_packages, plist) {
1202 for (rd = rp->domains; rd < rp->domains + rp->nr_domains;
1203 rd++) {
1204 pr_debug("unregister zone/package %d, %s domain\n",
1205 rp->id, rd->name);
1206 powercap_unregister_zone(control_type, &rd->power_zone);
1207 }
1208 }
1209
1210 return ret;
1211}
1212
1213static int rapl_check_domain(int cpu, int domain)
1214{
1215 unsigned msr;
9d31c676 1216 u64 val = 0;
2d281d81
JP		 1217
1218 switch (domain) {
1219 case RAPL_DOMAIN_PACKAGE:
1220 msr = MSR_PKG_ENERGY_STATUS;
1221 break;
1222 case RAPL_DOMAIN_PP0:
1223 msr = MSR_PP0_ENERGY_STATUS;
1224 break;
1225 case RAPL_DOMAIN_PP1:
1226 msr = MSR_PP1_ENERGY_STATUS;
1227 break;
1228 case RAPL_DOMAIN_DRAM:
1229 msr = MSR_DRAM_ENERGY_STATUS;
1230 break;
1231 default:
1232 pr_err("invalid domain id %d\n", domain);
1233 return -EINVAL;
1234 }
9d31c676
JP		 1235 /* make sure domain counters are available and contains non-zero
1236 * values, otherwise skip it.
7b874772 1237 */
9d31c676
JP		 1238 if (rdmsrl_safe_on_cpu(cpu, msr, &val) || !val)
1239 return -ENODEV;
2d281d81 1240
9d31c676 1241 return 0;
2d281d81
JP		 1242}
1243
1244/* Detect active and valid domains for the given CPU, caller must
1245 * ensure the CPU belongs to the targeted package and CPU hotlug is disabled.
1246 */
1247static int rapl_detect_domains(struct rapl_package *rp, int cpu)
1248{
1249 int i;
1250 int ret = 0;
1251 struct rapl_domain *rd;
1252 u64 locked;
1253
1254 for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
1255 /* use physical package id to read counters */
fcdf1797 1256 if (!rapl_check_domain(cpu, i)) {
2d281d81 1257 rp->domain_map |= 1 << i;
fcdf1797
JP		 1258 pr_info("Found RAPL domain %s\n", rapl_domain_names[i]);
1259 }
2d281d81
JP		 1260 }
1261 rp->nr_domains = bitmap_weight(&rp->domain_map, RAPL_DOMAIN_MAX);
1262 if (!rp->nr_domains) {
1263 pr_err("no valid rapl domains found in package %d\n", rp->id);
1264 ret = -ENODEV;
1265 goto done;
1266 }
1267 pr_debug("found %d domains on package %d\n", rp->nr_domains, rp->id);
1268
1269 rp->domains = kcalloc(rp->nr_domains + 1, sizeof(struct rapl_domain),
1270 GFP_KERNEL);
1271 if (!rp->domains) {
1272 ret = -ENOMEM;
1273 goto done;
1274 }
1275 rapl_init_domains(rp);
1276
1277 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1278 /* check if the domain is locked by BIOS */
1279 if (rapl_read_data_raw(rd, FW_LOCK, false, &locked)) {
1280 pr_info("RAPL package %d domain %s locked by BIOS\n",
1281 rp->id, rd->name);
1282 rd->state |= DOMAIN_STATE_BIOS_LOCKED;
1283 }
1284 }
1285
1286
1287done:
1288 return ret;
1289}
1290
1291static bool is_package_new(int package)
1292{
1293 struct rapl_package *rp;
1294
1295 /* caller prevents cpu hotplug, there will be no new packages added
1296 * or deleted while traversing the package list, no need for locking.
1297 */
1298 list_for_each_entry(rp, &rapl_packages, plist)
1299 if (package == rp->id)
1300 return false;
1301
1302 return true;
1303}
1304
1305/* RAPL interface can be made of a two-level hierarchy: package level and domain
1306 * level. We first detect the number of packages then domains of each package.
1307 * We have to consider the possiblity of CPU online/offline due to hotplug and
1308 * other scenarios.
1309 */
1310static int rapl_detect_topology(void)
1311{
1312 int i;
1313 int phy_package_id;
1314 struct rapl_package *new_package, *rp;
1315
1316 for_each_online_cpu(i) {
1317 phy_package_id = topology_physical_package_id(i);
1318 if (is_package_new(phy_package_id)) {
1319 new_package = kzalloc(sizeof(*rp), GFP_KERNEL);
1320 if (!new_package) {
1321 rapl_cleanup_data();
1322 return -ENOMEM;
1323 }
1324 /* add the new package to the list */
1325 new_package->id = phy_package_id;
1326 new_package->nr_cpus = 1;
1327
1328 /* check if the package contains valid domains */
1329 if (rapl_detect_domains(new_package, i) ||
3c2c0845 1330 rapl_defaults->check_unit(new_package, i)) {
2d281d81
JP		 1331 kfree(new_package->domains);
1332 kfree(new_package);
1333 /* free up the packages already initialized */
1334 rapl_cleanup_data();
1335 return -ENODEV;
1336 }
1337 INIT_LIST_HEAD(&new_package->plist);
1338 list_add(&new_package->plist, &rapl_packages);
1339 } else {
1340 rp = find_package_by_id(phy_package_id);
1341 if (rp)
1342 ++rp->nr_cpus;
1343 }
1344 }
1345
1346 return 0;
1347}
1348
1349/* called from CPU hotplug notifier, hotplug lock held */
1350static void rapl_remove_package(struct rapl_package *rp)
1351{
1352 struct rapl_domain *rd, *rd_package = NULL;
1353
1354 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1355 if (rd->id == RAPL_DOMAIN_PACKAGE) {
1356 rd_package = rd;
1357 continue;
1358 }
1359 pr_debug("remove package %d, %s domain\n", rp->id, rd->name);
1360 powercap_unregister_zone(control_type, &rd->power_zone);
1361 }
1362 /* do parent zone last */
1363 powercap_unregister_zone(control_type, &rd_package->power_zone);
1364 list_del(&rp->plist);
1365 kfree(rp);
1366}
1367
1368/* called from CPU hotplug notifier, hotplug lock held */
1369static int rapl_add_package(int cpu)
1370{
1371 int ret = 0;
1372 int phy_package_id;
1373 struct rapl_package *rp;
1374
1375 phy_package_id = topology_physical_package_id(cpu);
1376 rp = kzalloc(sizeof(struct rapl_package), GFP_KERNEL);
1377 if (!rp)
1378 return -ENOMEM;
1379
1380 /* add the new package to the list */
1381 rp->id = phy_package_id;
1382 rp->nr_cpus = 1;
1383 /* check if the package contains valid domains */
1384 if (rapl_detect_domains(rp, cpu) ||
3c2c0845 1385 rapl_defaults->check_unit(rp, cpu)) {
2d281d81
JP		 1386 ret = -ENODEV;
1387 goto err_free_package;
1388 }
1389 if (!rapl_package_register_powercap(rp)) {
1390 INIT_LIST_HEAD(&rp->plist);
1391 list_add(&rp->plist, &rapl_packages);
1392 return ret;
1393 }
1394
1395err_free_package:
1396 kfree(rp->domains);
1397 kfree(rp);
1398
1399 return ret;
1400}
1401
1402/* Handles CPU hotplug on multi-socket systems.
1403 * If a CPU goes online as the first CPU of the physical package
1404 * we add the RAPL package to the system. Similarly, when the last
1405 * CPU of the package is removed, we remove the RAPL package and its
1406 * associated domains. Cooling devices are handled accordingly at
1407 * per-domain level.
1408 */
1409static int rapl_cpu_callback(struct notifier_block *nfb,
1410 unsigned long action, void *hcpu)
1411{
1412 unsigned long cpu = (unsigned long)hcpu;
1413 int phy_package_id;
1414 struct rapl_package *rp;
1415
1416 phy_package_id = topology_physical_package_id(cpu);
1417 switch (action) {
1418 case CPU_ONLINE:
1419 case CPU_ONLINE_FROZEN:
1420 case CPU_DOWN_FAILED:
1421 case CPU_DOWN_FAILED_FROZEN:
1422 rp = find_package_by_id(phy_package_id);
1423 if (rp)
1424 ++rp->nr_cpus;
1425 else
1426 rapl_add_package(cpu);
1427 break;
1428 case CPU_DOWN_PREPARE:
1429 case CPU_DOWN_PREPARE_FROZEN:
1430 rp = find_package_by_id(phy_package_id);
1431 if (!rp)
1432 break;
1433 if (--rp->nr_cpus == 0)
1434 rapl_remove_package(rp);
1435 }
1436
1437 return NOTIFY_OK;
1438}
1439
1440static struct notifier_block rapl_cpu_notifier = {
1441 .notifier_call = rapl_cpu_callback,
1442};
1443
1444static int __init rapl_init(void)
1445{
1446 int ret = 0;
087e9cba 1447 const struct x86_cpu_id *id;
2d281d81 1448
087e9cba
JP		 1449 id = x86_match_cpu(rapl_ids);
1450 if (!id) {
2d281d81
JP		 1451 pr_err("driver does not support CPU family %d model %d\n",
1452 boot_cpu_data.x86, boot_cpu_data.x86_model);
1453
1454 return -ENODEV;
1455 }
009f225e 1456
087e9cba
JP		 1457 rapl_defaults = (struct rapl_defaults *)id->driver_data;
1458
009f225e
SB		 1459 cpu_notifier_register_begin();
1460
2d281d81
JP		 1461 /* prevent CPU hotplug during detection */
1462 get_online_cpus();
1463 ret = rapl_detect_topology();
1464 if (ret)
1465 goto done;
1466
1467 if (rapl_register_powercap()) {
1468 rapl_cleanup_data();
1469 ret = -ENODEV;
1470 goto done;
1471 }
009f225e 1472 __register_hotcpu_notifier(&rapl_cpu_notifier);
2d281d81
JP		 1473done:
1474 put_online_cpus();
009f225e 1475 cpu_notifier_register_done();
2d281d81
JP		 1476
1477 return ret;
1478}
1479
1480static void __exit rapl_exit(void)
1481{
009f225e 1482 cpu_notifier_register_begin();
2d281d81 1483 get_online_cpus();
009f225e 1484 __unregister_hotcpu_notifier(&rapl_cpu_notifier);
2d281d81
JP		 1485 rapl_unregister_powercap();
1486 rapl_cleanup_data();
1487 put_online_cpus();
009f225e 1488 cpu_notifier_register_done();
2d281d81
JP		 1489}
1490
1491module_init(rapl_init);
1492module_exit(rapl_exit);
1493
1494MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit)");
1495MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>");
1496MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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